Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 1 | // Auto-generated file. Do not edit! |
| 2 | // Template: src/qs8-vaddc/avx2-mul32-ld64.c.in |
| 3 | // Generator: tools/xngen |
| 4 | // |
| 5 | // Copyright 2020 Google LLC |
| 6 | // |
| 7 | // This source code is licensed under the BSD-style license found in the |
| 8 | // LICENSE file in the root directory of this source tree. |
| 9 | |
| 10 | #include <assert.h> |
| 11 | |
| 12 | #include <immintrin.h> |
| 13 | |
| 14 | #include <xnnpack/intrinsics-polyfill.h> |
| 15 | #include <xnnpack/vadd.h> |
| 16 | |
| 17 | |
| 18 | void xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x24( |
| 19 | size_t n, |
Marat Dukhan | 076bcfe | 2021-07-19 19:24:42 -0700 | [diff] [blame] | 20 | const int8_t* input_a, |
| 21 | const int8_t* input_b, |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 22 | int8_t* output, |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 23 | const union xnn_qs8_add_minmax_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_DISABLE_TSAN |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 24 | { |
Marat Dukhan | 49d9005 | 2021-07-19 19:59:30 -0700 | [diff] [blame^] | 25 | const __m256i va_multiplier = _mm256_broadcastsi128_si256(_mm_load_si128((const __m128i*) params->sse2.a_multiplier)); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 26 | const __m256i vremainder_mask = _mm256_broadcastsi128_si256(_mm_load_si128((const __m128i*) params->sse2.remainder_mask)); |
| 27 | const __m256i vremainder_threshold = _mm256_broadcastsi128_si256(_mm_load_si128((const __m128i*) params->sse2.remainder_threshold)); |
| 28 | const __m128i vshift = _mm_cvtsi32_si128((int) params->sse2.shift); |
| 29 | const __m256i voutput_zero_point = _mm256_broadcastsi128_si256(_mm_load_si128((const __m128i*) params->sse2.output_zero_point)); |
| 30 | const __m256i voutput_min = _mm256_broadcastsi128_si256(_mm_load_si128((const __m128i*) params->sse2.output_min)); |
| 31 | const __m256i voutput_max = _mm256_broadcastsi128_si256(_mm_load_si128((const __m128i*) params->sse2.output_max)); |
| 32 | |
| 33 | __m256i vzero_point_product = _mm256_broadcastsi128_si256(_mm_add_epi32( |
Marat Dukhan | 49d9005 | 2021-07-19 19:59:30 -0700 | [diff] [blame^] | 34 | _mm_broadcastd_epi32(_mm_cvtsi32_si128(params->sse2.b_multiplier[0] * (int32_t) *input_b)), |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 35 | _mm_load_si128((const __m128i*) params->sse2.zero_point_product))); |
| 36 | for (; n >= 24 * sizeof(int8_t); n -= 24 * sizeof(int8_t)) { |
Marat Dukhan | 076bcfe | 2021-07-19 19:24:42 -0700 | [diff] [blame] | 37 | const __m256i va01234567 = _mm256_cvtepi8_epi32(_mm_loadl_epi64((const __m128i*) input_a)); |
| 38 | const __m256i va89ABCDEF = _mm256_cvtepi8_epi32(_mm_loadl_epi64((const __m128i*) (input_a + 8))); |
| 39 | const __m256i vaGHIJKLMN = _mm256_cvtepi8_epi32(_mm_loadl_epi64((const __m128i*) (input_a + 16))); |
| 40 | input_a += 24; |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 41 | |
Marat Dukhan | 076bcfe | 2021-07-19 19:24:42 -0700 | [diff] [blame] | 42 | __m256i vacc01234567 = _mm256_add_epi32(vzero_point_product, _mm256_mullo_epi32(va01234567, va_multiplier)); |
| 43 | __m256i vacc89ABCDEF = _mm256_add_epi32(vzero_point_product, _mm256_mullo_epi32(va89ABCDEF, va_multiplier)); |
| 44 | __m256i vaccGHIJKLMN = _mm256_add_epi32(vzero_point_product, _mm256_mullo_epi32(vaGHIJKLMN, va_multiplier)); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 45 | |
| 46 | const __m256i vrem01234567 = _mm256_add_epi32(_mm256_and_si256(vacc01234567, vremainder_mask), _mm256_srai_epi32(vacc01234567, 31)); |
| 47 | const __m256i vrem89ABCDEF = _mm256_add_epi32(_mm256_and_si256(vacc89ABCDEF, vremainder_mask), _mm256_srai_epi32(vacc89ABCDEF, 31)); |
| 48 | const __m256i vremGHIJKLMN = _mm256_add_epi32(_mm256_and_si256(vaccGHIJKLMN, vremainder_mask), _mm256_srai_epi32(vaccGHIJKLMN, 31)); |
| 49 | |
| 50 | vacc01234567 = _mm256_sub_epi32(_mm256_sra_epi32(vacc01234567, vshift), _mm256_cmpgt_epi32(vrem01234567, vremainder_threshold)); |
| 51 | vacc89ABCDEF = _mm256_sub_epi32(_mm256_sra_epi32(vacc89ABCDEF, vshift), _mm256_cmpgt_epi32(vrem89ABCDEF, vremainder_threshold)); |
| 52 | vaccGHIJKLMN = _mm256_sub_epi32(_mm256_sra_epi32(vaccGHIJKLMN, vshift), _mm256_cmpgt_epi32(vremGHIJKLMN, vremainder_threshold)); |
| 53 | |
| 54 | __m256i vout012389AB4567CDEF = _mm256_adds_epi16(_mm256_packs_epi32(vacc01234567, vacc89ABCDEF), voutput_zero_point); |
| 55 | __m128i voutGHIJKLMN = _mm_adds_epi16(_mm_packs_epi32(_mm256_castsi256_si128(vaccGHIJKLMN), _mm256_extracti128_si256(vaccGHIJKLMN, 1)), _mm256_castsi256_si128(voutput_zero_point)); |
| 56 | |
| 57 | vout012389AB4567CDEF = _mm256_min_epi16(_mm256_max_epi16(vout012389AB4567CDEF, voutput_min), voutput_max); |
| 58 | voutGHIJKLMN = _mm_min_epi16(_mm_max_epi16(voutGHIJKLMN, _mm256_castsi256_si128(voutput_min)), _mm256_castsi256_si128(voutput_max)); |
| 59 | |
| 60 | __m128i vout0123456789ABCDEF = _mm_shuffle_epi32(_mm_packs_epi16(_mm256_castsi256_si128(vout012389AB4567CDEF), _mm256_extracti128_si256(vout012389AB4567CDEF, 1)), _MM_SHUFFLE(3, 1, 2, 0)); |
| 61 | __m128i voutGHIJKLMNGHIJKLMN = _mm_packs_epi16(voutGHIJKLMN, voutGHIJKLMN); |
| 62 | |
| 63 | _mm_storeu_si128((__m128i*) output, vout0123456789ABCDEF); |
| 64 | _mm_storel_epi64((__m128i*) (output + 16), voutGHIJKLMNGHIJKLMN); |
| 65 | output += 24; |
| 66 | } |
| 67 | if XNN_UNLIKELY(n != 0) { |
| 68 | do { |
Marat Dukhan | 076bcfe | 2021-07-19 19:24:42 -0700 | [diff] [blame] | 69 | const __m256i va01234567 = _mm256_cvtepi8_epi32(_mm_loadl_epi64((const __m128i*) input_a)); |
| 70 | input_a += 8; |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 71 | |
Marat Dukhan | 076bcfe | 2021-07-19 19:24:42 -0700 | [diff] [blame] | 72 | __m256i vacc01234567 = _mm256_add_epi32(vzero_point_product, _mm256_mullo_epi32(va01234567, va_multiplier)); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 73 | |
| 74 | const __m256i vrem01234567 = _mm256_add_epi32(_mm256_and_si256(vacc01234567, vremainder_mask), _mm256_srai_epi32(vacc01234567, 31)); |
| 75 | |
| 76 | vacc01234567 = _mm256_sub_epi32(_mm256_sra_epi32(vacc01234567, vshift), _mm256_cmpgt_epi32(vrem01234567, vremainder_threshold)); |
| 77 | |
| 78 | __m128i vout01234567 = _mm_adds_epi16(_mm_packs_epi32(_mm256_castsi256_si128(vacc01234567), _mm256_extracti128_si256(vacc01234567, 1)), _mm256_castsi256_si128(voutput_zero_point)); |
| 79 | vout01234567 = _mm_min_epi16(_mm_max_epi16(vout01234567, _mm256_castsi256_si128(voutput_min)), _mm256_castsi256_si128(voutput_max)); |
| 80 | __m128i vout0123456701234567 = _mm_packs_epi16(vout01234567, vout01234567); |
| 81 | |
| 82 | if XNN_LIKELY(n >= (8 * sizeof(int8_t))) { |
| 83 | _mm_storel_epi64((__m128i*) output, vout0123456701234567); |
| 84 | output += 8; |
| 85 | n -= 8 * sizeof(int8_t); |
| 86 | } else { |
| 87 | if (n & (4 * sizeof(int8_t))) { |
| 88 | *((uint32_t*) output) = (uint32_t) _mm_cvtsi128_si32(vout0123456701234567); |
| 89 | vout0123456701234567 = _mm_srli_epi64(vout0123456701234567, 32); |
| 90 | output += 4; |
| 91 | } |
| 92 | if (n & (2 * sizeof(int8_t))) { |
| 93 | *((uint16_t*) output) = (uint16_t) _mm_extract_epi16(vout0123456701234567, 0); |
| 94 | vout0123456701234567 = _mm_srli_epi32(vout0123456701234567, 16); |
| 95 | output += 2; |
| 96 | } |
| 97 | if (n & (1 * sizeof(int8_t))) { |
| 98 | *output = (int8_t) _mm_extract_epi8(vout0123456701234567, 0); |
| 99 | } |
| 100 | n = 0; |
| 101 | } |
| 102 | } while (n != 0); |
| 103 | } |
| 104 | } |