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Marat Dukhan6674d692021-05-05 22:27:00 -07001// Copyright 2019 Google LLC
2//
3// This source code is licensed under the BSD-style license found in the
4// LICENSE file in the root directory of this source tree.
5//
6// Auto-generated file. Do not edit!
7// Specification: test/f32-vrelu.yaml
8// Generator: tools/generate-vunary-test.py
9
10
11#include <gtest/gtest.h>
12
13#include <xnnpack/common.h>
14#include <xnnpack/isa-checks.h>
15
16#include <xnnpack/vunary.h>
17#include "vunary-microkernel-tester.h"
18
19
20#if XNN_ARCH_ARM || XNN_ARCH_ARM64
21 TEST(F32_VRELU__NEON_X4, batch_eq_4) {
22 TEST_REQUIRES_ARM_NEON;
Marat Dukhan87ed45c2021-05-13 12:25:22 -070023 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -070024 .batch_size(4)
Marat Dukhan6eaab712021-05-13 15:20:58 -070025 .Test(xnn_f32_vrelu_ukernel__neon_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -070026 }
27
28 TEST(F32_VRELU__NEON_X4, batch_div_4) {
29 TEST_REQUIRES_ARM_NEON;
30 for (size_t batch_size = 8; batch_size < 40; batch_size += 4) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -070031 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -070032 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -070033 .Test(xnn_f32_vrelu_ukernel__neon_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -070034 }
35 }
36
37 TEST(F32_VRELU__NEON_X4, batch_lt_4) {
38 TEST_REQUIRES_ARM_NEON;
39 for (size_t batch_size = 1; batch_size < 4; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -070040 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -070041 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -070042 .Test(xnn_f32_vrelu_ukernel__neon_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -070043 }
44 }
45
46 TEST(F32_VRELU__NEON_X4, batch_gt_4) {
47 TEST_REQUIRES_ARM_NEON;
48 for (size_t batch_size = 5; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -070049 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -070050 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -070051 .Test(xnn_f32_vrelu_ukernel__neon_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -070052 }
53 }
54
55 TEST(F32_VRELU__NEON_X4, inplace) {
56 TEST_REQUIRES_ARM_NEON;
57 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -070058 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -070059 .batch_size(batch_size)
60 .inplace(true)
Marat Dukhan6eaab712021-05-13 15:20:58 -070061 .Test(xnn_f32_vrelu_ukernel__neon_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -070062 }
63 }
64#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
65
66
67#if XNN_ARCH_ARM || XNN_ARCH_ARM64
68 TEST(F32_VRELU__NEON_X8, batch_eq_8) {
69 TEST_REQUIRES_ARM_NEON;
Marat Dukhan87ed45c2021-05-13 12:25:22 -070070 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -070071 .batch_size(8)
Marat Dukhan6eaab712021-05-13 15:20:58 -070072 .Test(xnn_f32_vrelu_ukernel__neon_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -070073 }
74
75 TEST(F32_VRELU__NEON_X8, batch_div_8) {
76 TEST_REQUIRES_ARM_NEON;
77 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -070078 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -070079 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -070080 .Test(xnn_f32_vrelu_ukernel__neon_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -070081 }
82 }
83
84 TEST(F32_VRELU__NEON_X8, batch_lt_8) {
85 TEST_REQUIRES_ARM_NEON;
86 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -070087 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -070088 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -070089 .Test(xnn_f32_vrelu_ukernel__neon_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -070090 }
91 }
92
93 TEST(F32_VRELU__NEON_X8, batch_gt_8) {
94 TEST_REQUIRES_ARM_NEON;
95 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -070096 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -070097 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -070098 .Test(xnn_f32_vrelu_ukernel__neon_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -070099 }
100 }
101
102 TEST(F32_VRELU__NEON_X8, inplace) {
103 TEST_REQUIRES_ARM_NEON;
104 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700105 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700106 .batch_size(batch_size)
107 .inplace(true)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700108 .Test(xnn_f32_vrelu_ukernel__neon_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700109 }
110 }
111#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
112
113
114#if XNN_ARCH_X86 || XNN_ARCH_X86_64
115 TEST(F32_VRELU__SSE_X4, batch_eq_4) {
116 TEST_REQUIRES_X86_SSE;
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700117 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700118 .batch_size(4)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700119 .Test(xnn_f32_vrelu_ukernel__sse_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700120 }
121
122 TEST(F32_VRELU__SSE_X4, batch_div_4) {
123 TEST_REQUIRES_X86_SSE;
124 for (size_t batch_size = 8; batch_size < 40; batch_size += 4) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700125 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700126 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700127 .Test(xnn_f32_vrelu_ukernel__sse_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700128 }
129 }
130
131 TEST(F32_VRELU__SSE_X4, batch_lt_4) {
132 TEST_REQUIRES_X86_SSE;
133 for (size_t batch_size = 1; batch_size < 4; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700134 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700135 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700136 .Test(xnn_f32_vrelu_ukernel__sse_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700137 }
138 }
139
140 TEST(F32_VRELU__SSE_X4, batch_gt_4) {
141 TEST_REQUIRES_X86_SSE;
142 for (size_t batch_size = 5; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700143 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700144 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700145 .Test(xnn_f32_vrelu_ukernel__sse_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700146 }
147 }
148
149 TEST(F32_VRELU__SSE_X4, inplace) {
150 TEST_REQUIRES_X86_SSE;
151 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700152 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700153 .batch_size(batch_size)
154 .inplace(true)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700155 .Test(xnn_f32_vrelu_ukernel__sse_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700156 }
157 }
158#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
159
160
161#if XNN_ARCH_X86 || XNN_ARCH_X86_64
162 TEST(F32_VRELU__SSE_X8, batch_eq_8) {
163 TEST_REQUIRES_X86_SSE;
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700164 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700165 .batch_size(8)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700166 .Test(xnn_f32_vrelu_ukernel__sse_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700167 }
168
169 TEST(F32_VRELU__SSE_X8, batch_div_8) {
170 TEST_REQUIRES_X86_SSE;
171 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700172 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700173 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700174 .Test(xnn_f32_vrelu_ukernel__sse_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700175 }
176 }
177
178 TEST(F32_VRELU__SSE_X8, batch_lt_8) {
179 TEST_REQUIRES_X86_SSE;
180 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700181 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700182 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700183 .Test(xnn_f32_vrelu_ukernel__sse_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700184 }
185 }
186
187 TEST(F32_VRELU__SSE_X8, batch_gt_8) {
188 TEST_REQUIRES_X86_SSE;
189 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700190 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700191 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700192 .Test(xnn_f32_vrelu_ukernel__sse_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700193 }
194 }
195
196 TEST(F32_VRELU__SSE_X8, inplace) {
197 TEST_REQUIRES_X86_SSE;
198 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700199 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700200 .batch_size(batch_size)
201 .inplace(true)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700202 .Test(xnn_f32_vrelu_ukernel__sse_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700203 }
204 }
205#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
206
207
208#if XNN_ARCH_X86 || XNN_ARCH_X86_64
209 TEST(F32_VRELU__AVX_X8, batch_eq_8) {
210 TEST_REQUIRES_X86_AVX;
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700211 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700212 .batch_size(8)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700213 .Test(xnn_f32_vrelu_ukernel__avx_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700214 }
215
216 TEST(F32_VRELU__AVX_X8, batch_div_8) {
217 TEST_REQUIRES_X86_AVX;
218 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700219 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700220 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700221 .Test(xnn_f32_vrelu_ukernel__avx_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700222 }
223 }
224
225 TEST(F32_VRELU__AVX_X8, batch_lt_8) {
226 TEST_REQUIRES_X86_AVX;
227 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700228 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700229 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700230 .Test(xnn_f32_vrelu_ukernel__avx_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700231 }
232 }
233
234 TEST(F32_VRELU__AVX_X8, batch_gt_8) {
235 TEST_REQUIRES_X86_AVX;
236 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700237 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700238 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700239 .Test(xnn_f32_vrelu_ukernel__avx_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700240 }
241 }
242
243 TEST(F32_VRELU__AVX_X8, inplace) {
244 TEST_REQUIRES_X86_AVX;
245 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700246 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700247 .batch_size(batch_size)
248 .inplace(true)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700249 .Test(xnn_f32_vrelu_ukernel__avx_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700250 }
251 }
252#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
253
254
255#if XNN_ARCH_X86 || XNN_ARCH_X86_64
256 TEST(F32_VRELU__AVX_X16, batch_eq_16) {
257 TEST_REQUIRES_X86_AVX;
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700258 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700259 .batch_size(16)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700260 .Test(xnn_f32_vrelu_ukernel__avx_x16, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700261 }
262
263 TEST(F32_VRELU__AVX_X16, batch_div_16) {
264 TEST_REQUIRES_X86_AVX;
265 for (size_t batch_size = 32; batch_size < 160; batch_size += 16) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700266 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700267 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700268 .Test(xnn_f32_vrelu_ukernel__avx_x16, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700269 }
270 }
271
272 TEST(F32_VRELU__AVX_X16, batch_lt_16) {
273 TEST_REQUIRES_X86_AVX;
274 for (size_t batch_size = 1; batch_size < 16; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700275 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700276 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700277 .Test(xnn_f32_vrelu_ukernel__avx_x16, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700278 }
279 }
280
281 TEST(F32_VRELU__AVX_X16, batch_gt_16) {
282 TEST_REQUIRES_X86_AVX;
283 for (size_t batch_size = 17; batch_size < 32; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700284 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700285 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700286 .Test(xnn_f32_vrelu_ukernel__avx_x16, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700287 }
288 }
289
290 TEST(F32_VRELU__AVX_X16, inplace) {
291 TEST_REQUIRES_X86_AVX;
292 for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700293 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700294 .batch_size(batch_size)
295 .inplace(true)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700296 .Test(xnn_f32_vrelu_ukernel__avx_x16, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700297 }
298 }
299#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
300
301
302#if XNN_ARCH_X86 || XNN_ARCH_X86_64
303 TEST(F32_VRELU__AVX512F_X16, batch_eq_16) {
304 TEST_REQUIRES_X86_AVX512F;
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700305 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700306 .batch_size(16)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700307 .Test(xnn_f32_vrelu_ukernel__avx512f_x16, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700308 }
309
310 TEST(F32_VRELU__AVX512F_X16, batch_div_16) {
311 TEST_REQUIRES_X86_AVX512F;
312 for (size_t batch_size = 32; batch_size < 160; batch_size += 16) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700313 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700314 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700315 .Test(xnn_f32_vrelu_ukernel__avx512f_x16, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700316 }
317 }
318
319 TEST(F32_VRELU__AVX512F_X16, batch_lt_16) {
320 TEST_REQUIRES_X86_AVX512F;
321 for (size_t batch_size = 1; batch_size < 16; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700322 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700323 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700324 .Test(xnn_f32_vrelu_ukernel__avx512f_x16, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700325 }
326 }
327
328 TEST(F32_VRELU__AVX512F_X16, batch_gt_16) {
329 TEST_REQUIRES_X86_AVX512F;
330 for (size_t batch_size = 17; batch_size < 32; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700331 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700332 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700333 .Test(xnn_f32_vrelu_ukernel__avx512f_x16, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700334 }
335 }
336
337 TEST(F32_VRELU__AVX512F_X16, inplace) {
338 TEST_REQUIRES_X86_AVX512F;
339 for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700340 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700341 .batch_size(batch_size)
342 .inplace(true)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700343 .Test(xnn_f32_vrelu_ukernel__avx512f_x16, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700344 }
345 }
346#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
347
348
349#if XNN_ARCH_X86 || XNN_ARCH_X86_64
350 TEST(F32_VRELU__AVX512F_X32, batch_eq_32) {
351 TEST_REQUIRES_X86_AVX512F;
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700352 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700353 .batch_size(32)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700354 .Test(xnn_f32_vrelu_ukernel__avx512f_x32, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700355 }
356
357 TEST(F32_VRELU__AVX512F_X32, batch_div_32) {
358 TEST_REQUIRES_X86_AVX512F;
359 for (size_t batch_size = 64; batch_size < 320; batch_size += 32) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700360 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700361 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700362 .Test(xnn_f32_vrelu_ukernel__avx512f_x32, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700363 }
364 }
365
366 TEST(F32_VRELU__AVX512F_X32, batch_lt_32) {
367 TEST_REQUIRES_X86_AVX512F;
368 for (size_t batch_size = 1; batch_size < 32; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700369 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700370 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700371 .Test(xnn_f32_vrelu_ukernel__avx512f_x32, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700372 }
373 }
374
375 TEST(F32_VRELU__AVX512F_X32, batch_gt_32) {
376 TEST_REQUIRES_X86_AVX512F;
377 for (size_t batch_size = 33; batch_size < 64; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700378 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700379 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700380 .Test(xnn_f32_vrelu_ukernel__avx512f_x32, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700381 }
382 }
383
384 TEST(F32_VRELU__AVX512F_X32, inplace) {
385 TEST_REQUIRES_X86_AVX512F;
386 for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700387 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700388 .batch_size(batch_size)
389 .inplace(true)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700390 .Test(xnn_f32_vrelu_ukernel__avx512f_x32, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700391 }
392 }
393#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
394
395
396TEST(F32_VRELU__SCALAR_X1, batch_eq_1) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700397 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700398 .batch_size(1)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700399 .Test(xnn_f32_vrelu_ukernel__scalar_x1, VUnaryMicrokernelTester::OpType::ReLU, VUnaryMicrokernelTester::Variant::Scalar);
Marat Dukhan6674d692021-05-05 22:27:00 -0700400}
401
402TEST(F32_VRELU__SCALAR_X1, batch_gt_1) {
403 for (size_t batch_size = 2; batch_size < 10; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700404 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700405 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700406 .Test(xnn_f32_vrelu_ukernel__scalar_x1, VUnaryMicrokernelTester::OpType::ReLU, VUnaryMicrokernelTester::Variant::Scalar);
Marat Dukhan6674d692021-05-05 22:27:00 -0700407 }
408}
409
410TEST(F32_VRELU__SCALAR_X1, inplace) {
411 for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700412 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700413 .batch_size(batch_size)
414 .inplace(true)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700415 .Test(xnn_f32_vrelu_ukernel__scalar_x1, VUnaryMicrokernelTester::OpType::ReLU, VUnaryMicrokernelTester::Variant::Scalar);
Marat Dukhan6674d692021-05-05 22:27:00 -0700416 }
417}
418
419
420TEST(F32_VRELU__SCALAR_X2, batch_eq_2) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700421 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700422 .batch_size(2)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700423 .Test(xnn_f32_vrelu_ukernel__scalar_x2, VUnaryMicrokernelTester::OpType::ReLU, VUnaryMicrokernelTester::Variant::Scalar);
Marat Dukhan6674d692021-05-05 22:27:00 -0700424}
425
426TEST(F32_VRELU__SCALAR_X2, batch_div_2) {
427 for (size_t batch_size = 4; batch_size < 20; batch_size += 2) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700428 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700429 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700430 .Test(xnn_f32_vrelu_ukernel__scalar_x2, VUnaryMicrokernelTester::OpType::ReLU, VUnaryMicrokernelTester::Variant::Scalar);
Marat Dukhan6674d692021-05-05 22:27:00 -0700431 }
432}
433
434TEST(F32_VRELU__SCALAR_X2, batch_lt_2) {
435 for (size_t batch_size = 1; batch_size < 2; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700436 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700437 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700438 .Test(xnn_f32_vrelu_ukernel__scalar_x2, VUnaryMicrokernelTester::OpType::ReLU, VUnaryMicrokernelTester::Variant::Scalar);
Marat Dukhan6674d692021-05-05 22:27:00 -0700439 }
440}
441
442TEST(F32_VRELU__SCALAR_X2, batch_gt_2) {
443 for (size_t batch_size = 3; batch_size < 4; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700444 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700445 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700446 .Test(xnn_f32_vrelu_ukernel__scalar_x2, VUnaryMicrokernelTester::OpType::ReLU, VUnaryMicrokernelTester::Variant::Scalar);
Marat Dukhan6674d692021-05-05 22:27:00 -0700447 }
448}
449
450TEST(F32_VRELU__SCALAR_X2, inplace) {
451 for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700452 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700453 .batch_size(batch_size)
454 .inplace(true)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700455 .Test(xnn_f32_vrelu_ukernel__scalar_x2, VUnaryMicrokernelTester::OpType::ReLU, VUnaryMicrokernelTester::Variant::Scalar);
Marat Dukhan6674d692021-05-05 22:27:00 -0700456 }
457}
458
459
460TEST(F32_VRELU__SCALAR_X4, batch_eq_4) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700461 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700462 .batch_size(4)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700463 .Test(xnn_f32_vrelu_ukernel__scalar_x4, VUnaryMicrokernelTester::OpType::ReLU, VUnaryMicrokernelTester::Variant::Scalar);
Marat Dukhan6674d692021-05-05 22:27:00 -0700464}
465
466TEST(F32_VRELU__SCALAR_X4, batch_div_4) {
467 for (size_t batch_size = 8; batch_size < 40; batch_size += 4) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700468 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700469 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700470 .Test(xnn_f32_vrelu_ukernel__scalar_x4, VUnaryMicrokernelTester::OpType::ReLU, VUnaryMicrokernelTester::Variant::Scalar);
Marat Dukhan6674d692021-05-05 22:27:00 -0700471 }
472}
473
474TEST(F32_VRELU__SCALAR_X4, batch_lt_4) {
475 for (size_t batch_size = 1; batch_size < 4; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700476 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700477 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700478 .Test(xnn_f32_vrelu_ukernel__scalar_x4, VUnaryMicrokernelTester::OpType::ReLU, VUnaryMicrokernelTester::Variant::Scalar);
Marat Dukhan6674d692021-05-05 22:27:00 -0700479 }
480}
481
482TEST(F32_VRELU__SCALAR_X4, batch_gt_4) {
483 for (size_t batch_size = 5; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700484 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700485 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700486 .Test(xnn_f32_vrelu_ukernel__scalar_x4, VUnaryMicrokernelTester::OpType::ReLU, VUnaryMicrokernelTester::Variant::Scalar);
Marat Dukhan6674d692021-05-05 22:27:00 -0700487 }
488}
489
490TEST(F32_VRELU__SCALAR_X4, inplace) {
491 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700492 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700493 .batch_size(batch_size)
494 .inplace(true)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700495 .Test(xnn_f32_vrelu_ukernel__scalar_x4, VUnaryMicrokernelTester::OpType::ReLU, VUnaryMicrokernelTester::Variant::Scalar);
Marat Dukhan6674d692021-05-05 22:27:00 -0700496 }
497}
498
499
500TEST(F32_VRELU__SCALAR_X8, batch_eq_8) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700501 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700502 .batch_size(8)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700503 .Test(xnn_f32_vrelu_ukernel__scalar_x8, VUnaryMicrokernelTester::OpType::ReLU, VUnaryMicrokernelTester::Variant::Scalar);
Marat Dukhan6674d692021-05-05 22:27:00 -0700504}
505
506TEST(F32_VRELU__SCALAR_X8, batch_div_8) {
507 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700508 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700509 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700510 .Test(xnn_f32_vrelu_ukernel__scalar_x8, VUnaryMicrokernelTester::OpType::ReLU, VUnaryMicrokernelTester::Variant::Scalar);
Marat Dukhan6674d692021-05-05 22:27:00 -0700511 }
512}
513
514TEST(F32_VRELU__SCALAR_X8, batch_lt_8) {
515 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700516 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700517 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700518 .Test(xnn_f32_vrelu_ukernel__scalar_x8, VUnaryMicrokernelTester::OpType::ReLU, VUnaryMicrokernelTester::Variant::Scalar);
Marat Dukhan6674d692021-05-05 22:27:00 -0700519 }
520}
521
522TEST(F32_VRELU__SCALAR_X8, batch_gt_8) {
523 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700524 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700525 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700526 .Test(xnn_f32_vrelu_ukernel__scalar_x8, VUnaryMicrokernelTester::OpType::ReLU, VUnaryMicrokernelTester::Variant::Scalar);
Marat Dukhan6674d692021-05-05 22:27:00 -0700527 }
528}
529
530TEST(F32_VRELU__SCALAR_X8, inplace) {
531 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700532 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700533 .batch_size(batch_size)
534 .inplace(true)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700535 .Test(xnn_f32_vrelu_ukernel__scalar_x8, VUnaryMicrokernelTester::OpType::ReLU, VUnaryMicrokernelTester::Variant::Scalar);
Marat Dukhan6674d692021-05-05 22:27:00 -0700536 }
537}
538
539
Marat Dukhan4c617792021-12-21 15:47:58 -0800540#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan6674d692021-05-05 22:27:00 -0700541 TEST(F32_VRELU__WASM_X1, batch_eq_1) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700542 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700543 .batch_size(1)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700544 .Test(xnn_f32_vrelu_ukernel__wasm_x1, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700545 }
546
547 TEST(F32_VRELU__WASM_X1, batch_gt_1) {
548 for (size_t batch_size = 2; batch_size < 10; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700549 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700550 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700551 .Test(xnn_f32_vrelu_ukernel__wasm_x1, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700552 }
553 }
554
555 TEST(F32_VRELU__WASM_X1, inplace) {
556 for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700557 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700558 .batch_size(batch_size)
559 .inplace(true)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700560 .Test(xnn_f32_vrelu_ukernel__wasm_x1, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700561 }
562 }
Marat Dukhan4c617792021-12-21 15:47:58 -0800563#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan6674d692021-05-05 22:27:00 -0700564
565
Marat Dukhan4c617792021-12-21 15:47:58 -0800566#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan6674d692021-05-05 22:27:00 -0700567 TEST(F32_VRELU__WASM_X2, batch_eq_2) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700568 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700569 .batch_size(2)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700570 .Test(xnn_f32_vrelu_ukernel__wasm_x2, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700571 }
572
573 TEST(F32_VRELU__WASM_X2, batch_div_2) {
574 for (size_t batch_size = 4; batch_size < 20; batch_size += 2) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700575 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700576 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700577 .Test(xnn_f32_vrelu_ukernel__wasm_x2, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700578 }
579 }
580
581 TEST(F32_VRELU__WASM_X2, batch_lt_2) {
582 for (size_t batch_size = 1; batch_size < 2; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700583 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700584 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700585 .Test(xnn_f32_vrelu_ukernel__wasm_x2, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700586 }
587 }
588
589 TEST(F32_VRELU__WASM_X2, batch_gt_2) {
590 for (size_t batch_size = 3; batch_size < 4; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700591 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700592 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700593 .Test(xnn_f32_vrelu_ukernel__wasm_x2, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700594 }
595 }
596
597 TEST(F32_VRELU__WASM_X2, inplace) {
598 for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700599 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700600 .batch_size(batch_size)
601 .inplace(true)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700602 .Test(xnn_f32_vrelu_ukernel__wasm_x2, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700603 }
604 }
Marat Dukhan4c617792021-12-21 15:47:58 -0800605#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan6674d692021-05-05 22:27:00 -0700606
607
Marat Dukhan4c617792021-12-21 15:47:58 -0800608#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan6674d692021-05-05 22:27:00 -0700609 TEST(F32_VRELU__WASM_X4, batch_eq_4) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700610 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700611 .batch_size(4)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700612 .Test(xnn_f32_vrelu_ukernel__wasm_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700613 }
614
615 TEST(F32_VRELU__WASM_X4, batch_div_4) {
616 for (size_t batch_size = 8; batch_size < 40; batch_size += 4) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700617 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700618 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700619 .Test(xnn_f32_vrelu_ukernel__wasm_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700620 }
621 }
622
623 TEST(F32_VRELU__WASM_X4, batch_lt_4) {
624 for (size_t batch_size = 1; batch_size < 4; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700625 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700626 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700627 .Test(xnn_f32_vrelu_ukernel__wasm_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700628 }
629 }
630
631 TEST(F32_VRELU__WASM_X4, batch_gt_4) {
632 for (size_t batch_size = 5; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700633 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700634 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700635 .Test(xnn_f32_vrelu_ukernel__wasm_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700636 }
637 }
638
639 TEST(F32_VRELU__WASM_X4, inplace) {
640 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700641 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700642 .batch_size(batch_size)
643 .inplace(true)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700644 .Test(xnn_f32_vrelu_ukernel__wasm_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700645 }
646 }
Marat Dukhan4c617792021-12-21 15:47:58 -0800647#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan6674d692021-05-05 22:27:00 -0700648
649
Marat Dukhan4c617792021-12-21 15:47:58 -0800650#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan6674d692021-05-05 22:27:00 -0700651 TEST(F32_VRELU__WASM_X8, batch_eq_8) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700652 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700653 .batch_size(8)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700654 .Test(xnn_f32_vrelu_ukernel__wasm_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700655 }
656
657 TEST(F32_VRELU__WASM_X8, batch_div_8) {
658 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700659 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700660 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700661 .Test(xnn_f32_vrelu_ukernel__wasm_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700662 }
663 }
664
665 TEST(F32_VRELU__WASM_X8, batch_lt_8) {
666 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700667 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700668 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700669 .Test(xnn_f32_vrelu_ukernel__wasm_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700670 }
671 }
672
673 TEST(F32_VRELU__WASM_X8, batch_gt_8) {
674 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700675 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700676 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700677 .Test(xnn_f32_vrelu_ukernel__wasm_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700678 }
679 }
680
681 TEST(F32_VRELU__WASM_X8, inplace) {
682 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700683 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700684 .batch_size(batch_size)
685 .inplace(true)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700686 .Test(xnn_f32_vrelu_ukernel__wasm_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700687 }
688 }
Marat Dukhan4c617792021-12-21 15:47:58 -0800689#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan6674d692021-05-05 22:27:00 -0700690
691
Marat Dukhan4c617792021-12-21 15:47:58 -0800692#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan6674d692021-05-05 22:27:00 -0700693 TEST(F32_VRELU__WASMSIMD_X4, batch_eq_4) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700694 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700695 .batch_size(4)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700696 .Test(xnn_f32_vrelu_ukernel__wasmsimd_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700697 }
698
699 TEST(F32_VRELU__WASMSIMD_X4, batch_div_4) {
700 for (size_t batch_size = 8; batch_size < 40; batch_size += 4) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700701 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700702 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700703 .Test(xnn_f32_vrelu_ukernel__wasmsimd_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700704 }
705 }
706
707 TEST(F32_VRELU__WASMSIMD_X4, batch_lt_4) {
708 for (size_t batch_size = 1; batch_size < 4; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700709 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700710 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700711 .Test(xnn_f32_vrelu_ukernel__wasmsimd_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700712 }
713 }
714
715 TEST(F32_VRELU__WASMSIMD_X4, batch_gt_4) {
716 for (size_t batch_size = 5; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700717 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700718 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700719 .Test(xnn_f32_vrelu_ukernel__wasmsimd_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700720 }
721 }
722
723 TEST(F32_VRELU__WASMSIMD_X4, inplace) {
724 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700725 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700726 .batch_size(batch_size)
727 .inplace(true)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700728 .Test(xnn_f32_vrelu_ukernel__wasmsimd_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700729 }
730 }
Marat Dukhan4c617792021-12-21 15:47:58 -0800731#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan6674d692021-05-05 22:27:00 -0700732
733
Marat Dukhan4c617792021-12-21 15:47:58 -0800734#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan6674d692021-05-05 22:27:00 -0700735 TEST(F32_VRELU__WASMSIMD_X8, batch_eq_8) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700736 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700737 .batch_size(8)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700738 .Test(xnn_f32_vrelu_ukernel__wasmsimd_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700739 }
740
741 TEST(F32_VRELU__WASMSIMD_X8, batch_div_8) {
742 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700743 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700744 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700745 .Test(xnn_f32_vrelu_ukernel__wasmsimd_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700746 }
747 }
748
749 TEST(F32_VRELU__WASMSIMD_X8, batch_lt_8) {
750 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700751 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700752 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700753 .Test(xnn_f32_vrelu_ukernel__wasmsimd_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700754 }
755 }
756
757 TEST(F32_VRELU__WASMSIMD_X8, batch_gt_8) {
758 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700759 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700760 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700761 .Test(xnn_f32_vrelu_ukernel__wasmsimd_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700762 }
763 }
764
765 TEST(F32_VRELU__WASMSIMD_X8, inplace) {
766 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700767 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700768 .batch_size(batch_size)
769 .inplace(true)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700770 .Test(xnn_f32_vrelu_ukernel__wasmsimd_x8, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700771 }
772 }
Marat Dukhan4c617792021-12-21 15:47:58 -0800773#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan6674d692021-05-05 22:27:00 -0700774
775
Marat Dukhan4c617792021-12-21 15:47:58 -0800776#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan6674d692021-05-05 22:27:00 -0700777 TEST(F32_VRELU__WASMSIMD_X16, batch_eq_16) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700778 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700779 .batch_size(16)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700780 .Test(xnn_f32_vrelu_ukernel__wasmsimd_x16, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700781 }
782
783 TEST(F32_VRELU__WASMSIMD_X16, batch_div_16) {
784 for (size_t batch_size = 32; batch_size < 160; batch_size += 16) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700785 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700786 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700787 .Test(xnn_f32_vrelu_ukernel__wasmsimd_x16, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700788 }
789 }
790
791 TEST(F32_VRELU__WASMSIMD_X16, batch_lt_16) {
792 for (size_t batch_size = 1; batch_size < 16; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700793 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700794 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700795 .Test(xnn_f32_vrelu_ukernel__wasmsimd_x16, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700796 }
797 }
798
799 TEST(F32_VRELU__WASMSIMD_X16, batch_gt_16) {
800 for (size_t batch_size = 17; batch_size < 32; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700801 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700802 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700803 .Test(xnn_f32_vrelu_ukernel__wasmsimd_x16, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700804 }
805 }
806
807 TEST(F32_VRELU__WASMSIMD_X16, inplace) {
808 for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700809 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700810 .batch_size(batch_size)
811 .inplace(true)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700812 .Test(xnn_f32_vrelu_ukernel__wasmsimd_x16, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700813 }
814 }
Marat Dukhan4c617792021-12-21 15:47:58 -0800815#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan6674d692021-05-05 22:27:00 -0700816
817
818#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
819 TEST(F32_VRELU__WASM32_SHR_X1, batch_eq_1) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700820 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700821 .batch_size(1)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700822 .Test(xnn_f32_vrelu_ukernel__wasm32_shr_x1, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700823 }
824
825 TEST(F32_VRELU__WASM32_SHR_X1, batch_gt_1) {
826 for (size_t batch_size = 2; batch_size < 10; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700827 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700828 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700829 .Test(xnn_f32_vrelu_ukernel__wasm32_shr_x1, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700830 }
831 }
832
833 TEST(F32_VRELU__WASM32_SHR_X1, inplace) {
834 for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700835 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700836 .batch_size(batch_size)
837 .inplace(true)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700838 .Test(xnn_f32_vrelu_ukernel__wasm32_shr_x1, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700839 }
840 }
841#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
842
843
844#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
845 TEST(F32_VRELU__WASM32_SHR_X2, batch_eq_2) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700846 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700847 .batch_size(2)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700848 .Test(xnn_f32_vrelu_ukernel__wasm32_shr_x2, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700849 }
850
851 TEST(F32_VRELU__WASM32_SHR_X2, batch_div_2) {
852 for (size_t batch_size = 4; batch_size < 20; batch_size += 2) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700853 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700854 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700855 .Test(xnn_f32_vrelu_ukernel__wasm32_shr_x2, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700856 }
857 }
858
859 TEST(F32_VRELU__WASM32_SHR_X2, batch_lt_2) {
860 for (size_t batch_size = 1; batch_size < 2; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700861 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700862 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700863 .Test(xnn_f32_vrelu_ukernel__wasm32_shr_x2, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700864 }
865 }
866
867 TEST(F32_VRELU__WASM32_SHR_X2, batch_gt_2) {
868 for (size_t batch_size = 3; batch_size < 4; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700869 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700870 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700871 .Test(xnn_f32_vrelu_ukernel__wasm32_shr_x2, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700872 }
873 }
874
875 TEST(F32_VRELU__WASM32_SHR_X2, inplace) {
876 for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700877 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700878 .batch_size(batch_size)
879 .inplace(true)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700880 .Test(xnn_f32_vrelu_ukernel__wasm32_shr_x2, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700881 }
882 }
883#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
884
885
886#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
887 TEST(F32_VRELU__WASM32_SHR_X4, batch_eq_4) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700888 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700889 .batch_size(4)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700890 .Test(xnn_f32_vrelu_ukernel__wasm32_shr_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700891 }
892
893 TEST(F32_VRELU__WASM32_SHR_X4, batch_div_4) {
894 for (size_t batch_size = 8; batch_size < 40; batch_size += 4) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700895 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700896 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700897 .Test(xnn_f32_vrelu_ukernel__wasm32_shr_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700898 }
899 }
900
901 TEST(F32_VRELU__WASM32_SHR_X4, batch_lt_4) {
902 for (size_t batch_size = 1; batch_size < 4; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700903 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700904 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700905 .Test(xnn_f32_vrelu_ukernel__wasm32_shr_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700906 }
907 }
908
909 TEST(F32_VRELU__WASM32_SHR_X4, batch_gt_4) {
910 for (size_t batch_size = 5; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700911 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700912 .batch_size(batch_size)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700913 .Test(xnn_f32_vrelu_ukernel__wasm32_shr_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700914 }
915 }
916
917 TEST(F32_VRELU__WASM32_SHR_X4, inplace) {
918 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700919 VUnaryMicrokernelTester()
Marat Dukhan6674d692021-05-05 22:27:00 -0700920 .batch_size(batch_size)
921 .inplace(true)
Marat Dukhan6eaab712021-05-13 15:20:58 -0700922 .Test(xnn_f32_vrelu_ukernel__wasm32_shr_x4, VUnaryMicrokernelTester::OpType::ReLU);
Marat Dukhan6674d692021-05-05 22:27:00 -0700923 }
924 }
925#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD