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Marat Dukhane9c4b962021-04-02 16:56:55 -07001// Auto-generated file. Do not edit!
2// Template: src/qs8-vaddc/sse-mul32-ld32.c.in
3// Generator: tools/xngen
4//
5// Copyright 2020 Google LLC
6//
7// This source code is licensed under the BSD-style license found in the
8// LICENSE file in the root directory of this source tree.
9
10#include <assert.h>
11
12#include <immintrin.h>
13
14#include <xnnpack/intrinsics-polyfill.h>
15#include <xnnpack/vadd.h>
16
17
18void xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x24(
19 size_t n,
Marat Dukhan076bcfe2021-07-19 19:24:42 -070020 const int8_t* input_a,
21 const int8_t* input_b,
Marat Dukhane9c4b962021-04-02 16:56:55 -070022 int8_t* output,
Marat Dukhan6e0fc392021-07-19 18:38:24 -070023 const union xnn_qs8_add_minmax_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_DISABLE_TSAN
Marat Dukhane9c4b962021-04-02 16:56:55 -070024{
Marat Dukhan49d90052021-07-19 19:59:30 -070025 const __m128i va_multiplier = _mm_load_si128((const __m128i*) params->sse2.a_multiplier);
Marat Dukhane9c4b962021-04-02 16:56:55 -070026 const __m128i vremainder_mask = _mm_load_si128((const __m128i*) params->sse2.remainder_mask);
27 const __m128i vremainder_threshold = _mm_load_si128((const __m128i*) params->sse2.remainder_threshold);
28 const __m128i vshift = _mm_cvtsi32_si128((int) params->sse2.shift);
29 const __m128i voutput_zero_point = _mm_load_si128((const __m128i*) params->sse2.output_zero_point);
30 const __m128i voutput_min = _mm_load_si128((const __m128i*) params->sse2.output_min);
31 const __m128i voutput_max = _mm_load_si128((const __m128i*) params->sse2.output_max);
32
Marat Dukhana842fef2021-07-19 21:07:40 -070033 __m128i vbias = _mm_cvtsi32_si128(params->sse2.b_multiplier[0] * (int32_t) *input_b);
34 vbias = _mm_shuffle_epi32(vbias, _MM_SHUFFLE(0, 0, 0, 0));
35 vbias = _mm_add_epi32(vbias, _mm_load_si128((const __m128i*) params->sse2.bias));
Marat Dukhane9c4b962021-04-02 16:56:55 -070036 for (; n >= 24 * sizeof(int8_t); n -= 24 * sizeof(int8_t)) {
Marat Dukhan076bcfe2021-07-19 19:24:42 -070037 const __m128i va0123 = _mm_cvtepi8_epi32(_mm_loadu_si32(input_a));
38 const __m128i va4567 = _mm_cvtepi8_epi32(_mm_loadu_si32(input_a + 4));
39 const __m128i va89AB = _mm_cvtepi8_epi32(_mm_loadu_si32(input_a + 8));
40 const __m128i vaCDEF = _mm_cvtepi8_epi32(_mm_loadu_si32(input_a + 12));
41 const __m128i vaGHIJ = _mm_cvtepi8_epi32(_mm_loadu_si32(input_a + 16));
42 const __m128i vaKLMN = _mm_cvtepi8_epi32(_mm_loadu_si32(input_a + 20));
43 input_a += 24;
44 input_b += 24;
Marat Dukhane9c4b962021-04-02 16:56:55 -070045
Marat Dukhana842fef2021-07-19 21:07:40 -070046 __m128i vacc0123 = _mm_add_epi32(vbias, _mm_mullo_epi32(va0123, va_multiplier));
47 __m128i vacc4567 = _mm_add_epi32(vbias, _mm_mullo_epi32(va4567, va_multiplier));
48 __m128i vacc89AB = _mm_add_epi32(vbias, _mm_mullo_epi32(va89AB, va_multiplier));
49 __m128i vaccCDEF = _mm_add_epi32(vbias, _mm_mullo_epi32(vaCDEF, va_multiplier));
50 __m128i vaccGHIJ = _mm_add_epi32(vbias, _mm_mullo_epi32(vaGHIJ, va_multiplier));
51 __m128i vaccKLMN = _mm_add_epi32(vbias, _mm_mullo_epi32(vaKLMN, va_multiplier));
Marat Dukhane9c4b962021-04-02 16:56:55 -070052
53 const __m128i vrem0123 = _mm_add_epi32(_mm_and_si128(vacc0123, vremainder_mask), _mm_cmpgt_epi32(_mm_setzero_si128(), vacc0123));
54 const __m128i vrem4567 = _mm_add_epi32(_mm_and_si128(vacc4567, vremainder_mask), _mm_cmpgt_epi32(_mm_setzero_si128(), vacc4567));
55 const __m128i vrem89AB = _mm_add_epi32(_mm_and_si128(vacc89AB, vremainder_mask), _mm_cmpgt_epi32(_mm_setzero_si128(), vacc89AB));
56 const __m128i vremCDEF = _mm_add_epi32(_mm_and_si128(vaccCDEF, vremainder_mask), _mm_cmpgt_epi32(_mm_setzero_si128(), vaccCDEF));
57 const __m128i vremGHIJ = _mm_add_epi32(_mm_and_si128(vaccGHIJ, vremainder_mask), _mm_cmpgt_epi32(_mm_setzero_si128(), vaccGHIJ));
58 const __m128i vremKLMN = _mm_add_epi32(_mm_and_si128(vaccKLMN, vremainder_mask), _mm_cmpgt_epi32(_mm_setzero_si128(), vaccKLMN));
59
60 vacc0123 = _mm_sub_epi32(_mm_sra_epi32(vacc0123, vshift), _mm_cmpgt_epi32(vrem0123, vremainder_threshold));
61 vacc4567 = _mm_sub_epi32(_mm_sra_epi32(vacc4567, vshift), _mm_cmpgt_epi32(vrem4567, vremainder_threshold));
62 vacc89AB = _mm_sub_epi32(_mm_sra_epi32(vacc89AB, vshift), _mm_cmpgt_epi32(vrem89AB, vremainder_threshold));
63 vaccCDEF = _mm_sub_epi32(_mm_sra_epi32(vaccCDEF, vshift), _mm_cmpgt_epi32(vremCDEF, vremainder_threshold));
64 vaccGHIJ = _mm_sub_epi32(_mm_sra_epi32(vaccGHIJ, vshift), _mm_cmpgt_epi32(vremGHIJ, vremainder_threshold));
65 vaccKLMN = _mm_sub_epi32(_mm_sra_epi32(vaccKLMN, vshift), _mm_cmpgt_epi32(vremKLMN, vremainder_threshold));
66
67 __m128i vout01234567 = _mm_adds_epi16(_mm_packs_epi32(vacc0123, vacc4567), voutput_zero_point);
68 __m128i vout89ABCDEF = _mm_adds_epi16(_mm_packs_epi32(vacc89AB, vaccCDEF), voutput_zero_point);
69 __m128i voutGHIJKLMN = _mm_adds_epi16(_mm_packs_epi32(vaccGHIJ, vaccKLMN), voutput_zero_point);
70
71 vout01234567 = _mm_max_epi16(vout01234567, voutput_min);
72 vout89ABCDEF = _mm_max_epi16(vout89ABCDEF, voutput_min);
73 voutGHIJKLMN = _mm_max_epi16(voutGHIJKLMN, voutput_min);
74
75 vout01234567 = _mm_min_epi16(vout01234567, voutput_max);
76 vout89ABCDEF = _mm_min_epi16(vout89ABCDEF, voutput_max);
77 voutGHIJKLMN = _mm_min_epi16(voutGHIJKLMN, voutput_max);
78
79 const __m128i vout0123456789ABCDEF = _mm_packs_epi16(vout01234567, vout89ABCDEF);
80 const __m128i voutGHIJKLMNGHIJKLMN = _mm_packs_epi16(voutGHIJKLMN, voutGHIJKLMN);
81
82 _mm_storeu_si128((__m128i*) output, vout0123456789ABCDEF);
83 _mm_storel_epi64((__m128i*) (output + 16), voutGHIJKLMNGHIJKLMN);
84 output += 24;
85 }
86 if XNN_UNLIKELY(n != 0) {
87 do {
Marat Dukhan076bcfe2021-07-19 19:24:42 -070088 const __m128i va0123 = _mm_cvtepi8_epi32(_mm_loadu_si32(input_a));
89 const __m128i va4567 = _mm_cvtepi8_epi32(_mm_loadu_si32(input_a + 4));
90 input_a += 8;
Marat Dukhane9c4b962021-04-02 16:56:55 -070091
Marat Dukhana842fef2021-07-19 21:07:40 -070092 __m128i vacc0123 = _mm_add_epi32(vbias, _mm_mullo_epi32(va0123, va_multiplier));
93 __m128i vacc4567 = _mm_add_epi32(vbias, _mm_mullo_epi32(va4567, va_multiplier));
Marat Dukhane9c4b962021-04-02 16:56:55 -070094
95 const __m128i vrem0123 = _mm_add_epi32(_mm_and_si128(vacc0123, vremainder_mask), _mm_cmpgt_epi32(_mm_setzero_si128(), vacc0123));
96 const __m128i vrem4567 = _mm_add_epi32(_mm_and_si128(vacc4567, vremainder_mask), _mm_cmpgt_epi32(_mm_setzero_si128(), vacc4567));
97
98 vacc0123 = _mm_sub_epi32(_mm_sra_epi32(vacc0123, vshift), _mm_cmpgt_epi32(vrem0123, vremainder_threshold));
99 vacc4567 = _mm_sub_epi32(_mm_sra_epi32(vacc4567, vshift), _mm_cmpgt_epi32(vrem4567, vremainder_threshold));
100
101 __m128i vout01234567 = _mm_adds_epi16(_mm_packs_epi32(vacc0123, vacc4567), voutput_zero_point);
102 vout01234567 = _mm_max_epi16(vout01234567, voutput_min);
103 vout01234567 = _mm_min_epi16(vout01234567, voutput_max);
104
105 __m128i vout0123456701234567 = _mm_packs_epi16(vout01234567, vout01234567);
106
107 if XNN_LIKELY(n >= (8 * sizeof(int8_t))) {
108 _mm_storel_epi64((__m128i*) output, vout0123456701234567);
109 output += 8;
110 n -= 8 * sizeof(int8_t);
111 } else {
112 if (n & (4 * sizeof(int8_t))) {
113 *((uint32_t*) output) = (uint32_t) _mm_cvtsi128_si32(vout0123456701234567);
114 vout0123456701234567 = _mm_srli_epi64(vout0123456701234567, 32);
115 output += 4;
116 }
117 if (n & (2 * sizeof(int8_t))) {
118 *((uint16_t*) output) = (uint16_t) _mm_extract_epi16(vout0123456701234567, 0);
119 vout0123456701234567 = _mm_srli_epi32(vout0123456701234567, 16);
120 output += 2;
121 }
122 if (n & (1 * sizeof(int8_t))) {
123 *output = (int8_t) _mm_extract_epi8(vout0123456701234567, 0);
124 }
125 n = 0;
126 }
127 } while (n != 0);
128 }
129}