blob: c1ae9b04dc6d280b554de59d3fea1998e3ed402b [file] [log] [blame]
Marat Dukhand77f77d2021-10-24 15:39:59 -07001// Copyright 2021 Google LLC
2//
3// This source code is licensed under the BSD-style license found in the
4// LICENSE file in the root directory of this source tree.
5//
6// Auto-generated file. Do not edit!
7// Specification: test/f32-f16-vcvt.yaml
8// Generator: tools/generate-vcvt-test.py
9
10
11#include <gtest/gtest.h>
12
13#include <xnnpack/common.h>
14#include <xnnpack/isa-checks.h>
15
16#include <xnnpack/vcvt.h>
17#include "vcvt-microkernel-tester.h"
18
19
20#if XNN_ARCH_ARM || XNN_ARCH_ARM64
Marat Dukhan4edfdbf2021-11-09 13:47:11 -080021 TEST(F32_F16_VCVT__NEON_X8, batch_eq_8) {
22 TEST_REQUIRES_ARM_NEON;
23 VCvtMicrokernelTester()
24 .batch_size(8)
Marat Dukhanb7c1b712021-12-30 07:23:57 -080025 .Test(xnn_f32_f16_vcvt_ukernel__neon_x8, xnn_init_f32_f16_cvt_neon_params);
Marat Dukhan4edfdbf2021-11-09 13:47:11 -080026 }
27
28 TEST(F32_F16_VCVT__NEON_X8, batch_div_8) {
29 TEST_REQUIRES_ARM_NEON;
30 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
31 VCvtMicrokernelTester()
32 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -080033 .Test(xnn_f32_f16_vcvt_ukernel__neon_x8, xnn_init_f32_f16_cvt_neon_params);
Marat Dukhan4edfdbf2021-11-09 13:47:11 -080034 }
35 }
36
37 TEST(F32_F16_VCVT__NEON_X8, batch_lt_8) {
38 TEST_REQUIRES_ARM_NEON;
39 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
40 VCvtMicrokernelTester()
41 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -080042 .Test(xnn_f32_f16_vcvt_ukernel__neon_x8, xnn_init_f32_f16_cvt_neon_params);
Marat Dukhan4edfdbf2021-11-09 13:47:11 -080043 }
44 }
45
46 TEST(F32_F16_VCVT__NEON_X8, batch_gt_8) {
47 TEST_REQUIRES_ARM_NEON;
48 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
49 VCvtMicrokernelTester()
50 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -080051 .Test(xnn_f32_f16_vcvt_ukernel__neon_x8, xnn_init_f32_f16_cvt_neon_params);
Marat Dukhan4edfdbf2021-11-09 13:47:11 -080052 }
53 }
54#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
55
56
57#if XNN_ARCH_ARM || XNN_ARCH_ARM64
58 TEST(F32_F16_VCVT__NEON_X16, batch_eq_16) {
59 TEST_REQUIRES_ARM_NEON;
60 VCvtMicrokernelTester()
61 .batch_size(16)
Marat Dukhanb7c1b712021-12-30 07:23:57 -080062 .Test(xnn_f32_f16_vcvt_ukernel__neon_x16, xnn_init_f32_f16_cvt_neon_params);
Marat Dukhan4edfdbf2021-11-09 13:47:11 -080063 }
64
65 TEST(F32_F16_VCVT__NEON_X16, batch_div_16) {
66 TEST_REQUIRES_ARM_NEON;
67 for (size_t batch_size = 32; batch_size < 160; batch_size += 16) {
68 VCvtMicrokernelTester()
69 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -080070 .Test(xnn_f32_f16_vcvt_ukernel__neon_x16, xnn_init_f32_f16_cvt_neon_params);
Marat Dukhan4edfdbf2021-11-09 13:47:11 -080071 }
72 }
73
74 TEST(F32_F16_VCVT__NEON_X16, batch_lt_16) {
75 TEST_REQUIRES_ARM_NEON;
76 for (size_t batch_size = 1; batch_size < 16; batch_size++) {
77 VCvtMicrokernelTester()
78 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -080079 .Test(xnn_f32_f16_vcvt_ukernel__neon_x16, xnn_init_f32_f16_cvt_neon_params);
Marat Dukhan4edfdbf2021-11-09 13:47:11 -080080 }
81 }
82
83 TEST(F32_F16_VCVT__NEON_X16, batch_gt_16) {
84 TEST_REQUIRES_ARM_NEON;
85 for (size_t batch_size = 17; batch_size < 32; batch_size++) {
86 VCvtMicrokernelTester()
87 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -080088 .Test(xnn_f32_f16_vcvt_ukernel__neon_x16, xnn_init_f32_f16_cvt_neon_params);
Marat Dukhan4edfdbf2021-11-09 13:47:11 -080089 }
90 }
91#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
92
93
94#if XNN_ARCH_ARM || XNN_ARCH_ARM64
95 TEST(F32_F16_VCVT__NEON_X24, batch_eq_24) {
96 TEST_REQUIRES_ARM_NEON;
97 VCvtMicrokernelTester()
98 .batch_size(24)
Marat Dukhanb7c1b712021-12-30 07:23:57 -080099 .Test(xnn_f32_f16_vcvt_ukernel__neon_x24, xnn_init_f32_f16_cvt_neon_params);
Marat Dukhan4edfdbf2021-11-09 13:47:11 -0800100 }
101
102 TEST(F32_F16_VCVT__NEON_X24, batch_div_24) {
103 TEST_REQUIRES_ARM_NEON;
104 for (size_t batch_size = 48; batch_size < 240; batch_size += 24) {
105 VCvtMicrokernelTester()
106 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800107 .Test(xnn_f32_f16_vcvt_ukernel__neon_x24, xnn_init_f32_f16_cvt_neon_params);
Marat Dukhan4edfdbf2021-11-09 13:47:11 -0800108 }
109 }
110
111 TEST(F32_F16_VCVT__NEON_X24, batch_lt_24) {
112 TEST_REQUIRES_ARM_NEON;
113 for (size_t batch_size = 1; batch_size < 24; batch_size++) {
114 VCvtMicrokernelTester()
115 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800116 .Test(xnn_f32_f16_vcvt_ukernel__neon_x24, xnn_init_f32_f16_cvt_neon_params);
Marat Dukhan4edfdbf2021-11-09 13:47:11 -0800117 }
118 }
119
120 TEST(F32_F16_VCVT__NEON_X24, batch_gt_24) {
121 TEST_REQUIRES_ARM_NEON;
122 for (size_t batch_size = 25; batch_size < 48; batch_size++) {
123 VCvtMicrokernelTester()
124 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800125 .Test(xnn_f32_f16_vcvt_ukernel__neon_x24, xnn_init_f32_f16_cvt_neon_params);
Marat Dukhan4edfdbf2021-11-09 13:47:11 -0800126 }
127 }
128#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
129
130
131#if XNN_ARCH_ARM || XNN_ARCH_ARM64
132 TEST(F32_F16_VCVT__NEON_X32, batch_eq_32) {
133 TEST_REQUIRES_ARM_NEON;
134 VCvtMicrokernelTester()
135 .batch_size(32)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800136 .Test(xnn_f32_f16_vcvt_ukernel__neon_x32, xnn_init_f32_f16_cvt_neon_params);
Marat Dukhan4edfdbf2021-11-09 13:47:11 -0800137 }
138
139 TEST(F32_F16_VCVT__NEON_X32, batch_div_32) {
140 TEST_REQUIRES_ARM_NEON;
141 for (size_t batch_size = 64; batch_size < 320; batch_size += 32) {
142 VCvtMicrokernelTester()
143 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800144 .Test(xnn_f32_f16_vcvt_ukernel__neon_x32, xnn_init_f32_f16_cvt_neon_params);
Marat Dukhan4edfdbf2021-11-09 13:47:11 -0800145 }
146 }
147
148 TEST(F32_F16_VCVT__NEON_X32, batch_lt_32) {
149 TEST_REQUIRES_ARM_NEON;
150 for (size_t batch_size = 1; batch_size < 32; batch_size++) {
151 VCvtMicrokernelTester()
152 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800153 .Test(xnn_f32_f16_vcvt_ukernel__neon_x32, xnn_init_f32_f16_cvt_neon_params);
Marat Dukhan4edfdbf2021-11-09 13:47:11 -0800154 }
155 }
156
157 TEST(F32_F16_VCVT__NEON_X32, batch_gt_32) {
158 TEST_REQUIRES_ARM_NEON;
159 for (size_t batch_size = 33; batch_size < 64; batch_size++) {
160 VCvtMicrokernelTester()
161 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800162 .Test(xnn_f32_f16_vcvt_ukernel__neon_x32, xnn_init_f32_f16_cvt_neon_params);
Marat Dukhan4edfdbf2021-11-09 13:47:11 -0800163 }
164 }
165#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
166
167
168#if XNN_ARCH_ARM || XNN_ARCH_ARM64
Marat Dukhand77f77d2021-10-24 15:39:59 -0700169 TEST(F32_F16_VCVT__NEONFP16_X8, batch_eq_8) {
170 TEST_REQUIRES_ARM_NEON_FP16;
171 VCvtMicrokernelTester()
172 .batch_size(8)
173 .Test(xnn_f32_f16_vcvt_ukernel__neonfp16_x8);
174 }
175
176 TEST(F32_F16_VCVT__NEONFP16_X8, batch_div_8) {
177 TEST_REQUIRES_ARM_NEON_FP16;
178 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
179 VCvtMicrokernelTester()
180 .batch_size(batch_size)
181 .Test(xnn_f32_f16_vcvt_ukernel__neonfp16_x8);
182 }
183 }
184
185 TEST(F32_F16_VCVT__NEONFP16_X8, batch_lt_8) {
186 TEST_REQUIRES_ARM_NEON_FP16;
187 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
188 VCvtMicrokernelTester()
189 .batch_size(batch_size)
190 .Test(xnn_f32_f16_vcvt_ukernel__neonfp16_x8);
191 }
192 }
193
194 TEST(F32_F16_VCVT__NEONFP16_X8, batch_gt_8) {
195 TEST_REQUIRES_ARM_NEON_FP16;
196 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
197 VCvtMicrokernelTester()
198 .batch_size(batch_size)
199 .Test(xnn_f32_f16_vcvt_ukernel__neonfp16_x8);
200 }
201 }
202#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
203
204
205#if XNN_ARCH_ARM || XNN_ARCH_ARM64
206 TEST(F32_F16_VCVT__NEONFP16_X16, batch_eq_16) {
207 TEST_REQUIRES_ARM_NEON_FP16;
208 VCvtMicrokernelTester()
209 .batch_size(16)
210 .Test(xnn_f32_f16_vcvt_ukernel__neonfp16_x16);
211 }
212
213 TEST(F32_F16_VCVT__NEONFP16_X16, batch_div_16) {
214 TEST_REQUIRES_ARM_NEON_FP16;
215 for (size_t batch_size = 32; batch_size < 160; batch_size += 16) {
216 VCvtMicrokernelTester()
217 .batch_size(batch_size)
218 .Test(xnn_f32_f16_vcvt_ukernel__neonfp16_x16);
219 }
220 }
221
222 TEST(F32_F16_VCVT__NEONFP16_X16, batch_lt_16) {
223 TEST_REQUIRES_ARM_NEON_FP16;
224 for (size_t batch_size = 1; batch_size < 16; batch_size++) {
225 VCvtMicrokernelTester()
226 .batch_size(batch_size)
227 .Test(xnn_f32_f16_vcvt_ukernel__neonfp16_x16);
228 }
229 }
230
231 TEST(F32_F16_VCVT__NEONFP16_X16, batch_gt_16) {
232 TEST_REQUIRES_ARM_NEON_FP16;
233 for (size_t batch_size = 17; batch_size < 32; batch_size++) {
234 VCvtMicrokernelTester()
235 .batch_size(batch_size)
236 .Test(xnn_f32_f16_vcvt_ukernel__neonfp16_x16);
237 }
238 }
239#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
240
241
242#if XNN_ARCH_X86 || XNN_ARCH_X86_64
Marat Dukhaneb844232021-11-08 23:07:53 -0800243 TEST(F32_F16_VCVT__SSE2_X8, batch_eq_8) {
244 TEST_REQUIRES_X86_SSE2;
245 VCvtMicrokernelTester()
246 .batch_size(8)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800247 .Test(xnn_f32_f16_vcvt_ukernel__sse2_x8, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800248 }
249
250 TEST(F32_F16_VCVT__SSE2_X8, batch_div_8) {
251 TEST_REQUIRES_X86_SSE2;
252 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
253 VCvtMicrokernelTester()
254 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800255 .Test(xnn_f32_f16_vcvt_ukernel__sse2_x8, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800256 }
257 }
258
259 TEST(F32_F16_VCVT__SSE2_X8, batch_lt_8) {
260 TEST_REQUIRES_X86_SSE2;
261 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
262 VCvtMicrokernelTester()
263 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800264 .Test(xnn_f32_f16_vcvt_ukernel__sse2_x8, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800265 }
266 }
267
268 TEST(F32_F16_VCVT__SSE2_X8, batch_gt_8) {
269 TEST_REQUIRES_X86_SSE2;
270 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
271 VCvtMicrokernelTester()
272 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800273 .Test(xnn_f32_f16_vcvt_ukernel__sse2_x8, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800274 }
275 }
276#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
277
278
279#if XNN_ARCH_X86 || XNN_ARCH_X86_64
280 TEST(F32_F16_VCVT__SSE2_X16, batch_eq_16) {
281 TEST_REQUIRES_X86_SSE2;
282 VCvtMicrokernelTester()
283 .batch_size(16)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800284 .Test(xnn_f32_f16_vcvt_ukernel__sse2_x16, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800285 }
286
287 TEST(F32_F16_VCVT__SSE2_X16, batch_div_16) {
288 TEST_REQUIRES_X86_SSE2;
289 for (size_t batch_size = 32; batch_size < 160; batch_size += 16) {
290 VCvtMicrokernelTester()
291 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800292 .Test(xnn_f32_f16_vcvt_ukernel__sse2_x16, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800293 }
294 }
295
296 TEST(F32_F16_VCVT__SSE2_X16, batch_lt_16) {
297 TEST_REQUIRES_X86_SSE2;
298 for (size_t batch_size = 1; batch_size < 16; batch_size++) {
299 VCvtMicrokernelTester()
300 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800301 .Test(xnn_f32_f16_vcvt_ukernel__sse2_x16, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800302 }
303 }
304
305 TEST(F32_F16_VCVT__SSE2_X16, batch_gt_16) {
306 TEST_REQUIRES_X86_SSE2;
307 for (size_t batch_size = 17; batch_size < 32; batch_size++) {
308 VCvtMicrokernelTester()
309 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800310 .Test(xnn_f32_f16_vcvt_ukernel__sse2_x16, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800311 }
312 }
313#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
314
315
316#if XNN_ARCH_X86 || XNN_ARCH_X86_64
317 TEST(F32_F16_VCVT__SSE2_X24, batch_eq_24) {
318 TEST_REQUIRES_X86_SSE2;
319 VCvtMicrokernelTester()
320 .batch_size(24)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800321 .Test(xnn_f32_f16_vcvt_ukernel__sse2_x24, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800322 }
323
324 TEST(F32_F16_VCVT__SSE2_X24, batch_div_24) {
325 TEST_REQUIRES_X86_SSE2;
326 for (size_t batch_size = 48; batch_size < 240; batch_size += 24) {
327 VCvtMicrokernelTester()
328 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800329 .Test(xnn_f32_f16_vcvt_ukernel__sse2_x24, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800330 }
331 }
332
333 TEST(F32_F16_VCVT__SSE2_X24, batch_lt_24) {
334 TEST_REQUIRES_X86_SSE2;
335 for (size_t batch_size = 1; batch_size < 24; batch_size++) {
336 VCvtMicrokernelTester()
337 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800338 .Test(xnn_f32_f16_vcvt_ukernel__sse2_x24, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800339 }
340 }
341
342 TEST(F32_F16_VCVT__SSE2_X24, batch_gt_24) {
343 TEST_REQUIRES_X86_SSE2;
344 for (size_t batch_size = 25; batch_size < 48; batch_size++) {
345 VCvtMicrokernelTester()
346 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800347 .Test(xnn_f32_f16_vcvt_ukernel__sse2_x24, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800348 }
349 }
350#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
351
352
353#if XNN_ARCH_X86 || XNN_ARCH_X86_64
354 TEST(F32_F16_VCVT__SSE2_X32, batch_eq_32) {
355 TEST_REQUIRES_X86_SSE2;
356 VCvtMicrokernelTester()
357 .batch_size(32)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800358 .Test(xnn_f32_f16_vcvt_ukernel__sse2_x32, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800359 }
360
361 TEST(F32_F16_VCVT__SSE2_X32, batch_div_32) {
362 TEST_REQUIRES_X86_SSE2;
363 for (size_t batch_size = 64; batch_size < 320; batch_size += 32) {
364 VCvtMicrokernelTester()
365 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800366 .Test(xnn_f32_f16_vcvt_ukernel__sse2_x32, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800367 }
368 }
369
370 TEST(F32_F16_VCVT__SSE2_X32, batch_lt_32) {
371 TEST_REQUIRES_X86_SSE2;
372 for (size_t batch_size = 1; batch_size < 32; batch_size++) {
373 VCvtMicrokernelTester()
374 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800375 .Test(xnn_f32_f16_vcvt_ukernel__sse2_x32, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800376 }
377 }
378
379 TEST(F32_F16_VCVT__SSE2_X32, batch_gt_32) {
380 TEST_REQUIRES_X86_SSE2;
381 for (size_t batch_size = 33; batch_size < 64; batch_size++) {
382 VCvtMicrokernelTester()
383 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800384 .Test(xnn_f32_f16_vcvt_ukernel__sse2_x32, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800385 }
386 }
387#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
388
389
390#if XNN_ARCH_X86 || XNN_ARCH_X86_64
391 TEST(F32_F16_VCVT__SSE41_X8, batch_eq_8) {
392 TEST_REQUIRES_X86_SSE41;
393 VCvtMicrokernelTester()
394 .batch_size(8)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800395 .Test(xnn_f32_f16_vcvt_ukernel__sse41_x8, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800396 }
397
398 TEST(F32_F16_VCVT__SSE41_X8, batch_div_8) {
399 TEST_REQUIRES_X86_SSE41;
400 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
401 VCvtMicrokernelTester()
402 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800403 .Test(xnn_f32_f16_vcvt_ukernel__sse41_x8, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800404 }
405 }
406
407 TEST(F32_F16_VCVT__SSE41_X8, batch_lt_8) {
408 TEST_REQUIRES_X86_SSE41;
409 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
410 VCvtMicrokernelTester()
411 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800412 .Test(xnn_f32_f16_vcvt_ukernel__sse41_x8, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800413 }
414 }
415
416 TEST(F32_F16_VCVT__SSE41_X8, batch_gt_8) {
417 TEST_REQUIRES_X86_SSE41;
418 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
419 VCvtMicrokernelTester()
420 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800421 .Test(xnn_f32_f16_vcvt_ukernel__sse41_x8, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800422 }
423 }
424#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
425
426
427#if XNN_ARCH_X86 || XNN_ARCH_X86_64
428 TEST(F32_F16_VCVT__SSE41_X16, batch_eq_16) {
429 TEST_REQUIRES_X86_SSE41;
430 VCvtMicrokernelTester()
431 .batch_size(16)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800432 .Test(xnn_f32_f16_vcvt_ukernel__sse41_x16, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800433 }
434
435 TEST(F32_F16_VCVT__SSE41_X16, batch_div_16) {
436 TEST_REQUIRES_X86_SSE41;
437 for (size_t batch_size = 32; batch_size < 160; batch_size += 16) {
438 VCvtMicrokernelTester()
439 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800440 .Test(xnn_f32_f16_vcvt_ukernel__sse41_x16, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800441 }
442 }
443
444 TEST(F32_F16_VCVT__SSE41_X16, batch_lt_16) {
445 TEST_REQUIRES_X86_SSE41;
446 for (size_t batch_size = 1; batch_size < 16; batch_size++) {
447 VCvtMicrokernelTester()
448 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800449 .Test(xnn_f32_f16_vcvt_ukernel__sse41_x16, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800450 }
451 }
452
453 TEST(F32_F16_VCVT__SSE41_X16, batch_gt_16) {
454 TEST_REQUIRES_X86_SSE41;
455 for (size_t batch_size = 17; batch_size < 32; batch_size++) {
456 VCvtMicrokernelTester()
457 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800458 .Test(xnn_f32_f16_vcvt_ukernel__sse41_x16, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800459 }
460 }
461#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
462
463
464#if XNN_ARCH_X86 || XNN_ARCH_X86_64
465 TEST(F32_F16_VCVT__SSE41_X24, batch_eq_24) {
466 TEST_REQUIRES_X86_SSE41;
467 VCvtMicrokernelTester()
468 .batch_size(24)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800469 .Test(xnn_f32_f16_vcvt_ukernel__sse41_x24, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800470 }
471
472 TEST(F32_F16_VCVT__SSE41_X24, batch_div_24) {
473 TEST_REQUIRES_X86_SSE41;
474 for (size_t batch_size = 48; batch_size < 240; batch_size += 24) {
475 VCvtMicrokernelTester()
476 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800477 .Test(xnn_f32_f16_vcvt_ukernel__sse41_x24, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800478 }
479 }
480
481 TEST(F32_F16_VCVT__SSE41_X24, batch_lt_24) {
482 TEST_REQUIRES_X86_SSE41;
483 for (size_t batch_size = 1; batch_size < 24; batch_size++) {
484 VCvtMicrokernelTester()
485 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800486 .Test(xnn_f32_f16_vcvt_ukernel__sse41_x24, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800487 }
488 }
489
490 TEST(F32_F16_VCVT__SSE41_X24, batch_gt_24) {
491 TEST_REQUIRES_X86_SSE41;
492 for (size_t batch_size = 25; batch_size < 48; batch_size++) {
493 VCvtMicrokernelTester()
494 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800495 .Test(xnn_f32_f16_vcvt_ukernel__sse41_x24, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800496 }
497 }
498#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
499
500
501#if XNN_ARCH_X86 || XNN_ARCH_X86_64
502 TEST(F32_F16_VCVT__SSE41_X32, batch_eq_32) {
503 TEST_REQUIRES_X86_SSE41;
504 VCvtMicrokernelTester()
505 .batch_size(32)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800506 .Test(xnn_f32_f16_vcvt_ukernel__sse41_x32, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800507 }
508
509 TEST(F32_F16_VCVT__SSE41_X32, batch_div_32) {
510 TEST_REQUIRES_X86_SSE41;
511 for (size_t batch_size = 64; batch_size < 320; batch_size += 32) {
512 VCvtMicrokernelTester()
513 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800514 .Test(xnn_f32_f16_vcvt_ukernel__sse41_x32, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800515 }
516 }
517
518 TEST(F32_F16_VCVT__SSE41_X32, batch_lt_32) {
519 TEST_REQUIRES_X86_SSE41;
520 for (size_t batch_size = 1; batch_size < 32; batch_size++) {
521 VCvtMicrokernelTester()
522 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800523 .Test(xnn_f32_f16_vcvt_ukernel__sse41_x32, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800524 }
525 }
526
527 TEST(F32_F16_VCVT__SSE41_X32, batch_gt_32) {
528 TEST_REQUIRES_X86_SSE41;
529 for (size_t batch_size = 33; batch_size < 64; batch_size++) {
530 VCvtMicrokernelTester()
531 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800532 .Test(xnn_f32_f16_vcvt_ukernel__sse41_x32, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800533 }
534 }
535#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
536
537
538#if XNN_ARCH_X86 || XNN_ARCH_X86_64
539 TEST(F32_F16_VCVT__AVX_X8, batch_eq_8) {
540 TEST_REQUIRES_X86_AVX;
541 VCvtMicrokernelTester()
542 .batch_size(8)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800543 .Test(xnn_f32_f16_vcvt_ukernel__avx_x8, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800544 }
545
546 TEST(F32_F16_VCVT__AVX_X8, batch_div_8) {
547 TEST_REQUIRES_X86_AVX;
548 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
549 VCvtMicrokernelTester()
550 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800551 .Test(xnn_f32_f16_vcvt_ukernel__avx_x8, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800552 }
553 }
554
555 TEST(F32_F16_VCVT__AVX_X8, batch_lt_8) {
556 TEST_REQUIRES_X86_AVX;
557 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
558 VCvtMicrokernelTester()
559 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800560 .Test(xnn_f32_f16_vcvt_ukernel__avx_x8, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800561 }
562 }
563
564 TEST(F32_F16_VCVT__AVX_X8, batch_gt_8) {
565 TEST_REQUIRES_X86_AVX;
566 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
567 VCvtMicrokernelTester()
568 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800569 .Test(xnn_f32_f16_vcvt_ukernel__avx_x8, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800570 }
571 }
572#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
573
574
575#if XNN_ARCH_X86 || XNN_ARCH_X86_64
576 TEST(F32_F16_VCVT__AVX_X16, batch_eq_16) {
577 TEST_REQUIRES_X86_AVX;
578 VCvtMicrokernelTester()
579 .batch_size(16)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800580 .Test(xnn_f32_f16_vcvt_ukernel__avx_x16, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800581 }
582
583 TEST(F32_F16_VCVT__AVX_X16, batch_div_16) {
584 TEST_REQUIRES_X86_AVX;
585 for (size_t batch_size = 32; batch_size < 160; batch_size += 16) {
586 VCvtMicrokernelTester()
587 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800588 .Test(xnn_f32_f16_vcvt_ukernel__avx_x16, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800589 }
590 }
591
592 TEST(F32_F16_VCVT__AVX_X16, batch_lt_16) {
593 TEST_REQUIRES_X86_AVX;
594 for (size_t batch_size = 1; batch_size < 16; batch_size++) {
595 VCvtMicrokernelTester()
596 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800597 .Test(xnn_f32_f16_vcvt_ukernel__avx_x16, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800598 }
599 }
600
601 TEST(F32_F16_VCVT__AVX_X16, batch_gt_16) {
602 TEST_REQUIRES_X86_AVX;
603 for (size_t batch_size = 17; batch_size < 32; batch_size++) {
604 VCvtMicrokernelTester()
605 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800606 .Test(xnn_f32_f16_vcvt_ukernel__avx_x16, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800607 }
608 }
609#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
610
611
612#if XNN_ARCH_X86 || XNN_ARCH_X86_64
613 TEST(F32_F16_VCVT__AVX_X24, batch_eq_24) {
614 TEST_REQUIRES_X86_AVX;
615 VCvtMicrokernelTester()
616 .batch_size(24)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800617 .Test(xnn_f32_f16_vcvt_ukernel__avx_x24, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800618 }
619
620 TEST(F32_F16_VCVT__AVX_X24, batch_div_24) {
621 TEST_REQUIRES_X86_AVX;
622 for (size_t batch_size = 48; batch_size < 240; batch_size += 24) {
623 VCvtMicrokernelTester()
624 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800625 .Test(xnn_f32_f16_vcvt_ukernel__avx_x24, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800626 }
627 }
628
629 TEST(F32_F16_VCVT__AVX_X24, batch_lt_24) {
630 TEST_REQUIRES_X86_AVX;
631 for (size_t batch_size = 1; batch_size < 24; batch_size++) {
632 VCvtMicrokernelTester()
633 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800634 .Test(xnn_f32_f16_vcvt_ukernel__avx_x24, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800635 }
636 }
637
638 TEST(F32_F16_VCVT__AVX_X24, batch_gt_24) {
639 TEST_REQUIRES_X86_AVX;
640 for (size_t batch_size = 25; batch_size < 48; batch_size++) {
641 VCvtMicrokernelTester()
642 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800643 .Test(xnn_f32_f16_vcvt_ukernel__avx_x24, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800644 }
645 }
646#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
647
648
649#if XNN_ARCH_X86 || XNN_ARCH_X86_64
650 TEST(F32_F16_VCVT__AVX_X32, batch_eq_32) {
651 TEST_REQUIRES_X86_AVX;
652 VCvtMicrokernelTester()
653 .batch_size(32)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800654 .Test(xnn_f32_f16_vcvt_ukernel__avx_x32, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800655 }
656
657 TEST(F32_F16_VCVT__AVX_X32, batch_div_32) {
658 TEST_REQUIRES_X86_AVX;
659 for (size_t batch_size = 64; batch_size < 320; batch_size += 32) {
660 VCvtMicrokernelTester()
661 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800662 .Test(xnn_f32_f16_vcvt_ukernel__avx_x32, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800663 }
664 }
665
666 TEST(F32_F16_VCVT__AVX_X32, batch_lt_32) {
667 TEST_REQUIRES_X86_AVX;
668 for (size_t batch_size = 1; batch_size < 32; batch_size++) {
669 VCvtMicrokernelTester()
670 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800671 .Test(xnn_f32_f16_vcvt_ukernel__avx_x32, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800672 }
673 }
674
675 TEST(F32_F16_VCVT__AVX_X32, batch_gt_32) {
676 TEST_REQUIRES_X86_AVX;
677 for (size_t batch_size = 33; batch_size < 64; batch_size++) {
678 VCvtMicrokernelTester()
679 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800680 .Test(xnn_f32_f16_vcvt_ukernel__avx_x32, xnn_init_f32_f16_cvt_sse2_params);
Marat Dukhaneb844232021-11-08 23:07:53 -0800681 }
682 }
683#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
684
685
686#if XNN_ARCH_X86 || XNN_ARCH_X86_64
Marat Dukhand77f77d2021-10-24 15:39:59 -0700687 TEST(F32_F16_VCVT__F16C_X8, batch_eq_8) {
688 TEST_REQUIRES_X86_F16C;
689 VCvtMicrokernelTester()
690 .batch_size(8)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800691 .Test(xnn_f32_f16_vcvt_ukernel__f16c_x8, xnn_init_f32_f16_cvt_f16c_params);
Marat Dukhand77f77d2021-10-24 15:39:59 -0700692 }
693
694 TEST(F32_F16_VCVT__F16C_X8, batch_div_8) {
695 TEST_REQUIRES_X86_F16C;
696 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
697 VCvtMicrokernelTester()
698 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800699 .Test(xnn_f32_f16_vcvt_ukernel__f16c_x8, xnn_init_f32_f16_cvt_f16c_params);
Marat Dukhand77f77d2021-10-24 15:39:59 -0700700 }
701 }
702
703 TEST(F32_F16_VCVT__F16C_X8, batch_lt_8) {
704 TEST_REQUIRES_X86_F16C;
705 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
706 VCvtMicrokernelTester()
707 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800708 .Test(xnn_f32_f16_vcvt_ukernel__f16c_x8, xnn_init_f32_f16_cvt_f16c_params);
Marat Dukhand77f77d2021-10-24 15:39:59 -0700709 }
710 }
711
712 TEST(F32_F16_VCVT__F16C_X8, batch_gt_8) {
713 TEST_REQUIRES_X86_F16C;
714 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
715 VCvtMicrokernelTester()
716 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800717 .Test(xnn_f32_f16_vcvt_ukernel__f16c_x8, xnn_init_f32_f16_cvt_f16c_params);
Marat Dukhand77f77d2021-10-24 15:39:59 -0700718 }
719 }
720#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
721
722
723#if XNN_ARCH_X86 || XNN_ARCH_X86_64
724 TEST(F32_F16_VCVT__F16C_X16, batch_eq_16) {
725 TEST_REQUIRES_X86_F16C;
726 VCvtMicrokernelTester()
727 .batch_size(16)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800728 .Test(xnn_f32_f16_vcvt_ukernel__f16c_x16, xnn_init_f32_f16_cvt_f16c_params);
Marat Dukhand77f77d2021-10-24 15:39:59 -0700729 }
730
731 TEST(F32_F16_VCVT__F16C_X16, batch_div_16) {
732 TEST_REQUIRES_X86_F16C;
733 for (size_t batch_size = 32; batch_size < 160; batch_size += 16) {
734 VCvtMicrokernelTester()
735 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800736 .Test(xnn_f32_f16_vcvt_ukernel__f16c_x16, xnn_init_f32_f16_cvt_f16c_params);
Marat Dukhand77f77d2021-10-24 15:39:59 -0700737 }
738 }
739
740 TEST(F32_F16_VCVT__F16C_X16, batch_lt_16) {
741 TEST_REQUIRES_X86_F16C;
742 for (size_t batch_size = 1; batch_size < 16; batch_size++) {
743 VCvtMicrokernelTester()
744 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800745 .Test(xnn_f32_f16_vcvt_ukernel__f16c_x16, xnn_init_f32_f16_cvt_f16c_params);
Marat Dukhand77f77d2021-10-24 15:39:59 -0700746 }
747 }
748
749 TEST(F32_F16_VCVT__F16C_X16, batch_gt_16) {
750 TEST_REQUIRES_X86_F16C;
751 for (size_t batch_size = 17; batch_size < 32; batch_size++) {
752 VCvtMicrokernelTester()
753 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800754 .Test(xnn_f32_f16_vcvt_ukernel__f16c_x16, xnn_init_f32_f16_cvt_f16c_params);
Marat Dukhand77f77d2021-10-24 15:39:59 -0700755 }
756 }
757#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
758
759
760#if XNN_ARCH_X86 || XNN_ARCH_X86_64
761 TEST(F32_F16_VCVT__AVX512SKX_X16, batch_eq_16) {
762 TEST_REQUIRES_X86_AVX512SKX;
763 VCvtMicrokernelTester()
764 .batch_size(16)
765 .Test(xnn_f32_f16_vcvt_ukernel__avx512skx_x16);
766 }
767
768 TEST(F32_F16_VCVT__AVX512SKX_X16, batch_div_16) {
769 TEST_REQUIRES_X86_AVX512SKX;
770 for (size_t batch_size = 32; batch_size < 160; batch_size += 16) {
771 VCvtMicrokernelTester()
772 .batch_size(batch_size)
773 .Test(xnn_f32_f16_vcvt_ukernel__avx512skx_x16);
774 }
775 }
776
777 TEST(F32_F16_VCVT__AVX512SKX_X16, batch_lt_16) {
778 TEST_REQUIRES_X86_AVX512SKX;
779 for (size_t batch_size = 1; batch_size < 16; batch_size++) {
780 VCvtMicrokernelTester()
781 .batch_size(batch_size)
782 .Test(xnn_f32_f16_vcvt_ukernel__avx512skx_x16);
783 }
784 }
785
786 TEST(F32_F16_VCVT__AVX512SKX_X16, batch_gt_16) {
787 TEST_REQUIRES_X86_AVX512SKX;
788 for (size_t batch_size = 17; batch_size < 32; batch_size++) {
789 VCvtMicrokernelTester()
790 .batch_size(batch_size)
791 .Test(xnn_f32_f16_vcvt_ukernel__avx512skx_x16);
792 }
793 }
794#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
795
796
797#if XNN_ARCH_X86 || XNN_ARCH_X86_64
798 TEST(F32_F16_VCVT__AVX512SKX_X32, batch_eq_32) {
799 TEST_REQUIRES_X86_AVX512SKX;
800 VCvtMicrokernelTester()
801 .batch_size(32)
802 .Test(xnn_f32_f16_vcvt_ukernel__avx512skx_x32);
803 }
804
805 TEST(F32_F16_VCVT__AVX512SKX_X32, batch_div_32) {
806 TEST_REQUIRES_X86_AVX512SKX;
807 for (size_t batch_size = 64; batch_size < 320; batch_size += 32) {
808 VCvtMicrokernelTester()
809 .batch_size(batch_size)
810 .Test(xnn_f32_f16_vcvt_ukernel__avx512skx_x32);
811 }
812 }
813
814 TEST(F32_F16_VCVT__AVX512SKX_X32, batch_lt_32) {
815 TEST_REQUIRES_X86_AVX512SKX;
816 for (size_t batch_size = 1; batch_size < 32; batch_size++) {
817 VCvtMicrokernelTester()
818 .batch_size(batch_size)
819 .Test(xnn_f32_f16_vcvt_ukernel__avx512skx_x32);
820 }
821 }
822
823 TEST(F32_F16_VCVT__AVX512SKX_X32, batch_gt_32) {
824 TEST_REQUIRES_X86_AVX512SKX;
825 for (size_t batch_size = 33; batch_size < 64; batch_size++) {
826 VCvtMicrokernelTester()
827 .batch_size(batch_size)
828 .Test(xnn_f32_f16_vcvt_ukernel__avx512skx_x32);
829 }
830 }
831#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
Marat Dukhan22e31c82021-11-09 00:00:28 -0800832
833
Marat Dukhan4c617792021-12-21 15:47:58 -0800834#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan22e31c82021-11-09 00:00:28 -0800835 TEST(F32_F16_VCVT__WASMSIMD_X8, batch_eq_8) {
836 VCvtMicrokernelTester()
837 .batch_size(8)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800838 .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x8, xnn_init_f32_f16_cvt_wasmsimd_params);
Marat Dukhan22e31c82021-11-09 00:00:28 -0800839 }
840
841 TEST(F32_F16_VCVT__WASMSIMD_X8, batch_div_8) {
842 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
843 VCvtMicrokernelTester()
844 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800845 .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x8, xnn_init_f32_f16_cvt_wasmsimd_params);
Marat Dukhan22e31c82021-11-09 00:00:28 -0800846 }
847 }
848
849 TEST(F32_F16_VCVT__WASMSIMD_X8, batch_lt_8) {
850 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
851 VCvtMicrokernelTester()
852 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800853 .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x8, xnn_init_f32_f16_cvt_wasmsimd_params);
Marat Dukhan22e31c82021-11-09 00:00:28 -0800854 }
855 }
856
857 TEST(F32_F16_VCVT__WASMSIMD_X8, batch_gt_8) {
858 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
859 VCvtMicrokernelTester()
860 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800861 .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x8, xnn_init_f32_f16_cvt_wasmsimd_params);
Marat Dukhan22e31c82021-11-09 00:00:28 -0800862 }
863 }
Marat Dukhan4c617792021-12-21 15:47:58 -0800864#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan22e31c82021-11-09 00:00:28 -0800865
866
Marat Dukhan4c617792021-12-21 15:47:58 -0800867#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan22e31c82021-11-09 00:00:28 -0800868 TEST(F32_F16_VCVT__WASMSIMD_X16, batch_eq_16) {
869 VCvtMicrokernelTester()
870 .batch_size(16)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800871 .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x16, xnn_init_f32_f16_cvt_wasmsimd_params);
Marat Dukhan22e31c82021-11-09 00:00:28 -0800872 }
873
874 TEST(F32_F16_VCVT__WASMSIMD_X16, batch_div_16) {
875 for (size_t batch_size = 32; batch_size < 160; batch_size += 16) {
876 VCvtMicrokernelTester()
877 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800878 .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x16, xnn_init_f32_f16_cvt_wasmsimd_params);
Marat Dukhan22e31c82021-11-09 00:00:28 -0800879 }
880 }
881
882 TEST(F32_F16_VCVT__WASMSIMD_X16, batch_lt_16) {
883 for (size_t batch_size = 1; batch_size < 16; batch_size++) {
884 VCvtMicrokernelTester()
885 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800886 .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x16, xnn_init_f32_f16_cvt_wasmsimd_params);
Marat Dukhan22e31c82021-11-09 00:00:28 -0800887 }
888 }
889
890 TEST(F32_F16_VCVT__WASMSIMD_X16, batch_gt_16) {
891 for (size_t batch_size = 17; batch_size < 32; batch_size++) {
892 VCvtMicrokernelTester()
893 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800894 .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x16, xnn_init_f32_f16_cvt_wasmsimd_params);
Marat Dukhan22e31c82021-11-09 00:00:28 -0800895 }
896 }
Marat Dukhan4c617792021-12-21 15:47:58 -0800897#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan22e31c82021-11-09 00:00:28 -0800898
899
Marat Dukhan4c617792021-12-21 15:47:58 -0800900#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan22e31c82021-11-09 00:00:28 -0800901 TEST(F32_F16_VCVT__WASMSIMD_X24, batch_eq_24) {
902 VCvtMicrokernelTester()
903 .batch_size(24)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800904 .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x24, xnn_init_f32_f16_cvt_wasmsimd_params);
Marat Dukhan22e31c82021-11-09 00:00:28 -0800905 }
906
907 TEST(F32_F16_VCVT__WASMSIMD_X24, batch_div_24) {
908 for (size_t batch_size = 48; batch_size < 240; batch_size += 24) {
909 VCvtMicrokernelTester()
910 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800911 .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x24, xnn_init_f32_f16_cvt_wasmsimd_params);
Marat Dukhan22e31c82021-11-09 00:00:28 -0800912 }
913 }
914
915 TEST(F32_F16_VCVT__WASMSIMD_X24, batch_lt_24) {
916 for (size_t batch_size = 1; batch_size < 24; batch_size++) {
917 VCvtMicrokernelTester()
918 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800919 .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x24, xnn_init_f32_f16_cvt_wasmsimd_params);
Marat Dukhan22e31c82021-11-09 00:00:28 -0800920 }
921 }
922
923 TEST(F32_F16_VCVT__WASMSIMD_X24, batch_gt_24) {
924 for (size_t batch_size = 25; batch_size < 48; batch_size++) {
925 VCvtMicrokernelTester()
926 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800927 .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x24, xnn_init_f32_f16_cvt_wasmsimd_params);
Marat Dukhan22e31c82021-11-09 00:00:28 -0800928 }
929 }
Marat Dukhan4c617792021-12-21 15:47:58 -0800930#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan22e31c82021-11-09 00:00:28 -0800931
932
Marat Dukhan4c617792021-12-21 15:47:58 -0800933#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan22e31c82021-11-09 00:00:28 -0800934 TEST(F32_F16_VCVT__WASMSIMD_X32, batch_eq_32) {
935 VCvtMicrokernelTester()
936 .batch_size(32)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800937 .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x32, xnn_init_f32_f16_cvt_wasmsimd_params);
Marat Dukhan22e31c82021-11-09 00:00:28 -0800938 }
939
940 TEST(F32_F16_VCVT__WASMSIMD_X32, batch_div_32) {
941 for (size_t batch_size = 64; batch_size < 320; batch_size += 32) {
942 VCvtMicrokernelTester()
943 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800944 .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x32, xnn_init_f32_f16_cvt_wasmsimd_params);
Marat Dukhan22e31c82021-11-09 00:00:28 -0800945 }
946 }
947
948 TEST(F32_F16_VCVT__WASMSIMD_X32, batch_lt_32) {
949 for (size_t batch_size = 1; batch_size < 32; batch_size++) {
950 VCvtMicrokernelTester()
951 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800952 .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x32, xnn_init_f32_f16_cvt_wasmsimd_params);
Marat Dukhan22e31c82021-11-09 00:00:28 -0800953 }
954 }
955
956 TEST(F32_F16_VCVT__WASMSIMD_X32, batch_gt_32) {
957 for (size_t batch_size = 33; batch_size < 64; batch_size++) {
958 VCvtMicrokernelTester()
959 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800960 .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x32, xnn_init_f32_f16_cvt_wasmsimd_params);
Marat Dukhan22e31c82021-11-09 00:00:28 -0800961 }
962 }
Marat Dukhan4c617792021-12-21 15:47:58 -0800963#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan1fe89952021-11-10 01:27:15 -0800964
965
966TEST(F32_F16_VCVT__SCALAR_BITCAST_X1, batch_eq_1) {
967 VCvtMicrokernelTester()
968 .batch_size(1)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800969 .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x1, xnn_init_f32_f16_cvt_scalar_bitcast_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -0800970}
971
972TEST(F32_F16_VCVT__SCALAR_BITCAST_X1, batch_gt_1) {
973 for (size_t batch_size = 2; batch_size < 10; batch_size++) {
974 VCvtMicrokernelTester()
975 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800976 .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x1, xnn_init_f32_f16_cvt_scalar_bitcast_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -0800977 }
978}
979
Marat Dukhan4bdc9f52021-12-09 15:36:06 -0800980
Marat Dukhan1fe89952021-11-10 01:27:15 -0800981TEST(F32_F16_VCVT__SCALAR_BITCAST_X2, batch_eq_2) {
982 VCvtMicrokernelTester()
983 .batch_size(2)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800984 .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x2, xnn_init_f32_f16_cvt_scalar_bitcast_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -0800985}
986
987TEST(F32_F16_VCVT__SCALAR_BITCAST_X2, batch_div_2) {
988 for (size_t batch_size = 4; batch_size < 20; batch_size += 2) {
989 VCvtMicrokernelTester()
990 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800991 .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x2, xnn_init_f32_f16_cvt_scalar_bitcast_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -0800992 }
993}
994
995TEST(F32_F16_VCVT__SCALAR_BITCAST_X2, batch_lt_2) {
996 for (size_t batch_size = 1; batch_size < 2; batch_size++) {
997 VCvtMicrokernelTester()
998 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800999 .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x2, xnn_init_f32_f16_cvt_scalar_bitcast_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001000 }
1001}
1002
1003TEST(F32_F16_VCVT__SCALAR_BITCAST_X2, batch_gt_2) {
1004 for (size_t batch_size = 3; batch_size < 4; batch_size++) {
1005 VCvtMicrokernelTester()
1006 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -08001007 .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x2, xnn_init_f32_f16_cvt_scalar_bitcast_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001008 }
1009}
1010
Marat Dukhan4bdc9f52021-12-09 15:36:06 -08001011
Marat Dukhan1fe89952021-11-10 01:27:15 -08001012TEST(F32_F16_VCVT__SCALAR_BITCAST_X3, batch_eq_3) {
1013 VCvtMicrokernelTester()
1014 .batch_size(3)
Marat Dukhanb7c1b712021-12-30 07:23:57 -08001015 .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x3, xnn_init_f32_f16_cvt_scalar_bitcast_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001016}
1017
1018TEST(F32_F16_VCVT__SCALAR_BITCAST_X3, batch_div_3) {
1019 for (size_t batch_size = 6; batch_size < 30; batch_size += 3) {
1020 VCvtMicrokernelTester()
1021 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -08001022 .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x3, xnn_init_f32_f16_cvt_scalar_bitcast_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001023 }
1024}
1025
1026TEST(F32_F16_VCVT__SCALAR_BITCAST_X3, batch_lt_3) {
1027 for (size_t batch_size = 1; batch_size < 3; batch_size++) {
1028 VCvtMicrokernelTester()
1029 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -08001030 .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x3, xnn_init_f32_f16_cvt_scalar_bitcast_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001031 }
1032}
1033
1034TEST(F32_F16_VCVT__SCALAR_BITCAST_X3, batch_gt_3) {
1035 for (size_t batch_size = 4; batch_size < 6; batch_size++) {
1036 VCvtMicrokernelTester()
1037 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -08001038 .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x3, xnn_init_f32_f16_cvt_scalar_bitcast_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001039 }
1040}
1041
Marat Dukhan4bdc9f52021-12-09 15:36:06 -08001042
Marat Dukhan1fe89952021-11-10 01:27:15 -08001043TEST(F32_F16_VCVT__SCALAR_BITCAST_X4, batch_eq_4) {
1044 VCvtMicrokernelTester()
1045 .batch_size(4)
Marat Dukhanb7c1b712021-12-30 07:23:57 -08001046 .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x4, xnn_init_f32_f16_cvt_scalar_bitcast_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001047}
1048
1049TEST(F32_F16_VCVT__SCALAR_BITCAST_X4, batch_div_4) {
1050 for (size_t batch_size = 8; batch_size < 40; batch_size += 4) {
1051 VCvtMicrokernelTester()
1052 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -08001053 .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x4, xnn_init_f32_f16_cvt_scalar_bitcast_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001054 }
1055}
1056
1057TEST(F32_F16_VCVT__SCALAR_BITCAST_X4, batch_lt_4) {
1058 for (size_t batch_size = 1; batch_size < 4; batch_size++) {
1059 VCvtMicrokernelTester()
1060 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -08001061 .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x4, xnn_init_f32_f16_cvt_scalar_bitcast_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001062 }
1063}
1064
1065TEST(F32_F16_VCVT__SCALAR_BITCAST_X4, batch_gt_4) {
1066 for (size_t batch_size = 5; batch_size < 8; batch_size++) {
1067 VCvtMicrokernelTester()
1068 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -08001069 .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x4, xnn_init_f32_f16_cvt_scalar_bitcast_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001070 }
1071}
1072
Marat Dukhan4bdc9f52021-12-09 15:36:06 -08001073
Marat Dukhan1fe89952021-11-10 01:27:15 -08001074TEST(F32_F16_VCVT__SCALAR_FABSF_X1, batch_eq_1) {
1075 VCvtMicrokernelTester()
1076 .batch_size(1)
Marat Dukhanb7c1b712021-12-30 07:23:57 -08001077 .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x1, xnn_init_f32_f16_cvt_scalar_fabsf_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001078}
1079
1080TEST(F32_F16_VCVT__SCALAR_FABSF_X1, batch_gt_1) {
1081 for (size_t batch_size = 2; batch_size < 10; batch_size++) {
1082 VCvtMicrokernelTester()
1083 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -08001084 .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x1, xnn_init_f32_f16_cvt_scalar_fabsf_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001085 }
1086}
1087
Marat Dukhan4bdc9f52021-12-09 15:36:06 -08001088
Marat Dukhan1fe89952021-11-10 01:27:15 -08001089TEST(F32_F16_VCVT__SCALAR_FABSF_X2, batch_eq_2) {
1090 VCvtMicrokernelTester()
1091 .batch_size(2)
Marat Dukhanb7c1b712021-12-30 07:23:57 -08001092 .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x2, xnn_init_f32_f16_cvt_scalar_fabsf_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001093}
1094
1095TEST(F32_F16_VCVT__SCALAR_FABSF_X2, batch_div_2) {
1096 for (size_t batch_size = 4; batch_size < 20; batch_size += 2) {
1097 VCvtMicrokernelTester()
1098 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -08001099 .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x2, xnn_init_f32_f16_cvt_scalar_fabsf_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001100 }
1101}
1102
1103TEST(F32_F16_VCVT__SCALAR_FABSF_X2, batch_lt_2) {
1104 for (size_t batch_size = 1; batch_size < 2; batch_size++) {
1105 VCvtMicrokernelTester()
1106 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -08001107 .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x2, xnn_init_f32_f16_cvt_scalar_fabsf_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001108 }
1109}
1110
1111TEST(F32_F16_VCVT__SCALAR_FABSF_X2, batch_gt_2) {
1112 for (size_t batch_size = 3; batch_size < 4; batch_size++) {
1113 VCvtMicrokernelTester()
1114 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -08001115 .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x2, xnn_init_f32_f16_cvt_scalar_fabsf_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001116 }
1117}
1118
Marat Dukhan4bdc9f52021-12-09 15:36:06 -08001119
Marat Dukhan1fe89952021-11-10 01:27:15 -08001120TEST(F32_F16_VCVT__SCALAR_FABSF_X3, batch_eq_3) {
1121 VCvtMicrokernelTester()
1122 .batch_size(3)
Marat Dukhanb7c1b712021-12-30 07:23:57 -08001123 .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x3, xnn_init_f32_f16_cvt_scalar_fabsf_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001124}
1125
1126TEST(F32_F16_VCVT__SCALAR_FABSF_X3, batch_div_3) {
1127 for (size_t batch_size = 6; batch_size < 30; batch_size += 3) {
1128 VCvtMicrokernelTester()
1129 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -08001130 .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x3, xnn_init_f32_f16_cvt_scalar_fabsf_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001131 }
1132}
1133
1134TEST(F32_F16_VCVT__SCALAR_FABSF_X3, batch_lt_3) {
1135 for (size_t batch_size = 1; batch_size < 3; batch_size++) {
1136 VCvtMicrokernelTester()
1137 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -08001138 .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x3, xnn_init_f32_f16_cvt_scalar_fabsf_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001139 }
1140}
1141
1142TEST(F32_F16_VCVT__SCALAR_FABSF_X3, batch_gt_3) {
1143 for (size_t batch_size = 4; batch_size < 6; batch_size++) {
1144 VCvtMicrokernelTester()
1145 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -08001146 .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x3, xnn_init_f32_f16_cvt_scalar_fabsf_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001147 }
1148}
1149
Marat Dukhan4bdc9f52021-12-09 15:36:06 -08001150
Marat Dukhan1fe89952021-11-10 01:27:15 -08001151TEST(F32_F16_VCVT__SCALAR_FABSF_X4, batch_eq_4) {
1152 VCvtMicrokernelTester()
1153 .batch_size(4)
Marat Dukhanb7c1b712021-12-30 07:23:57 -08001154 .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x4, xnn_init_f32_f16_cvt_scalar_fabsf_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001155}
1156
1157TEST(F32_F16_VCVT__SCALAR_FABSF_X4, batch_div_4) {
1158 for (size_t batch_size = 8; batch_size < 40; batch_size += 4) {
1159 VCvtMicrokernelTester()
1160 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -08001161 .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x4, xnn_init_f32_f16_cvt_scalar_fabsf_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001162 }
1163}
1164
1165TEST(F32_F16_VCVT__SCALAR_FABSF_X4, batch_lt_4) {
1166 for (size_t batch_size = 1; batch_size < 4; batch_size++) {
1167 VCvtMicrokernelTester()
1168 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -08001169 .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x4, xnn_init_f32_f16_cvt_scalar_fabsf_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001170 }
1171}
1172
1173TEST(F32_F16_VCVT__SCALAR_FABSF_X4, batch_gt_4) {
1174 for (size_t batch_size = 5; batch_size < 8; batch_size++) {
1175 VCvtMicrokernelTester()
1176 .batch_size(batch_size)
Marat Dukhanb7c1b712021-12-30 07:23:57 -08001177 .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x4, xnn_init_f32_f16_cvt_scalar_fabsf_params);
Marat Dukhan1fe89952021-11-10 01:27:15 -08001178 }
Marat Dukhan4bdc9f52021-12-09 15:36:06 -08001179}