blob: 2d01c3826d80c261cd9ff444a7bc72e2fc5cce7c [file] [log] [blame]
Marat Dukhan329da642019-11-19 21:44:39 -08001// Copyright (c) Facebook, Inc. and its affiliates.
2// All rights reserved.
3//
XNNPACK Teamb455b122019-09-27 18:10:33 -07004// Copyright 2019 Google LLC
5//
6// This source code is licensed under the BSD-style license found in the
7// LICENSE file in the root directory of this source tree.
Marat Dukhan329da642019-11-19 21:44:39 -08008//
9// Auto-generated file. Do not edit!
Marat Dukhan99936602020-04-11 16:47:01 -070010// Specification: test/f32-maxpool-minmax.yaml
Marat Dukhan329da642019-11-19 21:44:39 -080011// Generator: tools/generate-maxpool-test.py
12
XNNPACK Teamb455b122019-09-27 18:10:33 -070013
XNNPACK Teamb455b122019-09-27 18:10:33 -070014#include <gtest/gtest.h>
15
Marat Dukhan1dadbf72019-10-01 10:46:20 -070016#include <xnnpack/common.h>
XNNPACK Teamb455b122019-09-27 18:10:33 -070017#include <xnnpack/isa-checks.h>
XNNPACK Teamb455b122019-09-27 18:10:33 -070018
Marat Dukhan1dadbf72019-10-01 10:46:20 -070019#include <xnnpack/maxpool.h>
XNNPACK Teamb455b122019-09-27 18:10:33 -070020#include "maxpool-microkernel-tester.h"
21
22
Marat Dukhan1dadbf72019-10-01 10:46:20 -070023#if XNN_ARCH_X86 || XNN_ARCH_X86_64
Marat Dukhan99936602020-04-11 16:47:01 -070024 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_eq_4_unipass_fulltile) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070025 TEST_REQUIRES_X86_SSE;
Marat Dukhan329da642019-11-19 21:44:39 -080026 MaxPoolMicrokernelTester()
27 .pooling_elements(9)
28 .pooling_tile(9, 8)
29 .channels(4)
Marat Dukhan99936602020-04-11 16:47:01 -070030 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -080031 }
32
Marat Dukhan99936602020-04-11 16:47:01 -070033 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_eq_4_unipass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -080034 TEST_REQUIRES_X86_SSE;
35 MaxPoolMicrokernelTester()
36 .pooling_elements(9)
37 .pooling_tile(9, 8)
38 .channels(4)
39 .input_offset(7)
Marat Dukhan99936602020-04-11 16:47:01 -070040 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -080041 }
42
Marat Dukhan99936602020-04-11 16:47:01 -070043 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_eq_4_unipass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -080044 TEST_REQUIRES_X86_SSE;
45 MaxPoolMicrokernelTester()
46 .pooling_elements(9)
47 .pooling_tile(9, 8)
48 .channels(4)
49 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -070050 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -080051 }
52
Marat Dukhan99936602020-04-11 16:47:01 -070053 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_eq_4_unipass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -080054 TEST_REQUIRES_X86_SSE;
55 MaxPoolMicrokernelTester()
56 .pooling_elements(9)
57 .pooling_tile(9, 8)
58 .channels(4)
59 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -070060 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -080061 }
62
Marat Dukhan99936602020-04-11 16:47:01 -070063 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_eq_4_unipass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -080064 TEST_REQUIRES_X86_SSE;
65 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
66 MaxPoolMicrokernelTester()
67 .pooling_elements(pooling_elements)
68 .pooling_tile(9, 8)
69 .channels(4)
Marat Dukhan99936602020-04-11 16:47:01 -070070 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
XNNPACK Teamb455b122019-09-27 18:10:33 -070071 }
72 }
73
Marat Dukhan99936602020-04-11 16:47:01 -070074 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_eq_4_unipass_subtile_with_input_offset) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070075 TEST_REQUIRES_X86_SSE;
Marat Dukhan329da642019-11-19 21:44:39 -080076 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
77 MaxPoolMicrokernelTester()
78 .pooling_elements(pooling_elements)
79 .pooling_tile(9, 8)
80 .channels(4)
81 .input_offset(7)
Marat Dukhan99936602020-04-11 16:47:01 -070082 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
XNNPACK Teamb455b122019-09-27 18:10:33 -070083 }
84 }
85
Marat Dukhan99936602020-04-11 16:47:01 -070086 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_div_4_unipass_fulltile) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070087 TEST_REQUIRES_X86_SSE;
Marat Dukhan329da642019-11-19 21:44:39 -080088 for (size_t channels = 8; channels < 32; channels += 4) {
89 MaxPoolMicrokernelTester()
90 .pooling_elements(9)
91 .pooling_tile(9, 8)
92 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -070093 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
XNNPACK Teamb455b122019-09-27 18:10:33 -070094 }
95 }
96
Marat Dukhan99936602020-04-11 16:47:01 -070097 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_div_4_unipass_fulltile_with_input_offset) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070098 TEST_REQUIRES_X86_SSE;
Marat Dukhan329da642019-11-19 21:44:39 -080099 for (size_t channels = 8; channels < 32; channels += 4) {
100 MaxPoolMicrokernelTester()
101 .pooling_elements(9)
102 .pooling_tile(9, 8)
103 .channels(channels)
104 .input_offset(37)
Marat Dukhan99936602020-04-11 16:47:01 -0700105 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700106 }
107 }
108
Marat Dukhan99936602020-04-11 16:47:01 -0700109 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_div_4_unipass_fulltile_with_qmin) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700110 TEST_REQUIRES_X86_SSE;
Marat Dukhan329da642019-11-19 21:44:39 -0800111 for (size_t channels = 8; channels < 32; channels += 4) {
112 MaxPoolMicrokernelTester()
113 .pooling_elements(9)
114 .pooling_tile(9, 8)
115 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700116 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700117 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800118 }
119 }
120
Marat Dukhan99936602020-04-11 16:47:01 -0700121 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_div_4_unipass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -0800122 TEST_REQUIRES_X86_SSE;
123 for (size_t channels = 8; channels < 32; channels += 4) {
124 MaxPoolMicrokernelTester()
125 .pooling_elements(9)
126 .pooling_tile(9, 8)
127 .channels(channels)
128 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700129 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800130 }
131 }
132
Marat Dukhan99936602020-04-11 16:47:01 -0700133 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_div_4_unipass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800134 TEST_REQUIRES_X86_SSE;
135 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
136 for (size_t channels = 8; channels < 32; channels += 4) {
137 MaxPoolMicrokernelTester()
138 .pooling_elements(pooling_elements)
139 .pooling_tile(9, 8)
140 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -0700141 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800142 }
143 }
144 }
145
Marat Dukhan99936602020-04-11 16:47:01 -0700146 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_div_4_unipass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800147 TEST_REQUIRES_X86_SSE;
148 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
149 for (size_t channels = 8; channels < 32; channels += 4) {
150 MaxPoolMicrokernelTester()
151 .pooling_elements(pooling_elements)
152 .pooling_tile(9, 8)
153 .channels(channels)
154 .input_offset(37)
Marat Dukhan99936602020-04-11 16:47:01 -0700155 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800156 }
157 }
158 }
159
Marat Dukhan99936602020-04-11 16:47:01 -0700160 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_lt_4_unipass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800161 TEST_REQUIRES_X86_SSE;
162 for (size_t channels = 1; channels < 4; channels++) {
163 MaxPoolMicrokernelTester()
164 .pooling_elements(9)
165 .pooling_tile(9, 8)
166 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -0700167 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800168 }
169 }
170
Marat Dukhan99936602020-04-11 16:47:01 -0700171 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_lt_4_unipass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800172 TEST_REQUIRES_X86_SSE;
173 for (size_t channels = 1; channels < 4; channels++) {
174 MaxPoolMicrokernelTester()
175 .pooling_elements(9)
176 .pooling_tile(9, 8)
177 .channels(channels)
178 .input_offset(5)
Marat Dukhan99936602020-04-11 16:47:01 -0700179 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800180 }
181 }
182
Marat Dukhan99936602020-04-11 16:47:01 -0700183 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_lt_4_unipass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -0800184 TEST_REQUIRES_X86_SSE;
185 for (size_t channels = 1; channels < 4; channels++) {
186 MaxPoolMicrokernelTester()
187 .pooling_elements(9)
188 .pooling_tile(9, 8)
189 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700190 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700191 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700192 }
193 }
194
Marat Dukhan99936602020-04-11 16:47:01 -0700195 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_lt_4_unipass_fulltile_with_qmax) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700196 TEST_REQUIRES_X86_SSE;
Marat Dukhan329da642019-11-19 21:44:39 -0800197 for (size_t channels = 1; channels < 4; channels++) {
198 MaxPoolMicrokernelTester()
199 .pooling_elements(9)
200 .pooling_tile(9, 8)
201 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700202 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700203 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800204 }
205 }
206
Marat Dukhan99936602020-04-11 16:47:01 -0700207 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_lt_4_unipass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800208 TEST_REQUIRES_X86_SSE;
209 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
210 for (size_t channels = 1; channels < 4; channels++) {
211 MaxPoolMicrokernelTester()
212 .pooling_elements(pooling_elements)
213 .pooling_tile(9, 8)
214 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -0700215 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800216 }
217 }
218 }
219
Marat Dukhan99936602020-04-11 16:47:01 -0700220 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_lt_4_unipass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800221 TEST_REQUIRES_X86_SSE;
222 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
223 for (size_t channels = 1; channels < 4; channels++) {
224 MaxPoolMicrokernelTester()
225 .pooling_elements(pooling_elements)
226 .pooling_tile(9, 8)
227 .channels(channels)
228 .input_offset(5)
Marat Dukhan99936602020-04-11 16:47:01 -0700229 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800230 }
231 }
232 }
233
Marat Dukhan99936602020-04-11 16:47:01 -0700234 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_gt_4_unipass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800235 TEST_REQUIRES_X86_SSE;
236 for (size_t channels = 5; channels < 8; channels++) {
237 MaxPoolMicrokernelTester()
238 .pooling_elements(9)
239 .pooling_tile(9, 8)
240 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -0700241 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800242 }
243 }
244
Marat Dukhan99936602020-04-11 16:47:01 -0700245 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_gt_4_unipass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800246 TEST_REQUIRES_X86_SSE;
247 for (size_t channels = 5; channels < 8; channels++) {
248 MaxPoolMicrokernelTester()
249 .pooling_elements(9)
250 .pooling_tile(9, 8)
251 .channels(channels)
252 .input_offset(11)
Marat Dukhan99936602020-04-11 16:47:01 -0700253 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800254 }
255 }
256
Marat Dukhan99936602020-04-11 16:47:01 -0700257 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_gt_4_unipass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -0800258 TEST_REQUIRES_X86_SSE;
259 for (size_t channels = 5; channels < 8; channels++) {
260 MaxPoolMicrokernelTester()
261 .pooling_elements(9)
262 .pooling_tile(9, 8)
263 .channels(channels)
264 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700265 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800266 }
267 }
268
Marat Dukhan99936602020-04-11 16:47:01 -0700269 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_gt_4_unipass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -0800270 TEST_REQUIRES_X86_SSE;
271 for (size_t channels = 5; channels < 8; channels++) {
272 MaxPoolMicrokernelTester()
273 .pooling_elements(9)
274 .pooling_tile(9, 8)
275 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700276 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700277 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700278 }
279 }
280
Marat Dukhan99936602020-04-11 16:47:01 -0700281 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_gt_4_unipass_subtile) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700282 TEST_REQUIRES_X86_SSE;
Marat Dukhan329da642019-11-19 21:44:39 -0800283 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
284 for (size_t channels = 5; channels < 8; channels++) {
285 MaxPoolMicrokernelTester()
286 .pooling_elements(pooling_elements)
287 .pooling_tile(9, 8)
288 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -0700289 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700290 }
291 }
292 }
293
Marat Dukhan99936602020-04-11 16:47:01 -0700294 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_gt_4_unipass_subtile_with_input_offset) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700295 TEST_REQUIRES_X86_SSE;
Marat Dukhan329da642019-11-19 21:44:39 -0800296 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
297 for (size_t channels = 5; channels < 8; channels++) {
298 MaxPoolMicrokernelTester()
299 .pooling_elements(pooling_elements)
300 .pooling_tile(9, 8)
301 .channels(channels)
302 .input_offset(11)
Marat Dukhan99936602020-04-11 16:47:01 -0700303 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800304 }
305 }
306 }
307
Marat Dukhan99936602020-04-11 16:47:01 -0700308 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_eq_4_twopass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800309 TEST_REQUIRES_X86_SSE;
310 MaxPoolMicrokernelTester()
311 .pooling_elements(17)
312 .pooling_tile(9, 8)
313 .channels(4)
Marat Dukhan99936602020-04-11 16:47:01 -0700314 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800315 }
316
Marat Dukhan99936602020-04-11 16:47:01 -0700317 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_eq_4_twopass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800318 TEST_REQUIRES_X86_SSE;
319 MaxPoolMicrokernelTester()
320 .pooling_elements(17)
321 .pooling_tile(9, 8)
322 .channels(4)
323 .input_offset(7)
Marat Dukhan99936602020-04-11 16:47:01 -0700324 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800325 }
326
Marat Dukhan99936602020-04-11 16:47:01 -0700327 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_eq_4_twopass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -0800328 TEST_REQUIRES_X86_SSE;
329 MaxPoolMicrokernelTester()
330 .pooling_elements(17)
331 .pooling_tile(9, 8)
332 .channels(4)
333 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700334 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800335 }
336
Marat Dukhan99936602020-04-11 16:47:01 -0700337 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_eq_4_twopass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -0800338 TEST_REQUIRES_X86_SSE;
339 MaxPoolMicrokernelTester()
340 .pooling_elements(17)
341 .pooling_tile(9, 8)
342 .channels(4)
343 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700344 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800345 }
346
Marat Dukhan99936602020-04-11 16:47:01 -0700347 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_eq_4_twopass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800348 TEST_REQUIRES_X86_SSE;
349 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
350 MaxPoolMicrokernelTester()
351 .pooling_elements(pooling_elements)
352 .pooling_tile(9, 8)
353 .channels(4)
Marat Dukhan99936602020-04-11 16:47:01 -0700354 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800355 }
356 }
357
Marat Dukhan99936602020-04-11 16:47:01 -0700358 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_eq_4_twopass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800359 TEST_REQUIRES_X86_SSE;
360 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
361 MaxPoolMicrokernelTester()
362 .pooling_elements(pooling_elements)
363 .pooling_tile(9, 8)
364 .channels(4)
365 .input_offset(7)
Marat Dukhan99936602020-04-11 16:47:01 -0700366 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800367 }
368 }
369
Marat Dukhan99936602020-04-11 16:47:01 -0700370 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_div_4_twopass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800371 TEST_REQUIRES_X86_SSE;
372 for (size_t channels = 8; channels < 32; channels += 4) {
373 MaxPoolMicrokernelTester()
374 .pooling_elements(17)
375 .pooling_tile(9, 8)
376 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -0700377 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800378 }
379 }
380
Marat Dukhan99936602020-04-11 16:47:01 -0700381 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_div_4_twopass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800382 TEST_REQUIRES_X86_SSE;
383 for (size_t channels = 8; channels < 32; channels += 4) {
384 MaxPoolMicrokernelTester()
385 .pooling_elements(17)
386 .pooling_tile(9, 8)
387 .channels(channels)
388 .input_offset(23)
Marat Dukhan99936602020-04-11 16:47:01 -0700389 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800390 }
391 }
392
Marat Dukhan99936602020-04-11 16:47:01 -0700393 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_div_4_twopass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -0800394 TEST_REQUIRES_X86_SSE;
395 for (size_t channels = 8; channels < 32; channels += 4) {
396 MaxPoolMicrokernelTester()
397 .pooling_elements(17)
398 .pooling_tile(9, 8)
399 .channels(channels)
400 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700401 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800402 }
403 }
404
Marat Dukhan99936602020-04-11 16:47:01 -0700405 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_div_4_twopass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -0800406 TEST_REQUIRES_X86_SSE;
407 for (size_t channels = 8; channels < 32; channels += 4) {
408 MaxPoolMicrokernelTester()
409 .pooling_elements(17)
410 .pooling_tile(9, 8)
411 .channels(channels)
412 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700413 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800414 }
415 }
416
Marat Dukhan99936602020-04-11 16:47:01 -0700417 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_div_4_twopass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800418 TEST_REQUIRES_X86_SSE;
419 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
420 for (size_t channels = 8; channels < 32; channels += 4) {
421 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800422 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800423 .pooling_tile(9, 8)
424 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -0700425 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800426 }
427 }
428 }
429
Marat Dukhan99936602020-04-11 16:47:01 -0700430 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_div_4_twopass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800431 TEST_REQUIRES_X86_SSE;
432 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
433 for (size_t channels = 8; channels < 32; channels += 4) {
434 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800435 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800436 .pooling_tile(9, 8)
437 .channels(channels)
438 .input_offset(37)
Marat Dukhan99936602020-04-11 16:47:01 -0700439 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800440 }
441 }
442 }
443
Marat Dukhan99936602020-04-11 16:47:01 -0700444 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_lt_4_twopass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800445 TEST_REQUIRES_X86_SSE;
446 for (size_t channels = 1; channels < 4; channels++) {
447 MaxPoolMicrokernelTester()
448 .pooling_elements(17)
449 .pooling_tile(9, 8)
450 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -0700451 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800452 }
453 }
454
Marat Dukhan99936602020-04-11 16:47:01 -0700455 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_lt_4_twopass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800456 TEST_REQUIRES_X86_SSE;
457 for (size_t channels = 1; channels < 4; channels++) {
458 MaxPoolMicrokernelTester()
459 .pooling_elements(17)
460 .pooling_tile(9, 8)
461 .channels(channels)
462 .input_offset(5)
Marat Dukhan99936602020-04-11 16:47:01 -0700463 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800464 }
465 }
466
Marat Dukhan99936602020-04-11 16:47:01 -0700467 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_lt_4_twopass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -0800468 TEST_REQUIRES_X86_SSE;
469 for (size_t channels = 1; channels < 4; channels++) {
470 MaxPoolMicrokernelTester()
471 .pooling_elements(17)
472 .pooling_tile(9, 8)
473 .channels(channels)
474 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700475 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800476 }
477 }
478
Marat Dukhan99936602020-04-11 16:47:01 -0700479 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_lt_4_twopass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -0800480 TEST_REQUIRES_X86_SSE;
481 for (size_t channels = 1; channels < 4; channels++) {
482 MaxPoolMicrokernelTester()
483 .pooling_elements(17)
484 .pooling_tile(9, 8)
485 .channels(channels)
486 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700487 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800488 }
489 }
490
Marat Dukhan99936602020-04-11 16:47:01 -0700491 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_lt_4_twopass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800492 TEST_REQUIRES_X86_SSE;
493 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
494 for (size_t channels = 1; channels < 4; channels++) {
495 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800496 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800497 .pooling_tile(9, 8)
498 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -0700499 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800500 }
501 }
502 }
503
Marat Dukhan99936602020-04-11 16:47:01 -0700504 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_lt_4_twopass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800505 TEST_REQUIRES_X86_SSE;
506 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
507 for (size_t channels = 1; channels < 4; channels++) {
508 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800509 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800510 .pooling_tile(9, 8)
511 .channels(channels)
512 .input_offset(5)
Marat Dukhan99936602020-04-11 16:47:01 -0700513 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800514 }
515 }
516 }
517
Marat Dukhan99936602020-04-11 16:47:01 -0700518 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_gt_4_twopass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800519 TEST_REQUIRES_X86_SSE;
520 for (size_t channels = 5; channels < 8; channels++) {
521 MaxPoolMicrokernelTester()
522 .pooling_elements(17)
523 .pooling_tile(9, 8)
524 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -0700525 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800526 }
527 }
528
Marat Dukhan99936602020-04-11 16:47:01 -0700529 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_gt_4_twopass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800530 TEST_REQUIRES_X86_SSE;
531 for (size_t channels = 5; channels < 8; channels++) {
532 MaxPoolMicrokernelTester()
533 .pooling_elements(17)
534 .pooling_tile(9, 8)
535 .channels(channels)
536 .input_offset(11)
Marat Dukhan99936602020-04-11 16:47:01 -0700537 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800538 }
539 }
540
Marat Dukhan99936602020-04-11 16:47:01 -0700541 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_gt_4_twopass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -0800542 TEST_REQUIRES_X86_SSE;
543 for (size_t channels = 5; channels < 8; channels++) {
544 MaxPoolMicrokernelTester()
545 .pooling_elements(17)
546 .pooling_tile(9, 8)
547 .channels(channels)
548 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700549 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800550 }
551 }
552
Marat Dukhan99936602020-04-11 16:47:01 -0700553 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_gt_4_twopass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -0800554 TEST_REQUIRES_X86_SSE;
555 for (size_t channels = 5; channels < 8; channels++) {
556 MaxPoolMicrokernelTester()
557 .pooling_elements(17)
558 .pooling_tile(9, 8)
559 .channels(channels)
560 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700561 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800562 }
563 }
564
Marat Dukhan99936602020-04-11 16:47:01 -0700565 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_gt_4_twopass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800566 TEST_REQUIRES_X86_SSE;
567 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
568 for (size_t channels = 5; channels < 8; channels++) {
569 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800570 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800571 .pooling_tile(9, 8)
572 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -0700573 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800574 }
575 }
576 }
577
Marat Dukhan99936602020-04-11 16:47:01 -0700578 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_gt_4_twopass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800579 TEST_REQUIRES_X86_SSE;
580 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
581 for (size_t channels = 5; channels < 8; channels++) {
582 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800583 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800584 .pooling_tile(9, 8)
585 .channels(channels)
586 .input_offset(11)
Marat Dukhan99936602020-04-11 16:47:01 -0700587 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800588 }
589 }
590 }
591
Marat Dukhan99936602020-04-11 16:47:01 -0700592 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_eq_4_multipass) {
Marat Dukhan329da642019-11-19 21:44:39 -0800593 TEST_REQUIRES_X86_SSE;
594 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
595 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800596 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800597 .pooling_tile(9, 8)
598 .channels(4)
Marat Dukhan99936602020-04-11 16:47:01 -0700599 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800600 }
601 }
602
Marat Dukhan99936602020-04-11 16:47:01 -0700603 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_eq_4_multipass_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800604 TEST_REQUIRES_X86_SSE;
605 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
606 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800607 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800608 .pooling_tile(9, 8)
609 .channels(4)
610 .input_offset(7)
Marat Dukhan99936602020-04-11 16:47:01 -0700611 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800612 }
613 }
614
Marat Dukhan99936602020-04-11 16:47:01 -0700615 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_eq_4_multipass_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -0800616 TEST_REQUIRES_X86_SSE;
617 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
618 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800619 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800620 .pooling_tile(9, 8)
621 .channels(4)
622 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700623 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800624 }
625 }
626
Marat Dukhan99936602020-04-11 16:47:01 -0700627 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_eq_4_multipass_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -0800628 TEST_REQUIRES_X86_SSE;
629 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
630 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800631 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800632 .pooling_tile(9, 8)
633 .channels(4)
634 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700635 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800636 }
637 }
638
Marat Dukhan99936602020-04-11 16:47:01 -0700639 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_div_4_multipass) {
Marat Dukhan329da642019-11-19 21:44:39 -0800640 TEST_REQUIRES_X86_SSE;
641 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
642 for (size_t channels = 8; channels < 32; channels += 4) {
643 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800644 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800645 .pooling_tile(9, 8)
646 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -0700647 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800648 }
649 }
650 }
651
Marat Dukhan99936602020-04-11 16:47:01 -0700652 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_div_4_multipass_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800653 TEST_REQUIRES_X86_SSE;
654 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
655 for (size_t channels = 8; channels < 32; channels += 4) {
656 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800657 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800658 .pooling_tile(9, 8)
659 .channels(channels)
660 .input_offset(37)
Marat Dukhan99936602020-04-11 16:47:01 -0700661 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800662 }
663 }
664 }
665
Marat Dukhan99936602020-04-11 16:47:01 -0700666 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_div_4_multipass_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -0800667 TEST_REQUIRES_X86_SSE;
668 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
669 for (size_t channels = 8; channels < 32; channels += 4) {
670 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800671 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800672 .pooling_tile(9, 8)
673 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700674 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700675 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800676 }
677 }
678 }
679
Marat Dukhan99936602020-04-11 16:47:01 -0700680 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_div_4_multipass_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -0800681 TEST_REQUIRES_X86_SSE;
682 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
683 for (size_t channels = 8; channels < 32; channels += 4) {
684 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800685 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800686 .pooling_tile(9, 8)
687 .channels(channels)
688 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700689 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800690 }
691 }
692 }
693
Marat Dukhan99936602020-04-11 16:47:01 -0700694 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_lt_4_multipass) {
Marat Dukhan329da642019-11-19 21:44:39 -0800695 TEST_REQUIRES_X86_SSE;
696 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
697 for (size_t channels = 1; channels < 4; channels++) {
698 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800699 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800700 .pooling_tile(9, 8)
701 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -0700702 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800703 }
704 }
705 }
706
Marat Dukhan99936602020-04-11 16:47:01 -0700707 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_lt_4_multipass_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800708 TEST_REQUIRES_X86_SSE;
709 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
710 for (size_t channels = 1; channels < 4; channels++) {
711 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800712 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800713 .pooling_tile(9, 8)
714 .channels(channels)
715 .input_offset(4)
Marat Dukhan99936602020-04-11 16:47:01 -0700716 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800717 }
718 }
719 }
720
Marat Dukhan99936602020-04-11 16:47:01 -0700721 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_lt_4_multipass_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -0800722 TEST_REQUIRES_X86_SSE;
723 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
724 for (size_t channels = 1; channels < 4; channels++) {
725 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800726 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800727 .pooling_tile(9, 8)
728 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700729 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700730 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700731 }
732 }
733 }
734
Marat Dukhan99936602020-04-11 16:47:01 -0700735 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_lt_4_multipass_with_qmax) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700736 TEST_REQUIRES_X86_SSE;
Marat Dukhan329da642019-11-19 21:44:39 -0800737 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
738 for (size_t channels = 1; channels < 4; channels++) {
739 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800740 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800741 .pooling_tile(9, 8)
742 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700743 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700744 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700745 }
746 }
747 }
748
Marat Dukhan99936602020-04-11 16:47:01 -0700749 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_gt_4_multipass) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700750 TEST_REQUIRES_X86_SSE;
Marat Dukhan329da642019-11-19 21:44:39 -0800751 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
752 for (size_t channels = 5; channels < 8; channels++) {
753 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800754 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800755 .pooling_tile(9, 8)
756 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -0700757 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700758 }
759 }
760 }
761
Marat Dukhan99936602020-04-11 16:47:01 -0700762 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_gt_4_multipass_with_input_offset) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700763 TEST_REQUIRES_X86_SSE;
Marat Dukhan329da642019-11-19 21:44:39 -0800764 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
765 for (size_t channels = 5; channels < 8; channels++) {
766 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800767 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800768 .pooling_tile(9, 8)
769 .channels(channels)
770 .input_offset(11)
Marat Dukhan99936602020-04-11 16:47:01 -0700771 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700772 }
773 }
774 }
775
Marat Dukhan99936602020-04-11 16:47:01 -0700776 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_gt_4_multipass_with_qmin) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700777 TEST_REQUIRES_X86_SSE;
Marat Dukhan329da642019-11-19 21:44:39 -0800778 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
779 for (size_t channels = 5; channels < 8; channels++) {
780 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800781 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800782 .pooling_tile(9, 8)
783 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700784 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700785 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700786 }
787 }
788 }
789
Marat Dukhan99936602020-04-11 16:47:01 -0700790 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, channels_gt_4_multipass_with_qmax) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700791 TEST_REQUIRES_X86_SSE;
Marat Dukhan329da642019-11-19 21:44:39 -0800792 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
793 for (size_t channels = 5; channels < 8; channels++) {
794 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800795 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800796 .pooling_tile(9, 8)
797 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700798 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700799 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700800 }
801 }
802 }
803
Marat Dukhan99936602020-04-11 16:47:01 -0700804 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, few_output_pixels) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700805 TEST_REQUIRES_X86_SSE;
Marat Dukhan329da642019-11-19 21:44:39 -0800806 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
807 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
808 for (size_t channels = 1; channels <= 20; channels += 3) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700809 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -0800810 .output_pixels(output_pixels)
811 .pooling_elements(pooling_elements)
812 .pooling_tile(9, 8)
813 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -0700814 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700815 }
816 }
817 }
818 }
819
Marat Dukhan99936602020-04-11 16:47:01 -0700820 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, few_output_pixels_with_input_offset) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700821 TEST_REQUIRES_X86_SSE;
Marat Dukhan329da642019-11-19 21:44:39 -0800822 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
823 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
824 for (size_t channels = 1; channels <= 20; channels += 3) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700825 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -0800826 .output_pixels(output_pixels)
827 .pooling_elements(pooling_elements)
828 .pooling_tile(9, 8)
829 .channels(channels)
830 .input_offset(23)
Marat Dukhan99936602020-04-11 16:47:01 -0700831 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700832 }
833 }
834 }
835 }
836
Marat Dukhan99936602020-04-11 16:47:01 -0700837 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, few_output_pixels_with_qmin) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700838 TEST_REQUIRES_X86_SSE;
Marat Dukhan329da642019-11-19 21:44:39 -0800839 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
840 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
841 for (size_t channels = 1; channels <= 20; channels += 3) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700842 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -0800843 .output_pixels(output_pixels)
844 .pooling_elements(pooling_elements)
845 .pooling_tile(9, 8)
846 .channels(channels)
847 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700848 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700849 }
850 }
851 }
852 }
853
Marat Dukhan99936602020-04-11 16:47:01 -0700854 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, few_output_pixels_with_qmax) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700855 TEST_REQUIRES_X86_SSE;
Marat Dukhan329da642019-11-19 21:44:39 -0800856 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
857 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
858 for (size_t channels = 1; channels <= 20; channels += 3) {
859 MaxPoolMicrokernelTester()
860 .output_pixels(output_pixels)
861 .pooling_elements(pooling_elements)
862 .pooling_tile(9, 8)
863 .channels(channels)
864 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700865 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800866 }
867 }
868 }
869 }
870
Marat Dukhan99936602020-04-11 16:47:01 -0700871 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, few_output_pixels_with_output_stride) {
Marat Dukhan329da642019-11-19 21:44:39 -0800872 TEST_REQUIRES_X86_SSE;
873 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
874 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
875 for (size_t channels = 1; channels <= 20; channels += 3) {
876 MaxPoolMicrokernelTester()
877 .output_pixels(output_pixels)
878 .pooling_elements(pooling_elements)
879 .pooling_tile(9, 8)
880 .channels(channels)
881 .output_stride(23)
Marat Dukhan99936602020-04-11 16:47:01 -0700882 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
Marat Dukhan329da642019-11-19 21:44:39 -0800883 }
884 }
885 }
886 }
887
Marat Dukhan99936602020-04-11 16:47:01 -0700888 TEST(F32_MAXPOOL_MINMAX_9P8X__SSE_C4, few_output_pixels_with_step) {
Marat Dukhan329da642019-11-19 21:44:39 -0800889 TEST_REQUIRES_X86_SSE;
890 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
891 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
892 for (size_t channels = 1; channels <= 20; channels += 3) {
893 for (size_t step = 2; step <= pooling_elements; step++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700894 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -0800895 .output_pixels(output_pixels)
896 .pooling_elements(pooling_elements)
897 .pooling_tile(9, 8)
898 .step(step)
899 .channels(channels)
900 .output_stride(23)
Marat Dukhan99936602020-04-11 16:47:01 -0700901 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__sse_c4);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700902 }
903 }
904 }
905 }
906 }
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700907#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
XNNPACK Teamb455b122019-09-27 18:10:33 -0700908
909
Frank Barchardf092a4a2020-03-03 14:22:46 -0800910#if XNN_ARCH_ARM || XNN_ARCH_ARM64
Marat Dukhan99936602020-04-11 16:47:01 -0700911 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_eq_4_unipass_fulltile) {
Frank Barchardf092a4a2020-03-03 14:22:46 -0800912 TEST_REQUIRES_ARM_NEON;
913 MaxPoolMicrokernelTester()
914 .pooling_elements(9)
915 .pooling_tile(9, 8)
916 .channels(4)
Marat Dukhan99936602020-04-11 16:47:01 -0700917 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -0800918 }
919
Marat Dukhan99936602020-04-11 16:47:01 -0700920 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_eq_4_unipass_fulltile_with_input_offset) {
Frank Barchardf092a4a2020-03-03 14:22:46 -0800921 TEST_REQUIRES_ARM_NEON;
922 MaxPoolMicrokernelTester()
923 .pooling_elements(9)
924 .pooling_tile(9, 8)
925 .channels(4)
926 .input_offset(7)
Marat Dukhan99936602020-04-11 16:47:01 -0700927 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -0800928 }
929
Marat Dukhan99936602020-04-11 16:47:01 -0700930 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_eq_4_unipass_fulltile_with_qmin) {
Frank Barchardf092a4a2020-03-03 14:22:46 -0800931 TEST_REQUIRES_ARM_NEON;
932 MaxPoolMicrokernelTester()
933 .pooling_elements(9)
934 .pooling_tile(9, 8)
935 .channels(4)
936 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700937 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -0800938 }
939
Marat Dukhan99936602020-04-11 16:47:01 -0700940 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_eq_4_unipass_fulltile_with_qmax) {
Frank Barchardf092a4a2020-03-03 14:22:46 -0800941 TEST_REQUIRES_ARM_NEON;
942 MaxPoolMicrokernelTester()
943 .pooling_elements(9)
944 .pooling_tile(9, 8)
945 .channels(4)
946 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -0700947 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -0800948 }
949
Marat Dukhan99936602020-04-11 16:47:01 -0700950 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_eq_4_unipass_subtile) {
Frank Barchardf092a4a2020-03-03 14:22:46 -0800951 TEST_REQUIRES_ARM_NEON;
952 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
953 MaxPoolMicrokernelTester()
954 .pooling_elements(pooling_elements)
955 .pooling_tile(9, 8)
956 .channels(4)
Marat Dukhan99936602020-04-11 16:47:01 -0700957 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -0800958 }
959 }
960
Marat Dukhan99936602020-04-11 16:47:01 -0700961 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_eq_4_unipass_subtile_with_input_offset) {
Frank Barchardf092a4a2020-03-03 14:22:46 -0800962 TEST_REQUIRES_ARM_NEON;
963 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
964 MaxPoolMicrokernelTester()
965 .pooling_elements(pooling_elements)
966 .pooling_tile(9, 8)
967 .channels(4)
968 .input_offset(7)
Marat Dukhan99936602020-04-11 16:47:01 -0700969 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -0800970 }
971 }
972
Marat Dukhan99936602020-04-11 16:47:01 -0700973 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_div_4_unipass_fulltile) {
Frank Barchardf092a4a2020-03-03 14:22:46 -0800974 TEST_REQUIRES_ARM_NEON;
975 for (size_t channels = 8; channels < 32; channels += 4) {
976 MaxPoolMicrokernelTester()
977 .pooling_elements(9)
978 .pooling_tile(9, 8)
979 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -0700980 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -0800981 }
982 }
983
Marat Dukhan99936602020-04-11 16:47:01 -0700984 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_div_4_unipass_fulltile_with_input_offset) {
Frank Barchardf092a4a2020-03-03 14:22:46 -0800985 TEST_REQUIRES_ARM_NEON;
986 for (size_t channels = 8; channels < 32; channels += 4) {
987 MaxPoolMicrokernelTester()
988 .pooling_elements(9)
989 .pooling_tile(9, 8)
990 .channels(channels)
991 .input_offset(37)
Marat Dukhan99936602020-04-11 16:47:01 -0700992 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -0800993 }
994 }
995
Marat Dukhan99936602020-04-11 16:47:01 -0700996 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_div_4_unipass_fulltile_with_qmin) {
Frank Barchardf092a4a2020-03-03 14:22:46 -0800997 TEST_REQUIRES_ARM_NEON;
998 for (size_t channels = 8; channels < 32; channels += 4) {
999 MaxPoolMicrokernelTester()
1000 .pooling_elements(9)
1001 .pooling_tile(9, 8)
1002 .channels(channels)
1003 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001004 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001005 }
1006 }
1007
Marat Dukhan99936602020-04-11 16:47:01 -07001008 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_div_4_unipass_fulltile_with_qmax) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001009 TEST_REQUIRES_ARM_NEON;
1010 for (size_t channels = 8; channels < 32; channels += 4) {
1011 MaxPoolMicrokernelTester()
1012 .pooling_elements(9)
1013 .pooling_tile(9, 8)
1014 .channels(channels)
1015 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001016 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001017 }
1018 }
1019
Marat Dukhan99936602020-04-11 16:47:01 -07001020 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_div_4_unipass_subtile) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001021 TEST_REQUIRES_ARM_NEON;
1022 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1023 for (size_t channels = 8; channels < 32; channels += 4) {
1024 MaxPoolMicrokernelTester()
1025 .pooling_elements(pooling_elements)
1026 .pooling_tile(9, 8)
1027 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07001028 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001029 }
1030 }
1031 }
1032
Marat Dukhan99936602020-04-11 16:47:01 -07001033 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_div_4_unipass_subtile_with_input_offset) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001034 TEST_REQUIRES_ARM_NEON;
1035 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1036 for (size_t channels = 8; channels < 32; channels += 4) {
1037 MaxPoolMicrokernelTester()
1038 .pooling_elements(pooling_elements)
1039 .pooling_tile(9, 8)
1040 .channels(channels)
1041 .input_offset(37)
Marat Dukhan99936602020-04-11 16:47:01 -07001042 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001043 }
1044 }
1045 }
1046
Marat Dukhan99936602020-04-11 16:47:01 -07001047 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_lt_4_unipass_fulltile) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001048 TEST_REQUIRES_ARM_NEON;
1049 for (size_t channels = 1; channels < 4; channels++) {
1050 MaxPoolMicrokernelTester()
1051 .pooling_elements(9)
1052 .pooling_tile(9, 8)
1053 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07001054 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001055 }
1056 }
1057
Marat Dukhan99936602020-04-11 16:47:01 -07001058 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_lt_4_unipass_fulltile_with_input_offset) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001059 TEST_REQUIRES_ARM_NEON;
1060 for (size_t channels = 1; channels < 4; channels++) {
1061 MaxPoolMicrokernelTester()
1062 .pooling_elements(9)
1063 .pooling_tile(9, 8)
1064 .channels(channels)
1065 .input_offset(5)
Marat Dukhan99936602020-04-11 16:47:01 -07001066 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001067 }
1068 }
1069
Marat Dukhan99936602020-04-11 16:47:01 -07001070 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_lt_4_unipass_fulltile_with_qmin) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001071 TEST_REQUIRES_ARM_NEON;
1072 for (size_t channels = 1; channels < 4; channels++) {
1073 MaxPoolMicrokernelTester()
1074 .pooling_elements(9)
1075 .pooling_tile(9, 8)
1076 .channels(channels)
1077 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001078 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001079 }
1080 }
1081
Marat Dukhan99936602020-04-11 16:47:01 -07001082 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_lt_4_unipass_fulltile_with_qmax) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001083 TEST_REQUIRES_ARM_NEON;
1084 for (size_t channels = 1; channels < 4; channels++) {
1085 MaxPoolMicrokernelTester()
1086 .pooling_elements(9)
1087 .pooling_tile(9, 8)
1088 .channels(channels)
1089 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001090 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001091 }
1092 }
1093
Marat Dukhan99936602020-04-11 16:47:01 -07001094 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_lt_4_unipass_subtile) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001095 TEST_REQUIRES_ARM_NEON;
1096 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1097 for (size_t channels = 1; channels < 4; channels++) {
1098 MaxPoolMicrokernelTester()
1099 .pooling_elements(pooling_elements)
1100 .pooling_tile(9, 8)
1101 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07001102 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001103 }
1104 }
1105 }
1106
Marat Dukhan99936602020-04-11 16:47:01 -07001107 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_lt_4_unipass_subtile_with_input_offset) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001108 TEST_REQUIRES_ARM_NEON;
1109 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1110 for (size_t channels = 1; channels < 4; channels++) {
1111 MaxPoolMicrokernelTester()
1112 .pooling_elements(pooling_elements)
1113 .pooling_tile(9, 8)
1114 .channels(channels)
1115 .input_offset(5)
Marat Dukhan99936602020-04-11 16:47:01 -07001116 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001117 }
1118 }
1119 }
1120
Marat Dukhan99936602020-04-11 16:47:01 -07001121 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_gt_4_unipass_fulltile) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001122 TEST_REQUIRES_ARM_NEON;
1123 for (size_t channels = 5; channels < 8; channels++) {
1124 MaxPoolMicrokernelTester()
1125 .pooling_elements(9)
1126 .pooling_tile(9, 8)
1127 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07001128 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001129 }
1130 }
1131
Marat Dukhan99936602020-04-11 16:47:01 -07001132 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_gt_4_unipass_fulltile_with_input_offset) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001133 TEST_REQUIRES_ARM_NEON;
1134 for (size_t channels = 5; channels < 8; channels++) {
1135 MaxPoolMicrokernelTester()
1136 .pooling_elements(9)
1137 .pooling_tile(9, 8)
1138 .channels(channels)
1139 .input_offset(11)
Marat Dukhan99936602020-04-11 16:47:01 -07001140 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001141 }
1142 }
1143
Marat Dukhan99936602020-04-11 16:47:01 -07001144 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_gt_4_unipass_fulltile_with_qmin) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001145 TEST_REQUIRES_ARM_NEON;
1146 for (size_t channels = 5; channels < 8; channels++) {
1147 MaxPoolMicrokernelTester()
1148 .pooling_elements(9)
1149 .pooling_tile(9, 8)
1150 .channels(channels)
1151 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001152 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001153 }
1154 }
1155
Marat Dukhan99936602020-04-11 16:47:01 -07001156 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_gt_4_unipass_fulltile_with_qmax) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001157 TEST_REQUIRES_ARM_NEON;
1158 for (size_t channels = 5; channels < 8; channels++) {
1159 MaxPoolMicrokernelTester()
1160 .pooling_elements(9)
1161 .pooling_tile(9, 8)
1162 .channels(channels)
1163 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001164 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001165 }
1166 }
1167
Marat Dukhan99936602020-04-11 16:47:01 -07001168 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_gt_4_unipass_subtile) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001169 TEST_REQUIRES_ARM_NEON;
1170 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1171 for (size_t channels = 5; channels < 8; channels++) {
1172 MaxPoolMicrokernelTester()
1173 .pooling_elements(pooling_elements)
1174 .pooling_tile(9, 8)
1175 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07001176 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001177 }
1178 }
1179 }
1180
Marat Dukhan99936602020-04-11 16:47:01 -07001181 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_gt_4_unipass_subtile_with_input_offset) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001182 TEST_REQUIRES_ARM_NEON;
1183 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1184 for (size_t channels = 5; channels < 8; channels++) {
1185 MaxPoolMicrokernelTester()
1186 .pooling_elements(pooling_elements)
1187 .pooling_tile(9, 8)
1188 .channels(channels)
1189 .input_offset(11)
Marat Dukhan99936602020-04-11 16:47:01 -07001190 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001191 }
1192 }
1193 }
1194
Marat Dukhan99936602020-04-11 16:47:01 -07001195 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_eq_4_twopass_fulltile) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001196 TEST_REQUIRES_ARM_NEON;
1197 MaxPoolMicrokernelTester()
1198 .pooling_elements(17)
1199 .pooling_tile(9, 8)
1200 .channels(4)
Marat Dukhan99936602020-04-11 16:47:01 -07001201 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001202 }
1203
Marat Dukhan99936602020-04-11 16:47:01 -07001204 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_eq_4_twopass_fulltile_with_input_offset) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001205 TEST_REQUIRES_ARM_NEON;
1206 MaxPoolMicrokernelTester()
1207 .pooling_elements(17)
1208 .pooling_tile(9, 8)
1209 .channels(4)
1210 .input_offset(7)
Marat Dukhan99936602020-04-11 16:47:01 -07001211 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001212 }
1213
Marat Dukhan99936602020-04-11 16:47:01 -07001214 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_eq_4_twopass_fulltile_with_qmin) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001215 TEST_REQUIRES_ARM_NEON;
1216 MaxPoolMicrokernelTester()
1217 .pooling_elements(17)
1218 .pooling_tile(9, 8)
1219 .channels(4)
1220 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001221 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001222 }
1223
Marat Dukhan99936602020-04-11 16:47:01 -07001224 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_eq_4_twopass_fulltile_with_qmax) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001225 TEST_REQUIRES_ARM_NEON;
1226 MaxPoolMicrokernelTester()
1227 .pooling_elements(17)
1228 .pooling_tile(9, 8)
1229 .channels(4)
1230 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001231 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001232 }
1233
Marat Dukhan99936602020-04-11 16:47:01 -07001234 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_eq_4_twopass_subtile) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001235 TEST_REQUIRES_ARM_NEON;
1236 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
1237 MaxPoolMicrokernelTester()
1238 .pooling_elements(pooling_elements)
1239 .pooling_tile(9, 8)
1240 .channels(4)
Marat Dukhan99936602020-04-11 16:47:01 -07001241 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001242 }
1243 }
1244
Marat Dukhan99936602020-04-11 16:47:01 -07001245 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_eq_4_twopass_subtile_with_input_offset) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001246 TEST_REQUIRES_ARM_NEON;
1247 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
1248 MaxPoolMicrokernelTester()
1249 .pooling_elements(pooling_elements)
1250 .pooling_tile(9, 8)
1251 .channels(4)
1252 .input_offset(7)
Marat Dukhan99936602020-04-11 16:47:01 -07001253 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001254 }
1255 }
1256
Marat Dukhan99936602020-04-11 16:47:01 -07001257 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_div_4_twopass_fulltile) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001258 TEST_REQUIRES_ARM_NEON;
1259 for (size_t channels = 8; channels < 32; channels += 4) {
1260 MaxPoolMicrokernelTester()
1261 .pooling_elements(17)
1262 .pooling_tile(9, 8)
1263 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07001264 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001265 }
1266 }
1267
Marat Dukhan99936602020-04-11 16:47:01 -07001268 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_div_4_twopass_fulltile_with_input_offset) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001269 TEST_REQUIRES_ARM_NEON;
1270 for (size_t channels = 8; channels < 32; channels += 4) {
1271 MaxPoolMicrokernelTester()
1272 .pooling_elements(17)
1273 .pooling_tile(9, 8)
1274 .channels(channels)
1275 .input_offset(23)
Marat Dukhan99936602020-04-11 16:47:01 -07001276 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001277 }
1278 }
1279
Marat Dukhan99936602020-04-11 16:47:01 -07001280 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_div_4_twopass_fulltile_with_qmin) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001281 TEST_REQUIRES_ARM_NEON;
1282 for (size_t channels = 8; channels < 32; channels += 4) {
1283 MaxPoolMicrokernelTester()
1284 .pooling_elements(17)
1285 .pooling_tile(9, 8)
1286 .channels(channels)
1287 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001288 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001289 }
1290 }
1291
Marat Dukhan99936602020-04-11 16:47:01 -07001292 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_div_4_twopass_fulltile_with_qmax) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001293 TEST_REQUIRES_ARM_NEON;
1294 for (size_t channels = 8; channels < 32; channels += 4) {
1295 MaxPoolMicrokernelTester()
1296 .pooling_elements(17)
1297 .pooling_tile(9, 8)
1298 .channels(channels)
1299 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001300 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001301 }
1302 }
1303
Marat Dukhan99936602020-04-11 16:47:01 -07001304 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_div_4_twopass_subtile) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001305 TEST_REQUIRES_ARM_NEON;
1306 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
1307 for (size_t channels = 8; channels < 32; channels += 4) {
1308 MaxPoolMicrokernelTester()
1309 .pooling_elements(pooling_elements)
1310 .pooling_tile(9, 8)
1311 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07001312 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001313 }
1314 }
1315 }
1316
Marat Dukhan99936602020-04-11 16:47:01 -07001317 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_div_4_twopass_subtile_with_input_offset) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001318 TEST_REQUIRES_ARM_NEON;
1319 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
1320 for (size_t channels = 8; channels < 32; channels += 4) {
1321 MaxPoolMicrokernelTester()
1322 .pooling_elements(pooling_elements)
1323 .pooling_tile(9, 8)
1324 .channels(channels)
1325 .input_offset(37)
Marat Dukhan99936602020-04-11 16:47:01 -07001326 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001327 }
1328 }
1329 }
1330
Marat Dukhan99936602020-04-11 16:47:01 -07001331 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_lt_4_twopass_fulltile) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001332 TEST_REQUIRES_ARM_NEON;
1333 for (size_t channels = 1; channels < 4; channels++) {
1334 MaxPoolMicrokernelTester()
1335 .pooling_elements(17)
1336 .pooling_tile(9, 8)
1337 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07001338 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001339 }
1340 }
1341
Marat Dukhan99936602020-04-11 16:47:01 -07001342 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_lt_4_twopass_fulltile_with_input_offset) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001343 TEST_REQUIRES_ARM_NEON;
1344 for (size_t channels = 1; channels < 4; channels++) {
1345 MaxPoolMicrokernelTester()
1346 .pooling_elements(17)
1347 .pooling_tile(9, 8)
1348 .channels(channels)
1349 .input_offset(5)
Marat Dukhan99936602020-04-11 16:47:01 -07001350 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001351 }
1352 }
1353
Marat Dukhan99936602020-04-11 16:47:01 -07001354 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_lt_4_twopass_fulltile_with_qmin) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001355 TEST_REQUIRES_ARM_NEON;
1356 for (size_t channels = 1; channels < 4; channels++) {
1357 MaxPoolMicrokernelTester()
1358 .pooling_elements(17)
1359 .pooling_tile(9, 8)
1360 .channels(channels)
1361 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001362 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001363 }
1364 }
1365
Marat Dukhan99936602020-04-11 16:47:01 -07001366 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_lt_4_twopass_fulltile_with_qmax) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001367 TEST_REQUIRES_ARM_NEON;
1368 for (size_t channels = 1; channels < 4; channels++) {
1369 MaxPoolMicrokernelTester()
1370 .pooling_elements(17)
1371 .pooling_tile(9, 8)
1372 .channels(channels)
1373 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001374 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001375 }
1376 }
1377
Marat Dukhan99936602020-04-11 16:47:01 -07001378 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_lt_4_twopass_subtile) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001379 TEST_REQUIRES_ARM_NEON;
1380 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
1381 for (size_t channels = 1; channels < 4; channels++) {
1382 MaxPoolMicrokernelTester()
1383 .pooling_elements(pooling_elements)
1384 .pooling_tile(9, 8)
1385 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07001386 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001387 }
1388 }
1389 }
1390
Marat Dukhan99936602020-04-11 16:47:01 -07001391 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_lt_4_twopass_subtile_with_input_offset) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001392 TEST_REQUIRES_ARM_NEON;
1393 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
1394 for (size_t channels = 1; channels < 4; channels++) {
1395 MaxPoolMicrokernelTester()
1396 .pooling_elements(pooling_elements)
1397 .pooling_tile(9, 8)
1398 .channels(channels)
1399 .input_offset(5)
Marat Dukhan99936602020-04-11 16:47:01 -07001400 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001401 }
1402 }
1403 }
1404
Marat Dukhan99936602020-04-11 16:47:01 -07001405 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_gt_4_twopass_fulltile) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001406 TEST_REQUIRES_ARM_NEON;
1407 for (size_t channels = 5; channels < 8; channels++) {
1408 MaxPoolMicrokernelTester()
1409 .pooling_elements(17)
1410 .pooling_tile(9, 8)
1411 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07001412 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001413 }
1414 }
1415
Marat Dukhan99936602020-04-11 16:47:01 -07001416 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_gt_4_twopass_fulltile_with_input_offset) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001417 TEST_REQUIRES_ARM_NEON;
1418 for (size_t channels = 5; channels < 8; channels++) {
1419 MaxPoolMicrokernelTester()
1420 .pooling_elements(17)
1421 .pooling_tile(9, 8)
1422 .channels(channels)
1423 .input_offset(11)
Marat Dukhan99936602020-04-11 16:47:01 -07001424 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001425 }
1426 }
1427
Marat Dukhan99936602020-04-11 16:47:01 -07001428 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_gt_4_twopass_fulltile_with_qmin) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001429 TEST_REQUIRES_ARM_NEON;
1430 for (size_t channels = 5; channels < 8; channels++) {
1431 MaxPoolMicrokernelTester()
1432 .pooling_elements(17)
1433 .pooling_tile(9, 8)
1434 .channels(channels)
1435 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001436 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001437 }
1438 }
1439
Marat Dukhan99936602020-04-11 16:47:01 -07001440 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_gt_4_twopass_fulltile_with_qmax) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001441 TEST_REQUIRES_ARM_NEON;
1442 for (size_t channels = 5; channels < 8; channels++) {
1443 MaxPoolMicrokernelTester()
1444 .pooling_elements(17)
1445 .pooling_tile(9, 8)
1446 .channels(channels)
1447 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001448 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001449 }
1450 }
1451
Marat Dukhan99936602020-04-11 16:47:01 -07001452 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_gt_4_twopass_subtile) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001453 TEST_REQUIRES_ARM_NEON;
1454 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
1455 for (size_t channels = 5; channels < 8; channels++) {
1456 MaxPoolMicrokernelTester()
1457 .pooling_elements(pooling_elements)
1458 .pooling_tile(9, 8)
1459 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07001460 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001461 }
1462 }
1463 }
1464
Marat Dukhan99936602020-04-11 16:47:01 -07001465 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_gt_4_twopass_subtile_with_input_offset) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001466 TEST_REQUIRES_ARM_NEON;
1467 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
1468 for (size_t channels = 5; channels < 8; channels++) {
1469 MaxPoolMicrokernelTester()
1470 .pooling_elements(pooling_elements)
1471 .pooling_tile(9, 8)
1472 .channels(channels)
1473 .input_offset(11)
Marat Dukhan99936602020-04-11 16:47:01 -07001474 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001475 }
1476 }
1477 }
1478
Marat Dukhan99936602020-04-11 16:47:01 -07001479 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_eq_4_multipass) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001480 TEST_REQUIRES_ARM_NEON;
1481 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1482 MaxPoolMicrokernelTester()
1483 .pooling_elements(pooling_elements)
1484 .pooling_tile(9, 8)
1485 .channels(4)
Marat Dukhan99936602020-04-11 16:47:01 -07001486 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001487 }
1488 }
1489
Marat Dukhan99936602020-04-11 16:47:01 -07001490 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_eq_4_multipass_with_input_offset) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001491 TEST_REQUIRES_ARM_NEON;
1492 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1493 MaxPoolMicrokernelTester()
1494 .pooling_elements(pooling_elements)
1495 .pooling_tile(9, 8)
1496 .channels(4)
1497 .input_offset(7)
Marat Dukhan99936602020-04-11 16:47:01 -07001498 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001499 }
1500 }
1501
Marat Dukhan99936602020-04-11 16:47:01 -07001502 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_eq_4_multipass_with_qmin) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001503 TEST_REQUIRES_ARM_NEON;
1504 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1505 MaxPoolMicrokernelTester()
1506 .pooling_elements(pooling_elements)
1507 .pooling_tile(9, 8)
1508 .channels(4)
1509 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001510 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001511 }
1512 }
1513
Marat Dukhan99936602020-04-11 16:47:01 -07001514 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_eq_4_multipass_with_qmax) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001515 TEST_REQUIRES_ARM_NEON;
1516 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1517 MaxPoolMicrokernelTester()
1518 .pooling_elements(pooling_elements)
1519 .pooling_tile(9, 8)
1520 .channels(4)
1521 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001522 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001523 }
1524 }
1525
Marat Dukhan99936602020-04-11 16:47:01 -07001526 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_div_4_multipass) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001527 TEST_REQUIRES_ARM_NEON;
1528 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1529 for (size_t channels = 8; channels < 32; channels += 4) {
1530 MaxPoolMicrokernelTester()
1531 .pooling_elements(pooling_elements)
1532 .pooling_tile(9, 8)
1533 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07001534 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001535 }
1536 }
1537 }
1538
Marat Dukhan99936602020-04-11 16:47:01 -07001539 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_div_4_multipass_with_input_offset) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001540 TEST_REQUIRES_ARM_NEON;
1541 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1542 for (size_t channels = 8; channels < 32; channels += 4) {
1543 MaxPoolMicrokernelTester()
1544 .pooling_elements(pooling_elements)
1545 .pooling_tile(9, 8)
1546 .channels(channels)
1547 .input_offset(37)
Marat Dukhan99936602020-04-11 16:47:01 -07001548 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001549 }
1550 }
1551 }
1552
Marat Dukhan99936602020-04-11 16:47:01 -07001553 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_div_4_multipass_with_qmin) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001554 TEST_REQUIRES_ARM_NEON;
1555 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1556 for (size_t channels = 8; channels < 32; channels += 4) {
1557 MaxPoolMicrokernelTester()
1558 .pooling_elements(pooling_elements)
1559 .pooling_tile(9, 8)
1560 .channels(channels)
1561 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001562 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001563 }
1564 }
1565 }
1566
Marat Dukhan99936602020-04-11 16:47:01 -07001567 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_div_4_multipass_with_qmax) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001568 TEST_REQUIRES_ARM_NEON;
1569 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1570 for (size_t channels = 8; channels < 32; channels += 4) {
1571 MaxPoolMicrokernelTester()
1572 .pooling_elements(pooling_elements)
1573 .pooling_tile(9, 8)
1574 .channels(channels)
1575 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001576 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001577 }
1578 }
1579 }
1580
Marat Dukhan99936602020-04-11 16:47:01 -07001581 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_lt_4_multipass) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001582 TEST_REQUIRES_ARM_NEON;
1583 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1584 for (size_t channels = 1; channels < 4; channels++) {
1585 MaxPoolMicrokernelTester()
1586 .pooling_elements(pooling_elements)
1587 .pooling_tile(9, 8)
1588 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07001589 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001590 }
1591 }
1592 }
1593
Marat Dukhan99936602020-04-11 16:47:01 -07001594 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_lt_4_multipass_with_input_offset) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001595 TEST_REQUIRES_ARM_NEON;
1596 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1597 for (size_t channels = 1; channels < 4; channels++) {
1598 MaxPoolMicrokernelTester()
1599 .pooling_elements(pooling_elements)
1600 .pooling_tile(9, 8)
1601 .channels(channels)
1602 .input_offset(4)
Marat Dukhan99936602020-04-11 16:47:01 -07001603 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001604 }
1605 }
1606 }
1607
Marat Dukhan99936602020-04-11 16:47:01 -07001608 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_lt_4_multipass_with_qmin) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001609 TEST_REQUIRES_ARM_NEON;
1610 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1611 for (size_t channels = 1; channels < 4; channels++) {
1612 MaxPoolMicrokernelTester()
1613 .pooling_elements(pooling_elements)
1614 .pooling_tile(9, 8)
1615 .channels(channels)
1616 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001617 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001618 }
1619 }
1620 }
1621
Marat Dukhan99936602020-04-11 16:47:01 -07001622 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_lt_4_multipass_with_qmax) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001623 TEST_REQUIRES_ARM_NEON;
1624 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1625 for (size_t channels = 1; channels < 4; channels++) {
1626 MaxPoolMicrokernelTester()
1627 .pooling_elements(pooling_elements)
1628 .pooling_tile(9, 8)
1629 .channels(channels)
1630 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001631 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001632 }
1633 }
1634 }
1635
Marat Dukhan99936602020-04-11 16:47:01 -07001636 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_gt_4_multipass) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001637 TEST_REQUIRES_ARM_NEON;
1638 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1639 for (size_t channels = 5; channels < 8; channels++) {
1640 MaxPoolMicrokernelTester()
1641 .pooling_elements(pooling_elements)
1642 .pooling_tile(9, 8)
1643 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07001644 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001645 }
1646 }
1647 }
1648
Marat Dukhan99936602020-04-11 16:47:01 -07001649 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_gt_4_multipass_with_input_offset) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001650 TEST_REQUIRES_ARM_NEON;
1651 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1652 for (size_t channels = 5; channels < 8; channels++) {
1653 MaxPoolMicrokernelTester()
1654 .pooling_elements(pooling_elements)
1655 .pooling_tile(9, 8)
1656 .channels(channels)
1657 .input_offset(11)
Marat Dukhan99936602020-04-11 16:47:01 -07001658 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001659 }
1660 }
1661 }
1662
Marat Dukhan99936602020-04-11 16:47:01 -07001663 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_gt_4_multipass_with_qmin) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001664 TEST_REQUIRES_ARM_NEON;
1665 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1666 for (size_t channels = 5; channels < 8; channels++) {
1667 MaxPoolMicrokernelTester()
1668 .pooling_elements(pooling_elements)
1669 .pooling_tile(9, 8)
1670 .channels(channels)
1671 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001672 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001673 }
1674 }
1675 }
1676
Marat Dukhan99936602020-04-11 16:47:01 -07001677 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, channels_gt_4_multipass_with_qmax) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001678 TEST_REQUIRES_ARM_NEON;
1679 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1680 for (size_t channels = 5; channels < 8; channels++) {
1681 MaxPoolMicrokernelTester()
1682 .pooling_elements(pooling_elements)
1683 .pooling_tile(9, 8)
1684 .channels(channels)
1685 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001686 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001687 }
1688 }
1689 }
1690
Marat Dukhan99936602020-04-11 16:47:01 -07001691 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, few_output_pixels) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001692 TEST_REQUIRES_ARM_NEON;
1693 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
1694 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
1695 for (size_t channels = 1; channels <= 20; channels += 3) {
1696 MaxPoolMicrokernelTester()
1697 .output_pixels(output_pixels)
1698 .pooling_elements(pooling_elements)
1699 .pooling_tile(9, 8)
1700 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07001701 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001702 }
1703 }
1704 }
1705 }
1706
Marat Dukhan99936602020-04-11 16:47:01 -07001707 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, few_output_pixels_with_input_offset) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001708 TEST_REQUIRES_ARM_NEON;
1709 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
1710 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
1711 for (size_t channels = 1; channels <= 20; channels += 3) {
1712 MaxPoolMicrokernelTester()
1713 .output_pixels(output_pixels)
1714 .pooling_elements(pooling_elements)
1715 .pooling_tile(9, 8)
1716 .channels(channels)
1717 .input_offset(23)
Marat Dukhan99936602020-04-11 16:47:01 -07001718 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001719 }
1720 }
1721 }
1722 }
1723
Marat Dukhan99936602020-04-11 16:47:01 -07001724 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, few_output_pixels_with_qmin) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001725 TEST_REQUIRES_ARM_NEON;
1726 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
1727 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
1728 for (size_t channels = 1; channels <= 20; channels += 3) {
1729 MaxPoolMicrokernelTester()
1730 .output_pixels(output_pixels)
1731 .pooling_elements(pooling_elements)
1732 .pooling_tile(9, 8)
1733 .channels(channels)
1734 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001735 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001736 }
1737 }
1738 }
1739 }
1740
Marat Dukhan99936602020-04-11 16:47:01 -07001741 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, few_output_pixels_with_qmax) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001742 TEST_REQUIRES_ARM_NEON;
1743 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
1744 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
1745 for (size_t channels = 1; channels <= 20; channels += 3) {
1746 MaxPoolMicrokernelTester()
1747 .output_pixels(output_pixels)
1748 .pooling_elements(pooling_elements)
1749 .pooling_tile(9, 8)
1750 .channels(channels)
1751 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001752 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001753 }
1754 }
1755 }
1756 }
1757
Marat Dukhan99936602020-04-11 16:47:01 -07001758 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, few_output_pixels_with_output_stride) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001759 TEST_REQUIRES_ARM_NEON;
1760 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
1761 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
1762 for (size_t channels = 1; channels <= 20; channels += 3) {
1763 MaxPoolMicrokernelTester()
1764 .output_pixels(output_pixels)
1765 .pooling_elements(pooling_elements)
1766 .pooling_tile(9, 8)
1767 .channels(channels)
1768 .output_stride(23)
Marat Dukhan99936602020-04-11 16:47:01 -07001769 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001770 }
1771 }
1772 }
1773 }
1774
Marat Dukhan99936602020-04-11 16:47:01 -07001775 TEST(F32_MAXPOOL_MINMAX_9P8X__NEON_C4, few_output_pixels_with_step) {
Frank Barchardf092a4a2020-03-03 14:22:46 -08001776 TEST_REQUIRES_ARM_NEON;
1777 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
1778 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
1779 for (size_t channels = 1; channels <= 20; channels += 3) {
1780 for (size_t step = 2; step <= pooling_elements; step++) {
1781 MaxPoolMicrokernelTester()
1782 .output_pixels(output_pixels)
1783 .pooling_elements(pooling_elements)
1784 .pooling_tile(9, 8)
1785 .step(step)
1786 .channels(channels)
1787 .output_stride(23)
Marat Dukhan99936602020-04-11 16:47:01 -07001788 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__neon_c4);
Frank Barchardf092a4a2020-03-03 14:22:46 -08001789 }
1790 }
1791 }
1792 }
1793 }
1794#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
1795
1796
Marat Dukhan29c6b262020-04-14 18:07:56 -07001797#if !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC
Marat Dukhan99936602020-04-11 16:47:01 -07001798 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_eq_4_unipass_fulltile) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001799 TEST_REQUIRES_PSIMD;
Marat Dukhan329da642019-11-19 21:44:39 -08001800 MaxPoolMicrokernelTester()
1801 .pooling_elements(9)
1802 .pooling_tile(9, 8)
1803 .channels(4)
Marat Dukhan99936602020-04-11 16:47:01 -07001804 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08001805 }
1806
Marat Dukhan99936602020-04-11 16:47:01 -07001807 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_eq_4_unipass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08001808 TEST_REQUIRES_PSIMD;
1809 MaxPoolMicrokernelTester()
1810 .pooling_elements(9)
1811 .pooling_tile(9, 8)
1812 .channels(4)
1813 .input_offset(7)
Marat Dukhan99936602020-04-11 16:47:01 -07001814 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08001815 }
1816
Marat Dukhan99936602020-04-11 16:47:01 -07001817 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_eq_4_unipass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08001818 TEST_REQUIRES_PSIMD;
1819 MaxPoolMicrokernelTester()
1820 .pooling_elements(9)
1821 .pooling_tile(9, 8)
1822 .channels(4)
1823 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001824 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08001825 }
1826
Marat Dukhan99936602020-04-11 16:47:01 -07001827 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_eq_4_unipass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08001828 TEST_REQUIRES_PSIMD;
1829 MaxPoolMicrokernelTester()
1830 .pooling_elements(9)
1831 .pooling_tile(9, 8)
1832 .channels(4)
1833 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001834 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08001835 }
1836
Marat Dukhan99936602020-04-11 16:47:01 -07001837 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_eq_4_unipass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -08001838 TEST_REQUIRES_PSIMD;
1839 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1840 MaxPoolMicrokernelTester()
1841 .pooling_elements(pooling_elements)
1842 .pooling_tile(9, 8)
1843 .channels(4)
Marat Dukhan99936602020-04-11 16:47:01 -07001844 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001845 }
1846 }
1847
Marat Dukhan99936602020-04-11 16:47:01 -07001848 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_eq_4_unipass_subtile_with_input_offset) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001849 TEST_REQUIRES_PSIMD;
Marat Dukhan329da642019-11-19 21:44:39 -08001850 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1851 MaxPoolMicrokernelTester()
1852 .pooling_elements(pooling_elements)
1853 .pooling_tile(9, 8)
1854 .channels(4)
1855 .input_offset(7)
Marat Dukhan99936602020-04-11 16:47:01 -07001856 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001857 }
1858 }
1859
Marat Dukhan99936602020-04-11 16:47:01 -07001860 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_div_4_unipass_fulltile) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001861 TEST_REQUIRES_PSIMD;
Marat Dukhan329da642019-11-19 21:44:39 -08001862 for (size_t channels = 8; channels < 32; channels += 4) {
1863 MaxPoolMicrokernelTester()
1864 .pooling_elements(9)
1865 .pooling_tile(9, 8)
1866 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07001867 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001868 }
1869 }
1870
Marat Dukhan99936602020-04-11 16:47:01 -07001871 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_div_4_unipass_fulltile_with_input_offset) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001872 TEST_REQUIRES_PSIMD;
Marat Dukhan329da642019-11-19 21:44:39 -08001873 for (size_t channels = 8; channels < 32; channels += 4) {
1874 MaxPoolMicrokernelTester()
1875 .pooling_elements(9)
1876 .pooling_tile(9, 8)
1877 .channels(channels)
1878 .input_offset(37)
Marat Dukhan99936602020-04-11 16:47:01 -07001879 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001880 }
1881 }
1882
Marat Dukhan99936602020-04-11 16:47:01 -07001883 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_div_4_unipass_fulltile_with_qmin) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001884 TEST_REQUIRES_PSIMD;
Marat Dukhan329da642019-11-19 21:44:39 -08001885 for (size_t channels = 8; channels < 32; channels += 4) {
1886 MaxPoolMicrokernelTester()
1887 .pooling_elements(9)
1888 .pooling_tile(9, 8)
1889 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07001890 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001891 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08001892 }
1893 }
1894
Marat Dukhan99936602020-04-11 16:47:01 -07001895 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_div_4_unipass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08001896 TEST_REQUIRES_PSIMD;
1897 for (size_t channels = 8; channels < 32; channels += 4) {
1898 MaxPoolMicrokernelTester()
1899 .pooling_elements(9)
1900 .pooling_tile(9, 8)
1901 .channels(channels)
1902 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001903 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08001904 }
1905 }
1906
Marat Dukhan99936602020-04-11 16:47:01 -07001907 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_div_4_unipass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -08001908 TEST_REQUIRES_PSIMD;
1909 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1910 for (size_t channels = 8; channels < 32; channels += 4) {
1911 MaxPoolMicrokernelTester()
1912 .pooling_elements(pooling_elements)
1913 .pooling_tile(9, 8)
1914 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07001915 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08001916 }
1917 }
1918 }
1919
Marat Dukhan99936602020-04-11 16:47:01 -07001920 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_div_4_unipass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08001921 TEST_REQUIRES_PSIMD;
1922 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1923 for (size_t channels = 8; channels < 32; channels += 4) {
1924 MaxPoolMicrokernelTester()
1925 .pooling_elements(pooling_elements)
1926 .pooling_tile(9, 8)
1927 .channels(channels)
1928 .input_offset(37)
Marat Dukhan99936602020-04-11 16:47:01 -07001929 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08001930 }
1931 }
1932 }
1933
Marat Dukhan99936602020-04-11 16:47:01 -07001934 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_lt_4_unipass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -08001935 TEST_REQUIRES_PSIMD;
1936 for (size_t channels = 1; channels < 4; channels++) {
1937 MaxPoolMicrokernelTester()
1938 .pooling_elements(9)
1939 .pooling_tile(9, 8)
1940 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07001941 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08001942 }
1943 }
1944
Marat Dukhan99936602020-04-11 16:47:01 -07001945 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_lt_4_unipass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08001946 TEST_REQUIRES_PSIMD;
1947 for (size_t channels = 1; channels < 4; channels++) {
1948 MaxPoolMicrokernelTester()
1949 .pooling_elements(9)
1950 .pooling_tile(9, 8)
1951 .channels(channels)
1952 .input_offset(5)
Marat Dukhan99936602020-04-11 16:47:01 -07001953 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08001954 }
1955 }
1956
Marat Dukhan99936602020-04-11 16:47:01 -07001957 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_lt_4_unipass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08001958 TEST_REQUIRES_PSIMD;
1959 for (size_t channels = 1; channels < 4; channels++) {
1960 MaxPoolMicrokernelTester()
1961 .pooling_elements(9)
1962 .pooling_tile(9, 8)
1963 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07001964 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001965 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001966 }
1967 }
1968
Marat Dukhan99936602020-04-11 16:47:01 -07001969 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_lt_4_unipass_fulltile_with_qmax) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001970 TEST_REQUIRES_PSIMD;
Marat Dukhan329da642019-11-19 21:44:39 -08001971 for (size_t channels = 1; channels < 4; channels++) {
1972 MaxPoolMicrokernelTester()
1973 .pooling_elements(9)
1974 .pooling_tile(9, 8)
1975 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07001976 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07001977 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08001978 }
1979 }
1980
Marat Dukhan99936602020-04-11 16:47:01 -07001981 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_lt_4_unipass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -08001982 TEST_REQUIRES_PSIMD;
1983 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1984 for (size_t channels = 1; channels < 4; channels++) {
1985 MaxPoolMicrokernelTester()
1986 .pooling_elements(pooling_elements)
1987 .pooling_tile(9, 8)
1988 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07001989 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08001990 }
1991 }
1992 }
1993
Marat Dukhan99936602020-04-11 16:47:01 -07001994 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_lt_4_unipass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08001995 TEST_REQUIRES_PSIMD;
1996 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1997 for (size_t channels = 1; channels < 4; channels++) {
1998 MaxPoolMicrokernelTester()
1999 .pooling_elements(pooling_elements)
2000 .pooling_tile(9, 8)
2001 .channels(channels)
2002 .input_offset(5)
Marat Dukhan99936602020-04-11 16:47:01 -07002003 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002004 }
2005 }
2006 }
2007
Marat Dukhan99936602020-04-11 16:47:01 -07002008 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_gt_4_unipass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -08002009 TEST_REQUIRES_PSIMD;
2010 for (size_t channels = 5; channels < 8; channels++) {
2011 MaxPoolMicrokernelTester()
2012 .pooling_elements(9)
2013 .pooling_tile(9, 8)
2014 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07002015 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002016 }
2017 }
2018
Marat Dukhan99936602020-04-11 16:47:01 -07002019 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_gt_4_unipass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08002020 TEST_REQUIRES_PSIMD;
2021 for (size_t channels = 5; channels < 8; channels++) {
2022 MaxPoolMicrokernelTester()
2023 .pooling_elements(9)
2024 .pooling_tile(9, 8)
2025 .channels(channels)
2026 .input_offset(11)
Marat Dukhan99936602020-04-11 16:47:01 -07002027 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002028 }
2029 }
2030
Marat Dukhan99936602020-04-11 16:47:01 -07002031 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_gt_4_unipass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08002032 TEST_REQUIRES_PSIMD;
2033 for (size_t channels = 5; channels < 8; channels++) {
2034 MaxPoolMicrokernelTester()
2035 .pooling_elements(9)
2036 .pooling_tile(9, 8)
2037 .channels(channels)
2038 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07002039 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002040 }
2041 }
2042
Marat Dukhan99936602020-04-11 16:47:01 -07002043 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_gt_4_unipass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08002044 TEST_REQUIRES_PSIMD;
2045 for (size_t channels = 5; channels < 8; channels++) {
2046 MaxPoolMicrokernelTester()
2047 .pooling_elements(9)
2048 .pooling_tile(9, 8)
2049 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07002050 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07002051 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002052 }
2053 }
2054
Marat Dukhan99936602020-04-11 16:47:01 -07002055 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_gt_4_unipass_subtile) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07002056 TEST_REQUIRES_PSIMD;
Marat Dukhan329da642019-11-19 21:44:39 -08002057 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
2058 for (size_t channels = 5; channels < 8; channels++) {
2059 MaxPoolMicrokernelTester()
2060 .pooling_elements(pooling_elements)
2061 .pooling_tile(9, 8)
2062 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07002063 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002064 }
2065 }
2066 }
2067
Marat Dukhan99936602020-04-11 16:47:01 -07002068 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_gt_4_unipass_subtile_with_input_offset) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07002069 TEST_REQUIRES_PSIMD;
Marat Dukhan329da642019-11-19 21:44:39 -08002070 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
2071 for (size_t channels = 5; channels < 8; channels++) {
2072 MaxPoolMicrokernelTester()
2073 .pooling_elements(pooling_elements)
2074 .pooling_tile(9, 8)
2075 .channels(channels)
2076 .input_offset(11)
Marat Dukhan99936602020-04-11 16:47:01 -07002077 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002078 }
2079 }
2080 }
2081
Marat Dukhan99936602020-04-11 16:47:01 -07002082 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_eq_4_twopass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -08002083 TEST_REQUIRES_PSIMD;
2084 MaxPoolMicrokernelTester()
2085 .pooling_elements(17)
2086 .pooling_tile(9, 8)
2087 .channels(4)
Marat Dukhan99936602020-04-11 16:47:01 -07002088 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002089 }
2090
Marat Dukhan99936602020-04-11 16:47:01 -07002091 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_eq_4_twopass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08002092 TEST_REQUIRES_PSIMD;
2093 MaxPoolMicrokernelTester()
2094 .pooling_elements(17)
2095 .pooling_tile(9, 8)
2096 .channels(4)
2097 .input_offset(7)
Marat Dukhan99936602020-04-11 16:47:01 -07002098 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002099 }
2100
Marat Dukhan99936602020-04-11 16:47:01 -07002101 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_eq_4_twopass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08002102 TEST_REQUIRES_PSIMD;
2103 MaxPoolMicrokernelTester()
2104 .pooling_elements(17)
2105 .pooling_tile(9, 8)
2106 .channels(4)
2107 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07002108 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002109 }
2110
Marat Dukhan99936602020-04-11 16:47:01 -07002111 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_eq_4_twopass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08002112 TEST_REQUIRES_PSIMD;
2113 MaxPoolMicrokernelTester()
2114 .pooling_elements(17)
2115 .pooling_tile(9, 8)
2116 .channels(4)
2117 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07002118 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002119 }
2120
Marat Dukhan99936602020-04-11 16:47:01 -07002121 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_eq_4_twopass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -08002122 TEST_REQUIRES_PSIMD;
2123 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
2124 MaxPoolMicrokernelTester()
2125 .pooling_elements(pooling_elements)
2126 .pooling_tile(9, 8)
2127 .channels(4)
Marat Dukhan99936602020-04-11 16:47:01 -07002128 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002129 }
2130 }
2131
Marat Dukhan99936602020-04-11 16:47:01 -07002132 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_eq_4_twopass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08002133 TEST_REQUIRES_PSIMD;
2134 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
2135 MaxPoolMicrokernelTester()
2136 .pooling_elements(pooling_elements)
2137 .pooling_tile(9, 8)
2138 .channels(4)
2139 .input_offset(7)
Marat Dukhan99936602020-04-11 16:47:01 -07002140 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002141 }
2142 }
2143
Marat Dukhan99936602020-04-11 16:47:01 -07002144 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_div_4_twopass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -08002145 TEST_REQUIRES_PSIMD;
2146 for (size_t channels = 8; channels < 32; channels += 4) {
2147 MaxPoolMicrokernelTester()
2148 .pooling_elements(17)
2149 .pooling_tile(9, 8)
2150 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07002151 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002152 }
2153 }
2154
Marat Dukhan99936602020-04-11 16:47:01 -07002155 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_div_4_twopass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08002156 TEST_REQUIRES_PSIMD;
2157 for (size_t channels = 8; channels < 32; channels += 4) {
2158 MaxPoolMicrokernelTester()
2159 .pooling_elements(17)
2160 .pooling_tile(9, 8)
2161 .channels(channels)
2162 .input_offset(23)
Marat Dukhan99936602020-04-11 16:47:01 -07002163 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002164 }
2165 }
2166
Marat Dukhan99936602020-04-11 16:47:01 -07002167 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_div_4_twopass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08002168 TEST_REQUIRES_PSIMD;
2169 for (size_t channels = 8; channels < 32; channels += 4) {
2170 MaxPoolMicrokernelTester()
2171 .pooling_elements(17)
2172 .pooling_tile(9, 8)
2173 .channels(channels)
2174 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07002175 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002176 }
2177 }
2178
Marat Dukhan99936602020-04-11 16:47:01 -07002179 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_div_4_twopass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08002180 TEST_REQUIRES_PSIMD;
2181 for (size_t channels = 8; channels < 32; channels += 4) {
2182 MaxPoolMicrokernelTester()
2183 .pooling_elements(17)
2184 .pooling_tile(9, 8)
2185 .channels(channels)
2186 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07002187 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002188 }
2189 }
2190
Marat Dukhan99936602020-04-11 16:47:01 -07002191 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_div_4_twopass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -08002192 TEST_REQUIRES_PSIMD;
2193 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
2194 for (size_t channels = 8; channels < 32; channels += 4) {
2195 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002196 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002197 .pooling_tile(9, 8)
2198 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07002199 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002200 }
2201 }
2202 }
2203
Marat Dukhan99936602020-04-11 16:47:01 -07002204 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_div_4_twopass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08002205 TEST_REQUIRES_PSIMD;
2206 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
2207 for (size_t channels = 8; channels < 32; channels += 4) {
2208 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002209 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002210 .pooling_tile(9, 8)
2211 .channels(channels)
2212 .input_offset(37)
Marat Dukhan99936602020-04-11 16:47:01 -07002213 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002214 }
2215 }
2216 }
2217
Marat Dukhan99936602020-04-11 16:47:01 -07002218 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_lt_4_twopass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -08002219 TEST_REQUIRES_PSIMD;
2220 for (size_t channels = 1; channels < 4; channels++) {
2221 MaxPoolMicrokernelTester()
2222 .pooling_elements(17)
2223 .pooling_tile(9, 8)
2224 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07002225 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002226 }
2227 }
2228
Marat Dukhan99936602020-04-11 16:47:01 -07002229 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_lt_4_twopass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08002230 TEST_REQUIRES_PSIMD;
2231 for (size_t channels = 1; channels < 4; channels++) {
2232 MaxPoolMicrokernelTester()
2233 .pooling_elements(17)
2234 .pooling_tile(9, 8)
2235 .channels(channels)
2236 .input_offset(5)
Marat Dukhan99936602020-04-11 16:47:01 -07002237 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002238 }
2239 }
2240
Marat Dukhan99936602020-04-11 16:47:01 -07002241 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_lt_4_twopass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08002242 TEST_REQUIRES_PSIMD;
2243 for (size_t channels = 1; channels < 4; channels++) {
2244 MaxPoolMicrokernelTester()
2245 .pooling_elements(17)
2246 .pooling_tile(9, 8)
2247 .channels(channels)
2248 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07002249 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002250 }
2251 }
2252
Marat Dukhan99936602020-04-11 16:47:01 -07002253 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_lt_4_twopass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08002254 TEST_REQUIRES_PSIMD;
2255 for (size_t channels = 1; channels < 4; channels++) {
2256 MaxPoolMicrokernelTester()
2257 .pooling_elements(17)
2258 .pooling_tile(9, 8)
2259 .channels(channels)
2260 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07002261 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002262 }
2263 }
2264
Marat Dukhan99936602020-04-11 16:47:01 -07002265 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_lt_4_twopass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -08002266 TEST_REQUIRES_PSIMD;
2267 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
2268 for (size_t channels = 1; channels < 4; channels++) {
2269 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002270 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002271 .pooling_tile(9, 8)
2272 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07002273 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002274 }
2275 }
2276 }
2277
Marat Dukhan99936602020-04-11 16:47:01 -07002278 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_lt_4_twopass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08002279 TEST_REQUIRES_PSIMD;
2280 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
2281 for (size_t channels = 1; channels < 4; channels++) {
2282 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002283 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002284 .pooling_tile(9, 8)
2285 .channels(channels)
2286 .input_offset(5)
Marat Dukhan99936602020-04-11 16:47:01 -07002287 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002288 }
2289 }
2290 }
2291
Marat Dukhan99936602020-04-11 16:47:01 -07002292 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_gt_4_twopass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -08002293 TEST_REQUIRES_PSIMD;
2294 for (size_t channels = 5; channels < 8; channels++) {
2295 MaxPoolMicrokernelTester()
2296 .pooling_elements(17)
2297 .pooling_tile(9, 8)
2298 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07002299 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002300 }
2301 }
2302
Marat Dukhan99936602020-04-11 16:47:01 -07002303 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_gt_4_twopass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08002304 TEST_REQUIRES_PSIMD;
2305 for (size_t channels = 5; channels < 8; channels++) {
2306 MaxPoolMicrokernelTester()
2307 .pooling_elements(17)
2308 .pooling_tile(9, 8)
2309 .channels(channels)
2310 .input_offset(11)
Marat Dukhan99936602020-04-11 16:47:01 -07002311 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002312 }
2313 }
2314
Marat Dukhan99936602020-04-11 16:47:01 -07002315 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_gt_4_twopass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08002316 TEST_REQUIRES_PSIMD;
2317 for (size_t channels = 5; channels < 8; channels++) {
2318 MaxPoolMicrokernelTester()
2319 .pooling_elements(17)
2320 .pooling_tile(9, 8)
2321 .channels(channels)
2322 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07002323 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002324 }
2325 }
2326
Marat Dukhan99936602020-04-11 16:47:01 -07002327 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_gt_4_twopass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08002328 TEST_REQUIRES_PSIMD;
2329 for (size_t channels = 5; channels < 8; channels++) {
2330 MaxPoolMicrokernelTester()
2331 .pooling_elements(17)
2332 .pooling_tile(9, 8)
2333 .channels(channels)
2334 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07002335 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002336 }
2337 }
2338
Marat Dukhan99936602020-04-11 16:47:01 -07002339 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_gt_4_twopass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -08002340 TEST_REQUIRES_PSIMD;
2341 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
2342 for (size_t channels = 5; channels < 8; channels++) {
2343 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002344 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002345 .pooling_tile(9, 8)
2346 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07002347 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002348 }
2349 }
2350 }
2351
Marat Dukhan99936602020-04-11 16:47:01 -07002352 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_gt_4_twopass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08002353 TEST_REQUIRES_PSIMD;
2354 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
2355 for (size_t channels = 5; channels < 8; channels++) {
2356 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002357 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002358 .pooling_tile(9, 8)
2359 .channels(channels)
2360 .input_offset(11)
Marat Dukhan99936602020-04-11 16:47:01 -07002361 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002362 }
2363 }
2364 }
2365
Marat Dukhan99936602020-04-11 16:47:01 -07002366 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_eq_4_multipass) {
Marat Dukhan329da642019-11-19 21:44:39 -08002367 TEST_REQUIRES_PSIMD;
2368 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2369 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002370 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002371 .pooling_tile(9, 8)
2372 .channels(4)
Marat Dukhan99936602020-04-11 16:47:01 -07002373 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002374 }
2375 }
2376
Marat Dukhan99936602020-04-11 16:47:01 -07002377 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_eq_4_multipass_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08002378 TEST_REQUIRES_PSIMD;
2379 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2380 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002381 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002382 .pooling_tile(9, 8)
2383 .channels(4)
2384 .input_offset(7)
Marat Dukhan99936602020-04-11 16:47:01 -07002385 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002386 }
2387 }
2388
Marat Dukhan99936602020-04-11 16:47:01 -07002389 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_eq_4_multipass_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08002390 TEST_REQUIRES_PSIMD;
2391 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2392 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002393 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002394 .pooling_tile(9, 8)
2395 .channels(4)
2396 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07002397 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002398 }
2399 }
2400
Marat Dukhan99936602020-04-11 16:47:01 -07002401 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_eq_4_multipass_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08002402 TEST_REQUIRES_PSIMD;
2403 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2404 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002405 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002406 .pooling_tile(9, 8)
2407 .channels(4)
2408 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07002409 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002410 }
2411 }
2412
Marat Dukhan99936602020-04-11 16:47:01 -07002413 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_div_4_multipass) {
Marat Dukhan329da642019-11-19 21:44:39 -08002414 TEST_REQUIRES_PSIMD;
2415 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2416 for (size_t channels = 8; channels < 32; channels += 4) {
2417 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002418 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002419 .pooling_tile(9, 8)
2420 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07002421 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002422 }
2423 }
2424 }
2425
Marat Dukhan99936602020-04-11 16:47:01 -07002426 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_div_4_multipass_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08002427 TEST_REQUIRES_PSIMD;
2428 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2429 for (size_t channels = 8; channels < 32; channels += 4) {
2430 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002431 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002432 .pooling_tile(9, 8)
2433 .channels(channels)
2434 .input_offset(37)
Marat Dukhan99936602020-04-11 16:47:01 -07002435 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002436 }
2437 }
2438 }
2439
Marat Dukhan99936602020-04-11 16:47:01 -07002440 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_div_4_multipass_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08002441 TEST_REQUIRES_PSIMD;
2442 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2443 for (size_t channels = 8; channels < 32; channels += 4) {
2444 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002445 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002446 .pooling_tile(9, 8)
2447 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07002448 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07002449 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002450 }
2451 }
2452 }
2453
Marat Dukhan99936602020-04-11 16:47:01 -07002454 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_div_4_multipass_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08002455 TEST_REQUIRES_PSIMD;
2456 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2457 for (size_t channels = 8; channels < 32; channels += 4) {
2458 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002459 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002460 .pooling_tile(9, 8)
2461 .channels(channels)
2462 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07002463 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002464 }
2465 }
2466 }
2467
Marat Dukhan99936602020-04-11 16:47:01 -07002468 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_lt_4_multipass) {
Marat Dukhan329da642019-11-19 21:44:39 -08002469 TEST_REQUIRES_PSIMD;
2470 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2471 for (size_t channels = 1; channels < 4; channels++) {
2472 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002473 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002474 .pooling_tile(9, 8)
2475 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07002476 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002477 }
2478 }
2479 }
2480
Marat Dukhan99936602020-04-11 16:47:01 -07002481 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_lt_4_multipass_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08002482 TEST_REQUIRES_PSIMD;
2483 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2484 for (size_t channels = 1; channels < 4; channels++) {
2485 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002486 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002487 .pooling_tile(9, 8)
2488 .channels(channels)
2489 .input_offset(4)
Marat Dukhan99936602020-04-11 16:47:01 -07002490 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002491 }
2492 }
2493 }
2494
Marat Dukhan99936602020-04-11 16:47:01 -07002495 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_lt_4_multipass_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08002496 TEST_REQUIRES_PSIMD;
2497 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2498 for (size_t channels = 1; channels < 4; channels++) {
2499 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002500 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002501 .pooling_tile(9, 8)
2502 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07002503 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07002504 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002505 }
2506 }
2507 }
2508
Marat Dukhan99936602020-04-11 16:47:01 -07002509 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_lt_4_multipass_with_qmax) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07002510 TEST_REQUIRES_PSIMD;
Marat Dukhan329da642019-11-19 21:44:39 -08002511 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2512 for (size_t channels = 1; channels < 4; channels++) {
2513 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002514 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002515 .pooling_tile(9, 8)
2516 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07002517 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07002518 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002519 }
2520 }
2521 }
2522
Marat Dukhan99936602020-04-11 16:47:01 -07002523 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_gt_4_multipass) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07002524 TEST_REQUIRES_PSIMD;
Marat Dukhan329da642019-11-19 21:44:39 -08002525 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2526 for (size_t channels = 5; channels < 8; channels++) {
2527 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002528 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002529 .pooling_tile(9, 8)
2530 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07002531 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002532 }
2533 }
2534 }
2535
Marat Dukhan99936602020-04-11 16:47:01 -07002536 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_gt_4_multipass_with_input_offset) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07002537 TEST_REQUIRES_PSIMD;
Marat Dukhan329da642019-11-19 21:44:39 -08002538 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2539 for (size_t channels = 5; channels < 8; channels++) {
2540 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002541 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002542 .pooling_tile(9, 8)
2543 .channels(channels)
2544 .input_offset(11)
Marat Dukhan99936602020-04-11 16:47:01 -07002545 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002546 }
2547 }
2548 }
2549
Marat Dukhan99936602020-04-11 16:47:01 -07002550 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_gt_4_multipass_with_qmin) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07002551 TEST_REQUIRES_PSIMD;
Marat Dukhan329da642019-11-19 21:44:39 -08002552 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2553 for (size_t channels = 5; channels < 8; channels++) {
2554 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002555 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002556 .pooling_tile(9, 8)
2557 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07002558 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07002559 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002560 }
2561 }
2562 }
2563
Marat Dukhan99936602020-04-11 16:47:01 -07002564 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, channels_gt_4_multipass_with_qmax) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07002565 TEST_REQUIRES_PSIMD;
Marat Dukhan329da642019-11-19 21:44:39 -08002566 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2567 for (size_t channels = 5; channels < 8; channels++) {
2568 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002569 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002570 .pooling_tile(9, 8)
2571 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07002572 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07002573 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002574 }
2575 }
2576 }
2577
Marat Dukhan99936602020-04-11 16:47:01 -07002578 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, few_output_pixels) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07002579 TEST_REQUIRES_PSIMD;
Marat Dukhan329da642019-11-19 21:44:39 -08002580 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
2581 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
2582 for (size_t channels = 1; channels <= 20; channels += 3) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07002583 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -08002584 .output_pixels(output_pixels)
2585 .pooling_elements(pooling_elements)
2586 .pooling_tile(9, 8)
2587 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07002588 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002589 }
2590 }
2591 }
2592 }
2593
Marat Dukhan99936602020-04-11 16:47:01 -07002594 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, few_output_pixels_with_input_offset) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07002595 TEST_REQUIRES_PSIMD;
Marat Dukhan329da642019-11-19 21:44:39 -08002596 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
2597 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
2598 for (size_t channels = 1; channels <= 20; channels += 3) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07002599 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -08002600 .output_pixels(output_pixels)
2601 .pooling_elements(pooling_elements)
2602 .pooling_tile(9, 8)
2603 .channels(channels)
2604 .input_offset(23)
Marat Dukhan99936602020-04-11 16:47:01 -07002605 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002606 }
2607 }
2608 }
2609 }
2610
Marat Dukhan99936602020-04-11 16:47:01 -07002611 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, few_output_pixels_with_qmin) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07002612 TEST_REQUIRES_PSIMD;
Marat Dukhan329da642019-11-19 21:44:39 -08002613 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
2614 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
2615 for (size_t channels = 1; channels <= 20; channels += 3) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07002616 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -08002617 .output_pixels(output_pixels)
2618 .pooling_elements(pooling_elements)
2619 .pooling_tile(9, 8)
2620 .channels(channels)
2621 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07002622 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002623 }
2624 }
2625 }
2626 }
2627
Marat Dukhan99936602020-04-11 16:47:01 -07002628 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, few_output_pixels_with_qmax) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07002629 TEST_REQUIRES_PSIMD;
Marat Dukhan329da642019-11-19 21:44:39 -08002630 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
2631 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
2632 for (size_t channels = 1; channels <= 20; channels += 3) {
2633 MaxPoolMicrokernelTester()
2634 .output_pixels(output_pixels)
2635 .pooling_elements(pooling_elements)
2636 .pooling_tile(9, 8)
2637 .channels(channels)
2638 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07002639 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002640 }
2641 }
2642 }
2643 }
2644
Marat Dukhan99936602020-04-11 16:47:01 -07002645 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, few_output_pixels_with_output_stride) {
Marat Dukhan329da642019-11-19 21:44:39 -08002646 TEST_REQUIRES_PSIMD;
2647 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
2648 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
2649 for (size_t channels = 1; channels <= 20; channels += 3) {
2650 MaxPoolMicrokernelTester()
2651 .output_pixels(output_pixels)
2652 .pooling_elements(pooling_elements)
2653 .pooling_tile(9, 8)
2654 .channels(channels)
2655 .output_stride(23)
Marat Dukhan99936602020-04-11 16:47:01 -07002656 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08002657 }
2658 }
2659 }
2660 }
2661
Marat Dukhan99936602020-04-11 16:47:01 -07002662 TEST(F32_MAXPOOL_MINMAX_9P8X__PSIMD_C4, few_output_pixels_with_step) {
Marat Dukhan329da642019-11-19 21:44:39 -08002663 TEST_REQUIRES_PSIMD;
2664 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
2665 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
2666 for (size_t channels = 1; channels <= 20; channels += 3) {
2667 for (size_t step = 2; step <= pooling_elements; step++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07002668 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -08002669 .output_pixels(output_pixels)
2670 .pooling_elements(pooling_elements)
2671 .pooling_tile(9, 8)
2672 .step(step)
2673 .channels(channels)
2674 .output_stride(23)
Marat Dukhan99936602020-04-11 16:47:01 -07002675 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__psimd_c4, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002676 }
2677 }
2678 }
2679 }
2680 }
Marat Dukhan29c6b262020-04-14 18:07:56 -07002681#endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC
XNNPACK Teamb455b122019-09-27 18:10:33 -07002682
2683
Marat Dukhanf6e24802020-07-08 22:20:40 -07002684#if XNN_ARCH_WASMSIMD
2685 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_eq_4_unipass_fulltile) {
2686 MaxPoolMicrokernelTester()
2687 .pooling_elements(9)
2688 .pooling_tile(9, 8)
2689 .channels(4)
2690 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2691 }
2692
2693 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_eq_4_unipass_fulltile_with_input_offset) {
2694 MaxPoolMicrokernelTester()
2695 .pooling_elements(9)
2696 .pooling_tile(9, 8)
2697 .channels(4)
2698 .input_offset(7)
2699 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2700 }
2701
2702 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_eq_4_unipass_fulltile_with_qmin) {
2703 MaxPoolMicrokernelTester()
2704 .pooling_elements(9)
2705 .pooling_tile(9, 8)
2706 .channels(4)
2707 .qmin(192)
2708 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2709 }
2710
2711 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_eq_4_unipass_fulltile_with_qmax) {
2712 MaxPoolMicrokernelTester()
2713 .pooling_elements(9)
2714 .pooling_tile(9, 8)
2715 .channels(4)
2716 .qmax(192)
2717 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2718 }
2719
2720 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_eq_4_unipass_subtile) {
2721 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
2722 MaxPoolMicrokernelTester()
2723 .pooling_elements(pooling_elements)
2724 .pooling_tile(9, 8)
2725 .channels(4)
2726 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2727 }
2728 }
2729
2730 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_eq_4_unipass_subtile_with_input_offset) {
2731 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
2732 MaxPoolMicrokernelTester()
2733 .pooling_elements(pooling_elements)
2734 .pooling_tile(9, 8)
2735 .channels(4)
2736 .input_offset(7)
2737 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2738 }
2739 }
2740
2741 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_div_4_unipass_fulltile) {
2742 for (size_t channels = 8; channels < 32; channels += 4) {
2743 MaxPoolMicrokernelTester()
2744 .pooling_elements(9)
2745 .pooling_tile(9, 8)
2746 .channels(channels)
2747 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2748 }
2749 }
2750
2751 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_div_4_unipass_fulltile_with_input_offset) {
2752 for (size_t channels = 8; channels < 32; channels += 4) {
2753 MaxPoolMicrokernelTester()
2754 .pooling_elements(9)
2755 .pooling_tile(9, 8)
2756 .channels(channels)
2757 .input_offset(37)
2758 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2759 }
2760 }
2761
2762 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_div_4_unipass_fulltile_with_qmin) {
2763 for (size_t channels = 8; channels < 32; channels += 4) {
2764 MaxPoolMicrokernelTester()
2765 .pooling_elements(9)
2766 .pooling_tile(9, 8)
2767 .channels(channels)
2768 .qmin(192)
2769 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2770 }
2771 }
2772
2773 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_div_4_unipass_fulltile_with_qmax) {
2774 for (size_t channels = 8; channels < 32; channels += 4) {
2775 MaxPoolMicrokernelTester()
2776 .pooling_elements(9)
2777 .pooling_tile(9, 8)
2778 .channels(channels)
2779 .qmax(192)
2780 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2781 }
2782 }
2783
2784 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_div_4_unipass_subtile) {
2785 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
2786 for (size_t channels = 8; channels < 32; channels += 4) {
2787 MaxPoolMicrokernelTester()
2788 .pooling_elements(pooling_elements)
2789 .pooling_tile(9, 8)
2790 .channels(channels)
2791 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2792 }
2793 }
2794 }
2795
2796 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_div_4_unipass_subtile_with_input_offset) {
2797 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
2798 for (size_t channels = 8; channels < 32; channels += 4) {
2799 MaxPoolMicrokernelTester()
2800 .pooling_elements(pooling_elements)
2801 .pooling_tile(9, 8)
2802 .channels(channels)
2803 .input_offset(37)
2804 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2805 }
2806 }
2807 }
2808
2809 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_lt_4_unipass_fulltile) {
2810 for (size_t channels = 1; channels < 4; channels++) {
2811 MaxPoolMicrokernelTester()
2812 .pooling_elements(9)
2813 .pooling_tile(9, 8)
2814 .channels(channels)
2815 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2816 }
2817 }
2818
2819 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_lt_4_unipass_fulltile_with_input_offset) {
2820 for (size_t channels = 1; channels < 4; channels++) {
2821 MaxPoolMicrokernelTester()
2822 .pooling_elements(9)
2823 .pooling_tile(9, 8)
2824 .channels(channels)
2825 .input_offset(5)
2826 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2827 }
2828 }
2829
2830 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_lt_4_unipass_fulltile_with_qmin) {
2831 for (size_t channels = 1; channels < 4; channels++) {
2832 MaxPoolMicrokernelTester()
2833 .pooling_elements(9)
2834 .pooling_tile(9, 8)
2835 .channels(channels)
2836 .qmin(192)
2837 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2838 }
2839 }
2840
2841 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_lt_4_unipass_fulltile_with_qmax) {
2842 for (size_t channels = 1; channels < 4; channels++) {
2843 MaxPoolMicrokernelTester()
2844 .pooling_elements(9)
2845 .pooling_tile(9, 8)
2846 .channels(channels)
2847 .qmax(192)
2848 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2849 }
2850 }
2851
2852 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_lt_4_unipass_subtile) {
2853 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
2854 for (size_t channels = 1; channels < 4; channels++) {
2855 MaxPoolMicrokernelTester()
2856 .pooling_elements(pooling_elements)
2857 .pooling_tile(9, 8)
2858 .channels(channels)
2859 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2860 }
2861 }
2862 }
2863
2864 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_lt_4_unipass_subtile_with_input_offset) {
2865 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
2866 for (size_t channels = 1; channels < 4; channels++) {
2867 MaxPoolMicrokernelTester()
2868 .pooling_elements(pooling_elements)
2869 .pooling_tile(9, 8)
2870 .channels(channels)
2871 .input_offset(5)
2872 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2873 }
2874 }
2875 }
2876
2877 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_gt_4_unipass_fulltile) {
2878 for (size_t channels = 5; channels < 8; channels++) {
2879 MaxPoolMicrokernelTester()
2880 .pooling_elements(9)
2881 .pooling_tile(9, 8)
2882 .channels(channels)
2883 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2884 }
2885 }
2886
2887 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_gt_4_unipass_fulltile_with_input_offset) {
2888 for (size_t channels = 5; channels < 8; channels++) {
2889 MaxPoolMicrokernelTester()
2890 .pooling_elements(9)
2891 .pooling_tile(9, 8)
2892 .channels(channels)
2893 .input_offset(11)
2894 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2895 }
2896 }
2897
2898 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_gt_4_unipass_fulltile_with_qmin) {
2899 for (size_t channels = 5; channels < 8; channels++) {
2900 MaxPoolMicrokernelTester()
2901 .pooling_elements(9)
2902 .pooling_tile(9, 8)
2903 .channels(channels)
2904 .qmin(192)
2905 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2906 }
2907 }
2908
2909 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_gt_4_unipass_fulltile_with_qmax) {
2910 for (size_t channels = 5; channels < 8; channels++) {
2911 MaxPoolMicrokernelTester()
2912 .pooling_elements(9)
2913 .pooling_tile(9, 8)
2914 .channels(channels)
2915 .qmax(192)
2916 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2917 }
2918 }
2919
2920 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_gt_4_unipass_subtile) {
2921 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
2922 for (size_t channels = 5; channels < 8; channels++) {
2923 MaxPoolMicrokernelTester()
2924 .pooling_elements(pooling_elements)
2925 .pooling_tile(9, 8)
2926 .channels(channels)
2927 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2928 }
2929 }
2930 }
2931
2932 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_gt_4_unipass_subtile_with_input_offset) {
2933 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
2934 for (size_t channels = 5; channels < 8; channels++) {
2935 MaxPoolMicrokernelTester()
2936 .pooling_elements(pooling_elements)
2937 .pooling_tile(9, 8)
2938 .channels(channels)
2939 .input_offset(11)
2940 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2941 }
2942 }
2943 }
2944
2945 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_eq_4_twopass_fulltile) {
2946 MaxPoolMicrokernelTester()
2947 .pooling_elements(17)
2948 .pooling_tile(9, 8)
2949 .channels(4)
2950 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2951 }
2952
2953 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_eq_4_twopass_fulltile_with_input_offset) {
2954 MaxPoolMicrokernelTester()
2955 .pooling_elements(17)
2956 .pooling_tile(9, 8)
2957 .channels(4)
2958 .input_offset(7)
2959 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2960 }
2961
2962 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_eq_4_twopass_fulltile_with_qmin) {
2963 MaxPoolMicrokernelTester()
2964 .pooling_elements(17)
2965 .pooling_tile(9, 8)
2966 .channels(4)
2967 .qmin(192)
2968 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2969 }
2970
2971 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_eq_4_twopass_fulltile_with_qmax) {
2972 MaxPoolMicrokernelTester()
2973 .pooling_elements(17)
2974 .pooling_tile(9, 8)
2975 .channels(4)
2976 .qmax(192)
2977 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2978 }
2979
2980 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_eq_4_twopass_subtile) {
2981 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
2982 MaxPoolMicrokernelTester()
2983 .pooling_elements(pooling_elements)
2984 .pooling_tile(9, 8)
2985 .channels(4)
2986 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2987 }
2988 }
2989
2990 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_eq_4_twopass_subtile_with_input_offset) {
2991 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
2992 MaxPoolMicrokernelTester()
2993 .pooling_elements(pooling_elements)
2994 .pooling_tile(9, 8)
2995 .channels(4)
2996 .input_offset(7)
2997 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
2998 }
2999 }
3000
3001 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_div_4_twopass_fulltile) {
3002 for (size_t channels = 8; channels < 32; channels += 4) {
3003 MaxPoolMicrokernelTester()
3004 .pooling_elements(17)
3005 .pooling_tile(9, 8)
3006 .channels(channels)
3007 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3008 }
3009 }
3010
3011 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_div_4_twopass_fulltile_with_input_offset) {
3012 for (size_t channels = 8; channels < 32; channels += 4) {
3013 MaxPoolMicrokernelTester()
3014 .pooling_elements(17)
3015 .pooling_tile(9, 8)
3016 .channels(channels)
3017 .input_offset(23)
3018 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3019 }
3020 }
3021
3022 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_div_4_twopass_fulltile_with_qmin) {
3023 for (size_t channels = 8; channels < 32; channels += 4) {
3024 MaxPoolMicrokernelTester()
3025 .pooling_elements(17)
3026 .pooling_tile(9, 8)
3027 .channels(channels)
3028 .qmin(192)
3029 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3030 }
3031 }
3032
3033 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_div_4_twopass_fulltile_with_qmax) {
3034 for (size_t channels = 8; channels < 32; channels += 4) {
3035 MaxPoolMicrokernelTester()
3036 .pooling_elements(17)
3037 .pooling_tile(9, 8)
3038 .channels(channels)
3039 .qmax(192)
3040 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3041 }
3042 }
3043
3044 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_div_4_twopass_subtile) {
3045 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
3046 for (size_t channels = 8; channels < 32; channels += 4) {
3047 MaxPoolMicrokernelTester()
3048 .pooling_elements(pooling_elements)
3049 .pooling_tile(9, 8)
3050 .channels(channels)
3051 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3052 }
3053 }
3054 }
3055
3056 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_div_4_twopass_subtile_with_input_offset) {
3057 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
3058 for (size_t channels = 8; channels < 32; channels += 4) {
3059 MaxPoolMicrokernelTester()
3060 .pooling_elements(pooling_elements)
3061 .pooling_tile(9, 8)
3062 .channels(channels)
3063 .input_offset(37)
3064 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3065 }
3066 }
3067 }
3068
3069 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_lt_4_twopass_fulltile) {
3070 for (size_t channels = 1; channels < 4; channels++) {
3071 MaxPoolMicrokernelTester()
3072 .pooling_elements(17)
3073 .pooling_tile(9, 8)
3074 .channels(channels)
3075 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3076 }
3077 }
3078
3079 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_lt_4_twopass_fulltile_with_input_offset) {
3080 for (size_t channels = 1; channels < 4; channels++) {
3081 MaxPoolMicrokernelTester()
3082 .pooling_elements(17)
3083 .pooling_tile(9, 8)
3084 .channels(channels)
3085 .input_offset(5)
3086 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3087 }
3088 }
3089
3090 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_lt_4_twopass_fulltile_with_qmin) {
3091 for (size_t channels = 1; channels < 4; channels++) {
3092 MaxPoolMicrokernelTester()
3093 .pooling_elements(17)
3094 .pooling_tile(9, 8)
3095 .channels(channels)
3096 .qmin(192)
3097 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3098 }
3099 }
3100
3101 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_lt_4_twopass_fulltile_with_qmax) {
3102 for (size_t channels = 1; channels < 4; channels++) {
3103 MaxPoolMicrokernelTester()
3104 .pooling_elements(17)
3105 .pooling_tile(9, 8)
3106 .channels(channels)
3107 .qmax(192)
3108 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3109 }
3110 }
3111
3112 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_lt_4_twopass_subtile) {
3113 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
3114 for (size_t channels = 1; channels < 4; channels++) {
3115 MaxPoolMicrokernelTester()
3116 .pooling_elements(pooling_elements)
3117 .pooling_tile(9, 8)
3118 .channels(channels)
3119 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3120 }
3121 }
3122 }
3123
3124 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_lt_4_twopass_subtile_with_input_offset) {
3125 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
3126 for (size_t channels = 1; channels < 4; channels++) {
3127 MaxPoolMicrokernelTester()
3128 .pooling_elements(pooling_elements)
3129 .pooling_tile(9, 8)
3130 .channels(channels)
3131 .input_offset(5)
3132 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3133 }
3134 }
3135 }
3136
3137 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_gt_4_twopass_fulltile) {
3138 for (size_t channels = 5; channels < 8; channels++) {
3139 MaxPoolMicrokernelTester()
3140 .pooling_elements(17)
3141 .pooling_tile(9, 8)
3142 .channels(channels)
3143 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3144 }
3145 }
3146
3147 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_gt_4_twopass_fulltile_with_input_offset) {
3148 for (size_t channels = 5; channels < 8; channels++) {
3149 MaxPoolMicrokernelTester()
3150 .pooling_elements(17)
3151 .pooling_tile(9, 8)
3152 .channels(channels)
3153 .input_offset(11)
3154 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3155 }
3156 }
3157
3158 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_gt_4_twopass_fulltile_with_qmin) {
3159 for (size_t channels = 5; channels < 8; channels++) {
3160 MaxPoolMicrokernelTester()
3161 .pooling_elements(17)
3162 .pooling_tile(9, 8)
3163 .channels(channels)
3164 .qmin(192)
3165 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3166 }
3167 }
3168
3169 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_gt_4_twopass_fulltile_with_qmax) {
3170 for (size_t channels = 5; channels < 8; channels++) {
3171 MaxPoolMicrokernelTester()
3172 .pooling_elements(17)
3173 .pooling_tile(9, 8)
3174 .channels(channels)
3175 .qmax(192)
3176 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3177 }
3178 }
3179
3180 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_gt_4_twopass_subtile) {
3181 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
3182 for (size_t channels = 5; channels < 8; channels++) {
3183 MaxPoolMicrokernelTester()
3184 .pooling_elements(pooling_elements)
3185 .pooling_tile(9, 8)
3186 .channels(channels)
3187 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3188 }
3189 }
3190 }
3191
3192 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_gt_4_twopass_subtile_with_input_offset) {
3193 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
3194 for (size_t channels = 5; channels < 8; channels++) {
3195 MaxPoolMicrokernelTester()
3196 .pooling_elements(pooling_elements)
3197 .pooling_tile(9, 8)
3198 .channels(channels)
3199 .input_offset(11)
3200 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3201 }
3202 }
3203 }
3204
3205 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_eq_4_multipass) {
3206 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
3207 MaxPoolMicrokernelTester()
3208 .pooling_elements(pooling_elements)
3209 .pooling_tile(9, 8)
3210 .channels(4)
3211 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3212 }
3213 }
3214
3215 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_eq_4_multipass_with_input_offset) {
3216 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
3217 MaxPoolMicrokernelTester()
3218 .pooling_elements(pooling_elements)
3219 .pooling_tile(9, 8)
3220 .channels(4)
3221 .input_offset(7)
3222 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3223 }
3224 }
3225
3226 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_eq_4_multipass_with_qmin) {
3227 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
3228 MaxPoolMicrokernelTester()
3229 .pooling_elements(pooling_elements)
3230 .pooling_tile(9, 8)
3231 .channels(4)
3232 .qmin(192)
3233 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3234 }
3235 }
3236
3237 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_eq_4_multipass_with_qmax) {
3238 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
3239 MaxPoolMicrokernelTester()
3240 .pooling_elements(pooling_elements)
3241 .pooling_tile(9, 8)
3242 .channels(4)
3243 .qmax(192)
3244 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3245 }
3246 }
3247
3248 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_div_4_multipass) {
3249 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
3250 for (size_t channels = 8; channels < 32; channels += 4) {
3251 MaxPoolMicrokernelTester()
3252 .pooling_elements(pooling_elements)
3253 .pooling_tile(9, 8)
3254 .channels(channels)
3255 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3256 }
3257 }
3258 }
3259
3260 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_div_4_multipass_with_input_offset) {
3261 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
3262 for (size_t channels = 8; channels < 32; channels += 4) {
3263 MaxPoolMicrokernelTester()
3264 .pooling_elements(pooling_elements)
3265 .pooling_tile(9, 8)
3266 .channels(channels)
3267 .input_offset(37)
3268 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3269 }
3270 }
3271 }
3272
3273 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_div_4_multipass_with_qmin) {
3274 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
3275 for (size_t channels = 8; channels < 32; channels += 4) {
3276 MaxPoolMicrokernelTester()
3277 .pooling_elements(pooling_elements)
3278 .pooling_tile(9, 8)
3279 .channels(channels)
3280 .qmin(192)
3281 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3282 }
3283 }
3284 }
3285
3286 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_div_4_multipass_with_qmax) {
3287 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
3288 for (size_t channels = 8; channels < 32; channels += 4) {
3289 MaxPoolMicrokernelTester()
3290 .pooling_elements(pooling_elements)
3291 .pooling_tile(9, 8)
3292 .channels(channels)
3293 .qmax(192)
3294 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3295 }
3296 }
3297 }
3298
3299 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_lt_4_multipass) {
3300 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
3301 for (size_t channels = 1; channels < 4; channels++) {
3302 MaxPoolMicrokernelTester()
3303 .pooling_elements(pooling_elements)
3304 .pooling_tile(9, 8)
3305 .channels(channels)
3306 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3307 }
3308 }
3309 }
3310
3311 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_lt_4_multipass_with_input_offset) {
3312 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
3313 for (size_t channels = 1; channels < 4; channels++) {
3314 MaxPoolMicrokernelTester()
3315 .pooling_elements(pooling_elements)
3316 .pooling_tile(9, 8)
3317 .channels(channels)
3318 .input_offset(4)
3319 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3320 }
3321 }
3322 }
3323
3324 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_lt_4_multipass_with_qmin) {
3325 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
3326 for (size_t channels = 1; channels < 4; channels++) {
3327 MaxPoolMicrokernelTester()
3328 .pooling_elements(pooling_elements)
3329 .pooling_tile(9, 8)
3330 .channels(channels)
3331 .qmin(192)
3332 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3333 }
3334 }
3335 }
3336
3337 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_lt_4_multipass_with_qmax) {
3338 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
3339 for (size_t channels = 1; channels < 4; channels++) {
3340 MaxPoolMicrokernelTester()
3341 .pooling_elements(pooling_elements)
3342 .pooling_tile(9, 8)
3343 .channels(channels)
3344 .qmax(192)
3345 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3346 }
3347 }
3348 }
3349
3350 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_gt_4_multipass) {
3351 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
3352 for (size_t channels = 5; channels < 8; channels++) {
3353 MaxPoolMicrokernelTester()
3354 .pooling_elements(pooling_elements)
3355 .pooling_tile(9, 8)
3356 .channels(channels)
3357 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3358 }
3359 }
3360 }
3361
3362 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_gt_4_multipass_with_input_offset) {
3363 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
3364 for (size_t channels = 5; channels < 8; channels++) {
3365 MaxPoolMicrokernelTester()
3366 .pooling_elements(pooling_elements)
3367 .pooling_tile(9, 8)
3368 .channels(channels)
3369 .input_offset(11)
3370 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3371 }
3372 }
3373 }
3374
3375 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_gt_4_multipass_with_qmin) {
3376 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
3377 for (size_t channels = 5; channels < 8; channels++) {
3378 MaxPoolMicrokernelTester()
3379 .pooling_elements(pooling_elements)
3380 .pooling_tile(9, 8)
3381 .channels(channels)
3382 .qmin(192)
3383 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3384 }
3385 }
3386 }
3387
3388 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_gt_4_multipass_with_qmax) {
3389 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
3390 for (size_t channels = 5; channels < 8; channels++) {
3391 MaxPoolMicrokernelTester()
3392 .pooling_elements(pooling_elements)
3393 .pooling_tile(9, 8)
3394 .channels(channels)
3395 .qmax(192)
3396 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3397 }
3398 }
3399 }
3400
3401 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, few_output_pixels) {
3402 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
3403 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
3404 for (size_t channels = 1; channels <= 20; channels += 3) {
3405 MaxPoolMicrokernelTester()
3406 .output_pixels(output_pixels)
3407 .pooling_elements(pooling_elements)
3408 .pooling_tile(9, 8)
3409 .channels(channels)
3410 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3411 }
3412 }
3413 }
3414 }
3415
3416 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, few_output_pixels_with_input_offset) {
3417 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
3418 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
3419 for (size_t channels = 1; channels <= 20; channels += 3) {
3420 MaxPoolMicrokernelTester()
3421 .output_pixels(output_pixels)
3422 .pooling_elements(pooling_elements)
3423 .pooling_tile(9, 8)
3424 .channels(channels)
3425 .input_offset(23)
3426 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3427 }
3428 }
3429 }
3430 }
3431
3432 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, few_output_pixels_with_qmin) {
3433 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
3434 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
3435 for (size_t channels = 1; channels <= 20; channels += 3) {
3436 MaxPoolMicrokernelTester()
3437 .output_pixels(output_pixels)
3438 .pooling_elements(pooling_elements)
3439 .pooling_tile(9, 8)
3440 .channels(channels)
3441 .qmin(192)
3442 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3443 }
3444 }
3445 }
3446 }
3447
3448 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, few_output_pixels_with_qmax) {
3449 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
3450 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
3451 for (size_t channels = 1; channels <= 20; channels += 3) {
3452 MaxPoolMicrokernelTester()
3453 .output_pixels(output_pixels)
3454 .pooling_elements(pooling_elements)
3455 .pooling_tile(9, 8)
3456 .channels(channels)
3457 .qmax(192)
3458 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3459 }
3460 }
3461 }
3462 }
3463
3464 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, few_output_pixels_with_output_stride) {
3465 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
3466 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
3467 for (size_t channels = 1; channels <= 20; channels += 3) {
3468 MaxPoolMicrokernelTester()
3469 .output_pixels(output_pixels)
3470 .pooling_elements(pooling_elements)
3471 .pooling_tile(9, 8)
3472 .channels(channels)
3473 .output_stride(23)
3474 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3475 }
3476 }
3477 }
3478 }
3479
3480 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, few_output_pixels_with_step) {
3481 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
3482 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
3483 for (size_t channels = 1; channels <= 20; channels += 3) {
3484 for (size_t step = 2; step <= pooling_elements; step++) {
3485 MaxPoolMicrokernelTester()
3486 .output_pixels(output_pixels)
3487 .pooling_elements(pooling_elements)
3488 .pooling_tile(9, 8)
3489 .step(step)
3490 .channels(channels)
3491 .output_stride(23)
3492 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_arm_c4);
3493 }
3494 }
3495 }
3496 }
3497 }
3498#endif // XNN_ARCH_WASMSIMD
3499
3500
3501#if XNN_ARCH_WASMSIMD
3502 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_eq_4_unipass_fulltile) {
3503 MaxPoolMicrokernelTester()
3504 .pooling_elements(9)
3505 .pooling_tile(9, 8)
3506 .channels(4)
3507 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3508 }
3509
3510 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_eq_4_unipass_fulltile_with_input_offset) {
3511 MaxPoolMicrokernelTester()
3512 .pooling_elements(9)
3513 .pooling_tile(9, 8)
3514 .channels(4)
3515 .input_offset(7)
3516 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3517 }
3518
3519 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_eq_4_unipass_fulltile_with_qmin) {
3520 MaxPoolMicrokernelTester()
3521 .pooling_elements(9)
3522 .pooling_tile(9, 8)
3523 .channels(4)
3524 .qmin(192)
3525 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3526 }
3527
3528 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_eq_4_unipass_fulltile_with_qmax) {
3529 MaxPoolMicrokernelTester()
3530 .pooling_elements(9)
3531 .pooling_tile(9, 8)
3532 .channels(4)
3533 .qmax(192)
3534 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3535 }
3536
3537 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_eq_4_unipass_subtile) {
3538 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
3539 MaxPoolMicrokernelTester()
3540 .pooling_elements(pooling_elements)
3541 .pooling_tile(9, 8)
3542 .channels(4)
3543 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3544 }
3545 }
3546
3547 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_eq_4_unipass_subtile_with_input_offset) {
3548 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
3549 MaxPoolMicrokernelTester()
3550 .pooling_elements(pooling_elements)
3551 .pooling_tile(9, 8)
3552 .channels(4)
3553 .input_offset(7)
3554 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3555 }
3556 }
3557
3558 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_div_4_unipass_fulltile) {
3559 for (size_t channels = 8; channels < 32; channels += 4) {
3560 MaxPoolMicrokernelTester()
3561 .pooling_elements(9)
3562 .pooling_tile(9, 8)
3563 .channels(channels)
3564 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3565 }
3566 }
3567
3568 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_div_4_unipass_fulltile_with_input_offset) {
3569 for (size_t channels = 8; channels < 32; channels += 4) {
3570 MaxPoolMicrokernelTester()
3571 .pooling_elements(9)
3572 .pooling_tile(9, 8)
3573 .channels(channels)
3574 .input_offset(37)
3575 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3576 }
3577 }
3578
3579 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_div_4_unipass_fulltile_with_qmin) {
3580 for (size_t channels = 8; channels < 32; channels += 4) {
3581 MaxPoolMicrokernelTester()
3582 .pooling_elements(9)
3583 .pooling_tile(9, 8)
3584 .channels(channels)
3585 .qmin(192)
3586 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3587 }
3588 }
3589
3590 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_div_4_unipass_fulltile_with_qmax) {
3591 for (size_t channels = 8; channels < 32; channels += 4) {
3592 MaxPoolMicrokernelTester()
3593 .pooling_elements(9)
3594 .pooling_tile(9, 8)
3595 .channels(channels)
3596 .qmax(192)
3597 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3598 }
3599 }
3600
3601 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_div_4_unipass_subtile) {
3602 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
3603 for (size_t channels = 8; channels < 32; channels += 4) {
3604 MaxPoolMicrokernelTester()
3605 .pooling_elements(pooling_elements)
3606 .pooling_tile(9, 8)
3607 .channels(channels)
3608 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3609 }
3610 }
3611 }
3612
3613 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_div_4_unipass_subtile_with_input_offset) {
3614 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
3615 for (size_t channels = 8; channels < 32; channels += 4) {
3616 MaxPoolMicrokernelTester()
3617 .pooling_elements(pooling_elements)
3618 .pooling_tile(9, 8)
3619 .channels(channels)
3620 .input_offset(37)
3621 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3622 }
3623 }
3624 }
3625
3626 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_lt_4_unipass_fulltile) {
3627 for (size_t channels = 1; channels < 4; channels++) {
3628 MaxPoolMicrokernelTester()
3629 .pooling_elements(9)
3630 .pooling_tile(9, 8)
3631 .channels(channels)
3632 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3633 }
3634 }
3635
3636 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_lt_4_unipass_fulltile_with_input_offset) {
3637 for (size_t channels = 1; channels < 4; channels++) {
3638 MaxPoolMicrokernelTester()
3639 .pooling_elements(9)
3640 .pooling_tile(9, 8)
3641 .channels(channels)
3642 .input_offset(5)
3643 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3644 }
3645 }
3646
3647 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_lt_4_unipass_fulltile_with_qmin) {
3648 for (size_t channels = 1; channels < 4; channels++) {
3649 MaxPoolMicrokernelTester()
3650 .pooling_elements(9)
3651 .pooling_tile(9, 8)
3652 .channels(channels)
3653 .qmin(192)
3654 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3655 }
3656 }
3657
3658 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_lt_4_unipass_fulltile_with_qmax) {
3659 for (size_t channels = 1; channels < 4; channels++) {
3660 MaxPoolMicrokernelTester()
3661 .pooling_elements(9)
3662 .pooling_tile(9, 8)
3663 .channels(channels)
3664 .qmax(192)
3665 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3666 }
3667 }
3668
3669 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_lt_4_unipass_subtile) {
3670 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
3671 for (size_t channels = 1; channels < 4; channels++) {
3672 MaxPoolMicrokernelTester()
3673 .pooling_elements(pooling_elements)
3674 .pooling_tile(9, 8)
3675 .channels(channels)
3676 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3677 }
3678 }
3679 }
3680
3681 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_lt_4_unipass_subtile_with_input_offset) {
3682 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
3683 for (size_t channels = 1; channels < 4; channels++) {
3684 MaxPoolMicrokernelTester()
3685 .pooling_elements(pooling_elements)
3686 .pooling_tile(9, 8)
3687 .channels(channels)
3688 .input_offset(5)
3689 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3690 }
3691 }
3692 }
3693
3694 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_gt_4_unipass_fulltile) {
3695 for (size_t channels = 5; channels < 8; channels++) {
3696 MaxPoolMicrokernelTester()
3697 .pooling_elements(9)
3698 .pooling_tile(9, 8)
3699 .channels(channels)
3700 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3701 }
3702 }
3703
3704 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_gt_4_unipass_fulltile_with_input_offset) {
3705 for (size_t channels = 5; channels < 8; channels++) {
3706 MaxPoolMicrokernelTester()
3707 .pooling_elements(9)
3708 .pooling_tile(9, 8)
3709 .channels(channels)
3710 .input_offset(11)
3711 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3712 }
3713 }
3714
3715 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_gt_4_unipass_fulltile_with_qmin) {
3716 for (size_t channels = 5; channels < 8; channels++) {
3717 MaxPoolMicrokernelTester()
3718 .pooling_elements(9)
3719 .pooling_tile(9, 8)
3720 .channels(channels)
3721 .qmin(192)
3722 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3723 }
3724 }
3725
3726 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_gt_4_unipass_fulltile_with_qmax) {
3727 for (size_t channels = 5; channels < 8; channels++) {
3728 MaxPoolMicrokernelTester()
3729 .pooling_elements(9)
3730 .pooling_tile(9, 8)
3731 .channels(channels)
3732 .qmax(192)
3733 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3734 }
3735 }
3736
3737 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_gt_4_unipass_subtile) {
3738 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
3739 for (size_t channels = 5; channels < 8; channels++) {
3740 MaxPoolMicrokernelTester()
3741 .pooling_elements(pooling_elements)
3742 .pooling_tile(9, 8)
3743 .channels(channels)
3744 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3745 }
3746 }
3747 }
3748
3749 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_gt_4_unipass_subtile_with_input_offset) {
3750 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
3751 for (size_t channels = 5; channels < 8; channels++) {
3752 MaxPoolMicrokernelTester()
3753 .pooling_elements(pooling_elements)
3754 .pooling_tile(9, 8)
3755 .channels(channels)
3756 .input_offset(11)
3757 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3758 }
3759 }
3760 }
3761
3762 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_eq_4_twopass_fulltile) {
3763 MaxPoolMicrokernelTester()
3764 .pooling_elements(17)
3765 .pooling_tile(9, 8)
3766 .channels(4)
3767 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3768 }
3769
3770 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_eq_4_twopass_fulltile_with_input_offset) {
3771 MaxPoolMicrokernelTester()
3772 .pooling_elements(17)
3773 .pooling_tile(9, 8)
3774 .channels(4)
3775 .input_offset(7)
3776 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3777 }
3778
3779 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_eq_4_twopass_fulltile_with_qmin) {
3780 MaxPoolMicrokernelTester()
3781 .pooling_elements(17)
3782 .pooling_tile(9, 8)
3783 .channels(4)
3784 .qmin(192)
3785 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3786 }
3787
3788 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_eq_4_twopass_fulltile_with_qmax) {
3789 MaxPoolMicrokernelTester()
3790 .pooling_elements(17)
3791 .pooling_tile(9, 8)
3792 .channels(4)
3793 .qmax(192)
3794 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3795 }
3796
3797 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_eq_4_twopass_subtile) {
3798 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
3799 MaxPoolMicrokernelTester()
3800 .pooling_elements(pooling_elements)
3801 .pooling_tile(9, 8)
3802 .channels(4)
3803 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3804 }
3805 }
3806
3807 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_eq_4_twopass_subtile_with_input_offset) {
3808 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
3809 MaxPoolMicrokernelTester()
3810 .pooling_elements(pooling_elements)
3811 .pooling_tile(9, 8)
3812 .channels(4)
3813 .input_offset(7)
3814 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3815 }
3816 }
3817
3818 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_div_4_twopass_fulltile) {
3819 for (size_t channels = 8; channels < 32; channels += 4) {
3820 MaxPoolMicrokernelTester()
3821 .pooling_elements(17)
3822 .pooling_tile(9, 8)
3823 .channels(channels)
3824 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3825 }
3826 }
3827
3828 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_div_4_twopass_fulltile_with_input_offset) {
3829 for (size_t channels = 8; channels < 32; channels += 4) {
3830 MaxPoolMicrokernelTester()
3831 .pooling_elements(17)
3832 .pooling_tile(9, 8)
3833 .channels(channels)
3834 .input_offset(23)
3835 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3836 }
3837 }
3838
3839 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_div_4_twopass_fulltile_with_qmin) {
3840 for (size_t channels = 8; channels < 32; channels += 4) {
3841 MaxPoolMicrokernelTester()
3842 .pooling_elements(17)
3843 .pooling_tile(9, 8)
3844 .channels(channels)
3845 .qmin(192)
3846 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3847 }
3848 }
3849
3850 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_div_4_twopass_fulltile_with_qmax) {
3851 for (size_t channels = 8; channels < 32; channels += 4) {
3852 MaxPoolMicrokernelTester()
3853 .pooling_elements(17)
3854 .pooling_tile(9, 8)
3855 .channels(channels)
3856 .qmax(192)
3857 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3858 }
3859 }
3860
3861 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_div_4_twopass_subtile) {
3862 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
3863 for (size_t channels = 8; channels < 32; channels += 4) {
3864 MaxPoolMicrokernelTester()
3865 .pooling_elements(pooling_elements)
3866 .pooling_tile(9, 8)
3867 .channels(channels)
3868 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3869 }
3870 }
3871 }
3872
3873 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_div_4_twopass_subtile_with_input_offset) {
3874 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
3875 for (size_t channels = 8; channels < 32; channels += 4) {
3876 MaxPoolMicrokernelTester()
3877 .pooling_elements(pooling_elements)
3878 .pooling_tile(9, 8)
3879 .channels(channels)
3880 .input_offset(37)
3881 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3882 }
3883 }
3884 }
3885
3886 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_lt_4_twopass_fulltile) {
3887 for (size_t channels = 1; channels < 4; channels++) {
3888 MaxPoolMicrokernelTester()
3889 .pooling_elements(17)
3890 .pooling_tile(9, 8)
3891 .channels(channels)
3892 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3893 }
3894 }
3895
3896 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_lt_4_twopass_fulltile_with_input_offset) {
3897 for (size_t channels = 1; channels < 4; channels++) {
3898 MaxPoolMicrokernelTester()
3899 .pooling_elements(17)
3900 .pooling_tile(9, 8)
3901 .channels(channels)
3902 .input_offset(5)
3903 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3904 }
3905 }
3906
3907 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_lt_4_twopass_fulltile_with_qmin) {
3908 for (size_t channels = 1; channels < 4; channels++) {
3909 MaxPoolMicrokernelTester()
3910 .pooling_elements(17)
3911 .pooling_tile(9, 8)
3912 .channels(channels)
3913 .qmin(192)
3914 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3915 }
3916 }
3917
3918 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_lt_4_twopass_fulltile_with_qmax) {
3919 for (size_t channels = 1; channels < 4; channels++) {
3920 MaxPoolMicrokernelTester()
3921 .pooling_elements(17)
3922 .pooling_tile(9, 8)
3923 .channels(channels)
3924 .qmax(192)
3925 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3926 }
3927 }
3928
3929 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_lt_4_twopass_subtile) {
3930 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
3931 for (size_t channels = 1; channels < 4; channels++) {
3932 MaxPoolMicrokernelTester()
3933 .pooling_elements(pooling_elements)
3934 .pooling_tile(9, 8)
3935 .channels(channels)
3936 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3937 }
3938 }
3939 }
3940
3941 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_lt_4_twopass_subtile_with_input_offset) {
3942 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
3943 for (size_t channels = 1; channels < 4; channels++) {
3944 MaxPoolMicrokernelTester()
3945 .pooling_elements(pooling_elements)
3946 .pooling_tile(9, 8)
3947 .channels(channels)
3948 .input_offset(5)
3949 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3950 }
3951 }
3952 }
3953
3954 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_gt_4_twopass_fulltile) {
3955 for (size_t channels = 5; channels < 8; channels++) {
3956 MaxPoolMicrokernelTester()
3957 .pooling_elements(17)
3958 .pooling_tile(9, 8)
3959 .channels(channels)
3960 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3961 }
3962 }
3963
3964 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_gt_4_twopass_fulltile_with_input_offset) {
3965 for (size_t channels = 5; channels < 8; channels++) {
3966 MaxPoolMicrokernelTester()
3967 .pooling_elements(17)
3968 .pooling_tile(9, 8)
3969 .channels(channels)
3970 .input_offset(11)
3971 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3972 }
3973 }
3974
3975 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_gt_4_twopass_fulltile_with_qmin) {
3976 for (size_t channels = 5; channels < 8; channels++) {
3977 MaxPoolMicrokernelTester()
3978 .pooling_elements(17)
3979 .pooling_tile(9, 8)
3980 .channels(channels)
3981 .qmin(192)
3982 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3983 }
3984 }
3985
3986 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_gt_4_twopass_fulltile_with_qmax) {
3987 for (size_t channels = 5; channels < 8; channels++) {
3988 MaxPoolMicrokernelTester()
3989 .pooling_elements(17)
3990 .pooling_tile(9, 8)
3991 .channels(channels)
3992 .qmax(192)
3993 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
3994 }
3995 }
3996
3997 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_gt_4_twopass_subtile) {
3998 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
3999 for (size_t channels = 5; channels < 8; channels++) {
4000 MaxPoolMicrokernelTester()
4001 .pooling_elements(pooling_elements)
4002 .pooling_tile(9, 8)
4003 .channels(channels)
4004 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4005 }
4006 }
4007 }
4008
4009 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_gt_4_twopass_subtile_with_input_offset) {
4010 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
4011 for (size_t channels = 5; channels < 8; channels++) {
4012 MaxPoolMicrokernelTester()
4013 .pooling_elements(pooling_elements)
4014 .pooling_tile(9, 8)
4015 .channels(channels)
4016 .input_offset(11)
4017 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4018 }
4019 }
4020 }
4021
4022 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_eq_4_multipass) {
4023 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4024 MaxPoolMicrokernelTester()
4025 .pooling_elements(pooling_elements)
4026 .pooling_tile(9, 8)
4027 .channels(4)
4028 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4029 }
4030 }
4031
4032 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_eq_4_multipass_with_input_offset) {
4033 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4034 MaxPoolMicrokernelTester()
4035 .pooling_elements(pooling_elements)
4036 .pooling_tile(9, 8)
4037 .channels(4)
4038 .input_offset(7)
4039 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4040 }
4041 }
4042
4043 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_eq_4_multipass_with_qmin) {
4044 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4045 MaxPoolMicrokernelTester()
4046 .pooling_elements(pooling_elements)
4047 .pooling_tile(9, 8)
4048 .channels(4)
4049 .qmin(192)
4050 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4051 }
4052 }
4053
4054 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_eq_4_multipass_with_qmax) {
4055 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4056 MaxPoolMicrokernelTester()
4057 .pooling_elements(pooling_elements)
4058 .pooling_tile(9, 8)
4059 .channels(4)
4060 .qmax(192)
4061 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4062 }
4063 }
4064
4065 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_div_4_multipass) {
4066 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4067 for (size_t channels = 8; channels < 32; channels += 4) {
4068 MaxPoolMicrokernelTester()
4069 .pooling_elements(pooling_elements)
4070 .pooling_tile(9, 8)
4071 .channels(channels)
4072 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4073 }
4074 }
4075 }
4076
4077 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_div_4_multipass_with_input_offset) {
4078 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4079 for (size_t channels = 8; channels < 32; channels += 4) {
4080 MaxPoolMicrokernelTester()
4081 .pooling_elements(pooling_elements)
4082 .pooling_tile(9, 8)
4083 .channels(channels)
4084 .input_offset(37)
4085 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4086 }
4087 }
4088 }
4089
4090 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_div_4_multipass_with_qmin) {
4091 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4092 for (size_t channels = 8; channels < 32; channels += 4) {
4093 MaxPoolMicrokernelTester()
4094 .pooling_elements(pooling_elements)
4095 .pooling_tile(9, 8)
4096 .channels(channels)
4097 .qmin(192)
4098 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4099 }
4100 }
4101 }
4102
4103 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_div_4_multipass_with_qmax) {
4104 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4105 for (size_t channels = 8; channels < 32; channels += 4) {
4106 MaxPoolMicrokernelTester()
4107 .pooling_elements(pooling_elements)
4108 .pooling_tile(9, 8)
4109 .channels(channels)
4110 .qmax(192)
4111 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4112 }
4113 }
4114 }
4115
4116 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_lt_4_multipass) {
4117 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4118 for (size_t channels = 1; channels < 4; channels++) {
4119 MaxPoolMicrokernelTester()
4120 .pooling_elements(pooling_elements)
4121 .pooling_tile(9, 8)
4122 .channels(channels)
4123 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4124 }
4125 }
4126 }
4127
4128 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_lt_4_multipass_with_input_offset) {
4129 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4130 for (size_t channels = 1; channels < 4; channels++) {
4131 MaxPoolMicrokernelTester()
4132 .pooling_elements(pooling_elements)
4133 .pooling_tile(9, 8)
4134 .channels(channels)
4135 .input_offset(4)
4136 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4137 }
4138 }
4139 }
4140
4141 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_lt_4_multipass_with_qmin) {
4142 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4143 for (size_t channels = 1; channels < 4; channels++) {
4144 MaxPoolMicrokernelTester()
4145 .pooling_elements(pooling_elements)
4146 .pooling_tile(9, 8)
4147 .channels(channels)
4148 .qmin(192)
4149 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4150 }
4151 }
4152 }
4153
4154 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_lt_4_multipass_with_qmax) {
4155 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4156 for (size_t channels = 1; channels < 4; channels++) {
4157 MaxPoolMicrokernelTester()
4158 .pooling_elements(pooling_elements)
4159 .pooling_tile(9, 8)
4160 .channels(channels)
4161 .qmax(192)
4162 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4163 }
4164 }
4165 }
4166
4167 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_gt_4_multipass) {
4168 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4169 for (size_t channels = 5; channels < 8; channels++) {
4170 MaxPoolMicrokernelTester()
4171 .pooling_elements(pooling_elements)
4172 .pooling_tile(9, 8)
4173 .channels(channels)
4174 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4175 }
4176 }
4177 }
4178
4179 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_gt_4_multipass_with_input_offset) {
4180 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4181 for (size_t channels = 5; channels < 8; channels++) {
4182 MaxPoolMicrokernelTester()
4183 .pooling_elements(pooling_elements)
4184 .pooling_tile(9, 8)
4185 .channels(channels)
4186 .input_offset(11)
4187 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4188 }
4189 }
4190 }
4191
4192 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_gt_4_multipass_with_qmin) {
4193 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4194 for (size_t channels = 5; channels < 8; channels++) {
4195 MaxPoolMicrokernelTester()
4196 .pooling_elements(pooling_elements)
4197 .pooling_tile(9, 8)
4198 .channels(channels)
4199 .qmin(192)
4200 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4201 }
4202 }
4203 }
4204
4205 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_gt_4_multipass_with_qmax) {
4206 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4207 for (size_t channels = 5; channels < 8; channels++) {
4208 MaxPoolMicrokernelTester()
4209 .pooling_elements(pooling_elements)
4210 .pooling_tile(9, 8)
4211 .channels(channels)
4212 .qmax(192)
4213 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4214 }
4215 }
4216 }
4217
4218 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, few_output_pixels) {
4219 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
4220 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
4221 for (size_t channels = 1; channels <= 20; channels += 3) {
4222 MaxPoolMicrokernelTester()
4223 .output_pixels(output_pixels)
4224 .pooling_elements(pooling_elements)
4225 .pooling_tile(9, 8)
4226 .channels(channels)
4227 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4228 }
4229 }
4230 }
4231 }
4232
4233 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, few_output_pixels_with_input_offset) {
4234 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
4235 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
4236 for (size_t channels = 1; channels <= 20; channels += 3) {
4237 MaxPoolMicrokernelTester()
4238 .output_pixels(output_pixels)
4239 .pooling_elements(pooling_elements)
4240 .pooling_tile(9, 8)
4241 .channels(channels)
4242 .input_offset(23)
4243 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4244 }
4245 }
4246 }
4247 }
4248
4249 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, few_output_pixels_with_qmin) {
4250 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
4251 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
4252 for (size_t channels = 1; channels <= 20; channels += 3) {
4253 MaxPoolMicrokernelTester()
4254 .output_pixels(output_pixels)
4255 .pooling_elements(pooling_elements)
4256 .pooling_tile(9, 8)
4257 .channels(channels)
4258 .qmin(192)
4259 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4260 }
4261 }
4262 }
4263 }
4264
4265 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, few_output_pixels_with_qmax) {
4266 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
4267 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
4268 for (size_t channels = 1; channels <= 20; channels += 3) {
4269 MaxPoolMicrokernelTester()
4270 .output_pixels(output_pixels)
4271 .pooling_elements(pooling_elements)
4272 .pooling_tile(9, 8)
4273 .channels(channels)
4274 .qmax(192)
4275 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4276 }
4277 }
4278 }
4279 }
4280
4281 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, few_output_pixels_with_output_stride) {
4282 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
4283 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
4284 for (size_t channels = 1; channels <= 20; channels += 3) {
4285 MaxPoolMicrokernelTester()
4286 .output_pixels(output_pixels)
4287 .pooling_elements(pooling_elements)
4288 .pooling_tile(9, 8)
4289 .channels(channels)
4290 .output_stride(23)
4291 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4292 }
4293 }
4294 }
4295 }
4296
4297 TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, few_output_pixels_with_step) {
4298 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
4299 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
4300 for (size_t channels = 1; channels <= 20; channels += 3) {
4301 for (size_t step = 2; step <= pooling_elements; step++) {
4302 MaxPoolMicrokernelTester()
4303 .output_pixels(output_pixels)
4304 .pooling_elements(pooling_elements)
4305 .pooling_tile(9, 8)
4306 .step(step)
4307 .channels(channels)
4308 .output_stride(23)
4309 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasmsimd_x86_c4);
4310 }
4311 }
4312 }
4313 }
4314 }
4315#endif // XNN_ARCH_WASMSIMD
4316
4317
Frank Barchard609ac842020-07-01 12:09:33 -07004318#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
Marat Dukhan99936602020-04-11 16:47:01 -07004319 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_eq_1_unipass_fulltile) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004320 MaxPoolMicrokernelTester()
4321 .pooling_elements(9)
4322 .pooling_tile(9, 8)
4323 .channels(1)
Frank Barchard609ac842020-07-01 12:09:33 -07004324 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004325 }
4326
Marat Dukhan99936602020-04-11 16:47:01 -07004327 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_eq_1_unipass_fulltile_with_input_offset) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004328 MaxPoolMicrokernelTester()
4329 .pooling_elements(9)
4330 .pooling_tile(9, 8)
4331 .channels(1)
4332 .input_offset(3)
Frank Barchard609ac842020-07-01 12:09:33 -07004333 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004334 }
4335
Marat Dukhan99936602020-04-11 16:47:01 -07004336 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_eq_1_unipass_fulltile_with_qmin) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004337 MaxPoolMicrokernelTester()
4338 .pooling_elements(9)
4339 .pooling_tile(9, 8)
4340 .channels(1)
4341 .qmin(192)
Frank Barchard609ac842020-07-01 12:09:33 -07004342 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004343 }
4344
Marat Dukhan99936602020-04-11 16:47:01 -07004345 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_eq_1_unipass_fulltile_with_qmax) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004346 MaxPoolMicrokernelTester()
4347 .pooling_elements(9)
4348 .pooling_tile(9, 8)
4349 .channels(1)
4350 .qmax(192)
Frank Barchard609ac842020-07-01 12:09:33 -07004351 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004352 }
4353
Marat Dukhan99936602020-04-11 16:47:01 -07004354 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_eq_1_unipass_subtile) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004355 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
4356 MaxPoolMicrokernelTester()
4357 .pooling_elements(pooling_elements)
4358 .pooling_tile(9, 8)
4359 .channels(1)
Frank Barchard609ac842020-07-01 12:09:33 -07004360 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004361 }
4362 }
4363
Marat Dukhan99936602020-04-11 16:47:01 -07004364 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_eq_1_unipass_subtile_with_input_offset) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004365 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
4366 MaxPoolMicrokernelTester()
4367 .pooling_elements(pooling_elements)
4368 .pooling_tile(9, 8)
4369 .channels(1)
4370 .input_offset(3)
Frank Barchard609ac842020-07-01 12:09:33 -07004371 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004372 }
4373 }
4374
Marat Dukhan99936602020-04-11 16:47:01 -07004375 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_gt_1_unipass_fulltile) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004376 for (size_t channels = 2; channels < 10; channels++) {
4377 MaxPoolMicrokernelTester()
4378 .pooling_elements(9)
4379 .pooling_tile(9, 8)
4380 .channels(channels)
Frank Barchard609ac842020-07-01 12:09:33 -07004381 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004382 }
4383 }
4384
Marat Dukhan99936602020-04-11 16:47:01 -07004385 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_gt_1_unipass_fulltile_with_input_offset) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004386 for (size_t channels = 2; channels < 10; channels++) {
4387 MaxPoolMicrokernelTester()
4388 .pooling_elements(9)
4389 .pooling_tile(9, 8)
4390 .channels(channels)
4391 .input_offset(3)
Frank Barchard609ac842020-07-01 12:09:33 -07004392 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004393 }
4394 }
4395
Marat Dukhan99936602020-04-11 16:47:01 -07004396 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_gt_1_unipass_fulltile_with_qmin) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004397 for (size_t channels = 2; channels < 10; channels++) {
4398 MaxPoolMicrokernelTester()
4399 .pooling_elements(9)
4400 .pooling_tile(9, 8)
4401 .channels(channels)
4402 .qmin(192)
Frank Barchard609ac842020-07-01 12:09:33 -07004403 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004404 }
4405 }
4406
Marat Dukhan99936602020-04-11 16:47:01 -07004407 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_gt_1_unipass_fulltile_with_qmax) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004408 for (size_t channels = 2; channels < 10; channels++) {
4409 MaxPoolMicrokernelTester()
4410 .pooling_elements(9)
4411 .pooling_tile(9, 8)
4412 .channels(channels)
4413 .qmax(192)
Frank Barchard609ac842020-07-01 12:09:33 -07004414 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004415 }
4416 }
4417
Marat Dukhan99936602020-04-11 16:47:01 -07004418 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_gt_1_unipass_subtile) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004419 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
4420 for (size_t channels = 2; channels < 10; channels++) {
4421 MaxPoolMicrokernelTester()
4422 .pooling_elements(pooling_elements)
4423 .pooling_tile(9, 8)
4424 .channels(channels)
Frank Barchard609ac842020-07-01 12:09:33 -07004425 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004426 }
4427 }
4428 }
4429
Marat Dukhan99936602020-04-11 16:47:01 -07004430 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_gt_1_unipass_subtile_with_input_offset) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004431 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
4432 for (size_t channels = 2; channels < 10; channels++) {
4433 MaxPoolMicrokernelTester()
4434 .pooling_elements(pooling_elements)
4435 .pooling_tile(9, 8)
4436 .channels(channels)
4437 .input_offset(3)
Frank Barchard609ac842020-07-01 12:09:33 -07004438 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004439 }
4440 }
4441 }
4442
Marat Dukhan99936602020-04-11 16:47:01 -07004443 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_eq_1_twopass_fulltile) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004444 MaxPoolMicrokernelTester()
4445 .pooling_elements(17)
4446 .pooling_tile(9, 8)
4447 .channels(1)
Frank Barchard609ac842020-07-01 12:09:33 -07004448 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004449 }
4450
Marat Dukhan99936602020-04-11 16:47:01 -07004451 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_eq_1_twopass_fulltile_with_input_offset) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004452 MaxPoolMicrokernelTester()
4453 .pooling_elements(17)
4454 .pooling_tile(9, 8)
4455 .channels(1)
4456 .input_offset(3)
Frank Barchard609ac842020-07-01 12:09:33 -07004457 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004458 }
4459
Marat Dukhan99936602020-04-11 16:47:01 -07004460 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_eq_1_twopass_fulltile_with_qmin) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004461 MaxPoolMicrokernelTester()
4462 .pooling_elements(17)
4463 .pooling_tile(9, 8)
4464 .channels(1)
4465 .qmin(192)
Frank Barchard609ac842020-07-01 12:09:33 -07004466 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004467 }
4468
Marat Dukhan99936602020-04-11 16:47:01 -07004469 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_eq_1_twopass_fulltile_with_qmax) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004470 MaxPoolMicrokernelTester()
4471 .pooling_elements(17)
4472 .pooling_tile(9, 8)
4473 .channels(1)
4474 .qmax(192)
Frank Barchard609ac842020-07-01 12:09:33 -07004475 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004476 }
4477
Marat Dukhan99936602020-04-11 16:47:01 -07004478 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_eq_1_twopass_subtile) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004479 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
4480 MaxPoolMicrokernelTester()
4481 .pooling_elements(pooling_elements)
4482 .pooling_tile(9, 8)
4483 .channels(1)
Frank Barchard609ac842020-07-01 12:09:33 -07004484 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004485 }
4486 }
4487
Marat Dukhan99936602020-04-11 16:47:01 -07004488 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_eq_1_twopass_subtile_with_input_offset) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004489 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
4490 MaxPoolMicrokernelTester()
4491 .pooling_elements(pooling_elements)
4492 .pooling_tile(9, 8)
4493 .channels(1)
4494 .input_offset(3)
Frank Barchard609ac842020-07-01 12:09:33 -07004495 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004496 }
4497 }
4498
Marat Dukhan99936602020-04-11 16:47:01 -07004499 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_gt_1_twopass_fulltile) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004500 for (size_t channels = 2; channels < 10; channels++) {
4501 MaxPoolMicrokernelTester()
4502 .pooling_elements(17)
4503 .pooling_tile(9, 8)
4504 .channels(channels)
Frank Barchard609ac842020-07-01 12:09:33 -07004505 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004506 }
4507 }
4508
Marat Dukhan99936602020-04-11 16:47:01 -07004509 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_gt_1_twopass_fulltile_with_input_offset) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004510 for (size_t channels = 2; channels < 10; channels++) {
4511 MaxPoolMicrokernelTester()
4512 .pooling_elements(17)
4513 .pooling_tile(9, 8)
4514 .channels(channels)
4515 .input_offset(3)
Frank Barchard609ac842020-07-01 12:09:33 -07004516 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004517 }
4518 }
4519
Marat Dukhan99936602020-04-11 16:47:01 -07004520 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_gt_1_twopass_fulltile_with_qmin) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004521 for (size_t channels = 2; channels < 10; channels++) {
4522 MaxPoolMicrokernelTester()
4523 .pooling_elements(17)
4524 .pooling_tile(9, 8)
4525 .channels(channels)
4526 .qmin(192)
Frank Barchard609ac842020-07-01 12:09:33 -07004527 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004528 }
4529 }
4530
Marat Dukhan99936602020-04-11 16:47:01 -07004531 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_gt_1_twopass_fulltile_with_qmax) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004532 for (size_t channels = 2; channels < 10; channels++) {
4533 MaxPoolMicrokernelTester()
4534 .pooling_elements(17)
4535 .pooling_tile(9, 8)
4536 .channels(channels)
4537 .qmax(192)
Frank Barchard609ac842020-07-01 12:09:33 -07004538 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004539 }
4540 }
4541
Marat Dukhan99936602020-04-11 16:47:01 -07004542 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_gt_1_twopass_subtile) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004543 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
4544 for (size_t channels = 2; channels < 10; channels++) {
4545 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08004546 .pooling_elements(pooling_elements)
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004547 .pooling_tile(9, 8)
4548 .channels(channels)
Frank Barchard609ac842020-07-01 12:09:33 -07004549 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004550 }
4551 }
4552 }
4553
Marat Dukhan99936602020-04-11 16:47:01 -07004554 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_gt_1_twopass_subtile_with_input_offset) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004555 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
4556 for (size_t channels = 2; channels < 10; channels++) {
4557 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08004558 .pooling_elements(pooling_elements)
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004559 .pooling_tile(9, 8)
4560 .channels(channels)
4561 .input_offset(3)
Frank Barchard609ac842020-07-01 12:09:33 -07004562 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004563 }
4564 }
4565 }
4566
Marat Dukhan99936602020-04-11 16:47:01 -07004567 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_eq_1_multipass) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004568 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4569 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08004570 .pooling_elements(pooling_elements)
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004571 .pooling_tile(9, 8)
4572 .channels(1)
Frank Barchard609ac842020-07-01 12:09:33 -07004573 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004574 }
4575 }
4576
Marat Dukhan99936602020-04-11 16:47:01 -07004577 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_eq_1_multipass_with_input_offset) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004578 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4579 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08004580 .pooling_elements(pooling_elements)
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004581 .pooling_tile(9, 8)
4582 .channels(1)
4583 .input_offset(3)
Frank Barchard609ac842020-07-01 12:09:33 -07004584 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004585 }
4586 }
4587
Marat Dukhan99936602020-04-11 16:47:01 -07004588 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_eq_1_multipass_with_qmin) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004589 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4590 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08004591 .pooling_elements(pooling_elements)
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004592 .pooling_tile(9, 8)
4593 .channels(1)
4594 .qmin(192)
Frank Barchard609ac842020-07-01 12:09:33 -07004595 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004596 }
4597 }
4598
Marat Dukhan99936602020-04-11 16:47:01 -07004599 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_eq_1_multipass_with_qmax) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004600 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4601 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08004602 .pooling_elements(pooling_elements)
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004603 .pooling_tile(9, 8)
4604 .channels(1)
4605 .qmax(192)
Frank Barchard609ac842020-07-01 12:09:33 -07004606 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004607 }
4608 }
4609
Marat Dukhan99936602020-04-11 16:47:01 -07004610 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_gt_1_multipass) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004611 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4612 for (size_t channels = 2; channels < 10; channels++) {
4613 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08004614 .pooling_elements(pooling_elements)
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004615 .pooling_tile(9, 8)
4616 .channels(channels)
Frank Barchard609ac842020-07-01 12:09:33 -07004617 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004618 }
4619 }
4620 }
4621
Marat Dukhan99936602020-04-11 16:47:01 -07004622 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_gt_1_multipass_with_input_offset) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004623 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4624 for (size_t channels = 2; channels < 10; channels++) {
4625 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08004626 .pooling_elements(pooling_elements)
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004627 .pooling_tile(9, 8)
4628 .channels(channels)
4629 .input_offset(3)
Frank Barchard609ac842020-07-01 12:09:33 -07004630 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004631 }
4632 }
4633 }
4634
Marat Dukhan99936602020-04-11 16:47:01 -07004635 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_gt_1_multipass_with_qmin) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004636 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4637 for (size_t channels = 2; channels < 10; channels++) {
4638 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08004639 .pooling_elements(pooling_elements)
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004640 .pooling_tile(9, 8)
4641 .channels(channels)
4642 .qmin(192)
Frank Barchard609ac842020-07-01 12:09:33 -07004643 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004644 }
4645 }
4646 }
4647
Marat Dukhan99936602020-04-11 16:47:01 -07004648 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_gt_1_multipass_with_qmax) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004649 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
4650 for (size_t channels = 2; channels < 10; channels++) {
4651 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08004652 .pooling_elements(pooling_elements)
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004653 .pooling_tile(9, 8)
4654 .channels(channels)
4655 .qmax(192)
Frank Barchard609ac842020-07-01 12:09:33 -07004656 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004657 }
4658 }
4659 }
4660
Marat Dukhan99936602020-04-11 16:47:01 -07004661 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, few_output_pixels) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004662 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
4663 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
4664 for (size_t channels = 1; channels <= 5; channels += 1) {
4665 MaxPoolMicrokernelTester()
4666 .output_pixels(output_pixels)
4667 .pooling_elements(pooling_elements)
4668 .pooling_tile(9, 8)
4669 .channels(channels)
Frank Barchard609ac842020-07-01 12:09:33 -07004670 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004671 }
4672 }
4673 }
4674 }
4675
Marat Dukhan99936602020-04-11 16:47:01 -07004676 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, few_output_pixels_with_input_offset) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004677 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
4678 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
4679 for (size_t channels = 1; channels <= 5; channels += 1) {
4680 MaxPoolMicrokernelTester()
4681 .output_pixels(output_pixels)
4682 .pooling_elements(pooling_elements)
4683 .pooling_tile(9, 8)
4684 .channels(channels)
4685 .input_offset(7)
Frank Barchard609ac842020-07-01 12:09:33 -07004686 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004687 }
4688 }
4689 }
4690 }
4691
Marat Dukhan99936602020-04-11 16:47:01 -07004692 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, few_output_pixels_with_qmin) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004693 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
4694 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
4695 for (size_t channels = 1; channels <= 5; channels += 1) {
4696 MaxPoolMicrokernelTester()
4697 .output_pixels(output_pixels)
4698 .pooling_elements(pooling_elements)
4699 .pooling_tile(9, 8)
4700 .channels(channels)
4701 .qmin(192)
Frank Barchard609ac842020-07-01 12:09:33 -07004702 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004703 }
4704 }
4705 }
4706 }
4707
Marat Dukhan99936602020-04-11 16:47:01 -07004708 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, few_output_pixels_with_qmax) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004709 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
4710 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
4711 for (size_t channels = 1; channels <= 5; channels += 1) {
4712 MaxPoolMicrokernelTester()
4713 .output_pixels(output_pixels)
4714 .pooling_elements(pooling_elements)
4715 .pooling_tile(9, 8)
4716 .channels(channels)
4717 .qmax(192)
Frank Barchard609ac842020-07-01 12:09:33 -07004718 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004719 }
4720 }
4721 }
4722 }
4723
Marat Dukhan99936602020-04-11 16:47:01 -07004724 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, few_output_pixels_with_output_stride) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004725 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
4726 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
4727 for (size_t channels = 1; channels <= 5; channels += 1) {
4728 MaxPoolMicrokernelTester()
4729 .output_pixels(output_pixels)
4730 .pooling_elements(pooling_elements)
4731 .pooling_tile(9, 8)
4732 .channels(channels)
4733 .output_stride(7)
Frank Barchard609ac842020-07-01 12:09:33 -07004734 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004735 }
4736 }
4737 }
4738 }
4739
Marat Dukhan99936602020-04-11 16:47:01 -07004740 TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, few_output_pixels_with_step) {
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004741 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
4742 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
4743 for (size_t channels = 1; channels <= 5; channels += 1) {
4744 for (size_t step = 2; step <= pooling_elements; step++) {
4745 MaxPoolMicrokernelTester()
4746 .output_pixels(output_pixels)
4747 .pooling_elements(pooling_elements)
4748 .pooling_tile(9, 8)
4749 .step(step)
4750 .channels(channels)
4751 .output_stride(7)
Frank Barchard609ac842020-07-01 12:09:33 -07004752 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__wasm_c1);
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004753 }
4754 }
4755 }
4756 }
4757 }
Frank Barchard609ac842020-07-01 12:09:33 -07004758#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
Marat Dukhan5cb8ff02020-02-26 21:02:33 -08004759
4760
Marat Dukhan99936602020-04-11 16:47:01 -07004761TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_unipass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -08004762 MaxPoolMicrokernelTester()
4763 .pooling_elements(9)
4764 .pooling_tile(9, 8)
4765 .channels(1)
Marat Dukhan99936602020-04-11 16:47:01 -07004766 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08004767}
4768
Marat Dukhan99936602020-04-11 16:47:01 -07004769TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_unipass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08004770 MaxPoolMicrokernelTester()
4771 .pooling_elements(9)
4772 .pooling_tile(9, 8)
4773 .channels(1)
4774 .input_offset(3)
Marat Dukhan99936602020-04-11 16:47:01 -07004775 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08004776}
4777
Marat Dukhan99936602020-04-11 16:47:01 -07004778TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_unipass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08004779 MaxPoolMicrokernelTester()
4780 .pooling_elements(9)
4781 .pooling_tile(9, 8)
4782 .channels(1)
4783 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07004784 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08004785}
4786
Marat Dukhan99936602020-04-11 16:47:01 -07004787TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_unipass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08004788 MaxPoolMicrokernelTester()
4789 .pooling_elements(9)
4790 .pooling_tile(9, 8)
4791 .channels(1)
4792 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07004793 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08004794}
4795
Marat Dukhan99936602020-04-11 16:47:01 -07004796TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_unipass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -08004797 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
4798 MaxPoolMicrokernelTester()
4799 .pooling_elements(pooling_elements)
4800 .pooling_tile(9, 8)
4801 .channels(1)
Marat Dukhan99936602020-04-11 16:47:01 -07004802 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07004803 }
4804}
4805
Marat Dukhan99936602020-04-11 16:47:01 -07004806TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_unipass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08004807 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
4808 MaxPoolMicrokernelTester()
4809 .pooling_elements(pooling_elements)
4810 .pooling_tile(9, 8)
4811 .channels(1)
4812 .input_offset(3)
Marat Dukhan99936602020-04-11 16:47:01 -07004813 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07004814 }
4815}
4816
Marat Dukhan99936602020-04-11 16:47:01 -07004817TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_unipass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -08004818 for (size_t channels = 2; channels < 10; channels++) {
4819 MaxPoolMicrokernelTester()
4820 .pooling_elements(9)
4821 .pooling_tile(9, 8)
4822 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07004823 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07004824 }
4825}
4826
Marat Dukhan99936602020-04-11 16:47:01 -07004827TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_unipass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08004828 for (size_t channels = 2; channels < 10; channels++) {
4829 MaxPoolMicrokernelTester()
4830 .pooling_elements(9)
4831 .pooling_tile(9, 8)
4832 .channels(channels)
4833 .input_offset(3)
Marat Dukhan99936602020-04-11 16:47:01 -07004834 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07004835 }
4836}
4837
Marat Dukhan99936602020-04-11 16:47:01 -07004838TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_unipass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08004839 for (size_t channels = 2; channels < 10; channels++) {
4840 MaxPoolMicrokernelTester()
4841 .pooling_elements(9)
4842 .pooling_tile(9, 8)
4843 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07004844 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07004845 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08004846 }
4847}
4848
Marat Dukhan99936602020-04-11 16:47:01 -07004849TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_unipass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08004850 for (size_t channels = 2; channels < 10; channels++) {
4851 MaxPoolMicrokernelTester()
4852 .pooling_elements(9)
4853 .pooling_tile(9, 8)
4854 .channels(channels)
4855 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07004856 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08004857 }
4858}
4859
Marat Dukhan99936602020-04-11 16:47:01 -07004860TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_unipass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -08004861 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
4862 for (size_t channels = 2; channels < 10; channels++) {
4863 MaxPoolMicrokernelTester()
4864 .pooling_elements(pooling_elements)
4865 .pooling_tile(9, 8)
4866 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07004867 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08004868 }
4869 }
4870}
4871
Marat Dukhan99936602020-04-11 16:47:01 -07004872TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_unipass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08004873 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
4874 for (size_t channels = 2; channels < 10; channels++) {
4875 MaxPoolMicrokernelTester()
4876 .pooling_elements(pooling_elements)
4877 .pooling_tile(9, 8)
4878 .channels(channels)
4879 .input_offset(3)
Marat Dukhan99936602020-04-11 16:47:01 -07004880 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08004881 }
4882 }
4883}
4884
Marat Dukhan99936602020-04-11 16:47:01 -07004885TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_twopass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -08004886 MaxPoolMicrokernelTester()
4887 .pooling_elements(17)
4888 .pooling_tile(9, 8)
4889 .channels(1)
Marat Dukhan99936602020-04-11 16:47:01 -07004890 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08004891}
4892
Marat Dukhan99936602020-04-11 16:47:01 -07004893TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_twopass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08004894 MaxPoolMicrokernelTester()
4895 .pooling_elements(17)
4896 .pooling_tile(9, 8)
4897 .channels(1)
4898 .input_offset(3)
Marat Dukhan99936602020-04-11 16:47:01 -07004899 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08004900}
4901
Marat Dukhan99936602020-04-11 16:47:01 -07004902TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_twopass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08004903 MaxPoolMicrokernelTester()
4904 .pooling_elements(17)
4905 .pooling_tile(9, 8)
4906 .channels(1)
4907 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07004908 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08004909}
4910
Marat Dukhan99936602020-04-11 16:47:01 -07004911TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_twopass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08004912 MaxPoolMicrokernelTester()
4913 .pooling_elements(17)
4914 .pooling_tile(9, 8)
4915 .channels(1)
4916 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07004917 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08004918}
4919
Marat Dukhan99936602020-04-11 16:47:01 -07004920TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_twopass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -08004921 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
4922 MaxPoolMicrokernelTester()
4923 .pooling_elements(pooling_elements)
4924 .pooling_tile(9, 8)
4925 .channels(1)
Marat Dukhan99936602020-04-11 16:47:01 -07004926 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08004927 }
4928}
4929
Marat Dukhan99936602020-04-11 16:47:01 -07004930TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_twopass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08004931 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
4932 MaxPoolMicrokernelTester()
4933 .pooling_elements(pooling_elements)
4934 .pooling_tile(9, 8)
4935 .channels(1)
4936 .input_offset(3)
Marat Dukhan99936602020-04-11 16:47:01 -07004937 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08004938 }
4939}
4940
Marat Dukhan99936602020-04-11 16:47:01 -07004941TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_twopass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -08004942 for (size_t channels = 2; channels < 10; channels++) {
4943 MaxPoolMicrokernelTester()
4944 .pooling_elements(17)
4945 .pooling_tile(9, 8)
4946 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07004947 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08004948 }
4949}
4950
Marat Dukhan99936602020-04-11 16:47:01 -07004951TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_twopass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08004952 for (size_t channels = 2; channels < 10; channels++) {
4953 MaxPoolMicrokernelTester()
4954 .pooling_elements(17)
4955 .pooling_tile(9, 8)
4956 .channels(channels)
4957 .input_offset(3)
Marat Dukhan99936602020-04-11 16:47:01 -07004958 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08004959 }
4960}
4961
Marat Dukhan99936602020-04-11 16:47:01 -07004962TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_twopass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08004963 for (size_t channels = 2; channels < 10; channels++) {
4964 MaxPoolMicrokernelTester()
4965 .pooling_elements(17)
4966 .pooling_tile(9, 8)
4967 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07004968 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07004969 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07004970 }
4971}
4972
Marat Dukhan99936602020-04-11 16:47:01 -07004973TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_twopass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08004974 for (size_t channels = 2; channels < 10; channels++) {
4975 MaxPoolMicrokernelTester()
4976 .pooling_elements(17)
4977 .pooling_tile(9, 8)
4978 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07004979 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07004980 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08004981 }
4982}
4983
Marat Dukhan99936602020-04-11 16:47:01 -07004984TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_twopass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -08004985 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
4986 for (size_t channels = 2; channels < 10; channels++) {
4987 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08004988 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08004989 .pooling_tile(9, 8)
4990 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07004991 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08004992 }
4993 }
4994}
4995
Marat Dukhan99936602020-04-11 16:47:01 -07004996TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_twopass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08004997 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
4998 for (size_t channels = 2; channels < 10; channels++) {
4999 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08005000 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08005001 .pooling_tile(9, 8)
5002 .channels(channels)
5003 .input_offset(3)
Marat Dukhan99936602020-04-11 16:47:01 -07005004 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08005005 }
5006 }
5007}
5008
Marat Dukhan99936602020-04-11 16:47:01 -07005009TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_multipass) {
Marat Dukhan329da642019-11-19 21:44:39 -08005010 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
5011 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08005012 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08005013 .pooling_tile(9, 8)
5014 .channels(1)
Marat Dukhan99936602020-04-11 16:47:01 -07005015 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08005016 }
5017}
5018
Marat Dukhan99936602020-04-11 16:47:01 -07005019TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_multipass_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08005020 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
5021 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08005022 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08005023 .pooling_tile(9, 8)
5024 .channels(1)
5025 .input_offset(3)
Marat Dukhan99936602020-04-11 16:47:01 -07005026 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08005027 }
5028}
5029
Marat Dukhan99936602020-04-11 16:47:01 -07005030TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_multipass_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08005031 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
5032 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08005033 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08005034 .pooling_tile(9, 8)
5035 .channels(1)
5036 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07005037 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08005038 }
5039}
5040
Marat Dukhan99936602020-04-11 16:47:01 -07005041TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_multipass_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08005042 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
5043 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08005044 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08005045 .pooling_tile(9, 8)
5046 .channels(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -07005047 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07005048 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07005049 }
5050}
5051
Marat Dukhan99936602020-04-11 16:47:01 -07005052TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_multipass) {
Marat Dukhan329da642019-11-19 21:44:39 -08005053 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
5054 for (size_t channels = 2; channels < 10; channels++) {
5055 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08005056 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08005057 .pooling_tile(9, 8)
5058 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07005059 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07005060 }
5061 }
5062}
5063
Marat Dukhan99936602020-04-11 16:47:01 -07005064TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_multipass_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08005065 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
5066 for (size_t channels = 2; channels < 10; channels++) {
5067 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08005068 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08005069 .pooling_tile(9, 8)
5070 .channels(channels)
5071 .input_offset(3)
Marat Dukhan99936602020-04-11 16:47:01 -07005072 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08005073 }
5074 }
5075}
5076
Marat Dukhan99936602020-04-11 16:47:01 -07005077TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_multipass_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08005078 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
5079 for (size_t channels = 2; channels < 10; channels++) {
5080 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08005081 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08005082 .pooling_tile(9, 8)
5083 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07005084 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07005085 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07005086 }
5087 }
5088}
5089
Marat Dukhan99936602020-04-11 16:47:01 -07005090TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_multipass_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08005091 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
5092 for (size_t channels = 2; channels < 10; channels++) {
5093 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08005094 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08005095 .pooling_tile(9, 8)
5096 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07005097 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07005098 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07005099 }
5100 }
5101}
5102
Marat Dukhan99936602020-04-11 16:47:01 -07005103TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, few_output_pixels) {
Marat Dukhan329da642019-11-19 21:44:39 -08005104 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
5105 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
5106 for (size_t channels = 1; channels <= 5; channels += 1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07005107 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -08005108 .output_pixels(output_pixels)
5109 .pooling_elements(pooling_elements)
5110 .pooling_tile(9, 8)
5111 .channels(channels)
Marat Dukhan99936602020-04-11 16:47:01 -07005112 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07005113 }
5114 }
5115 }
5116}
5117
Marat Dukhan99936602020-04-11 16:47:01 -07005118TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, few_output_pixels_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08005119 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
5120 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
5121 for (size_t channels = 1; channels <= 5; channels += 1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07005122 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -08005123 .output_pixels(output_pixels)
5124 .pooling_elements(pooling_elements)
5125 .pooling_tile(9, 8)
5126 .channels(channels)
5127 .input_offset(7)
Marat Dukhan99936602020-04-11 16:47:01 -07005128 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07005129 }
5130 }
5131 }
5132}
5133
Marat Dukhan99936602020-04-11 16:47:01 -07005134TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, few_output_pixels_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08005135 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
5136 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
5137 for (size_t channels = 1; channels <= 5; channels += 1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07005138 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -08005139 .output_pixels(output_pixels)
5140 .pooling_elements(pooling_elements)
5141 .pooling_tile(9, 8)
5142 .channels(channels)
5143 .qmin(192)
Marat Dukhan99936602020-04-11 16:47:01 -07005144 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07005145 }
5146 }
5147 }
5148}
5149
Marat Dukhan99936602020-04-11 16:47:01 -07005150TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, few_output_pixels_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08005151 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
5152 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
5153 for (size_t channels = 1; channels <= 5; channels += 1) {
5154 MaxPoolMicrokernelTester()
5155 .output_pixels(output_pixels)
5156 .pooling_elements(pooling_elements)
5157 .pooling_tile(9, 8)
5158 .channels(channels)
5159 .qmax(192)
Marat Dukhan99936602020-04-11 16:47:01 -07005160 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08005161 }
5162 }
5163 }
5164}
5165
Marat Dukhan99936602020-04-11 16:47:01 -07005166TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, few_output_pixels_with_output_stride) {
Marat Dukhan329da642019-11-19 21:44:39 -08005167 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
5168 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
5169 for (size_t channels = 1; channels <= 5; channels += 1) {
5170 MaxPoolMicrokernelTester()
5171 .output_pixels(output_pixels)
5172 .pooling_elements(pooling_elements)
5173 .pooling_tile(9, 8)
5174 .channels(channels)
5175 .output_stride(7)
Marat Dukhan99936602020-04-11 16:47:01 -07005176 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
Marat Dukhan329da642019-11-19 21:44:39 -08005177 }
5178 }
5179 }
5180}
5181
Marat Dukhan99936602020-04-11 16:47:01 -07005182TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, few_output_pixels_with_step) {
Marat Dukhan329da642019-11-19 21:44:39 -08005183 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
5184 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
5185 for (size_t channels = 1; channels <= 5; channels += 1) {
5186 for (size_t step = 2; step <= pooling_elements; step++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07005187 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -08005188 .output_pixels(output_pixels)
5189 .pooling_elements(pooling_elements)
5190 .pooling_tile(9, 8)
5191 .step(step)
5192 .channels(channels)
5193 .output_stride(7)
Marat Dukhan99936602020-04-11 16:47:01 -07005194 .Test(xnn_f32_maxpool_minmax_ukernel_9p8x__scalar_c1, MaxPoolMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07005195 }
5196 }
5197 }
5198 }
Marat Dukhan329da642019-11-19 21:44:39 -08005199}