Marat Dukhan | f1a6ed3 | 2021-09-26 13:40:19 -0700 | [diff] [blame] | 1 | // Copyright 2021 Google LLC |
| 2 | // |
| 3 | // This source code is licensed under the BSD-style license found in the |
| 4 | // LICENSE file in the root directory of this source tree. |
| 5 | // |
| 6 | // Auto-generated file. Do not edit! |
| 7 | // Specification: test/f16-f32-vcvt.yaml |
| 8 | // Generator: tools/generate-vcvt-test.py |
| 9 | |
| 10 | |
| 11 | #include <gtest/gtest.h> |
| 12 | |
| 13 | #include <xnnpack/common.h> |
| 14 | #include <xnnpack/isa-checks.h> |
| 15 | |
| 16 | #include <xnnpack/vcvt.h> |
| 17 | #include "vcvt-microkernel-tester.h" |
| 18 | |
| 19 | |
Marat Dukhan | 8ff372c | 2021-09-28 14:43:17 -0700 | [diff] [blame] | 20 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 21 | TEST(F16_F32_VCVT__NEON_INT16_X8, batch_eq_8) { |
| 22 | TEST_REQUIRES_ARM_NEON; |
| 23 | VCvtMicrokernelTester() |
| 24 | .batch_size(8) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 25 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int16_x8, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 26 | } |
| 27 | |
| 28 | TEST(F16_F32_VCVT__NEON_INT16_X8, batch_div_8) { |
| 29 | TEST_REQUIRES_ARM_NEON; |
| 30 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 31 | VCvtMicrokernelTester() |
| 32 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 33 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int16_x8, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 34 | } |
| 35 | } |
| 36 | |
| 37 | TEST(F16_F32_VCVT__NEON_INT16_X8, batch_lt_8) { |
| 38 | TEST_REQUIRES_ARM_NEON; |
| 39 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 40 | VCvtMicrokernelTester() |
| 41 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 42 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int16_x8, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 43 | } |
| 44 | } |
| 45 | |
| 46 | TEST(F16_F32_VCVT__NEON_INT16_X8, batch_gt_8) { |
| 47 | TEST_REQUIRES_ARM_NEON; |
| 48 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 49 | VCvtMicrokernelTester() |
| 50 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 51 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int16_x8, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 52 | } |
| 53 | } |
| 54 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 55 | |
| 56 | |
| 57 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 58 | TEST(F16_F32_VCVT__NEON_INT16_X16, batch_eq_16) { |
| 59 | TEST_REQUIRES_ARM_NEON; |
| 60 | VCvtMicrokernelTester() |
| 61 | .batch_size(16) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 62 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int16_x16, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 63 | } |
| 64 | |
| 65 | TEST(F16_F32_VCVT__NEON_INT16_X16, batch_div_16) { |
| 66 | TEST_REQUIRES_ARM_NEON; |
| 67 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 68 | VCvtMicrokernelTester() |
| 69 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 70 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int16_x16, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 71 | } |
| 72 | } |
| 73 | |
| 74 | TEST(F16_F32_VCVT__NEON_INT16_X16, batch_lt_16) { |
| 75 | TEST_REQUIRES_ARM_NEON; |
| 76 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 77 | VCvtMicrokernelTester() |
| 78 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 79 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int16_x16, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 80 | } |
| 81 | } |
| 82 | |
| 83 | TEST(F16_F32_VCVT__NEON_INT16_X16, batch_gt_16) { |
| 84 | TEST_REQUIRES_ARM_NEON; |
| 85 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 86 | VCvtMicrokernelTester() |
| 87 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 88 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int16_x16, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 89 | } |
| 90 | } |
| 91 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 92 | |
| 93 | |
| 94 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 95 | TEST(F16_F32_VCVT__NEON_INT16_X24, batch_eq_24) { |
| 96 | TEST_REQUIRES_ARM_NEON; |
| 97 | VCvtMicrokernelTester() |
| 98 | .batch_size(24) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 99 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int16_x24, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 100 | } |
| 101 | |
| 102 | TEST(F16_F32_VCVT__NEON_INT16_X24, batch_div_24) { |
| 103 | TEST_REQUIRES_ARM_NEON; |
| 104 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 105 | VCvtMicrokernelTester() |
| 106 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 107 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int16_x24, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 108 | } |
| 109 | } |
| 110 | |
| 111 | TEST(F16_F32_VCVT__NEON_INT16_X24, batch_lt_24) { |
| 112 | TEST_REQUIRES_ARM_NEON; |
| 113 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 114 | VCvtMicrokernelTester() |
| 115 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 116 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int16_x24, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 117 | } |
| 118 | } |
| 119 | |
| 120 | TEST(F16_F32_VCVT__NEON_INT16_X24, batch_gt_24) { |
| 121 | TEST_REQUIRES_ARM_NEON; |
| 122 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 123 | VCvtMicrokernelTester() |
| 124 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 125 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int16_x24, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 126 | } |
| 127 | } |
| 128 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 129 | |
| 130 | |
| 131 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 132 | TEST(F16_F32_VCVT__NEON_INT16_X32, batch_eq_32) { |
| 133 | TEST_REQUIRES_ARM_NEON; |
| 134 | VCvtMicrokernelTester() |
| 135 | .batch_size(32) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 136 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int16_x32, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 137 | } |
| 138 | |
| 139 | TEST(F16_F32_VCVT__NEON_INT16_X32, batch_div_32) { |
| 140 | TEST_REQUIRES_ARM_NEON; |
| 141 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 142 | VCvtMicrokernelTester() |
| 143 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 144 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int16_x32, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 145 | } |
| 146 | } |
| 147 | |
| 148 | TEST(F16_F32_VCVT__NEON_INT16_X32, batch_lt_32) { |
| 149 | TEST_REQUIRES_ARM_NEON; |
| 150 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 151 | VCvtMicrokernelTester() |
| 152 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 153 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int16_x32, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 154 | } |
| 155 | } |
| 156 | |
| 157 | TEST(F16_F32_VCVT__NEON_INT16_X32, batch_gt_32) { |
| 158 | TEST_REQUIRES_ARM_NEON; |
| 159 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 160 | VCvtMicrokernelTester() |
| 161 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 162 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int16_x32, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 163 | } |
| 164 | } |
| 165 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 166 | |
| 167 | |
| 168 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 169 | TEST(F16_F32_VCVT__NEON_INT32_X8, batch_eq_8) { |
| 170 | TEST_REQUIRES_ARM_NEON; |
| 171 | VCvtMicrokernelTester() |
| 172 | .batch_size(8) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 173 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int32_x8, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 174 | } |
| 175 | |
| 176 | TEST(F16_F32_VCVT__NEON_INT32_X8, batch_div_8) { |
| 177 | TEST_REQUIRES_ARM_NEON; |
| 178 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 179 | VCvtMicrokernelTester() |
| 180 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 181 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int32_x8, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 182 | } |
| 183 | } |
| 184 | |
| 185 | TEST(F16_F32_VCVT__NEON_INT32_X8, batch_lt_8) { |
| 186 | TEST_REQUIRES_ARM_NEON; |
| 187 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 188 | VCvtMicrokernelTester() |
| 189 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 190 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int32_x8, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 191 | } |
| 192 | } |
| 193 | |
| 194 | TEST(F16_F32_VCVT__NEON_INT32_X8, batch_gt_8) { |
| 195 | TEST_REQUIRES_ARM_NEON; |
| 196 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 197 | VCvtMicrokernelTester() |
| 198 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 199 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int32_x8, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 200 | } |
| 201 | } |
| 202 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 203 | |
| 204 | |
| 205 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 206 | TEST(F16_F32_VCVT__NEON_INT32_X16, batch_eq_16) { |
| 207 | TEST_REQUIRES_ARM_NEON; |
| 208 | VCvtMicrokernelTester() |
| 209 | .batch_size(16) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 210 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int32_x16, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 211 | } |
| 212 | |
| 213 | TEST(F16_F32_VCVT__NEON_INT32_X16, batch_div_16) { |
| 214 | TEST_REQUIRES_ARM_NEON; |
| 215 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 216 | VCvtMicrokernelTester() |
| 217 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 218 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int32_x16, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 219 | } |
| 220 | } |
| 221 | |
| 222 | TEST(F16_F32_VCVT__NEON_INT32_X16, batch_lt_16) { |
| 223 | TEST_REQUIRES_ARM_NEON; |
| 224 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 225 | VCvtMicrokernelTester() |
| 226 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 227 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int32_x16, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 228 | } |
| 229 | } |
| 230 | |
| 231 | TEST(F16_F32_VCVT__NEON_INT32_X16, batch_gt_16) { |
| 232 | TEST_REQUIRES_ARM_NEON; |
| 233 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 234 | VCvtMicrokernelTester() |
| 235 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 236 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int32_x16, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 237 | } |
| 238 | } |
| 239 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 240 | |
| 241 | |
| 242 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 243 | TEST(F16_F32_VCVT__NEON_INT32_X24, batch_eq_24) { |
| 244 | TEST_REQUIRES_ARM_NEON; |
| 245 | VCvtMicrokernelTester() |
| 246 | .batch_size(24) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 247 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int32_x24, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 248 | } |
| 249 | |
| 250 | TEST(F16_F32_VCVT__NEON_INT32_X24, batch_div_24) { |
| 251 | TEST_REQUIRES_ARM_NEON; |
| 252 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 253 | VCvtMicrokernelTester() |
| 254 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 255 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int32_x24, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 256 | } |
| 257 | } |
| 258 | |
| 259 | TEST(F16_F32_VCVT__NEON_INT32_X24, batch_lt_24) { |
| 260 | TEST_REQUIRES_ARM_NEON; |
| 261 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 262 | VCvtMicrokernelTester() |
| 263 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 264 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int32_x24, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 265 | } |
| 266 | } |
| 267 | |
| 268 | TEST(F16_F32_VCVT__NEON_INT32_X24, batch_gt_24) { |
| 269 | TEST_REQUIRES_ARM_NEON; |
| 270 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 271 | VCvtMicrokernelTester() |
| 272 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 273 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int32_x24, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 274 | } |
| 275 | } |
| 276 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 277 | |
| 278 | |
| 279 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 280 | TEST(F16_F32_VCVT__NEON_INT32_X32, batch_eq_32) { |
| 281 | TEST_REQUIRES_ARM_NEON; |
| 282 | VCvtMicrokernelTester() |
| 283 | .batch_size(32) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 284 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int32_x32, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 285 | } |
| 286 | |
| 287 | TEST(F16_F32_VCVT__NEON_INT32_X32, batch_div_32) { |
| 288 | TEST_REQUIRES_ARM_NEON; |
| 289 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 290 | VCvtMicrokernelTester() |
| 291 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 292 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int32_x32, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 293 | } |
| 294 | } |
| 295 | |
| 296 | TEST(F16_F32_VCVT__NEON_INT32_X32, batch_lt_32) { |
| 297 | TEST_REQUIRES_ARM_NEON; |
| 298 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 299 | VCvtMicrokernelTester() |
| 300 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 301 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int32_x32, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 302 | } |
| 303 | } |
| 304 | |
| 305 | TEST(F16_F32_VCVT__NEON_INT32_X32, batch_gt_32) { |
| 306 | TEST_REQUIRES_ARM_NEON; |
| 307 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 308 | VCvtMicrokernelTester() |
| 309 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 310 | .Test(xnn_f16_f32_vcvt_ukernel__neon_int32_x32, xnn_init_f16_f32_cvt_neon_params); |
Marat Dukhan | 322ed6f | 2021-10-16 17:44:16 -0700 | [diff] [blame] | 311 | } |
| 312 | } |
| 313 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 314 | |
| 315 | |
| 316 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 8ff372c | 2021-09-28 14:43:17 -0700 | [diff] [blame] | 317 | TEST(F16_F32_VCVT__NEONFP16_X8, batch_eq_8) { |
| 318 | TEST_REQUIRES_ARM_NEON_FP16; |
| 319 | VCvtMicrokernelTester() |
| 320 | .batch_size(8) |
| 321 | .Test(xnn_f16_f32_vcvt_ukernel__neonfp16_x8); |
| 322 | } |
| 323 | |
| 324 | TEST(F16_F32_VCVT__NEONFP16_X8, batch_div_8) { |
| 325 | TEST_REQUIRES_ARM_NEON_FP16; |
| 326 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 327 | VCvtMicrokernelTester() |
| 328 | .batch_size(batch_size) |
| 329 | .Test(xnn_f16_f32_vcvt_ukernel__neonfp16_x8); |
| 330 | } |
| 331 | } |
| 332 | |
| 333 | TEST(F16_F32_VCVT__NEONFP16_X8, batch_lt_8) { |
| 334 | TEST_REQUIRES_ARM_NEON_FP16; |
| 335 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 336 | VCvtMicrokernelTester() |
| 337 | .batch_size(batch_size) |
| 338 | .Test(xnn_f16_f32_vcvt_ukernel__neonfp16_x8); |
| 339 | } |
| 340 | } |
| 341 | |
| 342 | TEST(F16_F32_VCVT__NEONFP16_X8, batch_gt_8) { |
| 343 | TEST_REQUIRES_ARM_NEON_FP16; |
| 344 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 345 | VCvtMicrokernelTester() |
| 346 | .batch_size(batch_size) |
| 347 | .Test(xnn_f16_f32_vcvt_ukernel__neonfp16_x8); |
| 348 | } |
| 349 | } |
| 350 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 351 | |
| 352 | |
| 353 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 354 | TEST(F16_F32_VCVT__NEONFP16_X16, batch_eq_16) { |
| 355 | TEST_REQUIRES_ARM_NEON_FP16; |
| 356 | VCvtMicrokernelTester() |
| 357 | .batch_size(16) |
| 358 | .Test(xnn_f16_f32_vcvt_ukernel__neonfp16_x16); |
| 359 | } |
| 360 | |
| 361 | TEST(F16_F32_VCVT__NEONFP16_X16, batch_div_16) { |
| 362 | TEST_REQUIRES_ARM_NEON_FP16; |
| 363 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 364 | VCvtMicrokernelTester() |
| 365 | .batch_size(batch_size) |
| 366 | .Test(xnn_f16_f32_vcvt_ukernel__neonfp16_x16); |
| 367 | } |
| 368 | } |
| 369 | |
| 370 | TEST(F16_F32_VCVT__NEONFP16_X16, batch_lt_16) { |
| 371 | TEST_REQUIRES_ARM_NEON_FP16; |
| 372 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 373 | VCvtMicrokernelTester() |
| 374 | .batch_size(batch_size) |
| 375 | .Test(xnn_f16_f32_vcvt_ukernel__neonfp16_x16); |
| 376 | } |
| 377 | } |
| 378 | |
| 379 | TEST(F16_F32_VCVT__NEONFP16_X16, batch_gt_16) { |
| 380 | TEST_REQUIRES_ARM_NEON_FP16; |
| 381 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 382 | VCvtMicrokernelTester() |
| 383 | .batch_size(batch_size) |
| 384 | .Test(xnn_f16_f32_vcvt_ukernel__neonfp16_x16); |
| 385 | } |
| 386 | } |
| 387 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 388 | |
| 389 | |
Marat Dukhan | f1a6ed3 | 2021-09-26 13:40:19 -0700 | [diff] [blame] | 390 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 391 | TEST(F16_F32_VCVT__SSE2_INT16_X8, batch_eq_8) { |
| 392 | TEST_REQUIRES_X86_SSE2; |
| 393 | VCvtMicrokernelTester() |
| 394 | .batch_size(8) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 395 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int16_x8, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 396 | } |
| 397 | |
| 398 | TEST(F16_F32_VCVT__SSE2_INT16_X8, batch_div_8) { |
| 399 | TEST_REQUIRES_X86_SSE2; |
| 400 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 401 | VCvtMicrokernelTester() |
| 402 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 403 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int16_x8, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 404 | } |
| 405 | } |
| 406 | |
| 407 | TEST(F16_F32_VCVT__SSE2_INT16_X8, batch_lt_8) { |
| 408 | TEST_REQUIRES_X86_SSE2; |
| 409 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 410 | VCvtMicrokernelTester() |
| 411 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 412 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int16_x8, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 413 | } |
| 414 | } |
| 415 | |
| 416 | TEST(F16_F32_VCVT__SSE2_INT16_X8, batch_gt_8) { |
| 417 | TEST_REQUIRES_X86_SSE2; |
| 418 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 419 | VCvtMicrokernelTester() |
| 420 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 421 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int16_x8, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 422 | } |
| 423 | } |
| 424 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 425 | |
| 426 | |
| 427 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 428 | TEST(F16_F32_VCVT__SSE2_INT16_X16, batch_eq_16) { |
| 429 | TEST_REQUIRES_X86_SSE2; |
| 430 | VCvtMicrokernelTester() |
| 431 | .batch_size(16) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 432 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int16_x16, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 433 | } |
| 434 | |
| 435 | TEST(F16_F32_VCVT__SSE2_INT16_X16, batch_div_16) { |
| 436 | TEST_REQUIRES_X86_SSE2; |
| 437 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 438 | VCvtMicrokernelTester() |
| 439 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 440 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int16_x16, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 441 | } |
| 442 | } |
| 443 | |
| 444 | TEST(F16_F32_VCVT__SSE2_INT16_X16, batch_lt_16) { |
| 445 | TEST_REQUIRES_X86_SSE2; |
| 446 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 447 | VCvtMicrokernelTester() |
| 448 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 449 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int16_x16, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 450 | } |
| 451 | } |
| 452 | |
| 453 | TEST(F16_F32_VCVT__SSE2_INT16_X16, batch_gt_16) { |
| 454 | TEST_REQUIRES_X86_SSE2; |
| 455 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 456 | VCvtMicrokernelTester() |
| 457 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 458 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int16_x16, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 459 | } |
| 460 | } |
| 461 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 462 | |
| 463 | |
| 464 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 465 | TEST(F16_F32_VCVT__SSE2_INT16_X24, batch_eq_24) { |
| 466 | TEST_REQUIRES_X86_SSE2; |
| 467 | VCvtMicrokernelTester() |
| 468 | .batch_size(24) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 469 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int16_x24, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 470 | } |
| 471 | |
| 472 | TEST(F16_F32_VCVT__SSE2_INT16_X24, batch_div_24) { |
| 473 | TEST_REQUIRES_X86_SSE2; |
| 474 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 475 | VCvtMicrokernelTester() |
| 476 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 477 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int16_x24, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 478 | } |
| 479 | } |
| 480 | |
| 481 | TEST(F16_F32_VCVT__SSE2_INT16_X24, batch_lt_24) { |
| 482 | TEST_REQUIRES_X86_SSE2; |
| 483 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 484 | VCvtMicrokernelTester() |
| 485 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 486 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int16_x24, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 487 | } |
| 488 | } |
| 489 | |
| 490 | TEST(F16_F32_VCVT__SSE2_INT16_X24, batch_gt_24) { |
| 491 | TEST_REQUIRES_X86_SSE2; |
| 492 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 493 | VCvtMicrokernelTester() |
| 494 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 495 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int16_x24, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 496 | } |
| 497 | } |
| 498 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 499 | |
| 500 | |
| 501 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 502 | TEST(F16_F32_VCVT__SSE2_INT16_X32, batch_eq_32) { |
| 503 | TEST_REQUIRES_X86_SSE2; |
| 504 | VCvtMicrokernelTester() |
| 505 | .batch_size(32) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 506 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int16_x32, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 507 | } |
| 508 | |
| 509 | TEST(F16_F32_VCVT__SSE2_INT16_X32, batch_div_32) { |
| 510 | TEST_REQUIRES_X86_SSE2; |
| 511 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 512 | VCvtMicrokernelTester() |
| 513 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 514 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int16_x32, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 515 | } |
| 516 | } |
| 517 | |
| 518 | TEST(F16_F32_VCVT__SSE2_INT16_X32, batch_lt_32) { |
| 519 | TEST_REQUIRES_X86_SSE2; |
| 520 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 521 | VCvtMicrokernelTester() |
| 522 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 523 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int16_x32, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 524 | } |
| 525 | } |
| 526 | |
| 527 | TEST(F16_F32_VCVT__SSE2_INT16_X32, batch_gt_32) { |
| 528 | TEST_REQUIRES_X86_SSE2; |
| 529 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 530 | VCvtMicrokernelTester() |
| 531 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 532 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int16_x32, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 533 | } |
| 534 | } |
| 535 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 536 | |
| 537 | |
| 538 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 539 | TEST(F16_F32_VCVT__SSE2_INT32_X8, batch_eq_8) { |
| 540 | TEST_REQUIRES_X86_SSE2; |
| 541 | VCvtMicrokernelTester() |
| 542 | .batch_size(8) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 543 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int32_x8, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 544 | } |
| 545 | |
| 546 | TEST(F16_F32_VCVT__SSE2_INT32_X8, batch_div_8) { |
| 547 | TEST_REQUIRES_X86_SSE2; |
| 548 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 549 | VCvtMicrokernelTester() |
| 550 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 551 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int32_x8, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 552 | } |
| 553 | } |
| 554 | |
| 555 | TEST(F16_F32_VCVT__SSE2_INT32_X8, batch_lt_8) { |
| 556 | TEST_REQUIRES_X86_SSE2; |
| 557 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 558 | VCvtMicrokernelTester() |
| 559 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 560 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int32_x8, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 561 | } |
| 562 | } |
| 563 | |
| 564 | TEST(F16_F32_VCVT__SSE2_INT32_X8, batch_gt_8) { |
| 565 | TEST_REQUIRES_X86_SSE2; |
| 566 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 567 | VCvtMicrokernelTester() |
| 568 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 569 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int32_x8, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 570 | } |
| 571 | } |
| 572 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 573 | |
| 574 | |
| 575 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 576 | TEST(F16_F32_VCVT__SSE2_INT32_X16, batch_eq_16) { |
| 577 | TEST_REQUIRES_X86_SSE2; |
| 578 | VCvtMicrokernelTester() |
| 579 | .batch_size(16) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 580 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int32_x16, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 581 | } |
| 582 | |
| 583 | TEST(F16_F32_VCVT__SSE2_INT32_X16, batch_div_16) { |
| 584 | TEST_REQUIRES_X86_SSE2; |
| 585 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 586 | VCvtMicrokernelTester() |
| 587 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 588 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int32_x16, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 589 | } |
| 590 | } |
| 591 | |
| 592 | TEST(F16_F32_VCVT__SSE2_INT32_X16, batch_lt_16) { |
| 593 | TEST_REQUIRES_X86_SSE2; |
| 594 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 595 | VCvtMicrokernelTester() |
| 596 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 597 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int32_x16, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 598 | } |
| 599 | } |
| 600 | |
| 601 | TEST(F16_F32_VCVT__SSE2_INT32_X16, batch_gt_16) { |
| 602 | TEST_REQUIRES_X86_SSE2; |
| 603 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 604 | VCvtMicrokernelTester() |
| 605 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 606 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int32_x16, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 607 | } |
| 608 | } |
| 609 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 610 | |
| 611 | |
| 612 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 613 | TEST(F16_F32_VCVT__SSE2_INT32_X24, batch_eq_24) { |
| 614 | TEST_REQUIRES_X86_SSE2; |
| 615 | VCvtMicrokernelTester() |
| 616 | .batch_size(24) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 617 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int32_x24, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 618 | } |
| 619 | |
| 620 | TEST(F16_F32_VCVT__SSE2_INT32_X24, batch_div_24) { |
| 621 | TEST_REQUIRES_X86_SSE2; |
| 622 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 623 | VCvtMicrokernelTester() |
| 624 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 625 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int32_x24, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 626 | } |
| 627 | } |
| 628 | |
| 629 | TEST(F16_F32_VCVT__SSE2_INT32_X24, batch_lt_24) { |
| 630 | TEST_REQUIRES_X86_SSE2; |
| 631 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 632 | VCvtMicrokernelTester() |
| 633 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 634 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int32_x24, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 635 | } |
| 636 | } |
| 637 | |
| 638 | TEST(F16_F32_VCVT__SSE2_INT32_X24, batch_gt_24) { |
| 639 | TEST_REQUIRES_X86_SSE2; |
| 640 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 641 | VCvtMicrokernelTester() |
| 642 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 643 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int32_x24, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 644 | } |
| 645 | } |
| 646 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 647 | |
| 648 | |
| 649 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 650 | TEST(F16_F32_VCVT__SSE2_INT32_X32, batch_eq_32) { |
| 651 | TEST_REQUIRES_X86_SSE2; |
| 652 | VCvtMicrokernelTester() |
| 653 | .batch_size(32) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 654 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int32_x32, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 655 | } |
| 656 | |
| 657 | TEST(F16_F32_VCVT__SSE2_INT32_X32, batch_div_32) { |
| 658 | TEST_REQUIRES_X86_SSE2; |
| 659 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 660 | VCvtMicrokernelTester() |
| 661 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 662 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int32_x32, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 663 | } |
| 664 | } |
| 665 | |
| 666 | TEST(F16_F32_VCVT__SSE2_INT32_X32, batch_lt_32) { |
| 667 | TEST_REQUIRES_X86_SSE2; |
| 668 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 669 | VCvtMicrokernelTester() |
| 670 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 671 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int32_x32, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 672 | } |
| 673 | } |
| 674 | |
| 675 | TEST(F16_F32_VCVT__SSE2_INT32_X32, batch_gt_32) { |
| 676 | TEST_REQUIRES_X86_SSE2; |
| 677 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 678 | VCvtMicrokernelTester() |
| 679 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 680 | .Test(xnn_f16_f32_vcvt_ukernel__sse2_int32_x32, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 681 | } |
| 682 | } |
| 683 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 684 | |
| 685 | |
| 686 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 687 | TEST(F16_F32_VCVT__SSE41_INT16_X8, batch_eq_8) { |
| 688 | TEST_REQUIRES_X86_SSE41; |
| 689 | VCvtMicrokernelTester() |
| 690 | .batch_size(8) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 691 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int16_x8, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 692 | } |
| 693 | |
| 694 | TEST(F16_F32_VCVT__SSE41_INT16_X8, batch_div_8) { |
| 695 | TEST_REQUIRES_X86_SSE41; |
| 696 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 697 | VCvtMicrokernelTester() |
| 698 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 699 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int16_x8, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 700 | } |
| 701 | } |
| 702 | |
| 703 | TEST(F16_F32_VCVT__SSE41_INT16_X8, batch_lt_8) { |
| 704 | TEST_REQUIRES_X86_SSE41; |
| 705 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 706 | VCvtMicrokernelTester() |
| 707 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 708 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int16_x8, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 709 | } |
| 710 | } |
| 711 | |
| 712 | TEST(F16_F32_VCVT__SSE41_INT16_X8, batch_gt_8) { |
| 713 | TEST_REQUIRES_X86_SSE41; |
| 714 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 715 | VCvtMicrokernelTester() |
| 716 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 717 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int16_x8, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 718 | } |
| 719 | } |
| 720 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 721 | |
| 722 | |
| 723 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 724 | TEST(F16_F32_VCVT__SSE41_INT16_X16, batch_eq_16) { |
| 725 | TEST_REQUIRES_X86_SSE41; |
| 726 | VCvtMicrokernelTester() |
| 727 | .batch_size(16) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 728 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int16_x16, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 729 | } |
| 730 | |
| 731 | TEST(F16_F32_VCVT__SSE41_INT16_X16, batch_div_16) { |
| 732 | TEST_REQUIRES_X86_SSE41; |
| 733 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 734 | VCvtMicrokernelTester() |
| 735 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 736 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int16_x16, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 737 | } |
| 738 | } |
| 739 | |
| 740 | TEST(F16_F32_VCVT__SSE41_INT16_X16, batch_lt_16) { |
| 741 | TEST_REQUIRES_X86_SSE41; |
| 742 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 743 | VCvtMicrokernelTester() |
| 744 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 745 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int16_x16, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 746 | } |
| 747 | } |
| 748 | |
| 749 | TEST(F16_F32_VCVT__SSE41_INT16_X16, batch_gt_16) { |
| 750 | TEST_REQUIRES_X86_SSE41; |
| 751 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 752 | VCvtMicrokernelTester() |
| 753 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 754 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int16_x16, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 755 | } |
| 756 | } |
| 757 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 758 | |
| 759 | |
| 760 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 761 | TEST(F16_F32_VCVT__SSE41_INT16_X24, batch_eq_24) { |
| 762 | TEST_REQUIRES_X86_SSE41; |
| 763 | VCvtMicrokernelTester() |
| 764 | .batch_size(24) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 765 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int16_x24, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 766 | } |
| 767 | |
| 768 | TEST(F16_F32_VCVT__SSE41_INT16_X24, batch_div_24) { |
| 769 | TEST_REQUIRES_X86_SSE41; |
| 770 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 771 | VCvtMicrokernelTester() |
| 772 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 773 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int16_x24, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 774 | } |
| 775 | } |
| 776 | |
| 777 | TEST(F16_F32_VCVT__SSE41_INT16_X24, batch_lt_24) { |
| 778 | TEST_REQUIRES_X86_SSE41; |
| 779 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 780 | VCvtMicrokernelTester() |
| 781 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 782 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int16_x24, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 783 | } |
| 784 | } |
| 785 | |
| 786 | TEST(F16_F32_VCVT__SSE41_INT16_X24, batch_gt_24) { |
| 787 | TEST_REQUIRES_X86_SSE41; |
| 788 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 789 | VCvtMicrokernelTester() |
| 790 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 791 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int16_x24, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 792 | } |
| 793 | } |
| 794 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 795 | |
| 796 | |
| 797 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 798 | TEST(F16_F32_VCVT__SSE41_INT16_X32, batch_eq_32) { |
| 799 | TEST_REQUIRES_X86_SSE41; |
| 800 | VCvtMicrokernelTester() |
| 801 | .batch_size(32) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 802 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int16_x32, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 803 | } |
| 804 | |
| 805 | TEST(F16_F32_VCVT__SSE41_INT16_X32, batch_div_32) { |
| 806 | TEST_REQUIRES_X86_SSE41; |
| 807 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 808 | VCvtMicrokernelTester() |
| 809 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 810 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int16_x32, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 811 | } |
| 812 | } |
| 813 | |
| 814 | TEST(F16_F32_VCVT__SSE41_INT16_X32, batch_lt_32) { |
| 815 | TEST_REQUIRES_X86_SSE41; |
| 816 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 817 | VCvtMicrokernelTester() |
| 818 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 819 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int16_x32, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 820 | } |
| 821 | } |
| 822 | |
| 823 | TEST(F16_F32_VCVT__SSE41_INT16_X32, batch_gt_32) { |
| 824 | TEST_REQUIRES_X86_SSE41; |
| 825 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 826 | VCvtMicrokernelTester() |
| 827 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 828 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int16_x32, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 829 | } |
| 830 | } |
| 831 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 832 | |
| 833 | |
| 834 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 835 | TEST(F16_F32_VCVT__SSE41_INT32_X8, batch_eq_8) { |
| 836 | TEST_REQUIRES_X86_SSE41; |
| 837 | VCvtMicrokernelTester() |
| 838 | .batch_size(8) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 839 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int32_x8, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 840 | } |
| 841 | |
| 842 | TEST(F16_F32_VCVT__SSE41_INT32_X8, batch_div_8) { |
| 843 | TEST_REQUIRES_X86_SSE41; |
| 844 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 845 | VCvtMicrokernelTester() |
| 846 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 847 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int32_x8, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 848 | } |
| 849 | } |
| 850 | |
| 851 | TEST(F16_F32_VCVT__SSE41_INT32_X8, batch_lt_8) { |
| 852 | TEST_REQUIRES_X86_SSE41; |
| 853 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 854 | VCvtMicrokernelTester() |
| 855 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 856 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int32_x8, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 857 | } |
| 858 | } |
| 859 | |
| 860 | TEST(F16_F32_VCVT__SSE41_INT32_X8, batch_gt_8) { |
| 861 | TEST_REQUIRES_X86_SSE41; |
| 862 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 863 | VCvtMicrokernelTester() |
| 864 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 865 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int32_x8, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 866 | } |
| 867 | } |
| 868 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 869 | |
| 870 | |
| 871 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 872 | TEST(F16_F32_VCVT__SSE41_INT32_X16, batch_eq_16) { |
| 873 | TEST_REQUIRES_X86_SSE41; |
| 874 | VCvtMicrokernelTester() |
| 875 | .batch_size(16) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 876 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int32_x16, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 877 | } |
| 878 | |
| 879 | TEST(F16_F32_VCVT__SSE41_INT32_X16, batch_div_16) { |
| 880 | TEST_REQUIRES_X86_SSE41; |
| 881 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 882 | VCvtMicrokernelTester() |
| 883 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 884 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int32_x16, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 885 | } |
| 886 | } |
| 887 | |
| 888 | TEST(F16_F32_VCVT__SSE41_INT32_X16, batch_lt_16) { |
| 889 | TEST_REQUIRES_X86_SSE41; |
| 890 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 891 | VCvtMicrokernelTester() |
| 892 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 893 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int32_x16, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 894 | } |
| 895 | } |
| 896 | |
| 897 | TEST(F16_F32_VCVT__SSE41_INT32_X16, batch_gt_16) { |
| 898 | TEST_REQUIRES_X86_SSE41; |
| 899 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 900 | VCvtMicrokernelTester() |
| 901 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 902 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int32_x16, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 903 | } |
| 904 | } |
| 905 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 906 | |
| 907 | |
| 908 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 909 | TEST(F16_F32_VCVT__SSE41_INT32_X24, batch_eq_24) { |
| 910 | TEST_REQUIRES_X86_SSE41; |
| 911 | VCvtMicrokernelTester() |
| 912 | .batch_size(24) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 913 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int32_x24, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 914 | } |
| 915 | |
| 916 | TEST(F16_F32_VCVT__SSE41_INT32_X24, batch_div_24) { |
| 917 | TEST_REQUIRES_X86_SSE41; |
| 918 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 919 | VCvtMicrokernelTester() |
| 920 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 921 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int32_x24, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 922 | } |
| 923 | } |
| 924 | |
| 925 | TEST(F16_F32_VCVT__SSE41_INT32_X24, batch_lt_24) { |
| 926 | TEST_REQUIRES_X86_SSE41; |
| 927 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 928 | VCvtMicrokernelTester() |
| 929 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 930 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int32_x24, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 931 | } |
| 932 | } |
| 933 | |
| 934 | TEST(F16_F32_VCVT__SSE41_INT32_X24, batch_gt_24) { |
| 935 | TEST_REQUIRES_X86_SSE41; |
| 936 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 937 | VCvtMicrokernelTester() |
| 938 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 939 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int32_x24, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 940 | } |
| 941 | } |
| 942 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 943 | |
| 944 | |
| 945 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 946 | TEST(F16_F32_VCVT__SSE41_INT32_X32, batch_eq_32) { |
| 947 | TEST_REQUIRES_X86_SSE41; |
| 948 | VCvtMicrokernelTester() |
| 949 | .batch_size(32) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 950 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int32_x32, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 951 | } |
| 952 | |
| 953 | TEST(F16_F32_VCVT__SSE41_INT32_X32, batch_div_32) { |
| 954 | TEST_REQUIRES_X86_SSE41; |
| 955 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 956 | VCvtMicrokernelTester() |
| 957 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 958 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int32_x32, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 959 | } |
| 960 | } |
| 961 | |
| 962 | TEST(F16_F32_VCVT__SSE41_INT32_X32, batch_lt_32) { |
| 963 | TEST_REQUIRES_X86_SSE41; |
| 964 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 965 | VCvtMicrokernelTester() |
| 966 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 967 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int32_x32, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 968 | } |
| 969 | } |
| 970 | |
| 971 | TEST(F16_F32_VCVT__SSE41_INT32_X32, batch_gt_32) { |
| 972 | TEST_REQUIRES_X86_SSE41; |
| 973 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 974 | VCvtMicrokernelTester() |
| 975 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 976 | .Test(xnn_f16_f32_vcvt_ukernel__sse41_int32_x32, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 977 | } |
| 978 | } |
| 979 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 980 | |
| 981 | |
| 982 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 983 | TEST(F16_F32_VCVT__AVX_INT16_X8, batch_eq_8) { |
| 984 | TEST_REQUIRES_X86_AVX; |
| 985 | VCvtMicrokernelTester() |
| 986 | .batch_size(8) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 987 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int16_x8, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 988 | } |
| 989 | |
| 990 | TEST(F16_F32_VCVT__AVX_INT16_X8, batch_div_8) { |
| 991 | TEST_REQUIRES_X86_AVX; |
| 992 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 993 | VCvtMicrokernelTester() |
| 994 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 995 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int16_x8, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 996 | } |
| 997 | } |
| 998 | |
| 999 | TEST(F16_F32_VCVT__AVX_INT16_X8, batch_lt_8) { |
| 1000 | TEST_REQUIRES_X86_AVX; |
| 1001 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 1002 | VCvtMicrokernelTester() |
| 1003 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1004 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int16_x8, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1005 | } |
| 1006 | } |
| 1007 | |
| 1008 | TEST(F16_F32_VCVT__AVX_INT16_X8, batch_gt_8) { |
| 1009 | TEST_REQUIRES_X86_AVX; |
| 1010 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 1011 | VCvtMicrokernelTester() |
| 1012 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1013 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int16_x8, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1014 | } |
| 1015 | } |
| 1016 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1017 | |
| 1018 | |
| 1019 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1020 | TEST(F16_F32_VCVT__AVX_INT16_X16, batch_eq_16) { |
| 1021 | TEST_REQUIRES_X86_AVX; |
| 1022 | VCvtMicrokernelTester() |
| 1023 | .batch_size(16) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1024 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int16_x16, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1025 | } |
| 1026 | |
| 1027 | TEST(F16_F32_VCVT__AVX_INT16_X16, batch_div_16) { |
| 1028 | TEST_REQUIRES_X86_AVX; |
| 1029 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 1030 | VCvtMicrokernelTester() |
| 1031 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1032 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int16_x16, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1033 | } |
| 1034 | } |
| 1035 | |
| 1036 | TEST(F16_F32_VCVT__AVX_INT16_X16, batch_lt_16) { |
| 1037 | TEST_REQUIRES_X86_AVX; |
| 1038 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 1039 | VCvtMicrokernelTester() |
| 1040 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1041 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int16_x16, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1042 | } |
| 1043 | } |
| 1044 | |
| 1045 | TEST(F16_F32_VCVT__AVX_INT16_X16, batch_gt_16) { |
| 1046 | TEST_REQUIRES_X86_AVX; |
| 1047 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 1048 | VCvtMicrokernelTester() |
| 1049 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1050 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int16_x16, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1051 | } |
| 1052 | } |
| 1053 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1054 | |
| 1055 | |
| 1056 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1057 | TEST(F16_F32_VCVT__AVX_INT16_X24, batch_eq_24) { |
| 1058 | TEST_REQUIRES_X86_AVX; |
| 1059 | VCvtMicrokernelTester() |
| 1060 | .batch_size(24) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1061 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int16_x24, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1062 | } |
| 1063 | |
| 1064 | TEST(F16_F32_VCVT__AVX_INT16_X24, batch_div_24) { |
| 1065 | TEST_REQUIRES_X86_AVX; |
| 1066 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 1067 | VCvtMicrokernelTester() |
| 1068 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1069 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int16_x24, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1070 | } |
| 1071 | } |
| 1072 | |
| 1073 | TEST(F16_F32_VCVT__AVX_INT16_X24, batch_lt_24) { |
| 1074 | TEST_REQUIRES_X86_AVX; |
| 1075 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 1076 | VCvtMicrokernelTester() |
| 1077 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1078 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int16_x24, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1079 | } |
| 1080 | } |
| 1081 | |
| 1082 | TEST(F16_F32_VCVT__AVX_INT16_X24, batch_gt_24) { |
| 1083 | TEST_REQUIRES_X86_AVX; |
| 1084 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 1085 | VCvtMicrokernelTester() |
| 1086 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1087 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int16_x24, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1088 | } |
| 1089 | } |
| 1090 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1091 | |
| 1092 | |
| 1093 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1094 | TEST(F16_F32_VCVT__AVX_INT16_X32, batch_eq_32) { |
| 1095 | TEST_REQUIRES_X86_AVX; |
| 1096 | VCvtMicrokernelTester() |
| 1097 | .batch_size(32) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1098 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int16_x32, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1099 | } |
| 1100 | |
| 1101 | TEST(F16_F32_VCVT__AVX_INT16_X32, batch_div_32) { |
| 1102 | TEST_REQUIRES_X86_AVX; |
| 1103 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 1104 | VCvtMicrokernelTester() |
| 1105 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1106 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int16_x32, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1107 | } |
| 1108 | } |
| 1109 | |
| 1110 | TEST(F16_F32_VCVT__AVX_INT16_X32, batch_lt_32) { |
| 1111 | TEST_REQUIRES_X86_AVX; |
| 1112 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 1113 | VCvtMicrokernelTester() |
| 1114 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1115 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int16_x32, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1116 | } |
| 1117 | } |
| 1118 | |
| 1119 | TEST(F16_F32_VCVT__AVX_INT16_X32, batch_gt_32) { |
| 1120 | TEST_REQUIRES_X86_AVX; |
| 1121 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 1122 | VCvtMicrokernelTester() |
| 1123 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1124 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int16_x32, xnn_init_f16_f32_cvt_sse_int16_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1125 | } |
| 1126 | } |
| 1127 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1128 | |
| 1129 | |
| 1130 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1131 | TEST(F16_F32_VCVT__AVX_INT32_X8, batch_eq_8) { |
| 1132 | TEST_REQUIRES_X86_AVX; |
| 1133 | VCvtMicrokernelTester() |
| 1134 | .batch_size(8) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1135 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int32_x8, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1136 | } |
| 1137 | |
| 1138 | TEST(F16_F32_VCVT__AVX_INT32_X8, batch_div_8) { |
| 1139 | TEST_REQUIRES_X86_AVX; |
| 1140 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 1141 | VCvtMicrokernelTester() |
| 1142 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1143 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int32_x8, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1144 | } |
| 1145 | } |
| 1146 | |
| 1147 | TEST(F16_F32_VCVT__AVX_INT32_X8, batch_lt_8) { |
| 1148 | TEST_REQUIRES_X86_AVX; |
| 1149 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 1150 | VCvtMicrokernelTester() |
| 1151 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1152 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int32_x8, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1153 | } |
| 1154 | } |
| 1155 | |
| 1156 | TEST(F16_F32_VCVT__AVX_INT32_X8, batch_gt_8) { |
| 1157 | TEST_REQUIRES_X86_AVX; |
| 1158 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 1159 | VCvtMicrokernelTester() |
| 1160 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1161 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int32_x8, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1162 | } |
| 1163 | } |
| 1164 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1165 | |
| 1166 | |
| 1167 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1168 | TEST(F16_F32_VCVT__AVX_INT32_X16, batch_eq_16) { |
| 1169 | TEST_REQUIRES_X86_AVX; |
| 1170 | VCvtMicrokernelTester() |
| 1171 | .batch_size(16) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1172 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int32_x16, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1173 | } |
| 1174 | |
| 1175 | TEST(F16_F32_VCVT__AVX_INT32_X16, batch_div_16) { |
| 1176 | TEST_REQUIRES_X86_AVX; |
| 1177 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 1178 | VCvtMicrokernelTester() |
| 1179 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1180 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int32_x16, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1181 | } |
| 1182 | } |
| 1183 | |
| 1184 | TEST(F16_F32_VCVT__AVX_INT32_X16, batch_lt_16) { |
| 1185 | TEST_REQUIRES_X86_AVX; |
| 1186 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 1187 | VCvtMicrokernelTester() |
| 1188 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1189 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int32_x16, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1190 | } |
| 1191 | } |
| 1192 | |
| 1193 | TEST(F16_F32_VCVT__AVX_INT32_X16, batch_gt_16) { |
| 1194 | TEST_REQUIRES_X86_AVX; |
| 1195 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 1196 | VCvtMicrokernelTester() |
| 1197 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1198 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int32_x16, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1199 | } |
| 1200 | } |
| 1201 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1202 | |
| 1203 | |
| 1204 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1205 | TEST(F16_F32_VCVT__AVX_INT32_X24, batch_eq_24) { |
| 1206 | TEST_REQUIRES_X86_AVX; |
| 1207 | VCvtMicrokernelTester() |
| 1208 | .batch_size(24) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1209 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int32_x24, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1210 | } |
| 1211 | |
| 1212 | TEST(F16_F32_VCVT__AVX_INT32_X24, batch_div_24) { |
| 1213 | TEST_REQUIRES_X86_AVX; |
| 1214 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 1215 | VCvtMicrokernelTester() |
| 1216 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1217 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int32_x24, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1218 | } |
| 1219 | } |
| 1220 | |
| 1221 | TEST(F16_F32_VCVT__AVX_INT32_X24, batch_lt_24) { |
| 1222 | TEST_REQUIRES_X86_AVX; |
| 1223 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 1224 | VCvtMicrokernelTester() |
| 1225 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1226 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int32_x24, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1227 | } |
| 1228 | } |
| 1229 | |
| 1230 | TEST(F16_F32_VCVT__AVX_INT32_X24, batch_gt_24) { |
| 1231 | TEST_REQUIRES_X86_AVX; |
| 1232 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 1233 | VCvtMicrokernelTester() |
| 1234 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1235 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int32_x24, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1236 | } |
| 1237 | } |
| 1238 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1239 | |
| 1240 | |
| 1241 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1242 | TEST(F16_F32_VCVT__AVX_INT32_X32, batch_eq_32) { |
| 1243 | TEST_REQUIRES_X86_AVX; |
| 1244 | VCvtMicrokernelTester() |
| 1245 | .batch_size(32) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1246 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int32_x32, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1247 | } |
| 1248 | |
| 1249 | TEST(F16_F32_VCVT__AVX_INT32_X32, batch_div_32) { |
| 1250 | TEST_REQUIRES_X86_AVX; |
| 1251 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 1252 | VCvtMicrokernelTester() |
| 1253 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1254 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int32_x32, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1255 | } |
| 1256 | } |
| 1257 | |
| 1258 | TEST(F16_F32_VCVT__AVX_INT32_X32, batch_lt_32) { |
| 1259 | TEST_REQUIRES_X86_AVX; |
| 1260 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 1261 | VCvtMicrokernelTester() |
| 1262 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1263 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int32_x32, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1264 | } |
| 1265 | } |
| 1266 | |
| 1267 | TEST(F16_F32_VCVT__AVX_INT32_X32, batch_gt_32) { |
| 1268 | TEST_REQUIRES_X86_AVX; |
| 1269 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 1270 | VCvtMicrokernelTester() |
| 1271 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1272 | .Test(xnn_f16_f32_vcvt_ukernel__avx_int32_x32, xnn_init_f16_f32_cvt_sse_int32_params); |
Marat Dukhan | 1227adb | 2021-10-16 17:33:51 -0700 | [diff] [blame] | 1273 | } |
| 1274 | } |
| 1275 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1276 | |
| 1277 | |
| 1278 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | f1a6ed3 | 2021-09-26 13:40:19 -0700 | [diff] [blame] | 1279 | TEST(F16_F32_VCVT__F16C_X8, batch_eq_8) { |
| 1280 | TEST_REQUIRES_X86_F16C; |
| 1281 | VCvtMicrokernelTester() |
| 1282 | .batch_size(8) |
| 1283 | .Test(xnn_f16_f32_vcvt_ukernel__f16c_x8); |
| 1284 | } |
| 1285 | |
| 1286 | TEST(F16_F32_VCVT__F16C_X8, batch_div_8) { |
| 1287 | TEST_REQUIRES_X86_F16C; |
| 1288 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 1289 | VCvtMicrokernelTester() |
| 1290 | .batch_size(batch_size) |
| 1291 | .Test(xnn_f16_f32_vcvt_ukernel__f16c_x8); |
| 1292 | } |
| 1293 | } |
| 1294 | |
| 1295 | TEST(F16_F32_VCVT__F16C_X8, batch_lt_8) { |
| 1296 | TEST_REQUIRES_X86_F16C; |
| 1297 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 1298 | VCvtMicrokernelTester() |
| 1299 | .batch_size(batch_size) |
| 1300 | .Test(xnn_f16_f32_vcvt_ukernel__f16c_x8); |
| 1301 | } |
| 1302 | } |
| 1303 | |
| 1304 | TEST(F16_F32_VCVT__F16C_X8, batch_gt_8) { |
| 1305 | TEST_REQUIRES_X86_F16C; |
| 1306 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 1307 | VCvtMicrokernelTester() |
| 1308 | .batch_size(batch_size) |
| 1309 | .Test(xnn_f16_f32_vcvt_ukernel__f16c_x8); |
| 1310 | } |
| 1311 | } |
| 1312 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1313 | |
| 1314 | |
| 1315 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1316 | TEST(F16_F32_VCVT__F16C_X16, batch_eq_16) { |
| 1317 | TEST_REQUIRES_X86_F16C; |
| 1318 | VCvtMicrokernelTester() |
| 1319 | .batch_size(16) |
| 1320 | .Test(xnn_f16_f32_vcvt_ukernel__f16c_x16); |
| 1321 | } |
| 1322 | |
| 1323 | TEST(F16_F32_VCVT__F16C_X16, batch_div_16) { |
| 1324 | TEST_REQUIRES_X86_F16C; |
| 1325 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 1326 | VCvtMicrokernelTester() |
| 1327 | .batch_size(batch_size) |
| 1328 | .Test(xnn_f16_f32_vcvt_ukernel__f16c_x16); |
| 1329 | } |
| 1330 | } |
| 1331 | |
| 1332 | TEST(F16_F32_VCVT__F16C_X16, batch_lt_16) { |
| 1333 | TEST_REQUIRES_X86_F16C; |
| 1334 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 1335 | VCvtMicrokernelTester() |
| 1336 | .batch_size(batch_size) |
| 1337 | .Test(xnn_f16_f32_vcvt_ukernel__f16c_x16); |
| 1338 | } |
| 1339 | } |
| 1340 | |
| 1341 | TEST(F16_F32_VCVT__F16C_X16, batch_gt_16) { |
| 1342 | TEST_REQUIRES_X86_F16C; |
| 1343 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 1344 | VCvtMicrokernelTester() |
| 1345 | .batch_size(batch_size) |
| 1346 | .Test(xnn_f16_f32_vcvt_ukernel__f16c_x16); |
| 1347 | } |
| 1348 | } |
| 1349 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | 79c76ab | 2021-09-26 20:26:39 -0700 | [diff] [blame] | 1350 | |
| 1351 | |
| 1352 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1353 | TEST(F16_F32_VCVT__AVX512SKX_X16, batch_eq_16) { |
| 1354 | TEST_REQUIRES_X86_AVX512SKX; |
| 1355 | VCvtMicrokernelTester() |
| 1356 | .batch_size(16) |
| 1357 | .Test(xnn_f16_f32_vcvt_ukernel__avx512skx_x16); |
| 1358 | } |
| 1359 | |
| 1360 | TEST(F16_F32_VCVT__AVX512SKX_X16, batch_div_16) { |
| 1361 | TEST_REQUIRES_X86_AVX512SKX; |
| 1362 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 1363 | VCvtMicrokernelTester() |
| 1364 | .batch_size(batch_size) |
| 1365 | .Test(xnn_f16_f32_vcvt_ukernel__avx512skx_x16); |
| 1366 | } |
| 1367 | } |
| 1368 | |
| 1369 | TEST(F16_F32_VCVT__AVX512SKX_X16, batch_lt_16) { |
| 1370 | TEST_REQUIRES_X86_AVX512SKX; |
| 1371 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 1372 | VCvtMicrokernelTester() |
| 1373 | .batch_size(batch_size) |
| 1374 | .Test(xnn_f16_f32_vcvt_ukernel__avx512skx_x16); |
| 1375 | } |
| 1376 | } |
| 1377 | |
| 1378 | TEST(F16_F32_VCVT__AVX512SKX_X16, batch_gt_16) { |
| 1379 | TEST_REQUIRES_X86_AVX512SKX; |
| 1380 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 1381 | VCvtMicrokernelTester() |
| 1382 | .batch_size(batch_size) |
| 1383 | .Test(xnn_f16_f32_vcvt_ukernel__avx512skx_x16); |
| 1384 | } |
| 1385 | } |
| 1386 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1387 | |
| 1388 | |
| 1389 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1390 | TEST(F16_F32_VCVT__AVX512SKX_X32, batch_eq_32) { |
| 1391 | TEST_REQUIRES_X86_AVX512SKX; |
| 1392 | VCvtMicrokernelTester() |
| 1393 | .batch_size(32) |
| 1394 | .Test(xnn_f16_f32_vcvt_ukernel__avx512skx_x32); |
| 1395 | } |
| 1396 | |
| 1397 | TEST(F16_F32_VCVT__AVX512SKX_X32, batch_div_32) { |
| 1398 | TEST_REQUIRES_X86_AVX512SKX; |
| 1399 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 1400 | VCvtMicrokernelTester() |
| 1401 | .batch_size(batch_size) |
| 1402 | .Test(xnn_f16_f32_vcvt_ukernel__avx512skx_x32); |
| 1403 | } |
| 1404 | } |
| 1405 | |
| 1406 | TEST(F16_F32_VCVT__AVX512SKX_X32, batch_lt_32) { |
| 1407 | TEST_REQUIRES_X86_AVX512SKX; |
| 1408 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 1409 | VCvtMicrokernelTester() |
| 1410 | .batch_size(batch_size) |
| 1411 | .Test(xnn_f16_f32_vcvt_ukernel__avx512skx_x32); |
| 1412 | } |
| 1413 | } |
| 1414 | |
| 1415 | TEST(F16_F32_VCVT__AVX512SKX_X32, batch_gt_32) { |
| 1416 | TEST_REQUIRES_X86_AVX512SKX; |
| 1417 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 1418 | VCvtMicrokernelTester() |
| 1419 | .batch_size(batch_size) |
| 1420 | .Test(xnn_f16_f32_vcvt_ukernel__avx512skx_x32); |
| 1421 | } |
| 1422 | } |
| 1423 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1424 | |
| 1425 | |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1426 | #if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1427 | TEST(F16_F32_VCVT__WASMSIMD_INT16_X8, batch_eq_8) { |
| 1428 | VCvtMicrokernelTester() |
| 1429 | .batch_size(8) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1430 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int16_x8, xnn_init_f16_f32_cvt_wasmsimd_int16_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1431 | } |
| 1432 | |
| 1433 | TEST(F16_F32_VCVT__WASMSIMD_INT16_X8, batch_div_8) { |
| 1434 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 1435 | VCvtMicrokernelTester() |
| 1436 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1437 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int16_x8, xnn_init_f16_f32_cvt_wasmsimd_int16_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1438 | } |
| 1439 | } |
| 1440 | |
| 1441 | TEST(F16_F32_VCVT__WASMSIMD_INT16_X8, batch_lt_8) { |
| 1442 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 1443 | VCvtMicrokernelTester() |
| 1444 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1445 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int16_x8, xnn_init_f16_f32_cvt_wasmsimd_int16_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1446 | } |
| 1447 | } |
| 1448 | |
| 1449 | TEST(F16_F32_VCVT__WASMSIMD_INT16_X8, batch_gt_8) { |
| 1450 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 1451 | VCvtMicrokernelTester() |
| 1452 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1453 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int16_x8, xnn_init_f16_f32_cvt_wasmsimd_int16_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1454 | } |
| 1455 | } |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1456 | #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1457 | |
| 1458 | |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1459 | #if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1460 | TEST(F16_F32_VCVT__WASMSIMD_INT16_X16, batch_eq_16) { |
| 1461 | VCvtMicrokernelTester() |
| 1462 | .batch_size(16) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1463 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int16_x16, xnn_init_f16_f32_cvt_wasmsimd_int16_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1464 | } |
| 1465 | |
| 1466 | TEST(F16_F32_VCVT__WASMSIMD_INT16_X16, batch_div_16) { |
| 1467 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 1468 | VCvtMicrokernelTester() |
| 1469 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1470 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int16_x16, xnn_init_f16_f32_cvt_wasmsimd_int16_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1471 | } |
| 1472 | } |
| 1473 | |
| 1474 | TEST(F16_F32_VCVT__WASMSIMD_INT16_X16, batch_lt_16) { |
| 1475 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 1476 | VCvtMicrokernelTester() |
| 1477 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1478 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int16_x16, xnn_init_f16_f32_cvt_wasmsimd_int16_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1479 | } |
| 1480 | } |
| 1481 | |
| 1482 | TEST(F16_F32_VCVT__WASMSIMD_INT16_X16, batch_gt_16) { |
| 1483 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 1484 | VCvtMicrokernelTester() |
| 1485 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1486 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int16_x16, xnn_init_f16_f32_cvt_wasmsimd_int16_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1487 | } |
| 1488 | } |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1489 | #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1490 | |
| 1491 | |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1492 | #if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1493 | TEST(F16_F32_VCVT__WASMSIMD_INT16_X24, batch_eq_24) { |
| 1494 | VCvtMicrokernelTester() |
| 1495 | .batch_size(24) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1496 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int16_x24, xnn_init_f16_f32_cvt_wasmsimd_int16_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1497 | } |
| 1498 | |
| 1499 | TEST(F16_F32_VCVT__WASMSIMD_INT16_X24, batch_div_24) { |
| 1500 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 1501 | VCvtMicrokernelTester() |
| 1502 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1503 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int16_x24, xnn_init_f16_f32_cvt_wasmsimd_int16_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1504 | } |
| 1505 | } |
| 1506 | |
| 1507 | TEST(F16_F32_VCVT__WASMSIMD_INT16_X24, batch_lt_24) { |
| 1508 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 1509 | VCvtMicrokernelTester() |
| 1510 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1511 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int16_x24, xnn_init_f16_f32_cvt_wasmsimd_int16_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1512 | } |
| 1513 | } |
| 1514 | |
| 1515 | TEST(F16_F32_VCVT__WASMSIMD_INT16_X24, batch_gt_24) { |
| 1516 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 1517 | VCvtMicrokernelTester() |
| 1518 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1519 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int16_x24, xnn_init_f16_f32_cvt_wasmsimd_int16_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1520 | } |
| 1521 | } |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1522 | #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1523 | |
| 1524 | |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1525 | #if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1526 | TEST(F16_F32_VCVT__WASMSIMD_INT16_X32, batch_eq_32) { |
| 1527 | VCvtMicrokernelTester() |
| 1528 | .batch_size(32) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1529 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int16_x32, xnn_init_f16_f32_cvt_wasmsimd_int16_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1530 | } |
| 1531 | |
| 1532 | TEST(F16_F32_VCVT__WASMSIMD_INT16_X32, batch_div_32) { |
| 1533 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 1534 | VCvtMicrokernelTester() |
| 1535 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1536 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int16_x32, xnn_init_f16_f32_cvt_wasmsimd_int16_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1537 | } |
| 1538 | } |
| 1539 | |
| 1540 | TEST(F16_F32_VCVT__WASMSIMD_INT16_X32, batch_lt_32) { |
| 1541 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 1542 | VCvtMicrokernelTester() |
| 1543 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1544 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int16_x32, xnn_init_f16_f32_cvt_wasmsimd_int16_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1545 | } |
| 1546 | } |
| 1547 | |
| 1548 | TEST(F16_F32_VCVT__WASMSIMD_INT16_X32, batch_gt_32) { |
| 1549 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 1550 | VCvtMicrokernelTester() |
| 1551 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1552 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int16_x32, xnn_init_f16_f32_cvt_wasmsimd_int16_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1553 | } |
| 1554 | } |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1555 | #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1556 | |
| 1557 | |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1558 | #if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1559 | TEST(F16_F32_VCVT__WASMSIMD_INT32_X8, batch_eq_8) { |
| 1560 | VCvtMicrokernelTester() |
| 1561 | .batch_size(8) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1562 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int32_x8, xnn_init_f16_f32_cvt_wasmsimd_int32_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1563 | } |
| 1564 | |
| 1565 | TEST(F16_F32_VCVT__WASMSIMD_INT32_X8, batch_div_8) { |
| 1566 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 1567 | VCvtMicrokernelTester() |
| 1568 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1569 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int32_x8, xnn_init_f16_f32_cvt_wasmsimd_int32_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1570 | } |
| 1571 | } |
| 1572 | |
| 1573 | TEST(F16_F32_VCVT__WASMSIMD_INT32_X8, batch_lt_8) { |
| 1574 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 1575 | VCvtMicrokernelTester() |
| 1576 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1577 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int32_x8, xnn_init_f16_f32_cvt_wasmsimd_int32_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1578 | } |
| 1579 | } |
| 1580 | |
| 1581 | TEST(F16_F32_VCVT__WASMSIMD_INT32_X8, batch_gt_8) { |
| 1582 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 1583 | VCvtMicrokernelTester() |
| 1584 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1585 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int32_x8, xnn_init_f16_f32_cvt_wasmsimd_int32_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1586 | } |
| 1587 | } |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1588 | #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1589 | |
| 1590 | |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1591 | #if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1592 | TEST(F16_F32_VCVT__WASMSIMD_INT32_X16, batch_eq_16) { |
| 1593 | VCvtMicrokernelTester() |
| 1594 | .batch_size(16) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1595 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int32_x16, xnn_init_f16_f32_cvt_wasmsimd_int32_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1596 | } |
| 1597 | |
| 1598 | TEST(F16_F32_VCVT__WASMSIMD_INT32_X16, batch_div_16) { |
| 1599 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 1600 | VCvtMicrokernelTester() |
| 1601 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1602 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int32_x16, xnn_init_f16_f32_cvt_wasmsimd_int32_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1603 | } |
| 1604 | } |
| 1605 | |
| 1606 | TEST(F16_F32_VCVT__WASMSIMD_INT32_X16, batch_lt_16) { |
| 1607 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 1608 | VCvtMicrokernelTester() |
| 1609 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1610 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int32_x16, xnn_init_f16_f32_cvt_wasmsimd_int32_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1611 | } |
| 1612 | } |
| 1613 | |
| 1614 | TEST(F16_F32_VCVT__WASMSIMD_INT32_X16, batch_gt_16) { |
| 1615 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 1616 | VCvtMicrokernelTester() |
| 1617 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1618 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int32_x16, xnn_init_f16_f32_cvt_wasmsimd_int32_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1619 | } |
| 1620 | } |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1621 | #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1622 | |
| 1623 | |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1624 | #if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1625 | TEST(F16_F32_VCVT__WASMSIMD_INT32_X24, batch_eq_24) { |
| 1626 | VCvtMicrokernelTester() |
| 1627 | .batch_size(24) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1628 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int32_x24, xnn_init_f16_f32_cvt_wasmsimd_int32_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1629 | } |
| 1630 | |
| 1631 | TEST(F16_F32_VCVT__WASMSIMD_INT32_X24, batch_div_24) { |
| 1632 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 1633 | VCvtMicrokernelTester() |
| 1634 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1635 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int32_x24, xnn_init_f16_f32_cvt_wasmsimd_int32_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1636 | } |
| 1637 | } |
| 1638 | |
| 1639 | TEST(F16_F32_VCVT__WASMSIMD_INT32_X24, batch_lt_24) { |
| 1640 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 1641 | VCvtMicrokernelTester() |
| 1642 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1643 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int32_x24, xnn_init_f16_f32_cvt_wasmsimd_int32_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1644 | } |
| 1645 | } |
| 1646 | |
| 1647 | TEST(F16_F32_VCVT__WASMSIMD_INT32_X24, batch_gt_24) { |
| 1648 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 1649 | VCvtMicrokernelTester() |
| 1650 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1651 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int32_x24, xnn_init_f16_f32_cvt_wasmsimd_int32_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1652 | } |
| 1653 | } |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1654 | #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1655 | |
| 1656 | |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1657 | #if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1658 | TEST(F16_F32_VCVT__WASMSIMD_INT32_X32, batch_eq_32) { |
| 1659 | VCvtMicrokernelTester() |
| 1660 | .batch_size(32) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1661 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int32_x32, xnn_init_f16_f32_cvt_wasmsimd_int32_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1662 | } |
| 1663 | |
| 1664 | TEST(F16_F32_VCVT__WASMSIMD_INT32_X32, batch_div_32) { |
| 1665 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 1666 | VCvtMicrokernelTester() |
| 1667 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1668 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int32_x32, xnn_init_f16_f32_cvt_wasmsimd_int32_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1669 | } |
| 1670 | } |
| 1671 | |
| 1672 | TEST(F16_F32_VCVT__WASMSIMD_INT32_X32, batch_lt_32) { |
| 1673 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 1674 | VCvtMicrokernelTester() |
| 1675 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1676 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int32_x32, xnn_init_f16_f32_cvt_wasmsimd_int32_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1677 | } |
| 1678 | } |
| 1679 | |
| 1680 | TEST(F16_F32_VCVT__WASMSIMD_INT32_X32, batch_gt_32) { |
| 1681 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 1682 | VCvtMicrokernelTester() |
| 1683 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1684 | .Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int32_x32, xnn_init_f16_f32_cvt_wasmsimd_int32_params); |
Marat Dukhan | f6507f8 | 2021-10-16 18:13:04 -0700 | [diff] [blame] | 1685 | } |
| 1686 | } |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1687 | #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1688 | |
| 1689 | |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1690 | TEST(F16_F32_VCVT__SCALAR_X1, batch_eq_1) { |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1691 | VCvtMicrokernelTester() |
| 1692 | .batch_size(1) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1693 | .Test(xnn_f16_f32_vcvt_ukernel__scalar_x1, xnn_init_f16_f32_cvt_scalar_params); |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1694 | } |
| 1695 | |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1696 | TEST(F16_F32_VCVT__SCALAR_X1, batch_gt_1) { |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1697 | for (size_t batch_size = 2; batch_size < 10; batch_size++) { |
| 1698 | VCvtMicrokernelTester() |
| 1699 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1700 | .Test(xnn_f16_f32_vcvt_ukernel__scalar_x1, xnn_init_f16_f32_cvt_scalar_params); |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1701 | } |
| 1702 | } |
| 1703 | |
Marat Dukhan | 4bdc9f5 | 2021-12-09 15:36:06 -0800 | [diff] [blame] | 1704 | |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1705 | TEST(F16_F32_VCVT__SCALAR_X2, batch_eq_2) { |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1706 | VCvtMicrokernelTester() |
| 1707 | .batch_size(2) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1708 | .Test(xnn_f16_f32_vcvt_ukernel__scalar_x2, xnn_init_f16_f32_cvt_scalar_params); |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1709 | } |
| 1710 | |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1711 | TEST(F16_F32_VCVT__SCALAR_X2, batch_div_2) { |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1712 | for (size_t batch_size = 4; batch_size < 20; batch_size += 2) { |
| 1713 | VCvtMicrokernelTester() |
| 1714 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1715 | .Test(xnn_f16_f32_vcvt_ukernel__scalar_x2, xnn_init_f16_f32_cvt_scalar_params); |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1716 | } |
| 1717 | } |
| 1718 | |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1719 | TEST(F16_F32_VCVT__SCALAR_X2, batch_lt_2) { |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1720 | for (size_t batch_size = 1; batch_size < 2; batch_size++) { |
| 1721 | VCvtMicrokernelTester() |
| 1722 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1723 | .Test(xnn_f16_f32_vcvt_ukernel__scalar_x2, xnn_init_f16_f32_cvt_scalar_params); |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1724 | } |
| 1725 | } |
| 1726 | |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1727 | TEST(F16_F32_VCVT__SCALAR_X2, batch_gt_2) { |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1728 | for (size_t batch_size = 3; batch_size < 4; batch_size++) { |
| 1729 | VCvtMicrokernelTester() |
| 1730 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1731 | .Test(xnn_f16_f32_vcvt_ukernel__scalar_x2, xnn_init_f16_f32_cvt_scalar_params); |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1732 | } |
| 1733 | } |
| 1734 | |
Marat Dukhan | 4bdc9f5 | 2021-12-09 15:36:06 -0800 | [diff] [blame] | 1735 | |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1736 | TEST(F16_F32_VCVT__SCALAR_X3, batch_eq_3) { |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1737 | VCvtMicrokernelTester() |
| 1738 | .batch_size(3) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1739 | .Test(xnn_f16_f32_vcvt_ukernel__scalar_x3, xnn_init_f16_f32_cvt_scalar_params); |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1740 | } |
| 1741 | |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1742 | TEST(F16_F32_VCVT__SCALAR_X3, batch_div_3) { |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1743 | for (size_t batch_size = 6; batch_size < 30; batch_size += 3) { |
| 1744 | VCvtMicrokernelTester() |
| 1745 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1746 | .Test(xnn_f16_f32_vcvt_ukernel__scalar_x3, xnn_init_f16_f32_cvt_scalar_params); |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1747 | } |
| 1748 | } |
| 1749 | |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1750 | TEST(F16_F32_VCVT__SCALAR_X3, batch_lt_3) { |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1751 | for (size_t batch_size = 1; batch_size < 3; batch_size++) { |
| 1752 | VCvtMicrokernelTester() |
| 1753 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1754 | .Test(xnn_f16_f32_vcvt_ukernel__scalar_x3, xnn_init_f16_f32_cvt_scalar_params); |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1755 | } |
| 1756 | } |
| 1757 | |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1758 | TEST(F16_F32_VCVT__SCALAR_X3, batch_gt_3) { |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1759 | for (size_t batch_size = 4; batch_size < 6; batch_size++) { |
| 1760 | VCvtMicrokernelTester() |
| 1761 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1762 | .Test(xnn_f16_f32_vcvt_ukernel__scalar_x3, xnn_init_f16_f32_cvt_scalar_params); |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1763 | } |
| 1764 | } |
| 1765 | |
Marat Dukhan | 4bdc9f5 | 2021-12-09 15:36:06 -0800 | [diff] [blame] | 1766 | |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1767 | TEST(F16_F32_VCVT__SCALAR_X4, batch_eq_4) { |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1768 | VCvtMicrokernelTester() |
| 1769 | .batch_size(4) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1770 | .Test(xnn_f16_f32_vcvt_ukernel__scalar_x4, xnn_init_f16_f32_cvt_scalar_params); |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1771 | } |
| 1772 | |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1773 | TEST(F16_F32_VCVT__SCALAR_X4, batch_div_4) { |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1774 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 1775 | VCvtMicrokernelTester() |
| 1776 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1777 | .Test(xnn_f16_f32_vcvt_ukernel__scalar_x4, xnn_init_f16_f32_cvt_scalar_params); |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1778 | } |
| 1779 | } |
| 1780 | |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1781 | TEST(F16_F32_VCVT__SCALAR_X4, batch_lt_4) { |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1782 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 1783 | VCvtMicrokernelTester() |
| 1784 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1785 | .Test(xnn_f16_f32_vcvt_ukernel__scalar_x4, xnn_init_f16_f32_cvt_scalar_params); |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1786 | } |
| 1787 | } |
| 1788 | |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1789 | TEST(F16_F32_VCVT__SCALAR_X4, batch_gt_4) { |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1790 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 1791 | VCvtMicrokernelTester() |
| 1792 | .batch_size(batch_size) |
Marat Dukhan | 134f984 | 2021-12-29 19:57:31 -0800 | [diff] [blame] | 1793 | .Test(xnn_f16_f32_vcvt_ukernel__scalar_x4, xnn_init_f16_f32_cvt_scalar_params); |
Marat Dukhan | e2c0001 | 2021-10-17 22:02:35 -0700 | [diff] [blame] | 1794 | } |
Marat Dukhan | 4bdc9f5 | 2021-12-09 15:36:06 -0800 | [diff] [blame] | 1795 | } |