blob: f1776938c20327f2d228d07748e295a40506f31e [file] [log] [blame]
XNNPACK Teamb455b122019-09-27 18:10:33 -07001// Copyright (c) Facebook, Inc. and its affiliates.
2// All rights reserved.
3//
4// Copyright 2019 Google LLC
5//
6// This source code is licensed under the BSD-style license found in the
7// LICENSE file in the root directory of this source tree.
Marat Dukhan329da642019-11-19 21:44:39 -08008//
9// Auto-generated file. Do not edit!
Marat Dukhan99936602020-04-11 16:47:01 -070010// Specification: test/u8-maxpool-minmax.yaml
Marat Dukhan329da642019-11-19 21:44:39 -080011// Generator: tools/generate-maxpool-test.py
12
XNNPACK Teamb455b122019-09-27 18:10:33 -070013
XNNPACK Teamb455b122019-09-27 18:10:33 -070014#include <gtest/gtest.h>
15
Marat Dukhan1dadbf72019-10-01 10:46:20 -070016#include <xnnpack/common.h>
XNNPACK Teamb455b122019-09-27 18:10:33 -070017#include <xnnpack/isa-checks.h>
XNNPACK Teamb455b122019-09-27 18:10:33 -070018
Marat Dukhan1dadbf72019-10-01 10:46:20 -070019#include <xnnpack/maxpool.h>
XNNPACK Teamb455b122019-09-27 18:10:33 -070020#include "maxpool-microkernel-tester.h"
21
22
Marat Dukhan1dadbf72019-10-01 10:46:20 -070023#if XNN_ARCH_ARM || XNN_ARCH_ARM64
Marat Dukhan99936602020-04-11 16:47:01 -070024 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_eq_16_unipass_fulltile) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070025 TEST_REQUIRES_ARM_NEON;
Marat Dukhan329da642019-11-19 21:44:39 -080026 MaxPoolMicrokernelTester()
27 .pooling_elements(9)
28 .pooling_tile(9, 8)
29 .channels(16)
Marat Dukhan2ea50a02021-08-16 12:59:19 -070030 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -080031 }
32
Marat Dukhan99936602020-04-11 16:47:01 -070033 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_eq_16_unipass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -080034 TEST_REQUIRES_ARM_NEON;
35 MaxPoolMicrokernelTester()
36 .pooling_elements(9)
37 .pooling_tile(9, 8)
38 .channels(16)
39 .input_offset(19)
Marat Dukhan2ea50a02021-08-16 12:59:19 -070040 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -080041 }
42
Marat Dukhan99936602020-04-11 16:47:01 -070043 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_eq_16_unipass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -080044 TEST_REQUIRES_ARM_NEON;
45 MaxPoolMicrokernelTester()
46 .pooling_elements(9)
47 .pooling_tile(9, 8)
48 .channels(16)
49 .qmin(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -070050 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -080051 }
52
Marat Dukhan99936602020-04-11 16:47:01 -070053 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_eq_16_unipass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -080054 TEST_REQUIRES_ARM_NEON;
55 MaxPoolMicrokernelTester()
56 .pooling_elements(9)
57 .pooling_tile(9, 8)
58 .channels(16)
59 .qmax(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -070060 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -080061 }
62
Marat Dukhan99936602020-04-11 16:47:01 -070063 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_eq_16_unipass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -080064 TEST_REQUIRES_ARM_NEON;
65 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
66 MaxPoolMicrokernelTester()
67 .pooling_elements(pooling_elements)
68 .pooling_tile(9, 8)
69 .channels(16)
Marat Dukhan2ea50a02021-08-16 12:59:19 -070070 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -070071 }
72 }
73
Marat Dukhan99936602020-04-11 16:47:01 -070074 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_eq_16_unipass_subtile_with_input_offset) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070075 TEST_REQUIRES_ARM_NEON;
Marat Dukhan329da642019-11-19 21:44:39 -080076 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
77 MaxPoolMicrokernelTester()
78 .pooling_elements(pooling_elements)
79 .pooling_tile(9, 8)
80 .channels(16)
81 .input_offset(19)
Marat Dukhan2ea50a02021-08-16 12:59:19 -070082 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -070083 }
84 }
85
Marat Dukhan99936602020-04-11 16:47:01 -070086 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_div_16_unipass_fulltile) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070087 TEST_REQUIRES_ARM_NEON;
Marat Dukhan329da642019-11-19 21:44:39 -080088 for (size_t channels = 32; channels < 128; channels += 16) {
89 MaxPoolMicrokernelTester()
90 .pooling_elements(9)
91 .pooling_tile(9, 8)
92 .channels(channels)
Marat Dukhan2ea50a02021-08-16 12:59:19 -070093 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -070094 }
95 }
96
Marat Dukhan99936602020-04-11 16:47:01 -070097 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_div_16_unipass_fulltile_with_input_offset) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070098 TEST_REQUIRES_ARM_NEON;
Marat Dukhan329da642019-11-19 21:44:39 -080099 for (size_t channels = 32; channels < 128; channels += 16) {
100 MaxPoolMicrokernelTester()
101 .pooling_elements(9)
102 .pooling_tile(9, 8)
103 .channels(channels)
104 .input_offset(131)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700105 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700106 }
107 }
108
Marat Dukhan99936602020-04-11 16:47:01 -0700109 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_div_16_unipass_fulltile_with_qmin) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700110 TEST_REQUIRES_ARM_NEON;
Marat Dukhan329da642019-11-19 21:44:39 -0800111 for (size_t channels = 32; channels < 128; channels += 16) {
112 MaxPoolMicrokernelTester()
113 .pooling_elements(9)
114 .pooling_tile(9, 8)
115 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700116 .qmin(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700117 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800118 }
119 }
120
Marat Dukhan99936602020-04-11 16:47:01 -0700121 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_div_16_unipass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -0800122 TEST_REQUIRES_ARM_NEON;
123 for (size_t channels = 32; channels < 128; channels += 16) {
124 MaxPoolMicrokernelTester()
125 .pooling_elements(9)
126 .pooling_tile(9, 8)
127 .channels(channels)
128 .qmax(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700129 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800130 }
131 }
132
Marat Dukhan99936602020-04-11 16:47:01 -0700133 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_div_16_unipass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800134 TEST_REQUIRES_ARM_NEON;
135 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
136 for (size_t channels = 32; channels < 128; channels += 16) {
137 MaxPoolMicrokernelTester()
138 .pooling_elements(pooling_elements)
139 .pooling_tile(9, 8)
140 .channels(channels)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700141 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800142 }
143 }
144 }
145
Marat Dukhan99936602020-04-11 16:47:01 -0700146 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_div_16_unipass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800147 TEST_REQUIRES_ARM_NEON;
148 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
149 for (size_t channels = 32; channels < 128; channels += 16) {
150 MaxPoolMicrokernelTester()
151 .pooling_elements(pooling_elements)
152 .pooling_tile(9, 8)
153 .channels(channels)
154 .input_offset(131)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700155 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800156 }
157 }
158 }
159
Marat Dukhan99936602020-04-11 16:47:01 -0700160 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_lt_16_unipass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800161 TEST_REQUIRES_ARM_NEON;
162 for (size_t channels = 1; channels < 16; channels++) {
163 MaxPoolMicrokernelTester()
164 .pooling_elements(9)
165 .pooling_tile(9, 8)
166 .channels(channels)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700167 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800168 }
169 }
170
Marat Dukhan99936602020-04-11 16:47:01 -0700171 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_lt_16_unipass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800172 TEST_REQUIRES_ARM_NEON;
173 for (size_t channels = 1; channels < 16; channels++) {
174 MaxPoolMicrokernelTester()
175 .pooling_elements(9)
176 .pooling_tile(9, 8)
177 .channels(channels)
178 .input_offset(17)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700179 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800180 }
181 }
182
Marat Dukhan99936602020-04-11 16:47:01 -0700183 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_lt_16_unipass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -0800184 TEST_REQUIRES_ARM_NEON;
185 for (size_t channels = 1; channels < 16; channels++) {
186 MaxPoolMicrokernelTester()
187 .pooling_elements(9)
188 .pooling_tile(9, 8)
189 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700190 .qmin(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700191 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700192 }
193 }
194
Marat Dukhan99936602020-04-11 16:47:01 -0700195 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_lt_16_unipass_fulltile_with_qmax) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700196 TEST_REQUIRES_ARM_NEON;
Marat Dukhan329da642019-11-19 21:44:39 -0800197 for (size_t channels = 1; channels < 16; channels++) {
198 MaxPoolMicrokernelTester()
199 .pooling_elements(9)
200 .pooling_tile(9, 8)
201 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700202 .qmax(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700203 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800204 }
205 }
206
Marat Dukhan99936602020-04-11 16:47:01 -0700207 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_lt_16_unipass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800208 TEST_REQUIRES_ARM_NEON;
209 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
210 for (size_t channels = 1; channels < 16; channels++) {
211 MaxPoolMicrokernelTester()
212 .pooling_elements(pooling_elements)
213 .pooling_tile(9, 8)
214 .channels(channels)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700215 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800216 }
217 }
218 }
219
Marat Dukhan99936602020-04-11 16:47:01 -0700220 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_lt_16_unipass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800221 TEST_REQUIRES_ARM_NEON;
222 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
223 for (size_t channels = 1; channels < 16; channels++) {
224 MaxPoolMicrokernelTester()
225 .pooling_elements(pooling_elements)
226 .pooling_tile(9, 8)
227 .channels(channels)
228 .input_offset(17)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700229 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800230 }
231 }
232 }
233
Marat Dukhan99936602020-04-11 16:47:01 -0700234 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_gt_16_unipass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800235 TEST_REQUIRES_ARM_NEON;
236 for (size_t channels = 17; channels < 32; channels++) {
237 MaxPoolMicrokernelTester()
238 .pooling_elements(9)
239 .pooling_tile(9, 8)
240 .channels(channels)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700241 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800242 }
243 }
244
Marat Dukhan99936602020-04-11 16:47:01 -0700245 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_gt_16_unipass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800246 TEST_REQUIRES_ARM_NEON;
247 for (size_t channels = 17; channels < 32; channels++) {
248 MaxPoolMicrokernelTester()
249 .pooling_elements(9)
250 .pooling_tile(9, 8)
251 .channels(channels)
252 .input_offset(37)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700253 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800254 }
255 }
256
Marat Dukhan99936602020-04-11 16:47:01 -0700257 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_gt_16_unipass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -0800258 TEST_REQUIRES_ARM_NEON;
259 for (size_t channels = 17; channels < 32; channels++) {
260 MaxPoolMicrokernelTester()
261 .pooling_elements(9)
262 .pooling_tile(9, 8)
263 .channels(channels)
264 .qmin(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700265 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800266 }
267 }
268
Marat Dukhan99936602020-04-11 16:47:01 -0700269 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_gt_16_unipass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -0800270 TEST_REQUIRES_ARM_NEON;
271 for (size_t channels = 17; channels < 32; channels++) {
272 MaxPoolMicrokernelTester()
273 .pooling_elements(9)
274 .pooling_tile(9, 8)
275 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700276 .qmax(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700277 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700278 }
279 }
280
Marat Dukhan99936602020-04-11 16:47:01 -0700281 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_gt_16_unipass_subtile) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700282 TEST_REQUIRES_ARM_NEON;
Marat Dukhan329da642019-11-19 21:44:39 -0800283 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
284 for (size_t channels = 17; channels < 32; channels++) {
285 MaxPoolMicrokernelTester()
286 .pooling_elements(pooling_elements)
287 .pooling_tile(9, 8)
288 .channels(channels)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700289 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700290 }
291 }
292 }
293
Marat Dukhan99936602020-04-11 16:47:01 -0700294 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_gt_16_unipass_subtile_with_input_offset) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700295 TEST_REQUIRES_ARM_NEON;
Marat Dukhan329da642019-11-19 21:44:39 -0800296 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
297 for (size_t channels = 17; channels < 32; channels++) {
298 MaxPoolMicrokernelTester()
299 .pooling_elements(pooling_elements)
300 .pooling_tile(9, 8)
301 .channels(channels)
302 .input_offset(37)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700303 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800304 }
305 }
306 }
307
Marat Dukhan99936602020-04-11 16:47:01 -0700308 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_eq_16_twopass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800309 TEST_REQUIRES_ARM_NEON;
310 MaxPoolMicrokernelTester()
311 .pooling_elements(17)
312 .pooling_tile(9, 8)
313 .channels(16)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700314 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800315 }
316
Marat Dukhan99936602020-04-11 16:47:01 -0700317 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_eq_16_twopass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800318 TEST_REQUIRES_ARM_NEON;
319 MaxPoolMicrokernelTester()
320 .pooling_elements(17)
321 .pooling_tile(9, 8)
322 .channels(16)
323 .input_offset(19)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700324 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800325 }
326
Marat Dukhan99936602020-04-11 16:47:01 -0700327 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_eq_16_twopass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -0800328 TEST_REQUIRES_ARM_NEON;
329 MaxPoolMicrokernelTester()
330 .pooling_elements(17)
331 .pooling_tile(9, 8)
332 .channels(16)
333 .qmin(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700334 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800335 }
336
Marat Dukhan99936602020-04-11 16:47:01 -0700337 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_eq_16_twopass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -0800338 TEST_REQUIRES_ARM_NEON;
339 MaxPoolMicrokernelTester()
340 .pooling_elements(17)
341 .pooling_tile(9, 8)
342 .channels(16)
343 .qmax(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700344 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800345 }
346
Marat Dukhan99936602020-04-11 16:47:01 -0700347 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_eq_16_twopass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800348 TEST_REQUIRES_ARM_NEON;
349 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
350 MaxPoolMicrokernelTester()
351 .pooling_elements(pooling_elements)
352 .pooling_tile(9, 8)
353 .channels(16)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700354 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800355 }
356 }
357
Marat Dukhan99936602020-04-11 16:47:01 -0700358 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_eq_16_twopass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800359 TEST_REQUIRES_ARM_NEON;
360 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
361 MaxPoolMicrokernelTester()
362 .pooling_elements(pooling_elements)
363 .pooling_tile(9, 8)
364 .channels(16)
365 .input_offset(19)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700366 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800367 }
368 }
369
Marat Dukhan99936602020-04-11 16:47:01 -0700370 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_div_16_twopass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800371 TEST_REQUIRES_ARM_NEON;
372 for (size_t channels = 32; channels < 128; channels += 16) {
373 MaxPoolMicrokernelTester()
374 .pooling_elements(17)
375 .pooling_tile(9, 8)
376 .channels(channels)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700377 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800378 }
379 }
380
Marat Dukhan99936602020-04-11 16:47:01 -0700381 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_div_16_twopass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800382 TEST_REQUIRES_ARM_NEON;
383 for (size_t channels = 32; channels < 128; channels += 16) {
384 MaxPoolMicrokernelTester()
385 .pooling_elements(17)
386 .pooling_tile(9, 8)
387 .channels(channels)
388 .input_offset(83)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700389 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800390 }
391 }
392
Marat Dukhan99936602020-04-11 16:47:01 -0700393 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_div_16_twopass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -0800394 TEST_REQUIRES_ARM_NEON;
395 for (size_t channels = 32; channels < 128; channels += 16) {
396 MaxPoolMicrokernelTester()
397 .pooling_elements(17)
398 .pooling_tile(9, 8)
399 .channels(channels)
400 .qmin(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700401 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800402 }
403 }
404
Marat Dukhan99936602020-04-11 16:47:01 -0700405 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_div_16_twopass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -0800406 TEST_REQUIRES_ARM_NEON;
407 for (size_t channels = 32; channels < 128; channels += 16) {
408 MaxPoolMicrokernelTester()
409 .pooling_elements(17)
410 .pooling_tile(9, 8)
411 .channels(channels)
412 .qmax(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700413 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800414 }
415 }
416
Marat Dukhan99936602020-04-11 16:47:01 -0700417 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_div_16_twopass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800418 TEST_REQUIRES_ARM_NEON;
419 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
420 for (size_t channels = 32; channels < 128; channels += 16) {
421 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800422 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800423 .pooling_tile(9, 8)
424 .channels(channels)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700425 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800426 }
427 }
428 }
429
Marat Dukhan99936602020-04-11 16:47:01 -0700430 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_div_16_twopass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800431 TEST_REQUIRES_ARM_NEON;
432 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
433 for (size_t channels = 32; channels < 128; channels += 16) {
434 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800435 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800436 .pooling_tile(9, 8)
437 .channels(channels)
438 .input_offset(131)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700439 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800440 }
441 }
442 }
443
Marat Dukhan99936602020-04-11 16:47:01 -0700444 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_lt_16_twopass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800445 TEST_REQUIRES_ARM_NEON;
446 for (size_t channels = 1; channels < 16; channels++) {
447 MaxPoolMicrokernelTester()
448 .pooling_elements(17)
449 .pooling_tile(9, 8)
450 .channels(channels)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700451 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800452 }
453 }
454
Marat Dukhan99936602020-04-11 16:47:01 -0700455 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_lt_16_twopass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800456 TEST_REQUIRES_ARM_NEON;
457 for (size_t channels = 1; channels < 16; channels++) {
458 MaxPoolMicrokernelTester()
459 .pooling_elements(17)
460 .pooling_tile(9, 8)
461 .channels(channels)
462 .input_offset(17)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700463 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800464 }
465 }
466
Marat Dukhan99936602020-04-11 16:47:01 -0700467 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_lt_16_twopass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -0800468 TEST_REQUIRES_ARM_NEON;
469 for (size_t channels = 1; channels < 16; channels++) {
470 MaxPoolMicrokernelTester()
471 .pooling_elements(17)
472 .pooling_tile(9, 8)
473 .channels(channels)
474 .qmin(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700475 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800476 }
477 }
478
Marat Dukhan99936602020-04-11 16:47:01 -0700479 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_lt_16_twopass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -0800480 TEST_REQUIRES_ARM_NEON;
481 for (size_t channels = 1; channels < 16; channels++) {
482 MaxPoolMicrokernelTester()
483 .pooling_elements(17)
484 .pooling_tile(9, 8)
485 .channels(channels)
486 .qmax(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700487 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800488 }
489 }
490
Marat Dukhan99936602020-04-11 16:47:01 -0700491 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_lt_16_twopass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800492 TEST_REQUIRES_ARM_NEON;
493 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
494 for (size_t channels = 1; channels < 16; channels++) {
495 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800496 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800497 .pooling_tile(9, 8)
498 .channels(channels)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700499 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800500 }
501 }
502 }
503
Marat Dukhan99936602020-04-11 16:47:01 -0700504 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_lt_16_twopass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800505 TEST_REQUIRES_ARM_NEON;
506 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
507 for (size_t channels = 1; channels < 16; channels++) {
508 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800509 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800510 .pooling_tile(9, 8)
511 .channels(channels)
512 .input_offset(17)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700513 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800514 }
515 }
516 }
517
Marat Dukhan99936602020-04-11 16:47:01 -0700518 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_gt_16_twopass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800519 TEST_REQUIRES_ARM_NEON;
520 for (size_t channels = 17; channels < 32; channels++) {
521 MaxPoolMicrokernelTester()
522 .pooling_elements(17)
523 .pooling_tile(9, 8)
524 .channels(channels)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700525 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800526 }
527 }
528
Marat Dukhan99936602020-04-11 16:47:01 -0700529 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_gt_16_twopass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800530 TEST_REQUIRES_ARM_NEON;
531 for (size_t channels = 17; channels < 32; channels++) {
532 MaxPoolMicrokernelTester()
533 .pooling_elements(17)
534 .pooling_tile(9, 8)
535 .channels(channels)
536 .input_offset(37)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700537 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800538 }
539 }
540
Marat Dukhan99936602020-04-11 16:47:01 -0700541 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_gt_16_twopass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -0800542 TEST_REQUIRES_ARM_NEON;
543 for (size_t channels = 17; channels < 32; channels++) {
544 MaxPoolMicrokernelTester()
545 .pooling_elements(17)
546 .pooling_tile(9, 8)
547 .channels(channels)
548 .qmin(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700549 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800550 }
551 }
552
Marat Dukhan99936602020-04-11 16:47:01 -0700553 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_gt_16_twopass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -0800554 TEST_REQUIRES_ARM_NEON;
555 for (size_t channels = 17; channels < 32; channels++) {
556 MaxPoolMicrokernelTester()
557 .pooling_elements(17)
558 .pooling_tile(9, 8)
559 .channels(channels)
560 .qmax(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700561 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800562 }
563 }
564
Marat Dukhan99936602020-04-11 16:47:01 -0700565 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_gt_16_twopass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800566 TEST_REQUIRES_ARM_NEON;
567 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
568 for (size_t channels = 17; channels < 32; channels++) {
569 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800570 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800571 .pooling_tile(9, 8)
572 .channels(channels)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700573 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800574 }
575 }
576 }
577
Marat Dukhan99936602020-04-11 16:47:01 -0700578 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_gt_16_twopass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800579 TEST_REQUIRES_ARM_NEON;
580 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
581 for (size_t channels = 17; channels < 32; channels++) {
582 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800583 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800584 .pooling_tile(9, 8)
585 .channels(channels)
586 .input_offset(37)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700587 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800588 }
589 }
590 }
591
Marat Dukhan99936602020-04-11 16:47:01 -0700592 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_eq_16_multipass) {
Marat Dukhan329da642019-11-19 21:44:39 -0800593 TEST_REQUIRES_ARM_NEON;
594 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
595 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800596 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800597 .pooling_tile(9, 8)
598 .channels(16)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700599 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800600 }
601 }
602
Marat Dukhan99936602020-04-11 16:47:01 -0700603 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_eq_16_multipass_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800604 TEST_REQUIRES_ARM_NEON;
605 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
606 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800607 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800608 .pooling_tile(9, 8)
609 .channels(16)
610 .input_offset(19)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700611 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800612 }
613 }
614
Marat Dukhan99936602020-04-11 16:47:01 -0700615 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_eq_16_multipass_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -0800616 TEST_REQUIRES_ARM_NEON;
617 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
618 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800619 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800620 .pooling_tile(9, 8)
621 .channels(16)
622 .qmin(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700623 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800624 }
625 }
626
Marat Dukhan99936602020-04-11 16:47:01 -0700627 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_eq_16_multipass_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -0800628 TEST_REQUIRES_ARM_NEON;
629 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
630 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800631 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800632 .pooling_tile(9, 8)
633 .channels(16)
634 .qmax(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700635 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800636 }
637 }
638
Marat Dukhan99936602020-04-11 16:47:01 -0700639 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_div_16_multipass) {
Marat Dukhan329da642019-11-19 21:44:39 -0800640 TEST_REQUIRES_ARM_NEON;
641 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
642 for (size_t channels = 32; channels < 128; channels += 16) {
643 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800644 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800645 .pooling_tile(9, 8)
646 .channels(channels)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700647 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800648 }
649 }
650 }
651
Marat Dukhan99936602020-04-11 16:47:01 -0700652 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_div_16_multipass_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800653 TEST_REQUIRES_ARM_NEON;
654 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
655 for (size_t channels = 32; channels < 128; channels += 16) {
656 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800657 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800658 .pooling_tile(9, 8)
659 .channels(channels)
660 .input_offset(131)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700661 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800662 }
663 }
664 }
665
Marat Dukhan99936602020-04-11 16:47:01 -0700666 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_div_16_multipass_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -0800667 TEST_REQUIRES_ARM_NEON;
668 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
669 for (size_t channels = 32; channels < 128; channels += 16) {
670 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800671 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800672 .pooling_tile(9, 8)
673 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700674 .qmin(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700675 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800676 }
677 }
678 }
679
Marat Dukhan99936602020-04-11 16:47:01 -0700680 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_div_16_multipass_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -0800681 TEST_REQUIRES_ARM_NEON;
682 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
683 for (size_t channels = 32; channels < 128; channels += 16) {
684 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800685 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800686 .pooling_tile(9, 8)
687 .channels(channels)
688 .qmax(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700689 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800690 }
691 }
692 }
693
Marat Dukhan99936602020-04-11 16:47:01 -0700694 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_lt_16_multipass) {
Marat Dukhan329da642019-11-19 21:44:39 -0800695 TEST_REQUIRES_ARM_NEON;
696 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
697 for (size_t channels = 1; channels < 16; channels++) {
698 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800699 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800700 .pooling_tile(9, 8)
701 .channels(channels)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700702 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800703 }
704 }
705 }
706
Marat Dukhan99936602020-04-11 16:47:01 -0700707 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_lt_16_multipass_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800708 TEST_REQUIRES_ARM_NEON;
709 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
710 for (size_t channels = 1; channels < 16; channels++) {
711 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800712 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800713 .pooling_tile(9, 8)
714 .channels(channels)
715 .input_offset(16)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700716 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800717 }
718 }
719 }
720
Marat Dukhan99936602020-04-11 16:47:01 -0700721 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_lt_16_multipass_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -0800722 TEST_REQUIRES_ARM_NEON;
723 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
724 for (size_t channels = 1; channels < 16; channels++) {
725 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800726 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800727 .pooling_tile(9, 8)
728 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700729 .qmin(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700730 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700731 }
732 }
733 }
734
Marat Dukhan99936602020-04-11 16:47:01 -0700735 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_lt_16_multipass_with_qmax) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700736 TEST_REQUIRES_ARM_NEON;
Marat Dukhan329da642019-11-19 21:44:39 -0800737 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
738 for (size_t channels = 1; channels < 16; channels++) {
739 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800740 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800741 .pooling_tile(9, 8)
742 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700743 .qmax(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700744 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700745 }
746 }
747 }
748
Marat Dukhan99936602020-04-11 16:47:01 -0700749 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_gt_16_multipass) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700750 TEST_REQUIRES_ARM_NEON;
Marat Dukhan329da642019-11-19 21:44:39 -0800751 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
752 for (size_t channels = 17; channels < 32; channels++) {
753 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800754 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800755 .pooling_tile(9, 8)
756 .channels(channels)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700757 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700758 }
759 }
760 }
761
Marat Dukhan99936602020-04-11 16:47:01 -0700762 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_gt_16_multipass_with_input_offset) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700763 TEST_REQUIRES_ARM_NEON;
Marat Dukhan329da642019-11-19 21:44:39 -0800764 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
765 for (size_t channels = 17; channels < 32; channels++) {
766 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800767 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800768 .pooling_tile(9, 8)
769 .channels(channels)
770 .input_offset(37)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700771 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700772 }
773 }
774 }
775
Marat Dukhan99936602020-04-11 16:47:01 -0700776 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_gt_16_multipass_with_qmin) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700777 TEST_REQUIRES_ARM_NEON;
Marat Dukhan329da642019-11-19 21:44:39 -0800778 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
779 for (size_t channels = 17; channels < 32; channels++) {
780 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800781 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800782 .pooling_tile(9, 8)
783 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700784 .qmin(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700785 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700786 }
787 }
788 }
789
Marat Dukhan99936602020-04-11 16:47:01 -0700790 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, channels_gt_16_multipass_with_qmax) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700791 TEST_REQUIRES_ARM_NEON;
Marat Dukhan329da642019-11-19 21:44:39 -0800792 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
793 for (size_t channels = 17; channels < 32; channels++) {
794 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -0800795 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -0800796 .pooling_tile(9, 8)
797 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700798 .qmax(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700799 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700800 }
801 }
802 }
803
Marat Dukhan99936602020-04-11 16:47:01 -0700804 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, few_output_pixels) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700805 TEST_REQUIRES_ARM_NEON;
Marat Dukhan329da642019-11-19 21:44:39 -0800806 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
807 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
808 for (size_t channels = 1; channels <= 80; channels += 15) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700809 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -0800810 .output_pixels(output_pixels)
811 .pooling_elements(pooling_elements)
812 .pooling_tile(9, 8)
813 .channels(channels)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700814 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700815 }
816 }
817 }
818 }
819
Marat Dukhan99936602020-04-11 16:47:01 -0700820 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, few_output_pixels_with_input_offset) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700821 TEST_REQUIRES_ARM_NEON;
Marat Dukhan329da642019-11-19 21:44:39 -0800822 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
823 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
824 for (size_t channels = 1; channels <= 80; channels += 15) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700825 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -0800826 .output_pixels(output_pixels)
827 .pooling_elements(pooling_elements)
828 .pooling_tile(9, 8)
829 .channels(channels)
830 .input_offset(83)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700831 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700832 }
833 }
834 }
835 }
836
Marat Dukhan99936602020-04-11 16:47:01 -0700837 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, few_output_pixels_with_qmin) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700838 TEST_REQUIRES_ARM_NEON;
Marat Dukhan329da642019-11-19 21:44:39 -0800839 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
840 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
841 for (size_t channels = 1; channels <= 80; channels += 15) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700842 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -0800843 .output_pixels(output_pixels)
844 .pooling_elements(pooling_elements)
845 .pooling_tile(9, 8)
846 .channels(channels)
847 .qmin(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700848 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700849 }
850 }
851 }
852 }
853
Marat Dukhan99936602020-04-11 16:47:01 -0700854 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, few_output_pixels_with_qmax) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700855 TEST_REQUIRES_ARM_NEON;
Marat Dukhan329da642019-11-19 21:44:39 -0800856 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
857 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
858 for (size_t channels = 1; channels <= 80; channels += 15) {
859 MaxPoolMicrokernelTester()
860 .output_pixels(output_pixels)
861 .pooling_elements(pooling_elements)
862 .pooling_tile(9, 8)
863 .channels(channels)
864 .qmax(192)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700865 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800866 }
867 }
868 }
869 }
870
Marat Dukhan99936602020-04-11 16:47:01 -0700871 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, few_output_pixels_with_output_stride) {
Marat Dukhan329da642019-11-19 21:44:39 -0800872 TEST_REQUIRES_ARM_NEON;
873 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
874 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
875 for (size_t channels = 1; channels <= 80; channels += 15) {
876 MaxPoolMicrokernelTester()
877 .output_pixels(output_pixels)
878 .pooling_elements(pooling_elements)
879 .pooling_tile(9, 8)
880 .channels(channels)
881 .output_stride(83)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700882 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800883 }
884 }
885 }
886 }
887
Marat Dukhan99936602020-04-11 16:47:01 -0700888 TEST(U8_MAXPOOL_MINMAX_9P8X__NEON_C16, few_output_pixels_with_step) {
Marat Dukhan329da642019-11-19 21:44:39 -0800889 TEST_REQUIRES_ARM_NEON;
890 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
891 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
892 for (size_t channels = 1; channels <= 80; channels += 15) {
893 for (size_t step = 2; step <= pooling_elements; step++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700894 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -0800895 .output_pixels(output_pixels)
896 .pooling_elements(pooling_elements)
897 .pooling_tile(9, 8)
898 .step(step)
899 .channels(channels)
900 .output_stride(83)
Marat Dukhan2ea50a02021-08-16 12:59:19 -0700901 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__neon_c16, xnn_init_u8_minmax_neon_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700902 }
903 }
904 }
905 }
906 }
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700907#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
XNNPACK Teamb455b122019-09-27 18:10:33 -0700908
Marat Dukhan329da642019-11-19 21:44:39 -0800909
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700910#if XNN_ARCH_X86 || XNN_ARCH_X86_64
Marat Dukhan99936602020-04-11 16:47:01 -0700911 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_eq_16_unipass_fulltile) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700912 TEST_REQUIRES_X86_SSE2;
Marat Dukhan329da642019-11-19 21:44:39 -0800913 MaxPoolMicrokernelTester()
914 .pooling_elements(9)
915 .pooling_tile(9, 8)
916 .channels(16)
Marat Dukhan91ae1652021-08-15 19:19:49 -0700917 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800918 }
919
Marat Dukhan99936602020-04-11 16:47:01 -0700920 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_eq_16_unipass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -0800921 TEST_REQUIRES_X86_SSE2;
922 MaxPoolMicrokernelTester()
923 .pooling_elements(9)
924 .pooling_tile(9, 8)
925 .channels(16)
926 .input_offset(19)
Marat Dukhan91ae1652021-08-15 19:19:49 -0700927 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800928 }
929
Marat Dukhan99936602020-04-11 16:47:01 -0700930 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_eq_16_unipass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -0800931 TEST_REQUIRES_X86_SSE2;
932 MaxPoolMicrokernelTester()
933 .pooling_elements(9)
934 .pooling_tile(9, 8)
935 .channels(16)
936 .qmin(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -0700937 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800938 }
939
Marat Dukhan99936602020-04-11 16:47:01 -0700940 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_eq_16_unipass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -0800941 TEST_REQUIRES_X86_SSE2;
942 MaxPoolMicrokernelTester()
943 .pooling_elements(9)
944 .pooling_tile(9, 8)
945 .channels(16)
946 .qmax(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -0700947 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -0800948 }
949
Marat Dukhan99936602020-04-11 16:47:01 -0700950 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_eq_16_unipass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -0800951 TEST_REQUIRES_X86_SSE2;
952 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
953 MaxPoolMicrokernelTester()
954 .pooling_elements(pooling_elements)
955 .pooling_tile(9, 8)
956 .channels(16)
Marat Dukhan91ae1652021-08-15 19:19:49 -0700957 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700958 }
959 }
960
Marat Dukhan99936602020-04-11 16:47:01 -0700961 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_eq_16_unipass_subtile_with_input_offset) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700962 TEST_REQUIRES_X86_SSE2;
Marat Dukhan329da642019-11-19 21:44:39 -0800963 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
964 MaxPoolMicrokernelTester()
965 .pooling_elements(pooling_elements)
966 .pooling_tile(9, 8)
967 .channels(16)
968 .input_offset(19)
Marat Dukhan91ae1652021-08-15 19:19:49 -0700969 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700970 }
971 }
972
Marat Dukhan99936602020-04-11 16:47:01 -0700973 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_div_16_unipass_fulltile) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700974 TEST_REQUIRES_X86_SSE2;
Marat Dukhan329da642019-11-19 21:44:39 -0800975 for (size_t channels = 32; channels < 128; channels += 16) {
976 MaxPoolMicrokernelTester()
977 .pooling_elements(9)
978 .pooling_tile(9, 8)
979 .channels(channels)
Marat Dukhan91ae1652021-08-15 19:19:49 -0700980 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700981 }
982 }
983
Marat Dukhan99936602020-04-11 16:47:01 -0700984 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_div_16_unipass_fulltile_with_input_offset) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700985 TEST_REQUIRES_X86_SSE2;
Marat Dukhan329da642019-11-19 21:44:39 -0800986 for (size_t channels = 32; channels < 128; channels += 16) {
987 MaxPoolMicrokernelTester()
988 .pooling_elements(9)
989 .pooling_tile(9, 8)
990 .channels(channels)
991 .input_offset(131)
Marat Dukhan91ae1652021-08-15 19:19:49 -0700992 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700993 }
994 }
995
Marat Dukhan99936602020-04-11 16:47:01 -0700996 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_div_16_unipass_fulltile_with_qmin) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700997 TEST_REQUIRES_X86_SSE2;
Marat Dukhan329da642019-11-19 21:44:39 -0800998 for (size_t channels = 32; channels < 128; channels += 16) {
999 MaxPoolMicrokernelTester()
1000 .pooling_elements(9)
1001 .pooling_tile(9, 8)
1002 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07001003 .qmin(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001004 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001005 }
1006 }
1007
Marat Dukhan99936602020-04-11 16:47:01 -07001008 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_div_16_unipass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08001009 TEST_REQUIRES_X86_SSE2;
1010 for (size_t channels = 32; channels < 128; channels += 16) {
1011 MaxPoolMicrokernelTester()
1012 .pooling_elements(9)
1013 .pooling_tile(9, 8)
1014 .channels(channels)
1015 .qmax(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001016 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001017 }
1018 }
1019
Marat Dukhan99936602020-04-11 16:47:01 -07001020 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_div_16_unipass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -08001021 TEST_REQUIRES_X86_SSE2;
1022 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1023 for (size_t channels = 32; channels < 128; channels += 16) {
1024 MaxPoolMicrokernelTester()
1025 .pooling_elements(pooling_elements)
1026 .pooling_tile(9, 8)
1027 .channels(channels)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001028 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001029 }
1030 }
1031 }
1032
Marat Dukhan99936602020-04-11 16:47:01 -07001033 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_div_16_unipass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08001034 TEST_REQUIRES_X86_SSE2;
1035 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1036 for (size_t channels = 32; channels < 128; channels += 16) {
1037 MaxPoolMicrokernelTester()
1038 .pooling_elements(pooling_elements)
1039 .pooling_tile(9, 8)
1040 .channels(channels)
1041 .input_offset(131)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001042 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001043 }
1044 }
1045 }
1046
Marat Dukhan99936602020-04-11 16:47:01 -07001047 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_lt_16_unipass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -08001048 TEST_REQUIRES_X86_SSE2;
1049 for (size_t channels = 1; channels < 16; channels++) {
1050 MaxPoolMicrokernelTester()
1051 .pooling_elements(9)
1052 .pooling_tile(9, 8)
1053 .channels(channels)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001054 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001055 }
1056 }
1057
Marat Dukhan99936602020-04-11 16:47:01 -07001058 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_lt_16_unipass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08001059 TEST_REQUIRES_X86_SSE2;
1060 for (size_t channels = 1; channels < 16; channels++) {
1061 MaxPoolMicrokernelTester()
1062 .pooling_elements(9)
1063 .pooling_tile(9, 8)
1064 .channels(channels)
1065 .input_offset(17)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001066 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001067 }
1068 }
1069
Marat Dukhan99936602020-04-11 16:47:01 -07001070 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_lt_16_unipass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08001071 TEST_REQUIRES_X86_SSE2;
1072 for (size_t channels = 1; channels < 16; channels++) {
1073 MaxPoolMicrokernelTester()
1074 .pooling_elements(9)
1075 .pooling_tile(9, 8)
1076 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07001077 .qmin(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001078 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001079 }
1080 }
1081
Marat Dukhan99936602020-04-11 16:47:01 -07001082 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_lt_16_unipass_fulltile_with_qmax) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001083 TEST_REQUIRES_X86_SSE2;
Marat Dukhan329da642019-11-19 21:44:39 -08001084 for (size_t channels = 1; channels < 16; channels++) {
1085 MaxPoolMicrokernelTester()
1086 .pooling_elements(9)
1087 .pooling_tile(9, 8)
1088 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07001089 .qmax(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001090 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001091 }
1092 }
1093
Marat Dukhan99936602020-04-11 16:47:01 -07001094 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_lt_16_unipass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -08001095 TEST_REQUIRES_X86_SSE2;
1096 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1097 for (size_t channels = 1; channels < 16; channels++) {
1098 MaxPoolMicrokernelTester()
1099 .pooling_elements(pooling_elements)
1100 .pooling_tile(9, 8)
1101 .channels(channels)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001102 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001103 }
1104 }
1105 }
1106
Marat Dukhan99936602020-04-11 16:47:01 -07001107 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_lt_16_unipass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08001108 TEST_REQUIRES_X86_SSE2;
1109 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1110 for (size_t channels = 1; channels < 16; channels++) {
1111 MaxPoolMicrokernelTester()
1112 .pooling_elements(pooling_elements)
1113 .pooling_tile(9, 8)
1114 .channels(channels)
1115 .input_offset(17)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001116 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001117 }
1118 }
1119 }
1120
Marat Dukhan99936602020-04-11 16:47:01 -07001121 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_gt_16_unipass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -08001122 TEST_REQUIRES_X86_SSE2;
1123 for (size_t channels = 17; channels < 32; channels++) {
1124 MaxPoolMicrokernelTester()
1125 .pooling_elements(9)
1126 .pooling_tile(9, 8)
1127 .channels(channels)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001128 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001129 }
1130 }
1131
Marat Dukhan99936602020-04-11 16:47:01 -07001132 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_gt_16_unipass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08001133 TEST_REQUIRES_X86_SSE2;
1134 for (size_t channels = 17; channels < 32; channels++) {
1135 MaxPoolMicrokernelTester()
1136 .pooling_elements(9)
1137 .pooling_tile(9, 8)
1138 .channels(channels)
1139 .input_offset(37)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001140 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001141 }
1142 }
1143
Marat Dukhan99936602020-04-11 16:47:01 -07001144 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_gt_16_unipass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08001145 TEST_REQUIRES_X86_SSE2;
1146 for (size_t channels = 17; channels < 32; channels++) {
1147 MaxPoolMicrokernelTester()
1148 .pooling_elements(9)
1149 .pooling_tile(9, 8)
1150 .channels(channels)
1151 .qmin(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001152 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001153 }
1154 }
1155
Marat Dukhan99936602020-04-11 16:47:01 -07001156 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_gt_16_unipass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08001157 TEST_REQUIRES_X86_SSE2;
1158 for (size_t channels = 17; channels < 32; channels++) {
1159 MaxPoolMicrokernelTester()
1160 .pooling_elements(9)
1161 .pooling_tile(9, 8)
1162 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07001163 .qmax(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001164 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001165 }
1166 }
1167
Marat Dukhan99936602020-04-11 16:47:01 -07001168 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_gt_16_unipass_subtile) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001169 TEST_REQUIRES_X86_SSE2;
Marat Dukhan329da642019-11-19 21:44:39 -08001170 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1171 for (size_t channels = 17; channels < 32; channels++) {
1172 MaxPoolMicrokernelTester()
1173 .pooling_elements(pooling_elements)
1174 .pooling_tile(9, 8)
1175 .channels(channels)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001176 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001177 }
1178 }
1179 }
1180
Marat Dukhan99936602020-04-11 16:47:01 -07001181 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_gt_16_unipass_subtile_with_input_offset) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001182 TEST_REQUIRES_X86_SSE2;
Marat Dukhan329da642019-11-19 21:44:39 -08001183 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1184 for (size_t channels = 17; channels < 32; channels++) {
1185 MaxPoolMicrokernelTester()
1186 .pooling_elements(pooling_elements)
1187 .pooling_tile(9, 8)
1188 .channels(channels)
1189 .input_offset(37)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001190 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001191 }
1192 }
1193 }
1194
Marat Dukhan99936602020-04-11 16:47:01 -07001195 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_eq_16_twopass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -08001196 TEST_REQUIRES_X86_SSE2;
1197 MaxPoolMicrokernelTester()
1198 .pooling_elements(17)
1199 .pooling_tile(9, 8)
1200 .channels(16)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001201 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001202 }
1203
Marat Dukhan99936602020-04-11 16:47:01 -07001204 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_eq_16_twopass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08001205 TEST_REQUIRES_X86_SSE2;
1206 MaxPoolMicrokernelTester()
1207 .pooling_elements(17)
1208 .pooling_tile(9, 8)
1209 .channels(16)
1210 .input_offset(19)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001211 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001212 }
1213
Marat Dukhan99936602020-04-11 16:47:01 -07001214 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_eq_16_twopass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08001215 TEST_REQUIRES_X86_SSE2;
1216 MaxPoolMicrokernelTester()
1217 .pooling_elements(17)
1218 .pooling_tile(9, 8)
1219 .channels(16)
1220 .qmin(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001221 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001222 }
1223
Marat Dukhan99936602020-04-11 16:47:01 -07001224 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_eq_16_twopass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08001225 TEST_REQUIRES_X86_SSE2;
1226 MaxPoolMicrokernelTester()
1227 .pooling_elements(17)
1228 .pooling_tile(9, 8)
1229 .channels(16)
1230 .qmax(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001231 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001232 }
1233
Marat Dukhan99936602020-04-11 16:47:01 -07001234 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_eq_16_twopass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -08001235 TEST_REQUIRES_X86_SSE2;
1236 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
1237 MaxPoolMicrokernelTester()
1238 .pooling_elements(pooling_elements)
1239 .pooling_tile(9, 8)
1240 .channels(16)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001241 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001242 }
1243 }
1244
Marat Dukhan99936602020-04-11 16:47:01 -07001245 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_eq_16_twopass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08001246 TEST_REQUIRES_X86_SSE2;
1247 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
1248 MaxPoolMicrokernelTester()
1249 .pooling_elements(pooling_elements)
1250 .pooling_tile(9, 8)
1251 .channels(16)
1252 .input_offset(19)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001253 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001254 }
1255 }
1256
Marat Dukhan99936602020-04-11 16:47:01 -07001257 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_div_16_twopass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -08001258 TEST_REQUIRES_X86_SSE2;
1259 for (size_t channels = 32; channels < 128; channels += 16) {
1260 MaxPoolMicrokernelTester()
1261 .pooling_elements(17)
1262 .pooling_tile(9, 8)
1263 .channels(channels)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001264 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001265 }
1266 }
1267
Marat Dukhan99936602020-04-11 16:47:01 -07001268 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_div_16_twopass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08001269 TEST_REQUIRES_X86_SSE2;
1270 for (size_t channels = 32; channels < 128; channels += 16) {
1271 MaxPoolMicrokernelTester()
1272 .pooling_elements(17)
1273 .pooling_tile(9, 8)
1274 .channels(channels)
1275 .input_offset(83)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001276 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001277 }
1278 }
1279
Marat Dukhan99936602020-04-11 16:47:01 -07001280 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_div_16_twopass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08001281 TEST_REQUIRES_X86_SSE2;
1282 for (size_t channels = 32; channels < 128; channels += 16) {
1283 MaxPoolMicrokernelTester()
1284 .pooling_elements(17)
1285 .pooling_tile(9, 8)
1286 .channels(channels)
1287 .qmin(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001288 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001289 }
1290 }
1291
Marat Dukhan99936602020-04-11 16:47:01 -07001292 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_div_16_twopass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08001293 TEST_REQUIRES_X86_SSE2;
1294 for (size_t channels = 32; channels < 128; channels += 16) {
1295 MaxPoolMicrokernelTester()
1296 .pooling_elements(17)
1297 .pooling_tile(9, 8)
1298 .channels(channels)
1299 .qmax(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001300 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001301 }
1302 }
1303
Marat Dukhan99936602020-04-11 16:47:01 -07001304 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_div_16_twopass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -08001305 TEST_REQUIRES_X86_SSE2;
1306 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
1307 for (size_t channels = 32; channels < 128; channels += 16) {
1308 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08001309 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08001310 .pooling_tile(9, 8)
1311 .channels(channels)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001312 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001313 }
1314 }
1315 }
1316
Marat Dukhan99936602020-04-11 16:47:01 -07001317 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_div_16_twopass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08001318 TEST_REQUIRES_X86_SSE2;
1319 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
1320 for (size_t channels = 32; channels < 128; channels += 16) {
1321 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08001322 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08001323 .pooling_tile(9, 8)
1324 .channels(channels)
1325 .input_offset(131)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001326 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001327 }
1328 }
1329 }
1330
Marat Dukhan99936602020-04-11 16:47:01 -07001331 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_lt_16_twopass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -08001332 TEST_REQUIRES_X86_SSE2;
1333 for (size_t channels = 1; channels < 16; channels++) {
1334 MaxPoolMicrokernelTester()
1335 .pooling_elements(17)
1336 .pooling_tile(9, 8)
1337 .channels(channels)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001338 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001339 }
1340 }
1341
Marat Dukhan99936602020-04-11 16:47:01 -07001342 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_lt_16_twopass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08001343 TEST_REQUIRES_X86_SSE2;
1344 for (size_t channels = 1; channels < 16; channels++) {
1345 MaxPoolMicrokernelTester()
1346 .pooling_elements(17)
1347 .pooling_tile(9, 8)
1348 .channels(channels)
1349 .input_offset(17)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001350 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001351 }
1352 }
1353
Marat Dukhan99936602020-04-11 16:47:01 -07001354 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_lt_16_twopass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08001355 TEST_REQUIRES_X86_SSE2;
1356 for (size_t channels = 1; channels < 16; channels++) {
1357 MaxPoolMicrokernelTester()
1358 .pooling_elements(17)
1359 .pooling_tile(9, 8)
1360 .channels(channels)
1361 .qmin(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001362 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001363 }
1364 }
1365
Marat Dukhan99936602020-04-11 16:47:01 -07001366 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_lt_16_twopass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08001367 TEST_REQUIRES_X86_SSE2;
1368 for (size_t channels = 1; channels < 16; channels++) {
1369 MaxPoolMicrokernelTester()
1370 .pooling_elements(17)
1371 .pooling_tile(9, 8)
1372 .channels(channels)
1373 .qmax(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001374 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001375 }
1376 }
1377
Marat Dukhan99936602020-04-11 16:47:01 -07001378 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_lt_16_twopass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -08001379 TEST_REQUIRES_X86_SSE2;
1380 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
1381 for (size_t channels = 1; channels < 16; channels++) {
1382 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08001383 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08001384 .pooling_tile(9, 8)
1385 .channels(channels)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001386 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001387 }
1388 }
1389 }
1390
Marat Dukhan99936602020-04-11 16:47:01 -07001391 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_lt_16_twopass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08001392 TEST_REQUIRES_X86_SSE2;
1393 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
1394 for (size_t channels = 1; channels < 16; channels++) {
1395 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08001396 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08001397 .pooling_tile(9, 8)
1398 .channels(channels)
1399 .input_offset(17)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001400 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001401 }
1402 }
1403 }
1404
Marat Dukhan99936602020-04-11 16:47:01 -07001405 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_gt_16_twopass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -08001406 TEST_REQUIRES_X86_SSE2;
1407 for (size_t channels = 17; channels < 32; channels++) {
1408 MaxPoolMicrokernelTester()
1409 .pooling_elements(17)
1410 .pooling_tile(9, 8)
1411 .channels(channels)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001412 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001413 }
1414 }
1415
Marat Dukhan99936602020-04-11 16:47:01 -07001416 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_gt_16_twopass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08001417 TEST_REQUIRES_X86_SSE2;
1418 for (size_t channels = 17; channels < 32; channels++) {
1419 MaxPoolMicrokernelTester()
1420 .pooling_elements(17)
1421 .pooling_tile(9, 8)
1422 .channels(channels)
1423 .input_offset(37)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001424 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001425 }
1426 }
1427
Marat Dukhan99936602020-04-11 16:47:01 -07001428 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_gt_16_twopass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08001429 TEST_REQUIRES_X86_SSE2;
1430 for (size_t channels = 17; channels < 32; channels++) {
1431 MaxPoolMicrokernelTester()
1432 .pooling_elements(17)
1433 .pooling_tile(9, 8)
1434 .channels(channels)
1435 .qmin(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001436 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001437 }
1438 }
1439
Marat Dukhan99936602020-04-11 16:47:01 -07001440 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_gt_16_twopass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08001441 TEST_REQUIRES_X86_SSE2;
1442 for (size_t channels = 17; channels < 32; channels++) {
1443 MaxPoolMicrokernelTester()
1444 .pooling_elements(17)
1445 .pooling_tile(9, 8)
1446 .channels(channels)
1447 .qmax(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001448 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001449 }
1450 }
1451
Marat Dukhan99936602020-04-11 16:47:01 -07001452 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_gt_16_twopass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -08001453 TEST_REQUIRES_X86_SSE2;
1454 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
1455 for (size_t channels = 17; channels < 32; channels++) {
1456 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08001457 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08001458 .pooling_tile(9, 8)
1459 .channels(channels)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001460 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001461 }
1462 }
1463 }
1464
Marat Dukhan99936602020-04-11 16:47:01 -07001465 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_gt_16_twopass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08001466 TEST_REQUIRES_X86_SSE2;
1467 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
1468 for (size_t channels = 17; channels < 32; channels++) {
1469 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08001470 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08001471 .pooling_tile(9, 8)
1472 .channels(channels)
1473 .input_offset(37)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001474 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001475 }
1476 }
1477 }
1478
Marat Dukhan99936602020-04-11 16:47:01 -07001479 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_eq_16_multipass) {
Marat Dukhan329da642019-11-19 21:44:39 -08001480 TEST_REQUIRES_X86_SSE2;
1481 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1482 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08001483 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08001484 .pooling_tile(9, 8)
1485 .channels(16)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001486 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001487 }
1488 }
1489
Marat Dukhan99936602020-04-11 16:47:01 -07001490 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_eq_16_multipass_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08001491 TEST_REQUIRES_X86_SSE2;
1492 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1493 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08001494 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08001495 .pooling_tile(9, 8)
1496 .channels(16)
1497 .input_offset(19)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001498 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001499 }
1500 }
1501
Marat Dukhan99936602020-04-11 16:47:01 -07001502 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_eq_16_multipass_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08001503 TEST_REQUIRES_X86_SSE2;
1504 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1505 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08001506 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08001507 .pooling_tile(9, 8)
1508 .channels(16)
1509 .qmin(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001510 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001511 }
1512 }
1513
Marat Dukhan99936602020-04-11 16:47:01 -07001514 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_eq_16_multipass_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08001515 TEST_REQUIRES_X86_SSE2;
1516 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1517 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08001518 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08001519 .pooling_tile(9, 8)
1520 .channels(16)
1521 .qmax(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001522 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001523 }
1524 }
1525
Marat Dukhan99936602020-04-11 16:47:01 -07001526 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_div_16_multipass) {
Marat Dukhan329da642019-11-19 21:44:39 -08001527 TEST_REQUIRES_X86_SSE2;
1528 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1529 for (size_t channels = 32; channels < 128; channels += 16) {
1530 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08001531 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08001532 .pooling_tile(9, 8)
1533 .channels(channels)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001534 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001535 }
1536 }
1537 }
1538
Marat Dukhan99936602020-04-11 16:47:01 -07001539 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_div_16_multipass_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08001540 TEST_REQUIRES_X86_SSE2;
1541 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1542 for (size_t channels = 32; channels < 128; channels += 16) {
1543 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08001544 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08001545 .pooling_tile(9, 8)
1546 .channels(channels)
1547 .input_offset(131)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001548 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001549 }
1550 }
1551 }
1552
Marat Dukhan99936602020-04-11 16:47:01 -07001553 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_div_16_multipass_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08001554 TEST_REQUIRES_X86_SSE2;
1555 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1556 for (size_t channels = 32; channels < 128; channels += 16) {
1557 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08001558 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08001559 .pooling_tile(9, 8)
1560 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07001561 .qmin(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001562 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001563 }
1564 }
1565 }
1566
Marat Dukhan99936602020-04-11 16:47:01 -07001567 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_div_16_multipass_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08001568 TEST_REQUIRES_X86_SSE2;
1569 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1570 for (size_t channels = 32; channels < 128; channels += 16) {
1571 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08001572 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08001573 .pooling_tile(9, 8)
1574 .channels(channels)
1575 .qmax(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001576 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001577 }
1578 }
1579 }
1580
Marat Dukhan99936602020-04-11 16:47:01 -07001581 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_lt_16_multipass) {
Marat Dukhan329da642019-11-19 21:44:39 -08001582 TEST_REQUIRES_X86_SSE2;
1583 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1584 for (size_t channels = 1; channels < 16; channels++) {
1585 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08001586 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08001587 .pooling_tile(9, 8)
1588 .channels(channels)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001589 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001590 }
1591 }
1592 }
1593
Marat Dukhan99936602020-04-11 16:47:01 -07001594 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_lt_16_multipass_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08001595 TEST_REQUIRES_X86_SSE2;
1596 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1597 for (size_t channels = 1; channels < 16; channels++) {
1598 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08001599 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08001600 .pooling_tile(9, 8)
1601 .channels(channels)
1602 .input_offset(16)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001603 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001604 }
1605 }
1606 }
1607
Marat Dukhan99936602020-04-11 16:47:01 -07001608 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_lt_16_multipass_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08001609 TEST_REQUIRES_X86_SSE2;
1610 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1611 for (size_t channels = 1; channels < 16; channels++) {
1612 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08001613 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08001614 .pooling_tile(9, 8)
1615 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07001616 .qmin(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001617 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001618 }
1619 }
1620 }
1621
Marat Dukhan99936602020-04-11 16:47:01 -07001622 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_lt_16_multipass_with_qmax) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001623 TEST_REQUIRES_X86_SSE2;
Marat Dukhan329da642019-11-19 21:44:39 -08001624 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1625 for (size_t channels = 1; channels < 16; channels++) {
1626 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08001627 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08001628 .pooling_tile(9, 8)
1629 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07001630 .qmax(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001631 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001632 }
1633 }
1634 }
1635
Marat Dukhan99936602020-04-11 16:47:01 -07001636 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_gt_16_multipass) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001637 TEST_REQUIRES_X86_SSE2;
Marat Dukhan329da642019-11-19 21:44:39 -08001638 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1639 for (size_t channels = 17; channels < 32; channels++) {
1640 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08001641 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08001642 .pooling_tile(9, 8)
1643 .channels(channels)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001644 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001645 }
1646 }
1647 }
1648
Marat Dukhan99936602020-04-11 16:47:01 -07001649 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_gt_16_multipass_with_input_offset) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001650 TEST_REQUIRES_X86_SSE2;
Marat Dukhan329da642019-11-19 21:44:39 -08001651 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1652 for (size_t channels = 17; channels < 32; channels++) {
1653 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08001654 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08001655 .pooling_tile(9, 8)
1656 .channels(channels)
1657 .input_offset(37)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001658 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001659 }
1660 }
1661 }
1662
Marat Dukhan99936602020-04-11 16:47:01 -07001663 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_gt_16_multipass_with_qmin) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001664 TEST_REQUIRES_X86_SSE2;
Marat Dukhan329da642019-11-19 21:44:39 -08001665 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1666 for (size_t channels = 17; channels < 32; channels++) {
1667 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08001668 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08001669 .pooling_tile(9, 8)
1670 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07001671 .qmin(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001672 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001673 }
1674 }
1675 }
1676
Marat Dukhan99936602020-04-11 16:47:01 -07001677 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, channels_gt_16_multipass_with_qmax) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001678 TEST_REQUIRES_X86_SSE2;
Marat Dukhan329da642019-11-19 21:44:39 -08001679 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
1680 for (size_t channels = 17; channels < 32; channels++) {
1681 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08001682 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08001683 .pooling_tile(9, 8)
1684 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07001685 .qmax(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001686 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001687 }
1688 }
1689 }
1690
Marat Dukhan99936602020-04-11 16:47:01 -07001691 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, few_output_pixels) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001692 TEST_REQUIRES_X86_SSE2;
Marat Dukhan329da642019-11-19 21:44:39 -08001693 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
1694 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
1695 for (size_t channels = 1; channels <= 80; channels += 15) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001696 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -08001697 .output_pixels(output_pixels)
1698 .pooling_elements(pooling_elements)
1699 .pooling_tile(9, 8)
1700 .channels(channels)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001701 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001702 }
1703 }
1704 }
1705 }
1706
Marat Dukhan99936602020-04-11 16:47:01 -07001707 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, few_output_pixels_with_input_offset) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001708 TEST_REQUIRES_X86_SSE2;
Marat Dukhan329da642019-11-19 21:44:39 -08001709 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
1710 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
1711 for (size_t channels = 1; channels <= 80; channels += 15) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001712 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -08001713 .output_pixels(output_pixels)
1714 .pooling_elements(pooling_elements)
1715 .pooling_tile(9, 8)
1716 .channels(channels)
1717 .input_offset(83)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001718 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001719 }
1720 }
1721 }
1722 }
1723
Marat Dukhan99936602020-04-11 16:47:01 -07001724 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, few_output_pixels_with_qmin) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001725 TEST_REQUIRES_X86_SSE2;
Marat Dukhan329da642019-11-19 21:44:39 -08001726 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
1727 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
1728 for (size_t channels = 1; channels <= 80; channels += 15) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001729 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -08001730 .output_pixels(output_pixels)
1731 .pooling_elements(pooling_elements)
1732 .pooling_tile(9, 8)
1733 .channels(channels)
1734 .qmin(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001735 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001736 }
1737 }
1738 }
1739 }
1740
Marat Dukhan99936602020-04-11 16:47:01 -07001741 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, few_output_pixels_with_qmax) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001742 TEST_REQUIRES_X86_SSE2;
Marat Dukhan329da642019-11-19 21:44:39 -08001743 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
1744 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
1745 for (size_t channels = 1; channels <= 80; channels += 15) {
1746 MaxPoolMicrokernelTester()
1747 .output_pixels(output_pixels)
1748 .pooling_elements(pooling_elements)
1749 .pooling_tile(9, 8)
1750 .channels(channels)
1751 .qmax(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001752 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001753 }
1754 }
1755 }
1756 }
1757
Marat Dukhan99936602020-04-11 16:47:01 -07001758 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, few_output_pixels_with_output_stride) {
Marat Dukhan329da642019-11-19 21:44:39 -08001759 TEST_REQUIRES_X86_SSE2;
1760 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
1761 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
1762 for (size_t channels = 1; channels <= 80; channels += 15) {
1763 MaxPoolMicrokernelTester()
1764 .output_pixels(output_pixels)
1765 .pooling_elements(pooling_elements)
1766 .pooling_tile(9, 8)
1767 .channels(channels)
1768 .output_stride(83)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001769 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
Marat Dukhan329da642019-11-19 21:44:39 -08001770 }
1771 }
1772 }
1773 }
1774
Marat Dukhan99936602020-04-11 16:47:01 -07001775 TEST(U8_MAXPOOL_MINMAX_9P8X__SSE2_C16, few_output_pixels_with_step) {
Marat Dukhan329da642019-11-19 21:44:39 -08001776 TEST_REQUIRES_X86_SSE2;
1777 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
1778 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
1779 for (size_t channels = 1; channels <= 80; channels += 15) {
1780 for (size_t step = 2; step <= pooling_elements; step++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001781 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -08001782 .output_pixels(output_pixels)
1783 .pooling_elements(pooling_elements)
1784 .pooling_tile(9, 8)
1785 .step(step)
1786 .channels(channels)
1787 .output_stride(83)
Marat Dukhan91ae1652021-08-15 19:19:49 -07001788 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__sse2_c16, xnn_init_u8_minmax_sse2_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001789 }
1790 }
1791 }
1792 }
1793 }
Marat Dukhan1dadbf72019-10-01 10:46:20 -07001794#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
XNNPACK Teamb455b122019-09-27 18:10:33 -07001795
Marat Dukhan329da642019-11-19 21:44:39 -08001796
Marat Dukhan4c617792021-12-21 15:47:58 -08001797#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhanf1589422021-08-15 20:37:06 -07001798 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_eq_16_unipass_fulltile) {
1799 MaxPoolMicrokernelTester()
1800 .pooling_elements(9)
1801 .pooling_tile(9, 8)
1802 .channels(16)
1803 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
1804 }
1805
1806 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_eq_16_unipass_fulltile_with_input_offset) {
1807 MaxPoolMicrokernelTester()
1808 .pooling_elements(9)
1809 .pooling_tile(9, 8)
1810 .channels(16)
1811 .input_offset(19)
1812 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
1813 }
1814
1815 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_eq_16_unipass_fulltile_with_qmin) {
1816 MaxPoolMicrokernelTester()
1817 .pooling_elements(9)
1818 .pooling_tile(9, 8)
1819 .channels(16)
1820 .qmin(192)
1821 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
1822 }
1823
1824 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_eq_16_unipass_fulltile_with_qmax) {
1825 MaxPoolMicrokernelTester()
1826 .pooling_elements(9)
1827 .pooling_tile(9, 8)
1828 .channels(16)
1829 .qmax(192)
1830 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
1831 }
1832
1833 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_eq_16_unipass_subtile) {
1834 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1835 MaxPoolMicrokernelTester()
1836 .pooling_elements(pooling_elements)
1837 .pooling_tile(9, 8)
1838 .channels(16)
1839 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
1840 }
1841 }
1842
1843 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_eq_16_unipass_subtile_with_input_offset) {
1844 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1845 MaxPoolMicrokernelTester()
1846 .pooling_elements(pooling_elements)
1847 .pooling_tile(9, 8)
1848 .channels(16)
1849 .input_offset(19)
1850 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
1851 }
1852 }
1853
1854 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_div_16_unipass_fulltile) {
1855 for (size_t channels = 32; channels < 128; channels += 16) {
1856 MaxPoolMicrokernelTester()
1857 .pooling_elements(9)
1858 .pooling_tile(9, 8)
1859 .channels(channels)
1860 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
1861 }
1862 }
1863
1864 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_div_16_unipass_fulltile_with_input_offset) {
1865 for (size_t channels = 32; channels < 128; channels += 16) {
1866 MaxPoolMicrokernelTester()
1867 .pooling_elements(9)
1868 .pooling_tile(9, 8)
1869 .channels(channels)
1870 .input_offset(131)
1871 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
1872 }
1873 }
1874
1875 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_div_16_unipass_fulltile_with_qmin) {
1876 for (size_t channels = 32; channels < 128; channels += 16) {
1877 MaxPoolMicrokernelTester()
1878 .pooling_elements(9)
1879 .pooling_tile(9, 8)
1880 .channels(channels)
1881 .qmin(192)
1882 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
1883 }
1884 }
1885
1886 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_div_16_unipass_fulltile_with_qmax) {
1887 for (size_t channels = 32; channels < 128; channels += 16) {
1888 MaxPoolMicrokernelTester()
1889 .pooling_elements(9)
1890 .pooling_tile(9, 8)
1891 .channels(channels)
1892 .qmax(192)
1893 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
1894 }
1895 }
1896
1897 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_div_16_unipass_subtile) {
1898 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1899 for (size_t channels = 32; channels < 128; channels += 16) {
1900 MaxPoolMicrokernelTester()
1901 .pooling_elements(pooling_elements)
1902 .pooling_tile(9, 8)
1903 .channels(channels)
1904 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
1905 }
1906 }
1907 }
1908
1909 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_div_16_unipass_subtile_with_input_offset) {
1910 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1911 for (size_t channels = 32; channels < 128; channels += 16) {
1912 MaxPoolMicrokernelTester()
1913 .pooling_elements(pooling_elements)
1914 .pooling_tile(9, 8)
1915 .channels(channels)
1916 .input_offset(131)
1917 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
1918 }
1919 }
1920 }
1921
1922 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_lt_16_unipass_fulltile) {
1923 for (size_t channels = 1; channels < 16; channels++) {
1924 MaxPoolMicrokernelTester()
1925 .pooling_elements(9)
1926 .pooling_tile(9, 8)
1927 .channels(channels)
1928 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
1929 }
1930 }
1931
1932 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_lt_16_unipass_fulltile_with_input_offset) {
1933 for (size_t channels = 1; channels < 16; channels++) {
1934 MaxPoolMicrokernelTester()
1935 .pooling_elements(9)
1936 .pooling_tile(9, 8)
1937 .channels(channels)
1938 .input_offset(17)
1939 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
1940 }
1941 }
1942
1943 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_lt_16_unipass_fulltile_with_qmin) {
1944 for (size_t channels = 1; channels < 16; channels++) {
1945 MaxPoolMicrokernelTester()
1946 .pooling_elements(9)
1947 .pooling_tile(9, 8)
1948 .channels(channels)
1949 .qmin(192)
1950 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
1951 }
1952 }
1953
1954 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_lt_16_unipass_fulltile_with_qmax) {
1955 for (size_t channels = 1; channels < 16; channels++) {
1956 MaxPoolMicrokernelTester()
1957 .pooling_elements(9)
1958 .pooling_tile(9, 8)
1959 .channels(channels)
1960 .qmax(192)
1961 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
1962 }
1963 }
1964
1965 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_lt_16_unipass_subtile) {
1966 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1967 for (size_t channels = 1; channels < 16; channels++) {
1968 MaxPoolMicrokernelTester()
1969 .pooling_elements(pooling_elements)
1970 .pooling_tile(9, 8)
1971 .channels(channels)
1972 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
1973 }
1974 }
1975 }
1976
1977 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_lt_16_unipass_subtile_with_input_offset) {
1978 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
1979 for (size_t channels = 1; channels < 16; channels++) {
1980 MaxPoolMicrokernelTester()
1981 .pooling_elements(pooling_elements)
1982 .pooling_tile(9, 8)
1983 .channels(channels)
1984 .input_offset(17)
1985 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
1986 }
1987 }
1988 }
1989
1990 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_gt_16_unipass_fulltile) {
1991 for (size_t channels = 17; channels < 32; channels++) {
1992 MaxPoolMicrokernelTester()
1993 .pooling_elements(9)
1994 .pooling_tile(9, 8)
1995 .channels(channels)
1996 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
1997 }
1998 }
1999
2000 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_gt_16_unipass_fulltile_with_input_offset) {
2001 for (size_t channels = 17; channels < 32; channels++) {
2002 MaxPoolMicrokernelTester()
2003 .pooling_elements(9)
2004 .pooling_tile(9, 8)
2005 .channels(channels)
2006 .input_offset(37)
2007 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2008 }
2009 }
2010
2011 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_gt_16_unipass_fulltile_with_qmin) {
2012 for (size_t channels = 17; channels < 32; channels++) {
2013 MaxPoolMicrokernelTester()
2014 .pooling_elements(9)
2015 .pooling_tile(9, 8)
2016 .channels(channels)
2017 .qmin(192)
2018 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2019 }
2020 }
2021
2022 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_gt_16_unipass_fulltile_with_qmax) {
2023 for (size_t channels = 17; channels < 32; channels++) {
2024 MaxPoolMicrokernelTester()
2025 .pooling_elements(9)
2026 .pooling_tile(9, 8)
2027 .channels(channels)
2028 .qmax(192)
2029 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2030 }
2031 }
2032
2033 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_gt_16_unipass_subtile) {
2034 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
2035 for (size_t channels = 17; channels < 32; channels++) {
2036 MaxPoolMicrokernelTester()
2037 .pooling_elements(pooling_elements)
2038 .pooling_tile(9, 8)
2039 .channels(channels)
2040 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2041 }
2042 }
2043 }
2044
2045 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_gt_16_unipass_subtile_with_input_offset) {
2046 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
2047 for (size_t channels = 17; channels < 32; channels++) {
2048 MaxPoolMicrokernelTester()
2049 .pooling_elements(pooling_elements)
2050 .pooling_tile(9, 8)
2051 .channels(channels)
2052 .input_offset(37)
2053 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2054 }
2055 }
2056 }
2057
2058 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_eq_16_twopass_fulltile) {
2059 MaxPoolMicrokernelTester()
2060 .pooling_elements(17)
2061 .pooling_tile(9, 8)
2062 .channels(16)
2063 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2064 }
2065
2066 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_eq_16_twopass_fulltile_with_input_offset) {
2067 MaxPoolMicrokernelTester()
2068 .pooling_elements(17)
2069 .pooling_tile(9, 8)
2070 .channels(16)
2071 .input_offset(19)
2072 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2073 }
2074
2075 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_eq_16_twopass_fulltile_with_qmin) {
2076 MaxPoolMicrokernelTester()
2077 .pooling_elements(17)
2078 .pooling_tile(9, 8)
2079 .channels(16)
2080 .qmin(192)
2081 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2082 }
2083
2084 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_eq_16_twopass_fulltile_with_qmax) {
2085 MaxPoolMicrokernelTester()
2086 .pooling_elements(17)
2087 .pooling_tile(9, 8)
2088 .channels(16)
2089 .qmax(192)
2090 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2091 }
2092
2093 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_eq_16_twopass_subtile) {
2094 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
2095 MaxPoolMicrokernelTester()
2096 .pooling_elements(pooling_elements)
2097 .pooling_tile(9, 8)
2098 .channels(16)
2099 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2100 }
2101 }
2102
2103 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_eq_16_twopass_subtile_with_input_offset) {
2104 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
2105 MaxPoolMicrokernelTester()
2106 .pooling_elements(pooling_elements)
2107 .pooling_tile(9, 8)
2108 .channels(16)
2109 .input_offset(19)
2110 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2111 }
2112 }
2113
2114 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_div_16_twopass_fulltile) {
2115 for (size_t channels = 32; channels < 128; channels += 16) {
2116 MaxPoolMicrokernelTester()
2117 .pooling_elements(17)
2118 .pooling_tile(9, 8)
2119 .channels(channels)
2120 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2121 }
2122 }
2123
2124 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_div_16_twopass_fulltile_with_input_offset) {
2125 for (size_t channels = 32; channels < 128; channels += 16) {
2126 MaxPoolMicrokernelTester()
2127 .pooling_elements(17)
2128 .pooling_tile(9, 8)
2129 .channels(channels)
2130 .input_offset(83)
2131 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2132 }
2133 }
2134
2135 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_div_16_twopass_fulltile_with_qmin) {
2136 for (size_t channels = 32; channels < 128; channels += 16) {
2137 MaxPoolMicrokernelTester()
2138 .pooling_elements(17)
2139 .pooling_tile(9, 8)
2140 .channels(channels)
2141 .qmin(192)
2142 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2143 }
2144 }
2145
2146 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_div_16_twopass_fulltile_with_qmax) {
2147 for (size_t channels = 32; channels < 128; channels += 16) {
2148 MaxPoolMicrokernelTester()
2149 .pooling_elements(17)
2150 .pooling_tile(9, 8)
2151 .channels(channels)
2152 .qmax(192)
2153 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2154 }
2155 }
2156
2157 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_div_16_twopass_subtile) {
2158 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
2159 for (size_t channels = 32; channels < 128; channels += 16) {
2160 MaxPoolMicrokernelTester()
2161 .pooling_elements(pooling_elements)
2162 .pooling_tile(9, 8)
2163 .channels(channels)
2164 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2165 }
2166 }
2167 }
2168
2169 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_div_16_twopass_subtile_with_input_offset) {
2170 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
2171 for (size_t channels = 32; channels < 128; channels += 16) {
2172 MaxPoolMicrokernelTester()
2173 .pooling_elements(pooling_elements)
2174 .pooling_tile(9, 8)
2175 .channels(channels)
2176 .input_offset(131)
2177 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2178 }
2179 }
2180 }
2181
2182 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_lt_16_twopass_fulltile) {
2183 for (size_t channels = 1; channels < 16; channels++) {
2184 MaxPoolMicrokernelTester()
2185 .pooling_elements(17)
2186 .pooling_tile(9, 8)
2187 .channels(channels)
2188 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2189 }
2190 }
2191
2192 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_lt_16_twopass_fulltile_with_input_offset) {
2193 for (size_t channels = 1; channels < 16; channels++) {
2194 MaxPoolMicrokernelTester()
2195 .pooling_elements(17)
2196 .pooling_tile(9, 8)
2197 .channels(channels)
2198 .input_offset(17)
2199 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2200 }
2201 }
2202
2203 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_lt_16_twopass_fulltile_with_qmin) {
2204 for (size_t channels = 1; channels < 16; channels++) {
2205 MaxPoolMicrokernelTester()
2206 .pooling_elements(17)
2207 .pooling_tile(9, 8)
2208 .channels(channels)
2209 .qmin(192)
2210 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2211 }
2212 }
2213
2214 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_lt_16_twopass_fulltile_with_qmax) {
2215 for (size_t channels = 1; channels < 16; channels++) {
2216 MaxPoolMicrokernelTester()
2217 .pooling_elements(17)
2218 .pooling_tile(9, 8)
2219 .channels(channels)
2220 .qmax(192)
2221 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2222 }
2223 }
2224
2225 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_lt_16_twopass_subtile) {
2226 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
2227 for (size_t channels = 1; channels < 16; channels++) {
2228 MaxPoolMicrokernelTester()
2229 .pooling_elements(pooling_elements)
2230 .pooling_tile(9, 8)
2231 .channels(channels)
2232 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2233 }
2234 }
2235 }
2236
2237 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_lt_16_twopass_subtile_with_input_offset) {
2238 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
2239 for (size_t channels = 1; channels < 16; channels++) {
2240 MaxPoolMicrokernelTester()
2241 .pooling_elements(pooling_elements)
2242 .pooling_tile(9, 8)
2243 .channels(channels)
2244 .input_offset(17)
2245 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2246 }
2247 }
2248 }
2249
2250 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_gt_16_twopass_fulltile) {
2251 for (size_t channels = 17; channels < 32; channels++) {
2252 MaxPoolMicrokernelTester()
2253 .pooling_elements(17)
2254 .pooling_tile(9, 8)
2255 .channels(channels)
2256 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2257 }
2258 }
2259
2260 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_gt_16_twopass_fulltile_with_input_offset) {
2261 for (size_t channels = 17; channels < 32; channels++) {
2262 MaxPoolMicrokernelTester()
2263 .pooling_elements(17)
2264 .pooling_tile(9, 8)
2265 .channels(channels)
2266 .input_offset(37)
2267 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2268 }
2269 }
2270
2271 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_gt_16_twopass_fulltile_with_qmin) {
2272 for (size_t channels = 17; channels < 32; channels++) {
2273 MaxPoolMicrokernelTester()
2274 .pooling_elements(17)
2275 .pooling_tile(9, 8)
2276 .channels(channels)
2277 .qmin(192)
2278 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2279 }
2280 }
2281
2282 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_gt_16_twopass_fulltile_with_qmax) {
2283 for (size_t channels = 17; channels < 32; channels++) {
2284 MaxPoolMicrokernelTester()
2285 .pooling_elements(17)
2286 .pooling_tile(9, 8)
2287 .channels(channels)
2288 .qmax(192)
2289 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2290 }
2291 }
2292
2293 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_gt_16_twopass_subtile) {
2294 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
2295 for (size_t channels = 17; channels < 32; channels++) {
2296 MaxPoolMicrokernelTester()
2297 .pooling_elements(pooling_elements)
2298 .pooling_tile(9, 8)
2299 .channels(channels)
2300 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2301 }
2302 }
2303 }
2304
2305 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_gt_16_twopass_subtile_with_input_offset) {
2306 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
2307 for (size_t channels = 17; channels < 32; channels++) {
2308 MaxPoolMicrokernelTester()
2309 .pooling_elements(pooling_elements)
2310 .pooling_tile(9, 8)
2311 .channels(channels)
2312 .input_offset(37)
2313 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2314 }
2315 }
2316 }
2317
2318 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_eq_16_multipass) {
2319 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2320 MaxPoolMicrokernelTester()
2321 .pooling_elements(pooling_elements)
2322 .pooling_tile(9, 8)
2323 .channels(16)
2324 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2325 }
2326 }
2327
2328 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_eq_16_multipass_with_input_offset) {
2329 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2330 MaxPoolMicrokernelTester()
2331 .pooling_elements(pooling_elements)
2332 .pooling_tile(9, 8)
2333 .channels(16)
2334 .input_offset(19)
2335 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2336 }
2337 }
2338
2339 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_eq_16_multipass_with_qmin) {
2340 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2341 MaxPoolMicrokernelTester()
2342 .pooling_elements(pooling_elements)
2343 .pooling_tile(9, 8)
2344 .channels(16)
2345 .qmin(192)
2346 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2347 }
2348 }
2349
2350 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_eq_16_multipass_with_qmax) {
2351 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2352 MaxPoolMicrokernelTester()
2353 .pooling_elements(pooling_elements)
2354 .pooling_tile(9, 8)
2355 .channels(16)
2356 .qmax(192)
2357 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2358 }
2359 }
2360
2361 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_div_16_multipass) {
2362 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2363 for (size_t channels = 32; channels < 128; channels += 16) {
2364 MaxPoolMicrokernelTester()
2365 .pooling_elements(pooling_elements)
2366 .pooling_tile(9, 8)
2367 .channels(channels)
2368 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2369 }
2370 }
2371 }
2372
2373 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_div_16_multipass_with_input_offset) {
2374 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2375 for (size_t channels = 32; channels < 128; channels += 16) {
2376 MaxPoolMicrokernelTester()
2377 .pooling_elements(pooling_elements)
2378 .pooling_tile(9, 8)
2379 .channels(channels)
2380 .input_offset(131)
2381 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2382 }
2383 }
2384 }
2385
2386 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_div_16_multipass_with_qmin) {
2387 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2388 for (size_t channels = 32; channels < 128; channels += 16) {
2389 MaxPoolMicrokernelTester()
2390 .pooling_elements(pooling_elements)
2391 .pooling_tile(9, 8)
2392 .channels(channels)
2393 .qmin(192)
2394 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2395 }
2396 }
2397 }
2398
2399 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_div_16_multipass_with_qmax) {
2400 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2401 for (size_t channels = 32; channels < 128; channels += 16) {
2402 MaxPoolMicrokernelTester()
2403 .pooling_elements(pooling_elements)
2404 .pooling_tile(9, 8)
2405 .channels(channels)
2406 .qmax(192)
2407 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2408 }
2409 }
2410 }
2411
2412 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_lt_16_multipass) {
2413 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2414 for (size_t channels = 1; channels < 16; channels++) {
2415 MaxPoolMicrokernelTester()
2416 .pooling_elements(pooling_elements)
2417 .pooling_tile(9, 8)
2418 .channels(channels)
2419 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2420 }
2421 }
2422 }
2423
2424 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_lt_16_multipass_with_input_offset) {
2425 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2426 for (size_t channels = 1; channels < 16; channels++) {
2427 MaxPoolMicrokernelTester()
2428 .pooling_elements(pooling_elements)
2429 .pooling_tile(9, 8)
2430 .channels(channels)
2431 .input_offset(16)
2432 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2433 }
2434 }
2435 }
2436
2437 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_lt_16_multipass_with_qmin) {
2438 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2439 for (size_t channels = 1; channels < 16; channels++) {
2440 MaxPoolMicrokernelTester()
2441 .pooling_elements(pooling_elements)
2442 .pooling_tile(9, 8)
2443 .channels(channels)
2444 .qmin(192)
2445 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2446 }
2447 }
2448 }
2449
2450 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_lt_16_multipass_with_qmax) {
2451 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2452 for (size_t channels = 1; channels < 16; channels++) {
2453 MaxPoolMicrokernelTester()
2454 .pooling_elements(pooling_elements)
2455 .pooling_tile(9, 8)
2456 .channels(channels)
2457 .qmax(192)
2458 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2459 }
2460 }
2461 }
2462
2463 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_gt_16_multipass) {
2464 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2465 for (size_t channels = 17; channels < 32; channels++) {
2466 MaxPoolMicrokernelTester()
2467 .pooling_elements(pooling_elements)
2468 .pooling_tile(9, 8)
2469 .channels(channels)
2470 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2471 }
2472 }
2473 }
2474
2475 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_gt_16_multipass_with_input_offset) {
2476 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2477 for (size_t channels = 17; channels < 32; channels++) {
2478 MaxPoolMicrokernelTester()
2479 .pooling_elements(pooling_elements)
2480 .pooling_tile(9, 8)
2481 .channels(channels)
2482 .input_offset(37)
2483 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2484 }
2485 }
2486 }
2487
2488 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_gt_16_multipass_with_qmin) {
2489 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2490 for (size_t channels = 17; channels < 32; channels++) {
2491 MaxPoolMicrokernelTester()
2492 .pooling_elements(pooling_elements)
2493 .pooling_tile(9, 8)
2494 .channels(channels)
2495 .qmin(192)
2496 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2497 }
2498 }
2499 }
2500
2501 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_gt_16_multipass_with_qmax) {
2502 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2503 for (size_t channels = 17; channels < 32; channels++) {
2504 MaxPoolMicrokernelTester()
2505 .pooling_elements(pooling_elements)
2506 .pooling_tile(9, 8)
2507 .channels(channels)
2508 .qmax(192)
2509 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2510 }
2511 }
2512 }
2513
2514 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, few_output_pixels) {
2515 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
2516 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
2517 for (size_t channels = 1; channels <= 80; channels += 15) {
2518 MaxPoolMicrokernelTester()
2519 .output_pixels(output_pixels)
2520 .pooling_elements(pooling_elements)
2521 .pooling_tile(9, 8)
2522 .channels(channels)
2523 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2524 }
2525 }
2526 }
2527 }
2528
2529 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, few_output_pixels_with_input_offset) {
2530 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
2531 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
2532 for (size_t channels = 1; channels <= 80; channels += 15) {
2533 MaxPoolMicrokernelTester()
2534 .output_pixels(output_pixels)
2535 .pooling_elements(pooling_elements)
2536 .pooling_tile(9, 8)
2537 .channels(channels)
2538 .input_offset(83)
2539 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2540 }
2541 }
2542 }
2543 }
2544
2545 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, few_output_pixels_with_qmin) {
2546 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
2547 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
2548 for (size_t channels = 1; channels <= 80; channels += 15) {
2549 MaxPoolMicrokernelTester()
2550 .output_pixels(output_pixels)
2551 .pooling_elements(pooling_elements)
2552 .pooling_tile(9, 8)
2553 .channels(channels)
2554 .qmin(192)
2555 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2556 }
2557 }
2558 }
2559 }
2560
2561 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, few_output_pixels_with_qmax) {
2562 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
2563 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
2564 for (size_t channels = 1; channels <= 80; channels += 15) {
2565 MaxPoolMicrokernelTester()
2566 .output_pixels(output_pixels)
2567 .pooling_elements(pooling_elements)
2568 .pooling_tile(9, 8)
2569 .channels(channels)
2570 .qmax(192)
2571 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2572 }
2573 }
2574 }
2575 }
2576
2577 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, few_output_pixels_with_output_stride) {
2578 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
2579 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
2580 for (size_t channels = 1; channels <= 80; channels += 15) {
2581 MaxPoolMicrokernelTester()
2582 .output_pixels(output_pixels)
2583 .pooling_elements(pooling_elements)
2584 .pooling_tile(9, 8)
2585 .channels(channels)
2586 .output_stride(83)
2587 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2588 }
2589 }
2590 }
2591 }
2592
2593 TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, few_output_pixels_with_step) {
2594 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
2595 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
2596 for (size_t channels = 1; channels <= 80; channels += 15) {
2597 for (size_t step = 2; step <= pooling_elements; step++) {
2598 MaxPoolMicrokernelTester()
2599 .output_pixels(output_pixels)
2600 .pooling_elements(pooling_elements)
2601 .pooling_tile(9, 8)
2602 .step(step)
2603 .channels(channels)
2604 .output_stride(83)
2605 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__wasmsimd_c16, xnn_init_u8_minmax_wasmsimd_params);
2606 }
2607 }
2608 }
2609 }
2610 }
Marat Dukhan4c617792021-12-21 15:47:58 -08002611#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhanf1589422021-08-15 20:37:06 -07002612
2613
Marat Dukhan99936602020-04-11 16:47:01 -07002614TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_unipass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -08002615 MaxPoolMicrokernelTester()
2616 .pooling_elements(9)
2617 .pooling_tile(9, 8)
2618 .channels(1)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002619 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08002620}
2621
Marat Dukhan99936602020-04-11 16:47:01 -07002622TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_unipass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08002623 MaxPoolMicrokernelTester()
2624 .pooling_elements(9)
2625 .pooling_tile(9, 8)
2626 .channels(1)
2627 .input_offset(3)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002628 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08002629}
2630
Marat Dukhan99936602020-04-11 16:47:01 -07002631TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_unipass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08002632 MaxPoolMicrokernelTester()
2633 .pooling_elements(9)
2634 .pooling_tile(9, 8)
2635 .channels(1)
2636 .qmin(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002637 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08002638}
2639
Marat Dukhan99936602020-04-11 16:47:01 -07002640TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_unipass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08002641 MaxPoolMicrokernelTester()
2642 .pooling_elements(9)
2643 .pooling_tile(9, 8)
2644 .channels(1)
2645 .qmax(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002646 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08002647}
2648
Marat Dukhan99936602020-04-11 16:47:01 -07002649TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_unipass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -08002650 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
2651 MaxPoolMicrokernelTester()
2652 .pooling_elements(pooling_elements)
2653 .pooling_tile(9, 8)
2654 .channels(1)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002655 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002656 }
2657}
2658
Marat Dukhan99936602020-04-11 16:47:01 -07002659TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_unipass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08002660 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
2661 MaxPoolMicrokernelTester()
2662 .pooling_elements(pooling_elements)
2663 .pooling_tile(9, 8)
2664 .channels(1)
2665 .input_offset(3)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002666 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002667 }
2668}
2669
Marat Dukhan99936602020-04-11 16:47:01 -07002670TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_unipass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -08002671 for (size_t channels = 2; channels < 10; channels++) {
2672 MaxPoolMicrokernelTester()
2673 .pooling_elements(9)
2674 .pooling_tile(9, 8)
2675 .channels(channels)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002676 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002677 }
2678}
2679
Marat Dukhan99936602020-04-11 16:47:01 -07002680TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_unipass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08002681 for (size_t channels = 2; channels < 10; channels++) {
2682 MaxPoolMicrokernelTester()
2683 .pooling_elements(9)
2684 .pooling_tile(9, 8)
2685 .channels(channels)
2686 .input_offset(3)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002687 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002688 }
2689}
2690
Marat Dukhan99936602020-04-11 16:47:01 -07002691TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_unipass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08002692 for (size_t channels = 2; channels < 10; channels++) {
2693 MaxPoolMicrokernelTester()
2694 .pooling_elements(9)
2695 .pooling_tile(9, 8)
2696 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07002697 .qmin(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002698 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08002699 }
2700}
2701
Marat Dukhan99936602020-04-11 16:47:01 -07002702TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_unipass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08002703 for (size_t channels = 2; channels < 10; channels++) {
2704 MaxPoolMicrokernelTester()
2705 .pooling_elements(9)
2706 .pooling_tile(9, 8)
2707 .channels(channels)
2708 .qmax(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002709 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08002710 }
2711}
2712
Marat Dukhan99936602020-04-11 16:47:01 -07002713TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_unipass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -08002714 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
2715 for (size_t channels = 2; channels < 10; channels++) {
2716 MaxPoolMicrokernelTester()
2717 .pooling_elements(pooling_elements)
2718 .pooling_tile(9, 8)
2719 .channels(channels)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002720 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08002721 }
2722 }
2723}
2724
Marat Dukhan99936602020-04-11 16:47:01 -07002725TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_unipass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08002726 for (size_t pooling_elements = 2; pooling_elements < 9; pooling_elements++) {
2727 for (size_t channels = 2; channels < 10; channels++) {
2728 MaxPoolMicrokernelTester()
2729 .pooling_elements(pooling_elements)
2730 .pooling_tile(9, 8)
2731 .channels(channels)
2732 .input_offset(3)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002733 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08002734 }
2735 }
2736}
2737
Marat Dukhan99936602020-04-11 16:47:01 -07002738TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_twopass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -08002739 MaxPoolMicrokernelTester()
2740 .pooling_elements(17)
2741 .pooling_tile(9, 8)
2742 .channels(1)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002743 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08002744}
2745
Marat Dukhan99936602020-04-11 16:47:01 -07002746TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_twopass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08002747 MaxPoolMicrokernelTester()
2748 .pooling_elements(17)
2749 .pooling_tile(9, 8)
2750 .channels(1)
2751 .input_offset(3)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002752 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08002753}
2754
Marat Dukhan99936602020-04-11 16:47:01 -07002755TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_twopass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08002756 MaxPoolMicrokernelTester()
2757 .pooling_elements(17)
2758 .pooling_tile(9, 8)
2759 .channels(1)
2760 .qmin(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002761 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08002762}
2763
Marat Dukhan99936602020-04-11 16:47:01 -07002764TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_twopass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08002765 MaxPoolMicrokernelTester()
2766 .pooling_elements(17)
2767 .pooling_tile(9, 8)
2768 .channels(1)
2769 .qmax(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002770 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08002771}
2772
Marat Dukhan99936602020-04-11 16:47:01 -07002773TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_twopass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -08002774 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
2775 MaxPoolMicrokernelTester()
2776 .pooling_elements(pooling_elements)
2777 .pooling_tile(9, 8)
2778 .channels(1)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002779 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08002780 }
2781}
2782
Marat Dukhan99936602020-04-11 16:47:01 -07002783TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_twopass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08002784 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
2785 MaxPoolMicrokernelTester()
2786 .pooling_elements(pooling_elements)
2787 .pooling_tile(9, 8)
2788 .channels(1)
2789 .input_offset(3)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002790 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08002791 }
2792}
2793
Marat Dukhan99936602020-04-11 16:47:01 -07002794TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_twopass_fulltile) {
Marat Dukhan329da642019-11-19 21:44:39 -08002795 for (size_t channels = 2; channels < 10; channels++) {
2796 MaxPoolMicrokernelTester()
2797 .pooling_elements(17)
2798 .pooling_tile(9, 8)
2799 .channels(channels)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002800 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08002801 }
2802}
2803
Marat Dukhan99936602020-04-11 16:47:01 -07002804TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_twopass_fulltile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08002805 for (size_t channels = 2; channels < 10; channels++) {
2806 MaxPoolMicrokernelTester()
2807 .pooling_elements(17)
2808 .pooling_tile(9, 8)
2809 .channels(channels)
2810 .input_offset(3)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002811 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08002812 }
2813}
2814
Marat Dukhan99936602020-04-11 16:47:01 -07002815TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_twopass_fulltile_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08002816 for (size_t channels = 2; channels < 10; channels++) {
2817 MaxPoolMicrokernelTester()
2818 .pooling_elements(17)
2819 .pooling_tile(9, 8)
2820 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07002821 .qmin(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002822 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002823 }
2824}
2825
Marat Dukhan99936602020-04-11 16:47:01 -07002826TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_twopass_fulltile_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08002827 for (size_t channels = 2; channels < 10; channels++) {
2828 MaxPoolMicrokernelTester()
2829 .pooling_elements(17)
2830 .pooling_tile(9, 8)
2831 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07002832 .qmax(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002833 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08002834 }
2835}
2836
Marat Dukhan99936602020-04-11 16:47:01 -07002837TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_twopass_subtile) {
Marat Dukhan329da642019-11-19 21:44:39 -08002838 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
2839 for (size_t channels = 2; channels < 10; channels++) {
2840 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002841 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002842 .pooling_tile(9, 8)
2843 .channels(channels)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002844 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08002845 }
2846 }
2847}
2848
Marat Dukhan99936602020-04-11 16:47:01 -07002849TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_twopass_subtile_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08002850 for (size_t pooling_elements = 10; pooling_elements < 17; pooling_elements++) {
2851 for (size_t channels = 2; channels < 10; channels++) {
2852 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002853 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002854 .pooling_tile(9, 8)
2855 .channels(channels)
2856 .input_offset(3)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002857 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08002858 }
2859 }
2860}
2861
Marat Dukhan99936602020-04-11 16:47:01 -07002862TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_multipass) {
Marat Dukhan329da642019-11-19 21:44:39 -08002863 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2864 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002865 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002866 .pooling_tile(9, 8)
2867 .channels(1)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002868 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08002869 }
2870}
2871
Marat Dukhan99936602020-04-11 16:47:01 -07002872TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_multipass_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08002873 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2874 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002875 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002876 .pooling_tile(9, 8)
2877 .channels(1)
2878 .input_offset(3)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002879 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08002880 }
2881}
2882
Marat Dukhan99936602020-04-11 16:47:01 -07002883TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_multipass_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08002884 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2885 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002886 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002887 .pooling_tile(9, 8)
2888 .channels(1)
2889 .qmin(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002890 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08002891 }
2892}
2893
Marat Dukhan99936602020-04-11 16:47:01 -07002894TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_multipass_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08002895 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2896 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002897 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002898 .pooling_tile(9, 8)
2899 .channels(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -07002900 .qmax(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002901 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002902 }
2903}
2904
Marat Dukhan99936602020-04-11 16:47:01 -07002905TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_multipass) {
Marat Dukhan329da642019-11-19 21:44:39 -08002906 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2907 for (size_t channels = 2; channels < 10; channels++) {
2908 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002909 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002910 .pooling_tile(9, 8)
2911 .channels(channels)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002912 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002913 }
2914 }
2915}
2916
Marat Dukhan99936602020-04-11 16:47:01 -07002917TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_multipass_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08002918 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2919 for (size_t channels = 2; channels < 10; channels++) {
2920 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002921 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002922 .pooling_tile(9, 8)
2923 .channels(channels)
2924 .input_offset(3)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002925 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08002926 }
2927 }
2928}
2929
Marat Dukhan99936602020-04-11 16:47:01 -07002930TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_multipass_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08002931 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2932 for (size_t channels = 2; channels < 10; channels++) {
2933 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002934 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002935 .pooling_tile(9, 8)
2936 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07002937 .qmin(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002938 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002939 }
2940 }
2941}
2942
Marat Dukhan99936602020-04-11 16:47:01 -07002943TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_gt_1_multipass_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08002944 for (size_t pooling_elements = 18; pooling_elements <= 33; pooling_elements += 3) {
2945 for (size_t channels = 2; channels < 10; channels++) {
2946 MaxPoolMicrokernelTester()
Marat Dukhanf5fec4b2020-02-27 13:48:33 -08002947 .pooling_elements(pooling_elements)
Marat Dukhan329da642019-11-19 21:44:39 -08002948 .pooling_tile(9, 8)
2949 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07002950 .qmax(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002951 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002952 }
2953 }
2954}
2955
Marat Dukhan99936602020-04-11 16:47:01 -07002956TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, few_output_pixels) {
Marat Dukhan329da642019-11-19 21:44:39 -08002957 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
2958 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
2959 for (size_t channels = 1; channels <= 5; channels += 1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07002960 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -08002961 .output_pixels(output_pixels)
2962 .pooling_elements(pooling_elements)
2963 .pooling_tile(9, 8)
2964 .channels(channels)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002965 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002966 }
2967 }
2968 }
2969}
2970
Marat Dukhan99936602020-04-11 16:47:01 -07002971TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, few_output_pixels_with_input_offset) {
Marat Dukhan329da642019-11-19 21:44:39 -08002972 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
2973 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
2974 for (size_t channels = 1; channels <= 5; channels += 1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07002975 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -08002976 .output_pixels(output_pixels)
2977 .pooling_elements(pooling_elements)
2978 .pooling_tile(9, 8)
2979 .channels(channels)
2980 .input_offset(7)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002981 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002982 }
2983 }
2984 }
2985}
2986
Marat Dukhan99936602020-04-11 16:47:01 -07002987TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, few_output_pixels_with_qmin) {
Marat Dukhan329da642019-11-19 21:44:39 -08002988 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
2989 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
2990 for (size_t channels = 1; channels <= 5; channels += 1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07002991 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -08002992 .output_pixels(output_pixels)
2993 .pooling_elements(pooling_elements)
2994 .pooling_tile(9, 8)
2995 .channels(channels)
2996 .qmin(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07002997 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07002998 }
2999 }
3000 }
3001}
3002
Marat Dukhan99936602020-04-11 16:47:01 -07003003TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, few_output_pixels_with_qmax) {
Marat Dukhan329da642019-11-19 21:44:39 -08003004 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
3005 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
3006 for (size_t channels = 1; channels <= 5; channels += 1) {
3007 MaxPoolMicrokernelTester()
3008 .output_pixels(output_pixels)
3009 .pooling_elements(pooling_elements)
3010 .pooling_tile(9, 8)
3011 .channels(channels)
3012 .qmax(192)
Marat Dukhan91ae1652021-08-15 19:19:49 -07003013 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08003014 }
3015 }
3016 }
3017}
3018
Marat Dukhan99936602020-04-11 16:47:01 -07003019TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, few_output_pixels_with_output_stride) {
Marat Dukhan329da642019-11-19 21:44:39 -08003020 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
3021 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
3022 for (size_t channels = 1; channels <= 5; channels += 1) {
3023 MaxPoolMicrokernelTester()
3024 .output_pixels(output_pixels)
3025 .pooling_elements(pooling_elements)
3026 .pooling_tile(9, 8)
3027 .channels(channels)
3028 .output_stride(7)
Marat Dukhan91ae1652021-08-15 19:19:49 -07003029 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
Marat Dukhan329da642019-11-19 21:44:39 -08003030 }
3031 }
3032 }
3033}
3034
Marat Dukhan99936602020-04-11 16:47:01 -07003035TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, few_output_pixels_with_step) {
Marat Dukhan329da642019-11-19 21:44:39 -08003036 for (size_t output_pixels = 2; output_pixels <= 5; output_pixels++) {
3037 for (size_t pooling_elements : std::vector<size_t>{{2, 9, 16}}) {
3038 for (size_t channels = 1; channels <= 5; channels += 1) {
3039 for (size_t step = 2; step <= pooling_elements; step++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07003040 MaxPoolMicrokernelTester()
Marat Dukhan329da642019-11-19 21:44:39 -08003041 .output_pixels(output_pixels)
3042 .pooling_elements(pooling_elements)
3043 .pooling_tile(9, 8)
3044 .step(step)
3045 .channels(channels)
3046 .output_stride(7)
Marat Dukhan91ae1652021-08-15 19:19:49 -07003047 .Test(xnn_u8_maxpool_minmax_ukernel_9p8x__scalar_c1, xnn_init_u8_minmax_scalar_params);
XNNPACK Teamb455b122019-09-27 18:10:33 -07003048 }
3049 }
3050 }
3051 }
Marat Dukhan329da642019-11-19 21:44:39 -08003052}