blob: 0a34355057193921aad08e8d54daf8bff837cd02 [file] [log] [blame]
Marat Dukhan5c5fa962020-03-10 18:38:33 -07001// Copyright 2020 Google LLC
XNNPACK Teamb455b122019-09-27 18:10:33 -07002//
3// This source code is licensed under the BSD-style license found in the
4// LICENSE file in the root directory of this source tree.
Marat Dukhan5c5fa962020-03-10 18:38:33 -07005//
6// Auto-generated file. Do not edit!
7// Specification: test/f32-clamp.yaml
8// Generator: tools/generate-clamp-test.py
9
XNNPACK Teamb455b122019-09-27 18:10:33 -070010
XNNPACK Teamb455b122019-09-27 18:10:33 -070011#include <gtest/gtest.h>
12
Marat Dukhan1dadbf72019-10-01 10:46:20 -070013#include <xnnpack/common.h>
XNNPACK Teamb455b122019-09-27 18:10:33 -070014#include <xnnpack/isa-checks.h>
XNNPACK Teamb455b122019-09-27 18:10:33 -070015
Marat Dukhan1dadbf72019-10-01 10:46:20 -070016#include <xnnpack/clamp.h>
XNNPACK Teamb455b122019-09-27 18:10:33 -070017#include "clamp-microkernel-tester.h"
18
19
Marat Dukhan1dadbf72019-10-01 10:46:20 -070020#if XNN_ARCH_ARM || XNN_ARCH_ARM64
Marat Dukhan5c5fa962020-03-10 18:38:33 -070021 TEST(F32_CLAMP__NEON_X4, batch_eq_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070022 TEST_REQUIRES_ARM_NEON;
23 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -070024 .batch_size(4)
25 .Test(xnn_f32_clamp_ukernel__neon_x4);
XNNPACK Teamb455b122019-09-27 18:10:33 -070026 }
27
Marat Dukhan5c5fa962020-03-10 18:38:33 -070028 TEST(F32_CLAMP__NEON_X4, batch_div_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070029 TEST_REQUIRES_ARM_NEON;
Marat Dukhan5c5fa962020-03-10 18:38:33 -070030 for (size_t batch_size = 8; batch_size < 40; batch_size += 4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070031 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -070032 .batch_size(batch_size)
33 .Test(xnn_f32_clamp_ukernel__neon_x4);
XNNPACK Teamb455b122019-09-27 18:10:33 -070034 }
35 }
36
Marat Dukhan5c5fa962020-03-10 18:38:33 -070037 TEST(F32_CLAMP__NEON_X4, batch_lt_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070038 TEST_REQUIRES_ARM_NEON;
Marat Dukhan5c5fa962020-03-10 18:38:33 -070039 for (size_t batch_size = 1; batch_size < 4; batch_size++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070040 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -070041 .batch_size(batch_size)
42 .Test(xnn_f32_clamp_ukernel__neon_x4);
XNNPACK Teamb455b122019-09-27 18:10:33 -070043 }
44 }
45
Marat Dukhan5c5fa962020-03-10 18:38:33 -070046 TEST(F32_CLAMP__NEON_X4, batch_gt_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070047 TEST_REQUIRES_ARM_NEON;
Marat Dukhan5c5fa962020-03-10 18:38:33 -070048 for (size_t batch_size = 5; batch_size < 8; batch_size++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070049 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -070050 .batch_size(batch_size)
51 .Test(xnn_f32_clamp_ukernel__neon_x4);
XNNPACK Teamb455b122019-09-27 18:10:33 -070052 }
53 }
54
Marat Dukhan5c5fa962020-03-10 18:38:33 -070055 TEST(F32_CLAMP__NEON_X4, inplace) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070056 TEST_REQUIRES_ARM_NEON;
Marat Dukhan5c5fa962020-03-10 18:38:33 -070057 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070058 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -070059 .batch_size(batch_size)
XNNPACK Teamb455b122019-09-27 18:10:33 -070060 .inplace(true)
Marat Dukhan5c5fa962020-03-10 18:38:33 -070061 .Test(xnn_f32_clamp_ukernel__neon_x4);
XNNPACK Teamb455b122019-09-27 18:10:33 -070062 }
63 }
64
Marat Dukhan5c5fa962020-03-10 18:38:33 -070065 TEST(F32_CLAMP__NEON_X4, qmin) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070066 TEST_REQUIRES_ARM_NEON;
Marat Dukhan5c5fa962020-03-10 18:38:33 -070067 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070068 for (uint8_t qmin = 1; qmin < 255; qmin++) {
69 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -070070 .batch_size(batch_size)
XNNPACK Teamb455b122019-09-27 18:10:33 -070071 .qmin(qmin)
72 .qmax(255)
Marat Dukhan5c5fa962020-03-10 18:38:33 -070073 .Test(xnn_f32_clamp_ukernel__neon_x4);
XNNPACK Teamb455b122019-09-27 18:10:33 -070074 }
75 }
76 }
77
Marat Dukhan5c5fa962020-03-10 18:38:33 -070078 TEST(F32_CLAMP__NEON_X4, qmax) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070079 TEST_REQUIRES_ARM_NEON;
Marat Dukhan5c5fa962020-03-10 18:38:33 -070080 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070081 for (uint8_t qmax = 1; qmax < 255; qmax++) {
82 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -070083 .batch_size(batch_size)
XNNPACK Teamb455b122019-09-27 18:10:33 -070084 .qmin(0)
85 .qmax(qmax)
Marat Dukhan5c5fa962020-03-10 18:38:33 -070086 .Test(xnn_f32_clamp_ukernel__neon_x4);
XNNPACK Teamb455b122019-09-27 18:10:33 -070087 }
88 }
89 }
Marat Dukhan1dadbf72019-10-01 10:46:20 -070090#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
XNNPACK Teamb455b122019-09-27 18:10:33 -070091
Marat Dukhan5c5fa962020-03-10 18:38:33 -070092
93#if XNN_ARCH_ARM || XNN_ARCH_ARM64
94 TEST(F32_CLAMP__NEON_X8, batch_eq_8) {
95 TEST_REQUIRES_ARM_NEON;
XNNPACK Teamb455b122019-09-27 18:10:33 -070096 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -070097 .batch_size(8)
98 .Test(xnn_f32_clamp_ukernel__neon_x8);
XNNPACK Teamb455b122019-09-27 18:10:33 -070099 }
100
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700101 TEST(F32_CLAMP__NEON_X8, batch_div_8) {
102 TEST_REQUIRES_ARM_NEON;
103 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700104 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700105 .batch_size(batch_size)
106 .Test(xnn_f32_clamp_ukernel__neon_x8);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700107 }
108 }
109
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700110 TEST(F32_CLAMP__NEON_X8, batch_lt_8) {
111 TEST_REQUIRES_ARM_NEON;
112 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700113 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700114 .batch_size(batch_size)
115 .Test(xnn_f32_clamp_ukernel__neon_x8);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700116 }
117 }
118
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700119 TEST(F32_CLAMP__NEON_X8, batch_gt_8) {
120 TEST_REQUIRES_ARM_NEON;
121 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700122 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700123 .batch_size(batch_size)
124 .Test(xnn_f32_clamp_ukernel__neon_x8);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700125 }
126 }
127
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700128 TEST(F32_CLAMP__NEON_X8, inplace) {
129 TEST_REQUIRES_ARM_NEON;
130 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700131 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700132 .batch_size(batch_size)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700133 .inplace(true)
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700134 .Test(xnn_f32_clamp_ukernel__neon_x8);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700135 }
136 }
137
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700138 TEST(F32_CLAMP__NEON_X8, qmin) {
139 TEST_REQUIRES_ARM_NEON;
140 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700141 for (uint8_t qmin = 1; qmin < 255; qmin++) {
142 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700143 .batch_size(batch_size)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700144 .qmin(qmin)
145 .qmax(255)
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700146 .Test(xnn_f32_clamp_ukernel__neon_x8);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700147 }
148 }
149 }
150
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700151 TEST(F32_CLAMP__NEON_X8, qmax) {
152 TEST_REQUIRES_ARM_NEON;
153 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700154 for (uint8_t qmax = 1; qmax < 255; qmax++) {
155 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700156 .batch_size(batch_size)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700157 .qmin(0)
158 .qmax(qmax)
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700159 .Test(xnn_f32_clamp_ukernel__neon_x8);
160 }
161 }
162 }
163#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
164
165
166#if XNN_ARCH_X86 || XNN_ARCH_X86_64
167 TEST(F32_CLAMP__SSE_X4, batch_eq_4) {
168 TEST_REQUIRES_X86_SSE;
169 ClampMicrokernelTester()
170 .batch_size(4)
171 .Test(xnn_f32_clamp_ukernel__sse_x4);
172 }
173
174 TEST(F32_CLAMP__SSE_X4, batch_div_4) {
175 TEST_REQUIRES_X86_SSE;
176 for (size_t batch_size = 8; batch_size < 40; batch_size += 4) {
177 ClampMicrokernelTester()
178 .batch_size(batch_size)
179 .Test(xnn_f32_clamp_ukernel__sse_x4);
180 }
181 }
182
183 TEST(F32_CLAMP__SSE_X4, batch_lt_4) {
184 TEST_REQUIRES_X86_SSE;
185 for (size_t batch_size = 1; batch_size < 4; batch_size++) {
186 ClampMicrokernelTester()
187 .batch_size(batch_size)
188 .Test(xnn_f32_clamp_ukernel__sse_x4);
189 }
190 }
191
192 TEST(F32_CLAMP__SSE_X4, batch_gt_4) {
193 TEST_REQUIRES_X86_SSE;
194 for (size_t batch_size = 5; batch_size < 8; batch_size++) {
195 ClampMicrokernelTester()
196 .batch_size(batch_size)
197 .Test(xnn_f32_clamp_ukernel__sse_x4);
198 }
199 }
200
201 TEST(F32_CLAMP__SSE_X4, inplace) {
202 TEST_REQUIRES_X86_SSE;
203 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
204 ClampMicrokernelTester()
205 .batch_size(batch_size)
206 .inplace(true)
207 .Test(xnn_f32_clamp_ukernel__sse_x4);
208 }
209 }
210
211 TEST(F32_CLAMP__SSE_X4, qmin) {
212 TEST_REQUIRES_X86_SSE;
213 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
214 for (uint8_t qmin = 1; qmin < 255; qmin++) {
215 ClampMicrokernelTester()
216 .batch_size(batch_size)
217 .qmin(qmin)
218 .qmax(255)
219 .Test(xnn_f32_clamp_ukernel__sse_x4);
220 }
221 }
222 }
223
224 TEST(F32_CLAMP__SSE_X4, qmax) {
225 TEST_REQUIRES_X86_SSE;
226 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
227 for (uint8_t qmax = 1; qmax < 255; qmax++) {
228 ClampMicrokernelTester()
229 .batch_size(batch_size)
230 .qmin(0)
231 .qmax(qmax)
232 .Test(xnn_f32_clamp_ukernel__sse_x4);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700233 }
234 }
235 }
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700236#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
Marat Dukhane2c3f292019-11-27 15:40:54 -0800237
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700238
Marat Dukhane2c3f292019-11-27 15:40:54 -0800239#if XNN_ARCH_X86 || XNN_ARCH_X86_64
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700240 TEST(F32_CLAMP__SSE_X8, batch_eq_8) {
241 TEST_REQUIRES_X86_SSE;
Marat Dukhane2c3f292019-11-27 15:40:54 -0800242 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700243 .batch_size(8)
244 .Test(xnn_f32_clamp_ukernel__sse_x8);
Marat Dukhane2c3f292019-11-27 15:40:54 -0800245 }
246
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700247 TEST(F32_CLAMP__SSE_X8, batch_div_8) {
248 TEST_REQUIRES_X86_SSE;
249 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
Marat Dukhane2c3f292019-11-27 15:40:54 -0800250 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700251 .batch_size(batch_size)
252 .Test(xnn_f32_clamp_ukernel__sse_x8);
Marat Dukhane2c3f292019-11-27 15:40:54 -0800253 }
254 }
255
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700256 TEST(F32_CLAMP__SSE_X8, batch_lt_8) {
257 TEST_REQUIRES_X86_SSE;
258 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
Marat Dukhane2c3f292019-11-27 15:40:54 -0800259 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700260 .batch_size(batch_size)
261 .Test(xnn_f32_clamp_ukernel__sse_x8);
Marat Dukhane2c3f292019-11-27 15:40:54 -0800262 }
263 }
264
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700265 TEST(F32_CLAMP__SSE_X8, batch_gt_8) {
266 TEST_REQUIRES_X86_SSE;
267 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
Marat Dukhane2c3f292019-11-27 15:40:54 -0800268 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700269 .batch_size(batch_size)
270 .Test(xnn_f32_clamp_ukernel__sse_x8);
Marat Dukhane2c3f292019-11-27 15:40:54 -0800271 }
272 }
273
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700274 TEST(F32_CLAMP__SSE_X8, inplace) {
275 TEST_REQUIRES_X86_SSE;
276 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhane2c3f292019-11-27 15:40:54 -0800277 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700278 .batch_size(batch_size)
Marat Dukhane2c3f292019-11-27 15:40:54 -0800279 .inplace(true)
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700280 .Test(xnn_f32_clamp_ukernel__sse_x8);
Marat Dukhane2c3f292019-11-27 15:40:54 -0800281 }
282 }
283
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700284 TEST(F32_CLAMP__SSE_X8, qmin) {
285 TEST_REQUIRES_X86_SSE;
286 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhane2c3f292019-11-27 15:40:54 -0800287 for (uint8_t qmin = 1; qmin < 255; qmin++) {
288 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700289 .batch_size(batch_size)
Marat Dukhane2c3f292019-11-27 15:40:54 -0800290 .qmin(qmin)
291 .qmax(255)
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700292 .Test(xnn_f32_clamp_ukernel__sse_x8);
Marat Dukhane2c3f292019-11-27 15:40:54 -0800293 }
294 }
295 }
296
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700297 TEST(F32_CLAMP__SSE_X8, qmax) {
298 TEST_REQUIRES_X86_SSE;
299 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhane2c3f292019-11-27 15:40:54 -0800300 for (uint8_t qmax = 1; qmax < 255; qmax++) {
301 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700302 .batch_size(batch_size)
Marat Dukhane2c3f292019-11-27 15:40:54 -0800303 .qmin(0)
304 .qmax(qmax)
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700305 .Test(xnn_f32_clamp_ukernel__sse_x8);
Marat Dukhane2c3f292019-11-27 15:40:54 -0800306 }
307 }
308 }
309#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
310
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700311
Marat Dukhane2c3f292019-11-27 15:40:54 -0800312#if XNN_ARCH_X86 || XNN_ARCH_X86_64
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700313 TEST(F32_CLAMP__AVX_X8, batch_eq_8) {
314 TEST_REQUIRES_X86_AVX;
Marat Dukhane2c3f292019-11-27 15:40:54 -0800315 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700316 .batch_size(8)
317 .Test(xnn_f32_clamp_ukernel__avx_x8);
Marat Dukhane2c3f292019-11-27 15:40:54 -0800318 }
319
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700320 TEST(F32_CLAMP__AVX_X8, batch_div_8) {
321 TEST_REQUIRES_X86_AVX;
322 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
Marat Dukhane2c3f292019-11-27 15:40:54 -0800323 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700324 .batch_size(batch_size)
325 .Test(xnn_f32_clamp_ukernel__avx_x8);
Marat Dukhane2c3f292019-11-27 15:40:54 -0800326 }
327 }
328
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700329 TEST(F32_CLAMP__AVX_X8, batch_lt_8) {
330 TEST_REQUIRES_X86_AVX;
331 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
Marat Dukhane2c3f292019-11-27 15:40:54 -0800332 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700333 .batch_size(batch_size)
334 .Test(xnn_f32_clamp_ukernel__avx_x8);
Marat Dukhane2c3f292019-11-27 15:40:54 -0800335 }
336 }
337
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700338 TEST(F32_CLAMP__AVX_X8, batch_gt_8) {
339 TEST_REQUIRES_X86_AVX;
340 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
Marat Dukhane2c3f292019-11-27 15:40:54 -0800341 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700342 .batch_size(batch_size)
343 .Test(xnn_f32_clamp_ukernel__avx_x8);
Marat Dukhane2c3f292019-11-27 15:40:54 -0800344 }
345 }
346
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700347 TEST(F32_CLAMP__AVX_X8, inplace) {
348 TEST_REQUIRES_X86_AVX;
349 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhane2c3f292019-11-27 15:40:54 -0800350 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700351 .batch_size(batch_size)
Marat Dukhane2c3f292019-11-27 15:40:54 -0800352 .inplace(true)
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700353 .Test(xnn_f32_clamp_ukernel__avx_x8);
Marat Dukhane2c3f292019-11-27 15:40:54 -0800354 }
355 }
356
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700357 TEST(F32_CLAMP__AVX_X8, qmin) {
358 TEST_REQUIRES_X86_AVX;
359 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhane2c3f292019-11-27 15:40:54 -0800360 for (uint8_t qmin = 1; qmin < 255; qmin++) {
361 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700362 .batch_size(batch_size)
Marat Dukhane2c3f292019-11-27 15:40:54 -0800363 .qmin(qmin)
364 .qmax(255)
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700365 .Test(xnn_f32_clamp_ukernel__avx_x8);
Marat Dukhane2c3f292019-11-27 15:40:54 -0800366 }
367 }
368 }
369
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700370 TEST(F32_CLAMP__AVX_X8, qmax) {
371 TEST_REQUIRES_X86_AVX;
372 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhane2c3f292019-11-27 15:40:54 -0800373 for (uint8_t qmax = 1; qmax < 255; qmax++) {
374 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700375 .batch_size(batch_size)
Marat Dukhane2c3f292019-11-27 15:40:54 -0800376 .qmin(0)
377 .qmax(qmax)
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700378 .Test(xnn_f32_clamp_ukernel__avx_x8);
Marat Dukhane2c3f292019-11-27 15:40:54 -0800379 }
380 }
381 }
382#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
383
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700384
385#if XNN_ARCH_X86 || XNN_ARCH_X86_64
386 TEST(F32_CLAMP__AVX_X16, batch_eq_16) {
387 TEST_REQUIRES_X86_AVX;
Marat Dukhane2c3f292019-11-27 15:40:54 -0800388 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700389 .batch_size(16)
390 .Test(xnn_f32_clamp_ukernel__avx_x16);
Marat Dukhane2c3f292019-11-27 15:40:54 -0800391 }
392
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700393 TEST(F32_CLAMP__AVX_X16, batch_div_16) {
394 TEST_REQUIRES_X86_AVX;
395 for (size_t batch_size = 32; batch_size < 160; batch_size += 16) {
Marat Dukhane2c3f292019-11-27 15:40:54 -0800396 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700397 .batch_size(batch_size)
398 .Test(xnn_f32_clamp_ukernel__avx_x16);
Marat Dukhane2c3f292019-11-27 15:40:54 -0800399 }
400 }
401
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700402 TEST(F32_CLAMP__AVX_X16, batch_lt_16) {
403 TEST_REQUIRES_X86_AVX;
404 for (size_t batch_size = 1; batch_size < 16; batch_size++) {
Marat Dukhane2c3f292019-11-27 15:40:54 -0800405 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700406 .batch_size(batch_size)
407 .Test(xnn_f32_clamp_ukernel__avx_x16);
Marat Dukhane2c3f292019-11-27 15:40:54 -0800408 }
409 }
410
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700411 TEST(F32_CLAMP__AVX_X16, batch_gt_16) {
412 TEST_REQUIRES_X86_AVX;
413 for (size_t batch_size = 17; batch_size < 32; batch_size++) {
Marat Dukhane2c3f292019-11-27 15:40:54 -0800414 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700415 .batch_size(batch_size)
416 .Test(xnn_f32_clamp_ukernel__avx_x16);
Marat Dukhane2c3f292019-11-27 15:40:54 -0800417 }
418 }
419
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700420 TEST(F32_CLAMP__AVX_X16, inplace) {
421 TEST_REQUIRES_X86_AVX;
422 for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) {
Marat Dukhane2c3f292019-11-27 15:40:54 -0800423 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700424 .batch_size(batch_size)
Marat Dukhane2c3f292019-11-27 15:40:54 -0800425 .inplace(true)
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700426 .Test(xnn_f32_clamp_ukernel__avx_x16);
Marat Dukhane2c3f292019-11-27 15:40:54 -0800427 }
428 }
429
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700430 TEST(F32_CLAMP__AVX_X16, qmin) {
431 TEST_REQUIRES_X86_AVX;
432 for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) {
Marat Dukhane2c3f292019-11-27 15:40:54 -0800433 for (uint8_t qmin = 1; qmin < 255; qmin++) {
434 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700435 .batch_size(batch_size)
Marat Dukhane2c3f292019-11-27 15:40:54 -0800436 .qmin(qmin)
437 .qmax(255)
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700438 .Test(xnn_f32_clamp_ukernel__avx_x16);
Marat Dukhane2c3f292019-11-27 15:40:54 -0800439 }
440 }
441 }
442
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700443 TEST(F32_CLAMP__AVX_X16, qmax) {
444 TEST_REQUIRES_X86_AVX;
445 for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) {
Marat Dukhane2c3f292019-11-27 15:40:54 -0800446 for (uint8_t qmax = 1; qmax < 255; qmax++) {
447 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700448 .batch_size(batch_size)
Marat Dukhane2c3f292019-11-27 15:40:54 -0800449 .qmin(0)
450 .qmax(qmax)
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700451 .Test(xnn_f32_clamp_ukernel__avx_x16);
Marat Dukhane2c3f292019-11-27 15:40:54 -0800452 }
453 }
454 }
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700455#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
456
457
458#if XNN_ARCH_X86 || XNN_ARCH_X86_64
459 TEST(F32_CLAMP__AVX512F_X16, batch_eq_16) {
460 TEST_REQUIRES_X86_AVX512F;
461 ClampMicrokernelTester()
462 .batch_size(16)
463 .Test(xnn_f32_clamp_ukernel__avx512f_x16);
464 }
465
466 TEST(F32_CLAMP__AVX512F_X16, batch_div_16) {
467 TEST_REQUIRES_X86_AVX512F;
468 for (size_t batch_size = 32; batch_size < 160; batch_size += 16) {
469 ClampMicrokernelTester()
470 .batch_size(batch_size)
471 .Test(xnn_f32_clamp_ukernel__avx512f_x16);
472 }
473 }
474
475 TEST(F32_CLAMP__AVX512F_X16, batch_lt_16) {
476 TEST_REQUIRES_X86_AVX512F;
477 for (size_t batch_size = 1; batch_size < 16; batch_size++) {
478 ClampMicrokernelTester()
479 .batch_size(batch_size)
480 .Test(xnn_f32_clamp_ukernel__avx512f_x16);
481 }
482 }
483
484 TEST(F32_CLAMP__AVX512F_X16, batch_gt_16) {
485 TEST_REQUIRES_X86_AVX512F;
486 for (size_t batch_size = 17; batch_size < 32; batch_size++) {
487 ClampMicrokernelTester()
488 .batch_size(batch_size)
489 .Test(xnn_f32_clamp_ukernel__avx512f_x16);
490 }
491 }
492
493 TEST(F32_CLAMP__AVX512F_X16, inplace) {
494 TEST_REQUIRES_X86_AVX512F;
495 for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) {
496 ClampMicrokernelTester()
497 .batch_size(batch_size)
498 .inplace(true)
499 .Test(xnn_f32_clamp_ukernel__avx512f_x16);
500 }
501 }
502
503 TEST(F32_CLAMP__AVX512F_X16, qmin) {
504 TEST_REQUIRES_X86_AVX512F;
505 for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) {
506 for (uint8_t qmin = 1; qmin < 255; qmin++) {
507 ClampMicrokernelTester()
508 .batch_size(batch_size)
509 .qmin(qmin)
510 .qmax(255)
511 .Test(xnn_f32_clamp_ukernel__avx512f_x16);
512 }
513 }
514 }
515
516 TEST(F32_CLAMP__AVX512F_X16, qmax) {
517 TEST_REQUIRES_X86_AVX512F;
518 for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) {
519 for (uint8_t qmax = 1; qmax < 255; qmax++) {
520 ClampMicrokernelTester()
521 .batch_size(batch_size)
522 .qmin(0)
523 .qmax(qmax)
524 .Test(xnn_f32_clamp_ukernel__avx512f_x16);
525 }
526 }
527 }
528#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
529
530
531#if XNN_ARCH_X86 || XNN_ARCH_X86_64
532 TEST(F32_CLAMP__AVX512F_X32, batch_eq_32) {
533 TEST_REQUIRES_X86_AVX512F;
534 ClampMicrokernelTester()
535 .batch_size(32)
536 .Test(xnn_f32_clamp_ukernel__avx512f_x32);
537 }
538
539 TEST(F32_CLAMP__AVX512F_X32, batch_div_32) {
540 TEST_REQUIRES_X86_AVX512F;
541 for (size_t batch_size = 64; batch_size < 320; batch_size += 32) {
542 ClampMicrokernelTester()
543 .batch_size(batch_size)
544 .Test(xnn_f32_clamp_ukernel__avx512f_x32);
545 }
546 }
547
548 TEST(F32_CLAMP__AVX512F_X32, batch_lt_32) {
549 TEST_REQUIRES_X86_AVX512F;
550 for (size_t batch_size = 1; batch_size < 32; batch_size++) {
551 ClampMicrokernelTester()
552 .batch_size(batch_size)
553 .Test(xnn_f32_clamp_ukernel__avx512f_x32);
554 }
555 }
556
557 TEST(F32_CLAMP__AVX512F_X32, batch_gt_32) {
558 TEST_REQUIRES_X86_AVX512F;
559 for (size_t batch_size = 33; batch_size < 64; batch_size++) {
560 ClampMicrokernelTester()
561 .batch_size(batch_size)
562 .Test(xnn_f32_clamp_ukernel__avx512f_x32);
563 }
564 }
565
566 TEST(F32_CLAMP__AVX512F_X32, inplace) {
567 TEST_REQUIRES_X86_AVX512F;
568 for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) {
569 ClampMicrokernelTester()
570 .batch_size(batch_size)
571 .inplace(true)
572 .Test(xnn_f32_clamp_ukernel__avx512f_x32);
573 }
574 }
575
576 TEST(F32_CLAMP__AVX512F_X32, qmin) {
577 TEST_REQUIRES_X86_AVX512F;
578 for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) {
579 for (uint8_t qmin = 1; qmin < 255; qmin++) {
580 ClampMicrokernelTester()
581 .batch_size(batch_size)
582 .qmin(qmin)
583 .qmax(255)
584 .Test(xnn_f32_clamp_ukernel__avx512f_x32);
585 }
586 }
587 }
588
589 TEST(F32_CLAMP__AVX512F_X32, qmax) {
590 TEST_REQUIRES_X86_AVX512F;
591 for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) {
592 for (uint8_t qmax = 1; qmax < 255; qmax++) {
593 ClampMicrokernelTester()
594 .batch_size(batch_size)
595 .qmin(0)
596 .qmax(qmax)
597 .Test(xnn_f32_clamp_ukernel__avx512f_x32);
598 }
599 }
600 }
601#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
602
603
Marat Dukhan3fa52c82020-07-08 12:54:33 -0700604#if XNN_ARCH_WASMSIMD
605 TEST(F32_CLAMP__WASMSIMD_ARM_X4, batch_eq_4) {
606 ClampMicrokernelTester()
607 .batch_size(4)
608 .Test(xnn_f32_clamp_ukernel__wasmsimd_arm_x4);
609 }
610
611 TEST(F32_CLAMP__WASMSIMD_ARM_X4, batch_div_4) {
612 for (size_t batch_size = 8; batch_size < 40; batch_size += 4) {
613 ClampMicrokernelTester()
614 .batch_size(batch_size)
615 .Test(xnn_f32_clamp_ukernel__wasmsimd_arm_x4);
616 }
617 }
618
619 TEST(F32_CLAMP__WASMSIMD_ARM_X4, batch_lt_4) {
620 for (size_t batch_size = 1; batch_size < 4; batch_size++) {
621 ClampMicrokernelTester()
622 .batch_size(batch_size)
623 .Test(xnn_f32_clamp_ukernel__wasmsimd_arm_x4);
624 }
625 }
626
627 TEST(F32_CLAMP__WASMSIMD_ARM_X4, batch_gt_4) {
628 for (size_t batch_size = 5; batch_size < 8; batch_size++) {
629 ClampMicrokernelTester()
630 .batch_size(batch_size)
631 .Test(xnn_f32_clamp_ukernel__wasmsimd_arm_x4);
632 }
633 }
634
635 TEST(F32_CLAMP__WASMSIMD_ARM_X4, inplace) {
636 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
637 ClampMicrokernelTester()
638 .batch_size(batch_size)
639 .inplace(true)
640 .Test(xnn_f32_clamp_ukernel__wasmsimd_arm_x4);
641 }
642 }
643
644 TEST(F32_CLAMP__WASMSIMD_ARM_X4, qmin) {
645 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
646 for (uint8_t qmin = 1; qmin < 255; qmin++) {
647 ClampMicrokernelTester()
648 .batch_size(batch_size)
649 .qmin(qmin)
650 .qmax(255)
651 .Test(xnn_f32_clamp_ukernel__wasmsimd_arm_x4);
652 }
653 }
654 }
655
656 TEST(F32_CLAMP__WASMSIMD_ARM_X4, qmax) {
657 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
658 for (uint8_t qmax = 1; qmax < 255; qmax++) {
659 ClampMicrokernelTester()
660 .batch_size(batch_size)
661 .qmin(0)
662 .qmax(qmax)
663 .Test(xnn_f32_clamp_ukernel__wasmsimd_arm_x4);
664 }
665 }
666 }
667#endif // XNN_ARCH_WASMSIMD
668
669
670#if XNN_ARCH_WASMSIMD
671 TEST(F32_CLAMP__WASMSIMD_ARM_X8, batch_eq_8) {
672 ClampMicrokernelTester()
673 .batch_size(8)
674 .Test(xnn_f32_clamp_ukernel__wasmsimd_arm_x8);
675 }
676
677 TEST(F32_CLAMP__WASMSIMD_ARM_X8, batch_div_8) {
678 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
679 ClampMicrokernelTester()
680 .batch_size(batch_size)
681 .Test(xnn_f32_clamp_ukernel__wasmsimd_arm_x8);
682 }
683 }
684
685 TEST(F32_CLAMP__WASMSIMD_ARM_X8, batch_lt_8) {
686 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
687 ClampMicrokernelTester()
688 .batch_size(batch_size)
689 .Test(xnn_f32_clamp_ukernel__wasmsimd_arm_x8);
690 }
691 }
692
693 TEST(F32_CLAMP__WASMSIMD_ARM_X8, batch_gt_8) {
694 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
695 ClampMicrokernelTester()
696 .batch_size(batch_size)
697 .Test(xnn_f32_clamp_ukernel__wasmsimd_arm_x8);
698 }
699 }
700
701 TEST(F32_CLAMP__WASMSIMD_ARM_X8, inplace) {
702 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
703 ClampMicrokernelTester()
704 .batch_size(batch_size)
705 .inplace(true)
706 .Test(xnn_f32_clamp_ukernel__wasmsimd_arm_x8);
707 }
708 }
709
710 TEST(F32_CLAMP__WASMSIMD_ARM_X8, qmin) {
711 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
712 for (uint8_t qmin = 1; qmin < 255; qmin++) {
713 ClampMicrokernelTester()
714 .batch_size(batch_size)
715 .qmin(qmin)
716 .qmax(255)
717 .Test(xnn_f32_clamp_ukernel__wasmsimd_arm_x8);
718 }
719 }
720 }
721
722 TEST(F32_CLAMP__WASMSIMD_ARM_X8, qmax) {
723 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
724 for (uint8_t qmax = 1; qmax < 255; qmax++) {
725 ClampMicrokernelTester()
726 .batch_size(batch_size)
727 .qmin(0)
728 .qmax(qmax)
729 .Test(xnn_f32_clamp_ukernel__wasmsimd_arm_x8);
730 }
731 }
732 }
733#endif // XNN_ARCH_WASMSIMD
734
735
736#if XNN_ARCH_WASMSIMD
737 TEST(F32_CLAMP__WASMSIMD_X86_X4, batch_eq_4) {
738 ClampMicrokernelTester()
739 .batch_size(4)
740 .Test(xnn_f32_clamp_ukernel__wasmsimd_x86_x4);
741 }
742
743 TEST(F32_CLAMP__WASMSIMD_X86_X4, batch_div_4) {
744 for (size_t batch_size = 8; batch_size < 40; batch_size += 4) {
745 ClampMicrokernelTester()
746 .batch_size(batch_size)
747 .Test(xnn_f32_clamp_ukernel__wasmsimd_x86_x4);
748 }
749 }
750
751 TEST(F32_CLAMP__WASMSIMD_X86_X4, batch_lt_4) {
752 for (size_t batch_size = 1; batch_size < 4; batch_size++) {
753 ClampMicrokernelTester()
754 .batch_size(batch_size)
755 .Test(xnn_f32_clamp_ukernel__wasmsimd_x86_x4);
756 }
757 }
758
759 TEST(F32_CLAMP__WASMSIMD_X86_X4, batch_gt_4) {
760 for (size_t batch_size = 5; batch_size < 8; batch_size++) {
761 ClampMicrokernelTester()
762 .batch_size(batch_size)
763 .Test(xnn_f32_clamp_ukernel__wasmsimd_x86_x4);
764 }
765 }
766
767 TEST(F32_CLAMP__WASMSIMD_X86_X4, inplace) {
768 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
769 ClampMicrokernelTester()
770 .batch_size(batch_size)
771 .inplace(true)
772 .Test(xnn_f32_clamp_ukernel__wasmsimd_x86_x4);
773 }
774 }
775
776 TEST(F32_CLAMP__WASMSIMD_X86_X4, qmin) {
777 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
778 for (uint8_t qmin = 1; qmin < 255; qmin++) {
779 ClampMicrokernelTester()
780 .batch_size(batch_size)
781 .qmin(qmin)
782 .qmax(255)
783 .Test(xnn_f32_clamp_ukernel__wasmsimd_x86_x4);
784 }
785 }
786 }
787
788 TEST(F32_CLAMP__WASMSIMD_X86_X4, qmax) {
789 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
790 for (uint8_t qmax = 1; qmax < 255; qmax++) {
791 ClampMicrokernelTester()
792 .batch_size(batch_size)
793 .qmin(0)
794 .qmax(qmax)
795 .Test(xnn_f32_clamp_ukernel__wasmsimd_x86_x4);
796 }
797 }
798 }
799#endif // XNN_ARCH_WASMSIMD
800
801
802#if XNN_ARCH_WASMSIMD
803 TEST(F32_CLAMP__WASMSIMD_X86_X8, batch_eq_8) {
804 ClampMicrokernelTester()
805 .batch_size(8)
806 .Test(xnn_f32_clamp_ukernel__wasmsimd_x86_x8);
807 }
808
809 TEST(F32_CLAMP__WASMSIMD_X86_X8, batch_div_8) {
810 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
811 ClampMicrokernelTester()
812 .batch_size(batch_size)
813 .Test(xnn_f32_clamp_ukernel__wasmsimd_x86_x8);
814 }
815 }
816
817 TEST(F32_CLAMP__WASMSIMD_X86_X8, batch_lt_8) {
818 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
819 ClampMicrokernelTester()
820 .batch_size(batch_size)
821 .Test(xnn_f32_clamp_ukernel__wasmsimd_x86_x8);
822 }
823 }
824
825 TEST(F32_CLAMP__WASMSIMD_X86_X8, batch_gt_8) {
826 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
827 ClampMicrokernelTester()
828 .batch_size(batch_size)
829 .Test(xnn_f32_clamp_ukernel__wasmsimd_x86_x8);
830 }
831 }
832
833 TEST(F32_CLAMP__WASMSIMD_X86_X8, inplace) {
834 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
835 ClampMicrokernelTester()
836 .batch_size(batch_size)
837 .inplace(true)
838 .Test(xnn_f32_clamp_ukernel__wasmsimd_x86_x8);
839 }
840 }
841
842 TEST(F32_CLAMP__WASMSIMD_X86_X8, qmin) {
843 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
844 for (uint8_t qmin = 1; qmin < 255; qmin++) {
845 ClampMicrokernelTester()
846 .batch_size(batch_size)
847 .qmin(qmin)
848 .qmax(255)
849 .Test(xnn_f32_clamp_ukernel__wasmsimd_x86_x8);
850 }
851 }
852 }
853
854 TEST(F32_CLAMP__WASMSIMD_X86_X8, qmax) {
855 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
856 for (uint8_t qmax = 1; qmax < 255; qmax++) {
857 ClampMicrokernelTester()
858 .batch_size(batch_size)
859 .qmin(0)
860 .qmax(qmax)
861 .Test(xnn_f32_clamp_ukernel__wasmsimd_x86_x8);
862 }
863 }
864 }
865#endif // XNN_ARCH_WASMSIMD
866
867
Marat Dukhanfb5b20a2020-06-26 13:14:50 -0700868#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700869 TEST(F32_CLAMP__WASM_X1, batch_eq_1) {
Marat Dukhan436ebe62019-12-04 15:10:12 -0800870 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700871 .batch_size(1)
Marat Dukhan47387d62020-06-29 12:53:20 -0700872 .Test(xnn_f32_clamp_ukernel__wasm_x1);
Marat Dukhan436ebe62019-12-04 15:10:12 -0800873 }
874
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700875 TEST(F32_CLAMP__WASM_X1, batch_gt_1) {
876 for (size_t batch_size = 2; batch_size < 10; batch_size++) {
Marat Dukhan436ebe62019-12-04 15:10:12 -0800877 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700878 .batch_size(batch_size)
Marat Dukhan47387d62020-06-29 12:53:20 -0700879 .Test(xnn_f32_clamp_ukernel__wasm_x1);
Marat Dukhan436ebe62019-12-04 15:10:12 -0800880 }
881 }
882
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700883 TEST(F32_CLAMP__WASM_X1, inplace) {
884 for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) {
Marat Dukhan436ebe62019-12-04 15:10:12 -0800885 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700886 .batch_size(batch_size)
Marat Dukhan436ebe62019-12-04 15:10:12 -0800887 .inplace(true)
Marat Dukhan47387d62020-06-29 12:53:20 -0700888 .Test(xnn_f32_clamp_ukernel__wasm_x1);
Marat Dukhan436ebe62019-12-04 15:10:12 -0800889 }
890 }
891
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700892 TEST(F32_CLAMP__WASM_X1, qmin) {
893 for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) {
Marat Dukhan436ebe62019-12-04 15:10:12 -0800894 for (uint8_t qmin = 1; qmin < 255; qmin++) {
895 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700896 .batch_size(batch_size)
Marat Dukhan436ebe62019-12-04 15:10:12 -0800897 .qmin(qmin)
898 .qmax(255)
Marat Dukhan47387d62020-06-29 12:53:20 -0700899 .Test(xnn_f32_clamp_ukernel__wasm_x1);
Marat Dukhan436ebe62019-12-04 15:10:12 -0800900 }
901 }
902 }
903
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700904 TEST(F32_CLAMP__WASM_X1, qmax) {
905 for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) {
Marat Dukhan436ebe62019-12-04 15:10:12 -0800906 for (uint8_t qmax = 1; qmax < 255; qmax++) {
907 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700908 .batch_size(batch_size)
Marat Dukhan436ebe62019-12-04 15:10:12 -0800909 .qmin(0)
910 .qmax(qmax)
Marat Dukhan47387d62020-06-29 12:53:20 -0700911 .Test(xnn_f32_clamp_ukernel__wasm_x1);
Marat Dukhan436ebe62019-12-04 15:10:12 -0800912 }
913 }
914 }
Marat Dukhanfb5b20a2020-06-26 13:14:50 -0700915#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
Marat Dukhan436ebe62019-12-04 15:10:12 -0800916
917
Marat Dukhanfb5b20a2020-06-26 13:14:50 -0700918#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700919 TEST(F32_CLAMP__WASM_X2, batch_eq_2) {
920 ClampMicrokernelTester()
921 .batch_size(2)
Marat Dukhan47387d62020-06-29 12:53:20 -0700922 .Test(xnn_f32_clamp_ukernel__wasm_x2);
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700923 }
924
925 TEST(F32_CLAMP__WASM_X2, batch_div_2) {
926 for (size_t batch_size = 4; batch_size < 20; batch_size += 2) {
927 ClampMicrokernelTester()
928 .batch_size(batch_size)
Marat Dukhan47387d62020-06-29 12:53:20 -0700929 .Test(xnn_f32_clamp_ukernel__wasm_x2);
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700930 }
931 }
932
933 TEST(F32_CLAMP__WASM_X2, batch_lt_2) {
934 for (size_t batch_size = 1; batch_size < 2; batch_size++) {
935 ClampMicrokernelTester()
936 .batch_size(batch_size)
Marat Dukhan47387d62020-06-29 12:53:20 -0700937 .Test(xnn_f32_clamp_ukernel__wasm_x2);
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700938 }
939 }
940
941 TEST(F32_CLAMP__WASM_X2, batch_gt_2) {
942 for (size_t batch_size = 3; batch_size < 4; batch_size++) {
943 ClampMicrokernelTester()
944 .batch_size(batch_size)
Marat Dukhan47387d62020-06-29 12:53:20 -0700945 .Test(xnn_f32_clamp_ukernel__wasm_x2);
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700946 }
947 }
948
949 TEST(F32_CLAMP__WASM_X2, inplace) {
950 for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) {
951 ClampMicrokernelTester()
952 .batch_size(batch_size)
953 .inplace(true)
Marat Dukhan47387d62020-06-29 12:53:20 -0700954 .Test(xnn_f32_clamp_ukernel__wasm_x2);
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700955 }
956 }
957
958 TEST(F32_CLAMP__WASM_X2, qmin) {
959 for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) {
960 for (uint8_t qmin = 1; qmin < 255; qmin++) {
961 ClampMicrokernelTester()
962 .batch_size(batch_size)
963 .qmin(qmin)
964 .qmax(255)
Marat Dukhan47387d62020-06-29 12:53:20 -0700965 .Test(xnn_f32_clamp_ukernel__wasm_x2);
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700966 }
967 }
968 }
969
970 TEST(F32_CLAMP__WASM_X2, qmax) {
971 for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) {
972 for (uint8_t qmax = 1; qmax < 255; qmax++) {
973 ClampMicrokernelTester()
974 .batch_size(batch_size)
975 .qmin(0)
976 .qmax(qmax)
Marat Dukhan47387d62020-06-29 12:53:20 -0700977 .Test(xnn_f32_clamp_ukernel__wasm_x2);
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700978 }
979 }
980 }
Marat Dukhanfb5b20a2020-06-26 13:14:50 -0700981#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700982
983
Marat Dukhanfb5b20a2020-06-26 13:14:50 -0700984#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700985 TEST(F32_CLAMP__WASM_X4, batch_eq_4) {
986 ClampMicrokernelTester()
987 .batch_size(4)
Marat Dukhan47387d62020-06-29 12:53:20 -0700988 .Test(xnn_f32_clamp_ukernel__wasm_x4);
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700989 }
990
991 TEST(F32_CLAMP__WASM_X4, batch_div_4) {
992 for (size_t batch_size = 8; batch_size < 40; batch_size += 4) {
993 ClampMicrokernelTester()
994 .batch_size(batch_size)
Marat Dukhan47387d62020-06-29 12:53:20 -0700995 .Test(xnn_f32_clamp_ukernel__wasm_x4);
Marat Dukhan5c5fa962020-03-10 18:38:33 -0700996 }
997 }
998
999 TEST(F32_CLAMP__WASM_X4, batch_lt_4) {
1000 for (size_t batch_size = 1; batch_size < 4; batch_size++) {
1001 ClampMicrokernelTester()
1002 .batch_size(batch_size)
Marat Dukhan47387d62020-06-29 12:53:20 -07001003 .Test(xnn_f32_clamp_ukernel__wasm_x4);
Marat Dukhan5c5fa962020-03-10 18:38:33 -07001004 }
1005 }
1006
1007 TEST(F32_CLAMP__WASM_X4, batch_gt_4) {
1008 for (size_t batch_size = 5; batch_size < 8; batch_size++) {
1009 ClampMicrokernelTester()
1010 .batch_size(batch_size)
Marat Dukhan47387d62020-06-29 12:53:20 -07001011 .Test(xnn_f32_clamp_ukernel__wasm_x4);
Marat Dukhan5c5fa962020-03-10 18:38:33 -07001012 }
1013 }
1014
1015 TEST(F32_CLAMP__WASM_X4, inplace) {
1016 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
1017 ClampMicrokernelTester()
1018 .batch_size(batch_size)
1019 .inplace(true)
Marat Dukhan47387d62020-06-29 12:53:20 -07001020 .Test(xnn_f32_clamp_ukernel__wasm_x4);
Marat Dukhan5c5fa962020-03-10 18:38:33 -07001021 }
1022 }
1023
1024 TEST(F32_CLAMP__WASM_X4, qmin) {
1025 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
1026 for (uint8_t qmin = 1; qmin < 255; qmin++) {
1027 ClampMicrokernelTester()
1028 .batch_size(batch_size)
1029 .qmin(qmin)
1030 .qmax(255)
Marat Dukhan47387d62020-06-29 12:53:20 -07001031 .Test(xnn_f32_clamp_ukernel__wasm_x4);
Marat Dukhan5c5fa962020-03-10 18:38:33 -07001032 }
1033 }
1034 }
1035
1036 TEST(F32_CLAMP__WASM_X4, qmax) {
1037 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
1038 for (uint8_t qmax = 1; qmax < 255; qmax++) {
1039 ClampMicrokernelTester()
1040 .batch_size(batch_size)
1041 .qmin(0)
1042 .qmax(qmax)
Marat Dukhan47387d62020-06-29 12:53:20 -07001043 .Test(xnn_f32_clamp_ukernel__wasm_x4);
Marat Dukhan5c5fa962020-03-10 18:38:33 -07001044 }
1045 }
1046 }
Marat Dukhanfb5b20a2020-06-26 13:14:50 -07001047#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
Marat Dukhan5c5fa962020-03-10 18:38:33 -07001048
1049
1050TEST(F32_CLAMP__SCALAR_X1, batch_eq_1) {
Marat Dukhane2c3f292019-11-27 15:40:54 -08001051 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -07001052 .batch_size(1)
1053 .Test(xnn_f32_clamp_ukernel__scalar_x1, ClampMicrokernelTester::Variant::Scalar);
Marat Dukhane2c3f292019-11-27 15:40:54 -08001054}
1055
Marat Dukhan5c5fa962020-03-10 18:38:33 -07001056TEST(F32_CLAMP__SCALAR_X1, batch_gt_1) {
1057 for (size_t batch_size = 2; batch_size < 10; batch_size++) {
Marat Dukhane2c3f292019-11-27 15:40:54 -08001058 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -07001059 .batch_size(batch_size)
1060 .Test(xnn_f32_clamp_ukernel__scalar_x1, ClampMicrokernelTester::Variant::Scalar);
Marat Dukhane2c3f292019-11-27 15:40:54 -08001061 }
1062}
1063
Marat Dukhan5c5fa962020-03-10 18:38:33 -07001064TEST(F32_CLAMP__SCALAR_X1, inplace) {
1065 for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) {
Marat Dukhane2c3f292019-11-27 15:40:54 -08001066 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -07001067 .batch_size(batch_size)
Marat Dukhane2c3f292019-11-27 15:40:54 -08001068 .inplace(true)
Marat Dukhan5c5fa962020-03-10 18:38:33 -07001069 .Test(xnn_f32_clamp_ukernel__scalar_x1, ClampMicrokernelTester::Variant::Scalar);
Marat Dukhane2c3f292019-11-27 15:40:54 -08001070 }
1071}
1072
Marat Dukhan5c5fa962020-03-10 18:38:33 -07001073TEST(F32_CLAMP__SCALAR_X1, qmin) {
1074 for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) {
Marat Dukhane2c3f292019-11-27 15:40:54 -08001075 for (uint8_t qmin = 1; qmin < 255; qmin++) {
1076 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -07001077 .batch_size(batch_size)
Marat Dukhane2c3f292019-11-27 15:40:54 -08001078 .qmin(qmin)
1079 .qmax(255)
Marat Dukhan5c5fa962020-03-10 18:38:33 -07001080 .Test(xnn_f32_clamp_ukernel__scalar_x1, ClampMicrokernelTester::Variant::Scalar);
Marat Dukhane2c3f292019-11-27 15:40:54 -08001081 }
1082 }
1083}
1084
Marat Dukhan5c5fa962020-03-10 18:38:33 -07001085TEST(F32_CLAMP__SCALAR_X1, qmax) {
1086 for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) {
Marat Dukhane2c3f292019-11-27 15:40:54 -08001087 for (uint8_t qmax = 1; qmax < 255; qmax++) {
1088 ClampMicrokernelTester()
Marat Dukhan5c5fa962020-03-10 18:38:33 -07001089 .batch_size(batch_size)
Marat Dukhane2c3f292019-11-27 15:40:54 -08001090 .qmin(0)
1091 .qmax(qmax)
Marat Dukhan5c5fa962020-03-10 18:38:33 -07001092 .Test(xnn_f32_clamp_ukernel__scalar_x1, ClampMicrokernelTester::Variant::Scalar);
Marat Dukhane2c3f292019-11-27 15:40:54 -08001093 }
1094 }
1095}
Marat Dukhan5c5fa962020-03-10 18:38:33 -07001096
1097TEST(F32_CLAMP__SCALAR_X2, batch_eq_2) {
1098 ClampMicrokernelTester()
1099 .batch_size(2)
1100 .Test(xnn_f32_clamp_ukernel__scalar_x2, ClampMicrokernelTester::Variant::Scalar);
1101}
1102
1103TEST(F32_CLAMP__SCALAR_X2, batch_div_2) {
1104 for (size_t batch_size = 4; batch_size < 20; batch_size += 2) {
1105 ClampMicrokernelTester()
1106 .batch_size(batch_size)
1107 .Test(xnn_f32_clamp_ukernel__scalar_x2, ClampMicrokernelTester::Variant::Scalar);
1108 }
1109}
1110
1111TEST(F32_CLAMP__SCALAR_X2, batch_lt_2) {
1112 for (size_t batch_size = 1; batch_size < 2; batch_size++) {
1113 ClampMicrokernelTester()
1114 .batch_size(batch_size)
1115 .Test(xnn_f32_clamp_ukernel__scalar_x2, ClampMicrokernelTester::Variant::Scalar);
1116 }
1117}
1118
1119TEST(F32_CLAMP__SCALAR_X2, batch_gt_2) {
1120 for (size_t batch_size = 3; batch_size < 4; batch_size++) {
1121 ClampMicrokernelTester()
1122 .batch_size(batch_size)
1123 .Test(xnn_f32_clamp_ukernel__scalar_x2, ClampMicrokernelTester::Variant::Scalar);
1124 }
1125}
1126
1127TEST(F32_CLAMP__SCALAR_X2, inplace) {
1128 for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) {
1129 ClampMicrokernelTester()
1130 .batch_size(batch_size)
1131 .inplace(true)
1132 .Test(xnn_f32_clamp_ukernel__scalar_x2, ClampMicrokernelTester::Variant::Scalar);
1133 }
1134}
1135
1136TEST(F32_CLAMP__SCALAR_X2, qmin) {
1137 for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) {
1138 for (uint8_t qmin = 1; qmin < 255; qmin++) {
1139 ClampMicrokernelTester()
1140 .batch_size(batch_size)
1141 .qmin(qmin)
1142 .qmax(255)
1143 .Test(xnn_f32_clamp_ukernel__scalar_x2, ClampMicrokernelTester::Variant::Scalar);
1144 }
1145 }
1146}
1147
1148TEST(F32_CLAMP__SCALAR_X2, qmax) {
1149 for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) {
1150 for (uint8_t qmax = 1; qmax < 255; qmax++) {
1151 ClampMicrokernelTester()
1152 .batch_size(batch_size)
1153 .qmin(0)
1154 .qmax(qmax)
1155 .Test(xnn_f32_clamp_ukernel__scalar_x2, ClampMicrokernelTester::Variant::Scalar);
1156 }
1157 }
1158}
1159
1160TEST(F32_CLAMP__SCALAR_X4, batch_eq_4) {
1161 ClampMicrokernelTester()
1162 .batch_size(4)
1163 .Test(xnn_f32_clamp_ukernel__scalar_x4, ClampMicrokernelTester::Variant::Scalar);
1164}
1165
1166TEST(F32_CLAMP__SCALAR_X4, batch_div_4) {
1167 for (size_t batch_size = 8; batch_size < 40; batch_size += 4) {
1168 ClampMicrokernelTester()
1169 .batch_size(batch_size)
1170 .Test(xnn_f32_clamp_ukernel__scalar_x4, ClampMicrokernelTester::Variant::Scalar);
1171 }
1172}
1173
1174TEST(F32_CLAMP__SCALAR_X4, batch_lt_4) {
1175 for (size_t batch_size = 1; batch_size < 4; batch_size++) {
1176 ClampMicrokernelTester()
1177 .batch_size(batch_size)
1178 .Test(xnn_f32_clamp_ukernel__scalar_x4, ClampMicrokernelTester::Variant::Scalar);
1179 }
1180}
1181
1182TEST(F32_CLAMP__SCALAR_X4, batch_gt_4) {
1183 for (size_t batch_size = 5; batch_size < 8; batch_size++) {
1184 ClampMicrokernelTester()
1185 .batch_size(batch_size)
1186 .Test(xnn_f32_clamp_ukernel__scalar_x4, ClampMicrokernelTester::Variant::Scalar);
1187 }
1188}
1189
1190TEST(F32_CLAMP__SCALAR_X4, inplace) {
1191 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
1192 ClampMicrokernelTester()
1193 .batch_size(batch_size)
1194 .inplace(true)
1195 .Test(xnn_f32_clamp_ukernel__scalar_x4, ClampMicrokernelTester::Variant::Scalar);
1196 }
1197}
1198
1199TEST(F32_CLAMP__SCALAR_X4, qmin) {
1200 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
1201 for (uint8_t qmin = 1; qmin < 255; qmin++) {
1202 ClampMicrokernelTester()
1203 .batch_size(batch_size)
1204 .qmin(qmin)
1205 .qmax(255)
1206 .Test(xnn_f32_clamp_ukernel__scalar_x4, ClampMicrokernelTester::Variant::Scalar);
1207 }
1208 }
1209}
1210
1211TEST(F32_CLAMP__SCALAR_X4, qmax) {
1212 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
1213 for (uint8_t qmax = 1; qmax < 255; qmax++) {
1214 ClampMicrokernelTester()
1215 .batch_size(batch_size)
1216 .qmin(0)
1217 .qmax(qmax)
1218 .Test(xnn_f32_clamp_ukernel__scalar_x4, ClampMicrokernelTester::Variant::Scalar);
1219 }
1220 }
1221}