| Marat Dukhan | 1f29b80 | 2020-05-15 23:46:39 -0700 | [diff] [blame] | 1 | // Copyright 2019 Google LLC |
| 2 | // |
| 3 | // This source code is licensed under the BSD-style license found in the |
| 4 | // LICENSE file in the root directory of this source tree. |
| 5 | |
| 6 | #include <gtest/gtest.h> |
| 7 | |
| 8 | #include <xnnpack/common.h> |
| 9 | #include <xnnpack/isa-checks.h> |
| 10 | |
| 11 | #include <xnnpack/gavgpool.h> |
| 12 | #include "gavgpool-cw-microkernel-tester.h" |
| 13 | |
| 14 | |
| 15 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 16 | TEST(F32_GAVGPOOL_CW__NEON_X4, elements_eq_4) { |
| 17 | TEST_REQUIRES_ARM_NEON; |
| 18 | GAvgPoolCWMicrokernelTester() |
| 19 | .elements(4) |
| 20 | .channels(4) |
| 21 | .Test(xnn_f32_gavgpool_cw_ukernel__neon_x4); |
| 22 | } |
| 23 | |
| 24 | TEST(F32_GAVGPOOL_CW__NEON_X4, elements_div_4) { |
| 25 | TEST_REQUIRES_ARM_NEON; |
| 26 | for (size_t elements = 8; elements < 32; elements += 4) { |
| 27 | GAvgPoolCWMicrokernelTester() |
| 28 | .elements(elements) |
| 29 | .channels(4) |
| 30 | .Test(xnn_f32_gavgpool_cw_ukernel__neon_x4); |
| 31 | } |
| 32 | } |
| 33 | |
| 34 | TEST(F32_GAVGPOOL_CW__NEON_X4, elements_lt_4) { |
| 35 | TEST_REQUIRES_ARM_NEON; |
| 36 | for (size_t elements = 1; elements < 4; elements++) { |
| 37 | GAvgPoolCWMicrokernelTester() |
| 38 | .elements(elements) |
| 39 | .channels(4) |
| 40 | .Test(xnn_f32_gavgpool_cw_ukernel__neon_x4); |
| 41 | } |
| 42 | } |
| 43 | |
| 44 | TEST(F32_GAVGPOOL_CW__NEON_X4, elements_gt_4) { |
| 45 | TEST_REQUIRES_ARM_NEON; |
| 46 | for (size_t elements = 5; elements < 8; elements++) { |
| 47 | GAvgPoolCWMicrokernelTester() |
| 48 | .elements(elements) |
| 49 | .channels(4) |
| 50 | .Test(xnn_f32_gavgpool_cw_ukernel__neon_x4); |
| 51 | } |
| 52 | } |
| 53 | |
| 54 | TEST(F32_GAVGPOOL_CW__NEON_X4, channels_lt_4) { |
| 55 | TEST_REQUIRES_ARM_NEON; |
| 56 | for (size_t channels = 1; channels < 4; channels++) { |
| 57 | for (size_t elements = 1; elements < 16; elements += 3) { |
| 58 | GAvgPoolCWMicrokernelTester() |
| 59 | .elements(elements) |
| 60 | .channels(channels) |
| 61 | .Test(xnn_f32_gavgpool_cw_ukernel__neon_x4); |
| 62 | } |
| 63 | } |
| 64 | } |
| 65 | |
| 66 | TEST(F32_GAVGPOOL_CW__NEON_X4, channels_gt_4) { |
| 67 | TEST_REQUIRES_ARM_NEON; |
| 68 | for (size_t channels = 5; channels < 8; channels++) { |
| 69 | for (size_t elements = 1; elements < 16; elements += 3) { |
| 70 | GAvgPoolCWMicrokernelTester() |
| 71 | .elements(elements) |
| 72 | .channels(channels) |
| 73 | .Test(xnn_f32_gavgpool_cw_ukernel__neon_x4); |
| 74 | } |
| 75 | } |
| 76 | } |
| 77 | |
| 78 | TEST(F32_GAVGPOOL_CW__NEON_X4, channels_div_4) { |
| 79 | TEST_REQUIRES_ARM_NEON; |
| 80 | for (size_t channels = 8; channels <= 16; channels += 4) { |
| 81 | for (size_t elements = 1; elements < 16; elements += 3) { |
| 82 | GAvgPoolCWMicrokernelTester() |
| 83 | .elements(elements) |
| 84 | .channels(channels) |
| 85 | .Test(xnn_f32_gavgpool_cw_ukernel__neon_x4); |
| 86 | } |
| 87 | } |
| 88 | } |
| 89 | |
| 90 | TEST(F32_GAVGPOOL_CW__NEON_X4, qmin) { |
| 91 | TEST_REQUIRES_ARM_NEON; |
| 92 | for (size_t elements = 1; elements < 16; elements += 3) { |
| 93 | GAvgPoolCWMicrokernelTester() |
| 94 | .elements(elements) |
| 95 | .channels(4) |
| 96 | .qmin(128) |
| 97 | .Test(xnn_f32_gavgpool_cw_ukernel__neon_x4); |
| 98 | } |
| 99 | } |
| 100 | |
| 101 | TEST(F32_GAVGPOOL_CW__NEON_X4, qmax) { |
| 102 | TEST_REQUIRES_ARM_NEON; |
| 103 | for (size_t elements = 1; elements < 16; elements += 3) { |
| 104 | GAvgPoolCWMicrokernelTester() |
| 105 | .elements(elements) |
| 106 | .channels(4) |
| 107 | .qmax(128) |
| 108 | .Test(xnn_f32_gavgpool_cw_ukernel__neon_x4); |
| 109 | } |
| 110 | } |
| 111 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 112 | |
| 113 | |
| 114 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 115 | TEST(F32_GAVGPOOL_CW__SSE_X4, elements_eq_4) { |
| 116 | TEST_REQUIRES_X86_SSE; |
| 117 | GAvgPoolCWMicrokernelTester() |
| 118 | .elements(4) |
| 119 | .channels(4) |
| 120 | .Test(xnn_f32_gavgpool_cw_ukernel__sse_x4); |
| 121 | } |
| 122 | |
| 123 | TEST(F32_GAVGPOOL_CW__SSE_X4, elements_div_4) { |
| 124 | TEST_REQUIRES_X86_SSE; |
| 125 | for (size_t elements = 8; elements < 32; elements += 4) { |
| 126 | GAvgPoolCWMicrokernelTester() |
| 127 | .elements(elements) |
| 128 | .channels(4) |
| 129 | .Test(xnn_f32_gavgpool_cw_ukernel__sse_x4); |
| 130 | } |
| 131 | } |
| 132 | |
| 133 | TEST(F32_GAVGPOOL_CW__SSE_X4, elements_lt_4) { |
| 134 | TEST_REQUIRES_X86_SSE; |
| 135 | for (size_t elements = 1; elements < 4; elements++) { |
| 136 | GAvgPoolCWMicrokernelTester() |
| 137 | .elements(elements) |
| 138 | .channels(4) |
| 139 | .Test(xnn_f32_gavgpool_cw_ukernel__sse_x4); |
| 140 | } |
| 141 | } |
| 142 | |
| 143 | TEST(F32_GAVGPOOL_CW__SSE_X4, elements_gt_4) { |
| 144 | TEST_REQUIRES_X86_SSE; |
| 145 | for (size_t elements = 5; elements < 8; elements++) { |
| 146 | GAvgPoolCWMicrokernelTester() |
| 147 | .elements(elements) |
| 148 | .channels(4) |
| 149 | .Test(xnn_f32_gavgpool_cw_ukernel__sse_x4); |
| 150 | } |
| 151 | } |
| 152 | |
| 153 | TEST(F32_GAVGPOOL_CW__SSE_X4, channels_lt_4) { |
| 154 | TEST_REQUIRES_X86_SSE; |
| 155 | for (size_t channels = 1; channels < 4; channels++) { |
| 156 | for (size_t elements = 1; elements < 16; elements += 3) { |
| 157 | GAvgPoolCWMicrokernelTester() |
| 158 | .elements(elements) |
| 159 | .channels(channels) |
| 160 | .Test(xnn_f32_gavgpool_cw_ukernel__sse_x4); |
| 161 | } |
| 162 | } |
| 163 | } |
| 164 | |
| 165 | TEST(F32_GAVGPOOL_CW__SSE_X4, channels_gt_4) { |
| 166 | TEST_REQUIRES_X86_SSE; |
| 167 | for (size_t channels = 5; channels < 8; channels++) { |
| 168 | for (size_t elements = 1; elements < 16; elements += 3) { |
| 169 | GAvgPoolCWMicrokernelTester() |
| 170 | .elements(elements) |
| 171 | .channels(channels) |
| 172 | .Test(xnn_f32_gavgpool_cw_ukernel__sse_x4); |
| 173 | } |
| 174 | } |
| 175 | } |
| 176 | |
| 177 | TEST(F32_GAVGPOOL_CW__SSE_X4, channels_div_4) { |
| 178 | TEST_REQUIRES_X86_SSE; |
| 179 | for (size_t channels = 8; channels <= 16; channels += 4) { |
| 180 | for (size_t elements = 1; elements < 16; elements += 3) { |
| 181 | GAvgPoolCWMicrokernelTester() |
| 182 | .elements(elements) |
| 183 | .channels(channels) |
| 184 | .Test(xnn_f32_gavgpool_cw_ukernel__sse_x4); |
| 185 | } |
| 186 | } |
| 187 | } |
| 188 | |
| 189 | TEST(F32_GAVGPOOL_CW__SSE_X4, qmin) { |
| 190 | TEST_REQUIRES_X86_SSE; |
| 191 | for (size_t elements = 1; elements < 16; elements += 3) { |
| 192 | GAvgPoolCWMicrokernelTester() |
| 193 | .elements(elements) |
| 194 | .channels(4) |
| 195 | .qmin(128) |
| 196 | .Test(xnn_f32_gavgpool_cw_ukernel__sse_x4); |
| 197 | } |
| 198 | } |
| 199 | |
| 200 | TEST(F32_GAVGPOOL_CW__SSE_X4, qmax) { |
| 201 | TEST_REQUIRES_X86_SSE; |
| 202 | for (size_t elements = 1; elements < 16; elements += 3) { |
| 203 | GAvgPoolCWMicrokernelTester() |
| 204 | .elements(elements) |
| 205 | .channels(4) |
| 206 | .qmax(128) |
| 207 | .Test(xnn_f32_gavgpool_cw_ukernel__sse_x4); |
| 208 | } |
| 209 | } |
| 210 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 211 | |
| Marat Dukhan | 1849351 | 2020-07-24 14:13:48 -0700 | [diff] [blame] | 212 | #if XNN_ARCH_WASMSIMD |
| 213 | TEST(F32_GAVGPOOL_CW__WASMSIMD_ARM_X4, elements_eq_4) { |
| 214 | GAvgPoolCWMicrokernelTester() |
| 215 | .elements(4) |
| 216 | .channels(4) |
| 217 | .Test(xnn_f32_gavgpool_cw_ukernel__wasmsimd_arm_x4); |
| 218 | } |
| 219 | |
| 220 | TEST(F32_GAVGPOOL_CW__WASMSIMD_ARM_X4, elements_div_4) { |
| 221 | for (size_t elements = 8; elements < 32; elements += 4) { |
| 222 | GAvgPoolCWMicrokernelTester() |
| 223 | .elements(elements) |
| 224 | .channels(4) |
| 225 | .Test(xnn_f32_gavgpool_cw_ukernel__wasmsimd_arm_x4); |
| 226 | } |
| 227 | } |
| 228 | |
| 229 | TEST(F32_GAVGPOOL_CW__WASMSIMD_ARM_X4, elements_lt_4) { |
| 230 | for (size_t elements = 1; elements < 4; elements++) { |
| 231 | GAvgPoolCWMicrokernelTester() |
| 232 | .elements(elements) |
| 233 | .channels(4) |
| 234 | .Test(xnn_f32_gavgpool_cw_ukernel__wasmsimd_arm_x4); |
| 235 | } |
| 236 | } |
| 237 | |
| 238 | TEST(F32_GAVGPOOL_CW__WASMSIMD_ARM_X4, elements_gt_4) { |
| 239 | for (size_t elements = 5; elements < 8; elements++) { |
| 240 | GAvgPoolCWMicrokernelTester() |
| 241 | .elements(elements) |
| 242 | .channels(4) |
| 243 | .Test(xnn_f32_gavgpool_cw_ukernel__wasmsimd_arm_x4); |
| 244 | } |
| 245 | } |
| 246 | |
| 247 | TEST(F32_GAVGPOOL_CW__WASMSIMD_ARM_X4, channels_lt_4) { |
| 248 | for (size_t channels = 1; channels < 4; channels++) { |
| 249 | for (size_t elements = 1; elements < 16; elements += 3) { |
| 250 | GAvgPoolCWMicrokernelTester() |
| 251 | .elements(elements) |
| 252 | .channels(channels) |
| 253 | .Test(xnn_f32_gavgpool_cw_ukernel__wasmsimd_arm_x4); |
| 254 | } |
| 255 | } |
| 256 | } |
| 257 | |
| 258 | TEST(F32_GAVGPOOL_CW__WASMSIMD_ARM_X4, channels_gt_4) { |
| 259 | for (size_t channels = 5; channels < 8; channels++) { |
| 260 | for (size_t elements = 1; elements < 16; elements += 3) { |
| 261 | GAvgPoolCWMicrokernelTester() |
| 262 | .elements(elements) |
| 263 | .channels(channels) |
| 264 | .Test(xnn_f32_gavgpool_cw_ukernel__wasmsimd_arm_x4); |
| 265 | } |
| 266 | } |
| 267 | } |
| 268 | |
| 269 | TEST(F32_GAVGPOOL_CW__WASMSIMD_ARM_X4, channels_div_4) { |
| 270 | for (size_t channels = 8; channels <= 16; channels += 4) { |
| 271 | for (size_t elements = 1; elements < 16; elements += 3) { |
| 272 | GAvgPoolCWMicrokernelTester() |
| 273 | .elements(elements) |
| 274 | .channels(channels) |
| 275 | .Test(xnn_f32_gavgpool_cw_ukernel__wasmsimd_arm_x4); |
| 276 | } |
| 277 | } |
| 278 | } |
| 279 | |
| 280 | TEST(F32_GAVGPOOL_CW__WASMSIMD_ARM_X4, qmin) { |
| 281 | for (size_t elements = 1; elements < 16; elements += 3) { |
| 282 | GAvgPoolCWMicrokernelTester() |
| 283 | .elements(elements) |
| 284 | .channels(4) |
| 285 | .qmin(128) |
| 286 | .Test(xnn_f32_gavgpool_cw_ukernel__wasmsimd_arm_x4); |
| 287 | } |
| 288 | } |
| 289 | |
| 290 | TEST(F32_GAVGPOOL_CW__WASMSIMD_ARM_X4, qmax) { |
| 291 | for (size_t elements = 1; elements < 16; elements += 3) { |
| 292 | GAvgPoolCWMicrokernelTester() |
| 293 | .elements(elements) |
| 294 | .channels(4) |
| 295 | .qmax(128) |
| 296 | .Test(xnn_f32_gavgpool_cw_ukernel__wasmsimd_arm_x4); |
| 297 | } |
| 298 | } |
| 299 | #endif // XNN_ARCH_WASMSIMD |
| 300 | |
| 301 | #if XNN_ARCH_WASMSIMD |
| 302 | TEST(F32_GAVGPOOL_CW__WASMSIMD_X86_X4, elements_eq_4) { |
| 303 | GAvgPoolCWMicrokernelTester() |
| 304 | .elements(4) |
| 305 | .channels(4) |
| 306 | .Test(xnn_f32_gavgpool_cw_ukernel__wasmsimd_x86_x4); |
| 307 | } |
| 308 | |
| 309 | TEST(F32_GAVGPOOL_CW__WASMSIMD_X86_X4, elements_div_4) { |
| 310 | for (size_t elements = 8; elements < 32; elements += 4) { |
| 311 | GAvgPoolCWMicrokernelTester() |
| 312 | .elements(elements) |
| 313 | .channels(4) |
| 314 | .Test(xnn_f32_gavgpool_cw_ukernel__wasmsimd_x86_x4); |
| 315 | } |
| 316 | } |
| 317 | |
| 318 | TEST(F32_GAVGPOOL_CW__WASMSIMD_X86_X4, elements_lt_4) { |
| 319 | for (size_t elements = 1; elements < 4; elements++) { |
| 320 | GAvgPoolCWMicrokernelTester() |
| 321 | .elements(elements) |
| 322 | .channels(4) |
| 323 | .Test(xnn_f32_gavgpool_cw_ukernel__wasmsimd_x86_x4); |
| 324 | } |
| 325 | } |
| 326 | |
| 327 | TEST(F32_GAVGPOOL_CW__WASMSIMD_X86_X4, elements_gt_4) { |
| 328 | for (size_t elements = 5; elements < 8; elements++) { |
| 329 | GAvgPoolCWMicrokernelTester() |
| 330 | .elements(elements) |
| 331 | .channels(4) |
| 332 | .Test(xnn_f32_gavgpool_cw_ukernel__wasmsimd_x86_x4); |
| 333 | } |
| 334 | } |
| 335 | |
| 336 | TEST(F32_GAVGPOOL_CW__WASMSIMD_X86_X4, channels_lt_4) { |
| 337 | for (size_t channels = 1; channels < 4; channels++) { |
| 338 | for (size_t elements = 1; elements < 16; elements += 3) { |
| 339 | GAvgPoolCWMicrokernelTester() |
| 340 | .elements(elements) |
| 341 | .channels(channels) |
| 342 | .Test(xnn_f32_gavgpool_cw_ukernel__wasmsimd_x86_x4); |
| 343 | } |
| 344 | } |
| 345 | } |
| 346 | |
| 347 | TEST(F32_GAVGPOOL_CW__WASMSIMD_X86_X4, channels_gt_4) { |
| 348 | for (size_t channels = 5; channels < 8; channels++) { |
| 349 | for (size_t elements = 1; elements < 16; elements += 3) { |
| 350 | GAvgPoolCWMicrokernelTester() |
| 351 | .elements(elements) |
| 352 | .channels(channels) |
| 353 | .Test(xnn_f32_gavgpool_cw_ukernel__wasmsimd_x86_x4); |
| 354 | } |
| 355 | } |
| 356 | } |
| 357 | |
| 358 | TEST(F32_GAVGPOOL_CW__WASMSIMD_X86_X4, channels_div_4) { |
| 359 | for (size_t channels = 8; channels <= 16; channels += 4) { |
| 360 | for (size_t elements = 1; elements < 16; elements += 3) { |
| 361 | GAvgPoolCWMicrokernelTester() |
| 362 | .elements(elements) |
| 363 | .channels(channels) |
| 364 | .Test(xnn_f32_gavgpool_cw_ukernel__wasmsimd_x86_x4); |
| 365 | } |
| 366 | } |
| 367 | } |
| 368 | |
| 369 | TEST(F32_GAVGPOOL_CW__WASMSIMD_X86_X4, qmin) { |
| 370 | for (size_t elements = 1; elements < 16; elements += 3) { |
| 371 | GAvgPoolCWMicrokernelTester() |
| 372 | .elements(elements) |
| 373 | .channels(4) |
| 374 | .qmin(128) |
| 375 | .Test(xnn_f32_gavgpool_cw_ukernel__wasmsimd_x86_x4); |
| 376 | } |
| 377 | } |
| 378 | |
| 379 | TEST(F32_GAVGPOOL_CW__WASMSIMD_X86_X4, qmax) { |
| 380 | for (size_t elements = 1; elements < 16; elements += 3) { |
| 381 | GAvgPoolCWMicrokernelTester() |
| 382 | .elements(elements) |
| 383 | .channels(4) |
| 384 | .qmax(128) |
| 385 | .Test(xnn_f32_gavgpool_cw_ukernel__wasmsimd_x86_x4); |
| 386 | } |
| 387 | } |
| 388 | #endif // XNN_ARCH_WASMSIMD |
| 389 | |
| Marat Dukhan | 1f29b80 | 2020-05-15 23:46:39 -0700 | [diff] [blame] | 390 | TEST(F32_GAVGPOOL_CW__SCALAR_X1, elements_eq_4) { |
| 391 | GAvgPoolCWMicrokernelTester() |
| 392 | .elements(4) |
| 393 | .channels(1) |
| 394 | .Test(xnn_f32_gavgpool_cw_ukernel__scalar_x1, GAvgPoolCWMicrokernelTester::Variant::Scalar); |
| 395 | } |
| 396 | |
| 397 | TEST(F32_GAVGPOOL_CW__SCALAR_X1, elements_div_4) { |
| 398 | for (size_t elements = 8; elements < 32; elements += 4) { |
| 399 | GAvgPoolCWMicrokernelTester() |
| 400 | .elements(elements) |
| 401 | .channels(1) |
| 402 | .Test(xnn_f32_gavgpool_cw_ukernel__scalar_x1, GAvgPoolCWMicrokernelTester::Variant::Scalar); |
| 403 | } |
| 404 | } |
| 405 | |
| 406 | TEST(F32_GAVGPOOL_CW__SCALAR_X1, elements_lt_4) { |
| 407 | for (size_t elements = 1; elements < 4; elements++) { |
| 408 | GAvgPoolCWMicrokernelTester() |
| 409 | .elements(elements) |
| 410 | .channels(1) |
| 411 | .Test(xnn_f32_gavgpool_cw_ukernel__scalar_x1, GAvgPoolCWMicrokernelTester::Variant::Scalar); |
| 412 | } |
| 413 | } |
| 414 | |
| 415 | TEST(F32_GAVGPOOL_CW__SCALAR_X1, elements_gt_4) { |
| 416 | for (size_t elements = 5; elements < 8; elements++) { |
| 417 | GAvgPoolCWMicrokernelTester() |
| 418 | .elements(elements) |
| 419 | .channels(1) |
| 420 | .Test(xnn_f32_gavgpool_cw_ukernel__scalar_x1, GAvgPoolCWMicrokernelTester::Variant::Scalar); |
| 421 | } |
| 422 | } |
| 423 | |
| 424 | TEST(F32_GAVGPOOL_CW__SCALAR_X1, channels_gt_1) { |
| 425 | for (size_t channels = 2; channels < 5; channels++) { |
| 426 | for (size_t elements = 1; elements < 16; elements += 3) { |
| 427 | GAvgPoolCWMicrokernelTester() |
| 428 | .elements(elements) |
| 429 | .channels(channels) |
| 430 | .Test(xnn_f32_gavgpool_cw_ukernel__scalar_x1, GAvgPoolCWMicrokernelTester::Variant::Scalar); |
| 431 | } |
| 432 | } |
| 433 | } |
| 434 | |
| 435 | TEST(F32_GAVGPOOL_CW__SCALAR_X1, qmin) { |
| 436 | for (size_t elements = 1; elements < 16; elements += 3) { |
| 437 | GAvgPoolCWMicrokernelTester() |
| 438 | .elements(elements) |
| 439 | .channels(4) |
| 440 | .qmin(128) |
| 441 | .Test(xnn_f32_gavgpool_cw_ukernel__scalar_x1, GAvgPoolCWMicrokernelTester::Variant::Scalar); |
| 442 | } |
| 443 | } |
| 444 | |
| 445 | TEST(F32_GAVGPOOL_CW__SCALAR_X1, qmax) { |
| 446 | for (size_t elements = 1; elements < 16; elements += 3) { |
| 447 | GAvgPoolCWMicrokernelTester() |
| 448 | .elements(elements) |
| 449 | .channels(4) |
| 450 | .qmax(128) |
| 451 | .Test(xnn_f32_gavgpool_cw_ukernel__scalar_x1, GAvgPoolCWMicrokernelTester::Variant::Scalar); |
| 452 | } |
| 453 | } |