| Marat Dukhan | 9757953 | 2019-10-18 16:40:39 -0700 | [diff] [blame] | 1 | // Copyright 2019 Google LLC |
| 2 | // |
| 3 | // This source code is licensed under the BSD-style license found in the |
| 4 | // LICENSE file in the root directory of this source tree. |
| Marat Dukhan | 4c4eb00 | 2019-12-08 21:27:49 -0800 | [diff] [blame] | 5 | // |
| 6 | // Auto-generated file. Do not edit! |
| 7 | // Specification: test/f32-raddstoreexpminusmax.yaml |
| 8 | // Generator: tools/generate-raddstoreexpminusmax-test.py |
| 9 | |
| Marat Dukhan | 9757953 | 2019-10-18 16:40:39 -0700 | [diff] [blame] | 10 | |
| 11 | #include <gtest/gtest.h> |
| 12 | |
| 13 | #include <xnnpack/common.h> |
| 14 | #include <xnnpack/isa-checks.h> |
| 15 | |
| 16 | #include <xnnpack/raddstoreexpminusmax.h> |
| 17 | #include "raddstoreexpminusmax-microkernel-tester.h" |
| 18 | |
| 19 | |
| Marat Dukhan | 8137e4c | 2020-01-25 12:56:58 -0800 | [diff] [blame] | 20 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 21 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X4, elements_eq_4) { |
| 22 | TEST_REQUIRES_ARM_NEON; |
| 23 | RAddStoreExpMinusMaxMicrokernelTester() |
| 24 | .elements(4) |
| 25 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x4); |
| 26 | } |
| 27 | |
| 28 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X4, elements_div_4) { |
| 29 | TEST_REQUIRES_ARM_NEON; |
| 30 | for (size_t elements = 8; elements < 40; elements += 4) { |
| 31 | RAddStoreExpMinusMaxMicrokernelTester() |
| 32 | .elements(elements) |
| 33 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x4); |
| 34 | } |
| 35 | } |
| 36 | |
| 37 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X4, elements_lt_4) { |
| 38 | TEST_REQUIRES_ARM_NEON; |
| 39 | for (size_t elements = 1; elements < 4; elements++) { |
| 40 | RAddStoreExpMinusMaxMicrokernelTester() |
| 41 | .elements(elements) |
| 42 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x4); |
| 43 | } |
| 44 | } |
| 45 | |
| 46 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X4, elements_gt_4) { |
| 47 | TEST_REQUIRES_ARM_NEON; |
| 48 | for (size_t elements = 5; elements < 8; elements++) { |
| 49 | RAddStoreExpMinusMaxMicrokernelTester() |
| 50 | .elements(elements) |
| 51 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x4); |
| 52 | } |
| 53 | } |
| 54 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 55 | |
| 56 | |
| 57 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 58 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X8, elements_eq_8) { |
| 59 | TEST_REQUIRES_ARM_NEON; |
| 60 | RAddStoreExpMinusMaxMicrokernelTester() |
| 61 | .elements(8) |
| 62 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x8); |
| 63 | } |
| 64 | |
| 65 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X8, elements_div_8) { |
| 66 | TEST_REQUIRES_ARM_NEON; |
| 67 | for (size_t elements = 16; elements < 80; elements += 8) { |
| 68 | RAddStoreExpMinusMaxMicrokernelTester() |
| 69 | .elements(elements) |
| 70 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x8); |
| 71 | } |
| 72 | } |
| 73 | |
| 74 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X8, elements_lt_8) { |
| 75 | TEST_REQUIRES_ARM_NEON; |
| 76 | for (size_t elements = 1; elements < 8; elements++) { |
| 77 | RAddStoreExpMinusMaxMicrokernelTester() |
| 78 | .elements(elements) |
| 79 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x8); |
| 80 | } |
| 81 | } |
| 82 | |
| 83 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X8, elements_gt_8) { |
| 84 | TEST_REQUIRES_ARM_NEON; |
| 85 | for (size_t elements = 9; elements < 16; elements++) { |
| 86 | RAddStoreExpMinusMaxMicrokernelTester() |
| 87 | .elements(elements) |
| 88 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x8); |
| 89 | } |
| 90 | } |
| 91 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 92 | |
| 93 | |
| 94 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 95 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X8_ACC2, elements_eq_8) { |
| 96 | TEST_REQUIRES_ARM_NEON; |
| 97 | RAddStoreExpMinusMaxMicrokernelTester() |
| 98 | .elements(8) |
| 99 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x8_acc2); |
| 100 | } |
| 101 | |
| 102 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X8_ACC2, elements_div_8) { |
| 103 | TEST_REQUIRES_ARM_NEON; |
| 104 | for (size_t elements = 16; elements < 80; elements += 8) { |
| 105 | RAddStoreExpMinusMaxMicrokernelTester() |
| 106 | .elements(elements) |
| 107 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x8_acc2); |
| 108 | } |
| 109 | } |
| 110 | |
| 111 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X8_ACC2, elements_lt_8) { |
| 112 | TEST_REQUIRES_ARM_NEON; |
| 113 | for (size_t elements = 1; elements < 8; elements++) { |
| 114 | RAddStoreExpMinusMaxMicrokernelTester() |
| 115 | .elements(elements) |
| 116 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x8_acc2); |
| 117 | } |
| 118 | } |
| 119 | |
| 120 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X8_ACC2, elements_gt_8) { |
| 121 | TEST_REQUIRES_ARM_NEON; |
| 122 | for (size_t elements = 9; elements < 16; elements++) { |
| 123 | RAddStoreExpMinusMaxMicrokernelTester() |
| 124 | .elements(elements) |
| 125 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x8_acc2); |
| 126 | } |
| 127 | } |
| 128 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 129 | |
| 130 | |
| 131 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 132 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X12, elements_eq_12) { |
| 133 | TEST_REQUIRES_ARM_NEON; |
| 134 | RAddStoreExpMinusMaxMicrokernelTester() |
| 135 | .elements(12) |
| 136 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x12); |
| 137 | } |
| 138 | |
| 139 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X12, elements_div_12) { |
| 140 | TEST_REQUIRES_ARM_NEON; |
| 141 | for (size_t elements = 24; elements < 120; elements += 12) { |
| 142 | RAddStoreExpMinusMaxMicrokernelTester() |
| 143 | .elements(elements) |
| 144 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x12); |
| 145 | } |
| 146 | } |
| 147 | |
| 148 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X12, elements_lt_12) { |
| 149 | TEST_REQUIRES_ARM_NEON; |
| 150 | for (size_t elements = 1; elements < 12; elements++) { |
| 151 | RAddStoreExpMinusMaxMicrokernelTester() |
| 152 | .elements(elements) |
| 153 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x12); |
| 154 | } |
| 155 | } |
| 156 | |
| 157 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X12, elements_gt_12) { |
| 158 | TEST_REQUIRES_ARM_NEON; |
| 159 | for (size_t elements = 13; elements < 24; elements++) { |
| 160 | RAddStoreExpMinusMaxMicrokernelTester() |
| 161 | .elements(elements) |
| 162 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x12); |
| 163 | } |
| 164 | } |
| 165 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 166 | |
| 167 | |
| 168 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 169 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X12_ACC2, elements_eq_12) { |
| 170 | TEST_REQUIRES_ARM_NEON; |
| 171 | RAddStoreExpMinusMaxMicrokernelTester() |
| 172 | .elements(12) |
| 173 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x12_acc2); |
| 174 | } |
| 175 | |
| 176 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X12_ACC2, elements_div_12) { |
| 177 | TEST_REQUIRES_ARM_NEON; |
| 178 | for (size_t elements = 24; elements < 120; elements += 12) { |
| 179 | RAddStoreExpMinusMaxMicrokernelTester() |
| 180 | .elements(elements) |
| 181 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x12_acc2); |
| 182 | } |
| 183 | } |
| 184 | |
| 185 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X12_ACC2, elements_lt_12) { |
| 186 | TEST_REQUIRES_ARM_NEON; |
| 187 | for (size_t elements = 1; elements < 12; elements++) { |
| 188 | RAddStoreExpMinusMaxMicrokernelTester() |
| 189 | .elements(elements) |
| 190 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x12_acc2); |
| 191 | } |
| 192 | } |
| 193 | |
| 194 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X12_ACC2, elements_gt_12) { |
| 195 | TEST_REQUIRES_ARM_NEON; |
| 196 | for (size_t elements = 13; elements < 24; elements++) { |
| 197 | RAddStoreExpMinusMaxMicrokernelTester() |
| 198 | .elements(elements) |
| 199 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x12_acc2); |
| 200 | } |
| 201 | } |
| 202 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 203 | |
| 204 | |
| 205 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 206 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X12_ACC3, elements_eq_12) { |
| 207 | TEST_REQUIRES_ARM_NEON; |
| 208 | RAddStoreExpMinusMaxMicrokernelTester() |
| 209 | .elements(12) |
| 210 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x12_acc3); |
| 211 | } |
| 212 | |
| 213 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X12_ACC3, elements_div_12) { |
| 214 | TEST_REQUIRES_ARM_NEON; |
| 215 | for (size_t elements = 24; elements < 120; elements += 12) { |
| 216 | RAddStoreExpMinusMaxMicrokernelTester() |
| 217 | .elements(elements) |
| 218 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x12_acc3); |
| 219 | } |
| 220 | } |
| 221 | |
| 222 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X12_ACC3, elements_lt_12) { |
| 223 | TEST_REQUIRES_ARM_NEON; |
| 224 | for (size_t elements = 1; elements < 12; elements++) { |
| 225 | RAddStoreExpMinusMaxMicrokernelTester() |
| 226 | .elements(elements) |
| 227 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x12_acc3); |
| 228 | } |
| 229 | } |
| 230 | |
| 231 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X12_ACC3, elements_gt_12) { |
| 232 | TEST_REQUIRES_ARM_NEON; |
| 233 | for (size_t elements = 13; elements < 24; elements++) { |
| 234 | RAddStoreExpMinusMaxMicrokernelTester() |
| 235 | .elements(elements) |
| 236 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x12_acc3); |
| 237 | } |
| 238 | } |
| 239 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 240 | |
| 241 | |
| 242 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 243 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X16, elements_eq_16) { |
| 244 | TEST_REQUIRES_ARM_NEON; |
| 245 | RAddStoreExpMinusMaxMicrokernelTester() |
| 246 | .elements(16) |
| 247 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x16); |
| 248 | } |
| 249 | |
| 250 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X16, elements_div_16) { |
| 251 | TEST_REQUIRES_ARM_NEON; |
| 252 | for (size_t elements = 32; elements < 160; elements += 16) { |
| 253 | RAddStoreExpMinusMaxMicrokernelTester() |
| 254 | .elements(elements) |
| 255 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x16); |
| 256 | } |
| 257 | } |
| 258 | |
| 259 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X16, elements_lt_16) { |
| 260 | TEST_REQUIRES_ARM_NEON; |
| 261 | for (size_t elements = 1; elements < 16; elements++) { |
| 262 | RAddStoreExpMinusMaxMicrokernelTester() |
| 263 | .elements(elements) |
| 264 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x16); |
| 265 | } |
| 266 | } |
| 267 | |
| 268 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X16, elements_gt_16) { |
| 269 | TEST_REQUIRES_ARM_NEON; |
| 270 | for (size_t elements = 17; elements < 32; elements++) { |
| 271 | RAddStoreExpMinusMaxMicrokernelTester() |
| 272 | .elements(elements) |
| 273 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x16); |
| 274 | } |
| 275 | } |
| 276 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 277 | |
| 278 | |
| 279 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 280 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X16_ACC2, elements_eq_16) { |
| 281 | TEST_REQUIRES_ARM_NEON; |
| 282 | RAddStoreExpMinusMaxMicrokernelTester() |
| 283 | .elements(16) |
| 284 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x16_acc2); |
| 285 | } |
| 286 | |
| 287 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X16_ACC2, elements_div_16) { |
| 288 | TEST_REQUIRES_ARM_NEON; |
| 289 | for (size_t elements = 32; elements < 160; elements += 16) { |
| 290 | RAddStoreExpMinusMaxMicrokernelTester() |
| 291 | .elements(elements) |
| 292 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x16_acc2); |
| 293 | } |
| 294 | } |
| 295 | |
| 296 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X16_ACC2, elements_lt_16) { |
| 297 | TEST_REQUIRES_ARM_NEON; |
| 298 | for (size_t elements = 1; elements < 16; elements++) { |
| 299 | RAddStoreExpMinusMaxMicrokernelTester() |
| 300 | .elements(elements) |
| 301 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x16_acc2); |
| 302 | } |
| 303 | } |
| 304 | |
| 305 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X16_ACC2, elements_gt_16) { |
| 306 | TEST_REQUIRES_ARM_NEON; |
| 307 | for (size_t elements = 17; elements < 32; elements++) { |
| 308 | RAddStoreExpMinusMaxMicrokernelTester() |
| 309 | .elements(elements) |
| 310 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x16_acc2); |
| 311 | } |
| 312 | } |
| 313 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 314 | |
| 315 | |
| 316 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 317 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X16_ACC4, elements_eq_16) { |
| 318 | TEST_REQUIRES_ARM_NEON; |
| 319 | RAddStoreExpMinusMaxMicrokernelTester() |
| 320 | .elements(16) |
| 321 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x16_acc4); |
| 322 | } |
| 323 | |
| 324 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X16_ACC4, elements_div_16) { |
| 325 | TEST_REQUIRES_ARM_NEON; |
| 326 | for (size_t elements = 32; elements < 160; elements += 16) { |
| 327 | RAddStoreExpMinusMaxMicrokernelTester() |
| 328 | .elements(elements) |
| 329 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x16_acc4); |
| 330 | } |
| 331 | } |
| 332 | |
| 333 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X16_ACC4, elements_lt_16) { |
| 334 | TEST_REQUIRES_ARM_NEON; |
| 335 | for (size_t elements = 1; elements < 16; elements++) { |
| 336 | RAddStoreExpMinusMaxMicrokernelTester() |
| 337 | .elements(elements) |
| 338 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x16_acc4); |
| 339 | } |
| 340 | } |
| 341 | |
| 342 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X16_ACC4, elements_gt_16) { |
| 343 | TEST_REQUIRES_ARM_NEON; |
| 344 | for (size_t elements = 17; elements < 32; elements++) { |
| 345 | RAddStoreExpMinusMaxMicrokernelTester() |
| 346 | .elements(elements) |
| 347 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x16_acc4); |
| 348 | } |
| 349 | } |
| 350 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 351 | |
| 352 | |
| 353 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 354 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X20, elements_eq_20) { |
| 355 | TEST_REQUIRES_ARM_NEON; |
| 356 | RAddStoreExpMinusMaxMicrokernelTester() |
| 357 | .elements(20) |
| 358 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x20); |
| 359 | } |
| 360 | |
| 361 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X20, elements_div_20) { |
| 362 | TEST_REQUIRES_ARM_NEON; |
| 363 | for (size_t elements = 40; elements < 200; elements += 20) { |
| 364 | RAddStoreExpMinusMaxMicrokernelTester() |
| 365 | .elements(elements) |
| 366 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x20); |
| 367 | } |
| 368 | } |
| 369 | |
| 370 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X20, elements_lt_20) { |
| 371 | TEST_REQUIRES_ARM_NEON; |
| 372 | for (size_t elements = 1; elements < 20; elements++) { |
| 373 | RAddStoreExpMinusMaxMicrokernelTester() |
| 374 | .elements(elements) |
| 375 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x20); |
| 376 | } |
| 377 | } |
| 378 | |
| 379 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X20, elements_gt_20) { |
| 380 | TEST_REQUIRES_ARM_NEON; |
| 381 | for (size_t elements = 21; elements < 40; elements++) { |
| 382 | RAddStoreExpMinusMaxMicrokernelTester() |
| 383 | .elements(elements) |
| 384 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x20); |
| 385 | } |
| 386 | } |
| 387 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 388 | |
| 389 | |
| 390 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 391 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X20_ACC2, elements_eq_20) { |
| 392 | TEST_REQUIRES_ARM_NEON; |
| 393 | RAddStoreExpMinusMaxMicrokernelTester() |
| 394 | .elements(20) |
| 395 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x20_acc2); |
| 396 | } |
| 397 | |
| 398 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X20_ACC2, elements_div_20) { |
| 399 | TEST_REQUIRES_ARM_NEON; |
| 400 | for (size_t elements = 40; elements < 200; elements += 20) { |
| 401 | RAddStoreExpMinusMaxMicrokernelTester() |
| 402 | .elements(elements) |
| 403 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x20_acc2); |
| 404 | } |
| 405 | } |
| 406 | |
| 407 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X20_ACC2, elements_lt_20) { |
| 408 | TEST_REQUIRES_ARM_NEON; |
| 409 | for (size_t elements = 1; elements < 20; elements++) { |
| 410 | RAddStoreExpMinusMaxMicrokernelTester() |
| 411 | .elements(elements) |
| 412 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x20_acc2); |
| 413 | } |
| 414 | } |
| 415 | |
| 416 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X20_ACC2, elements_gt_20) { |
| 417 | TEST_REQUIRES_ARM_NEON; |
| 418 | for (size_t elements = 21; elements < 40; elements++) { |
| 419 | RAddStoreExpMinusMaxMicrokernelTester() |
| 420 | .elements(elements) |
| 421 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x20_acc2); |
| 422 | } |
| 423 | } |
| 424 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 425 | |
| 426 | |
| 427 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 428 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X20_ACC5, elements_eq_20) { |
| 429 | TEST_REQUIRES_ARM_NEON; |
| 430 | RAddStoreExpMinusMaxMicrokernelTester() |
| 431 | .elements(20) |
| 432 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x20_acc5); |
| 433 | } |
| 434 | |
| 435 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X20_ACC5, elements_div_20) { |
| 436 | TEST_REQUIRES_ARM_NEON; |
| 437 | for (size_t elements = 40; elements < 200; elements += 20) { |
| 438 | RAddStoreExpMinusMaxMicrokernelTester() |
| 439 | .elements(elements) |
| 440 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x20_acc5); |
| 441 | } |
| 442 | } |
| 443 | |
| 444 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X20_ACC5, elements_lt_20) { |
| 445 | TEST_REQUIRES_ARM_NEON; |
| 446 | for (size_t elements = 1; elements < 20; elements++) { |
| 447 | RAddStoreExpMinusMaxMicrokernelTester() |
| 448 | .elements(elements) |
| 449 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x20_acc5); |
| 450 | } |
| 451 | } |
| 452 | |
| 453 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_P5_X20_ACC5, elements_gt_20) { |
| 454 | TEST_REQUIRES_ARM_NEON; |
| 455 | for (size_t elements = 21; elements < 40; elements++) { |
| 456 | RAddStoreExpMinusMaxMicrokernelTester() |
| 457 | .elements(elements) |
| 458 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x20_acc5); |
| 459 | } |
| 460 | } |
| 461 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 462 | |
| 463 | |
| 464 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 465 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X4, elements_eq_4) { |
| 466 | TEST_REQUIRES_ARM_NEON; |
| 467 | RAddStoreExpMinusMaxMicrokernelTester() |
| 468 | .elements(4) |
| 469 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x4); |
| 470 | } |
| 471 | |
| 472 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X4, elements_div_4) { |
| 473 | TEST_REQUIRES_ARM_NEON; |
| 474 | for (size_t elements = 8; elements < 40; elements += 4) { |
| 475 | RAddStoreExpMinusMaxMicrokernelTester() |
| 476 | .elements(elements) |
| 477 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x4); |
| 478 | } |
| 479 | } |
| 480 | |
| 481 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X4, elements_lt_4) { |
| 482 | TEST_REQUIRES_ARM_NEON; |
| 483 | for (size_t elements = 1; elements < 4; elements++) { |
| 484 | RAddStoreExpMinusMaxMicrokernelTester() |
| 485 | .elements(elements) |
| 486 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x4); |
| 487 | } |
| 488 | } |
| 489 | |
| 490 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X4, elements_gt_4) { |
| 491 | TEST_REQUIRES_ARM_NEON; |
| 492 | for (size_t elements = 5; elements < 8; elements++) { |
| 493 | RAddStoreExpMinusMaxMicrokernelTester() |
| 494 | .elements(elements) |
| 495 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x4); |
| 496 | } |
| 497 | } |
| 498 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 499 | |
| 500 | |
| 501 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 502 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X8, elements_eq_8) { |
| 503 | TEST_REQUIRES_ARM_NEON; |
| 504 | RAddStoreExpMinusMaxMicrokernelTester() |
| 505 | .elements(8) |
| 506 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x8); |
| 507 | } |
| 508 | |
| 509 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X8, elements_div_8) { |
| 510 | TEST_REQUIRES_ARM_NEON; |
| 511 | for (size_t elements = 16; elements < 80; elements += 8) { |
| 512 | RAddStoreExpMinusMaxMicrokernelTester() |
| 513 | .elements(elements) |
| 514 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x8); |
| 515 | } |
| 516 | } |
| 517 | |
| 518 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X8, elements_lt_8) { |
| 519 | TEST_REQUIRES_ARM_NEON; |
| 520 | for (size_t elements = 1; elements < 8; elements++) { |
| 521 | RAddStoreExpMinusMaxMicrokernelTester() |
| 522 | .elements(elements) |
| 523 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x8); |
| 524 | } |
| 525 | } |
| 526 | |
| 527 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X8, elements_gt_8) { |
| 528 | TEST_REQUIRES_ARM_NEON; |
| 529 | for (size_t elements = 9; elements < 16; elements++) { |
| 530 | RAddStoreExpMinusMaxMicrokernelTester() |
| 531 | .elements(elements) |
| 532 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x8); |
| 533 | } |
| 534 | } |
| 535 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 536 | |
| 537 | |
| 538 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 539 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X8_ACC2, elements_eq_8) { |
| 540 | TEST_REQUIRES_ARM_NEON; |
| 541 | RAddStoreExpMinusMaxMicrokernelTester() |
| 542 | .elements(8) |
| 543 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x8_acc2); |
| 544 | } |
| 545 | |
| 546 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X8_ACC2, elements_div_8) { |
| 547 | TEST_REQUIRES_ARM_NEON; |
| 548 | for (size_t elements = 16; elements < 80; elements += 8) { |
| 549 | RAddStoreExpMinusMaxMicrokernelTester() |
| 550 | .elements(elements) |
| 551 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x8_acc2); |
| 552 | } |
| 553 | } |
| 554 | |
| 555 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X8_ACC2, elements_lt_8) { |
| 556 | TEST_REQUIRES_ARM_NEON; |
| 557 | for (size_t elements = 1; elements < 8; elements++) { |
| 558 | RAddStoreExpMinusMaxMicrokernelTester() |
| 559 | .elements(elements) |
| 560 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x8_acc2); |
| 561 | } |
| 562 | } |
| 563 | |
| 564 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X8_ACC2, elements_gt_8) { |
| 565 | TEST_REQUIRES_ARM_NEON; |
| 566 | for (size_t elements = 9; elements < 16; elements++) { |
| 567 | RAddStoreExpMinusMaxMicrokernelTester() |
| 568 | .elements(elements) |
| 569 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x8_acc2); |
| 570 | } |
| 571 | } |
| 572 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 573 | |
| 574 | |
| 575 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 576 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X12, elements_eq_12) { |
| 577 | TEST_REQUIRES_ARM_NEON; |
| 578 | RAddStoreExpMinusMaxMicrokernelTester() |
| 579 | .elements(12) |
| 580 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x12); |
| 581 | } |
| 582 | |
| 583 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X12, elements_div_12) { |
| 584 | TEST_REQUIRES_ARM_NEON; |
| 585 | for (size_t elements = 24; elements < 120; elements += 12) { |
| 586 | RAddStoreExpMinusMaxMicrokernelTester() |
| 587 | .elements(elements) |
| 588 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x12); |
| 589 | } |
| 590 | } |
| 591 | |
| 592 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X12, elements_lt_12) { |
| 593 | TEST_REQUIRES_ARM_NEON; |
| 594 | for (size_t elements = 1; elements < 12; elements++) { |
| 595 | RAddStoreExpMinusMaxMicrokernelTester() |
| 596 | .elements(elements) |
| 597 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x12); |
| 598 | } |
| 599 | } |
| 600 | |
| 601 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X12, elements_gt_12) { |
| 602 | TEST_REQUIRES_ARM_NEON; |
| 603 | for (size_t elements = 13; elements < 24; elements++) { |
| 604 | RAddStoreExpMinusMaxMicrokernelTester() |
| 605 | .elements(elements) |
| 606 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x12); |
| 607 | } |
| 608 | } |
| 609 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 610 | |
| 611 | |
| 612 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 613 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X12_ACC2, elements_eq_12) { |
| 614 | TEST_REQUIRES_ARM_NEON; |
| 615 | RAddStoreExpMinusMaxMicrokernelTester() |
| 616 | .elements(12) |
| 617 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x12_acc2); |
| 618 | } |
| 619 | |
| 620 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X12_ACC2, elements_div_12) { |
| 621 | TEST_REQUIRES_ARM_NEON; |
| 622 | for (size_t elements = 24; elements < 120; elements += 12) { |
| 623 | RAddStoreExpMinusMaxMicrokernelTester() |
| 624 | .elements(elements) |
| 625 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x12_acc2); |
| 626 | } |
| 627 | } |
| 628 | |
| 629 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X12_ACC2, elements_lt_12) { |
| 630 | TEST_REQUIRES_ARM_NEON; |
| 631 | for (size_t elements = 1; elements < 12; elements++) { |
| 632 | RAddStoreExpMinusMaxMicrokernelTester() |
| 633 | .elements(elements) |
| 634 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x12_acc2); |
| 635 | } |
| 636 | } |
| 637 | |
| 638 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X12_ACC2, elements_gt_12) { |
| 639 | TEST_REQUIRES_ARM_NEON; |
| 640 | for (size_t elements = 13; elements < 24; elements++) { |
| 641 | RAddStoreExpMinusMaxMicrokernelTester() |
| 642 | .elements(elements) |
| 643 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x12_acc2); |
| 644 | } |
| 645 | } |
| 646 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 647 | |
| 648 | |
| 649 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 650 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X12_ACC3, elements_eq_12) { |
| 651 | TEST_REQUIRES_ARM_NEON; |
| 652 | RAddStoreExpMinusMaxMicrokernelTester() |
| 653 | .elements(12) |
| 654 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x12_acc3); |
| 655 | } |
| 656 | |
| 657 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X12_ACC3, elements_div_12) { |
| 658 | TEST_REQUIRES_ARM_NEON; |
| 659 | for (size_t elements = 24; elements < 120; elements += 12) { |
| 660 | RAddStoreExpMinusMaxMicrokernelTester() |
| 661 | .elements(elements) |
| 662 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x12_acc3); |
| 663 | } |
| 664 | } |
| 665 | |
| 666 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X12_ACC3, elements_lt_12) { |
| 667 | TEST_REQUIRES_ARM_NEON; |
| 668 | for (size_t elements = 1; elements < 12; elements++) { |
| 669 | RAddStoreExpMinusMaxMicrokernelTester() |
| 670 | .elements(elements) |
| 671 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x12_acc3); |
| 672 | } |
| 673 | } |
| 674 | |
| 675 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X12_ACC3, elements_gt_12) { |
| 676 | TEST_REQUIRES_ARM_NEON; |
| 677 | for (size_t elements = 13; elements < 24; elements++) { |
| 678 | RAddStoreExpMinusMaxMicrokernelTester() |
| 679 | .elements(elements) |
| 680 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x12_acc3); |
| 681 | } |
| 682 | } |
| 683 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 684 | |
| 685 | |
| 686 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 687 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X16, elements_eq_16) { |
| 688 | TEST_REQUIRES_ARM_NEON; |
| 689 | RAddStoreExpMinusMaxMicrokernelTester() |
| 690 | .elements(16) |
| 691 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x16); |
| 692 | } |
| 693 | |
| 694 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X16, elements_div_16) { |
| 695 | TEST_REQUIRES_ARM_NEON; |
| 696 | for (size_t elements = 32; elements < 160; elements += 16) { |
| 697 | RAddStoreExpMinusMaxMicrokernelTester() |
| 698 | .elements(elements) |
| 699 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x16); |
| 700 | } |
| 701 | } |
| 702 | |
| 703 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X16, elements_lt_16) { |
| 704 | TEST_REQUIRES_ARM_NEON; |
| 705 | for (size_t elements = 1; elements < 16; elements++) { |
| 706 | RAddStoreExpMinusMaxMicrokernelTester() |
| 707 | .elements(elements) |
| 708 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x16); |
| 709 | } |
| 710 | } |
| 711 | |
| 712 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X16, elements_gt_16) { |
| 713 | TEST_REQUIRES_ARM_NEON; |
| 714 | for (size_t elements = 17; elements < 32; elements++) { |
| 715 | RAddStoreExpMinusMaxMicrokernelTester() |
| 716 | .elements(elements) |
| 717 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x16); |
| 718 | } |
| 719 | } |
| 720 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 721 | |
| 722 | |
| 723 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 724 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X16_ACC2, elements_eq_16) { |
| 725 | TEST_REQUIRES_ARM_NEON; |
| 726 | RAddStoreExpMinusMaxMicrokernelTester() |
| 727 | .elements(16) |
| 728 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x16_acc2); |
| 729 | } |
| 730 | |
| 731 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X16_ACC2, elements_div_16) { |
| 732 | TEST_REQUIRES_ARM_NEON; |
| 733 | for (size_t elements = 32; elements < 160; elements += 16) { |
| 734 | RAddStoreExpMinusMaxMicrokernelTester() |
| 735 | .elements(elements) |
| 736 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x16_acc2); |
| 737 | } |
| 738 | } |
| 739 | |
| 740 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X16_ACC2, elements_lt_16) { |
| 741 | TEST_REQUIRES_ARM_NEON; |
| 742 | for (size_t elements = 1; elements < 16; elements++) { |
| 743 | RAddStoreExpMinusMaxMicrokernelTester() |
| 744 | .elements(elements) |
| 745 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x16_acc2); |
| 746 | } |
| 747 | } |
| 748 | |
| 749 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X16_ACC2, elements_gt_16) { |
| 750 | TEST_REQUIRES_ARM_NEON; |
| 751 | for (size_t elements = 17; elements < 32; elements++) { |
| 752 | RAddStoreExpMinusMaxMicrokernelTester() |
| 753 | .elements(elements) |
| 754 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x16_acc2); |
| 755 | } |
| 756 | } |
| 757 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 758 | |
| 759 | |
| 760 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 761 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X16_ACC4, elements_eq_16) { |
| 762 | TEST_REQUIRES_ARM_NEON; |
| 763 | RAddStoreExpMinusMaxMicrokernelTester() |
| 764 | .elements(16) |
| 765 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x16_acc4); |
| 766 | } |
| 767 | |
| 768 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X16_ACC4, elements_div_16) { |
| 769 | TEST_REQUIRES_ARM_NEON; |
| 770 | for (size_t elements = 32; elements < 160; elements += 16) { |
| 771 | RAddStoreExpMinusMaxMicrokernelTester() |
| 772 | .elements(elements) |
| 773 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x16_acc4); |
| 774 | } |
| 775 | } |
| 776 | |
| 777 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X16_ACC4, elements_lt_16) { |
| 778 | TEST_REQUIRES_ARM_NEON; |
| 779 | for (size_t elements = 1; elements < 16; elements++) { |
| 780 | RAddStoreExpMinusMaxMicrokernelTester() |
| 781 | .elements(elements) |
| 782 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x16_acc4); |
| 783 | } |
| 784 | } |
| 785 | |
| 786 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X16_ACC4, elements_gt_16) { |
| 787 | TEST_REQUIRES_ARM_NEON; |
| 788 | for (size_t elements = 17; elements < 32; elements++) { |
| 789 | RAddStoreExpMinusMaxMicrokernelTester() |
| 790 | .elements(elements) |
| 791 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x16_acc4); |
| 792 | } |
| 793 | } |
| 794 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 795 | |
| 796 | |
| 797 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 798 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X20, elements_eq_20) { |
| 799 | TEST_REQUIRES_ARM_NEON; |
| 800 | RAddStoreExpMinusMaxMicrokernelTester() |
| 801 | .elements(20) |
| 802 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x20); |
| 803 | } |
| 804 | |
| 805 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X20, elements_div_20) { |
| 806 | TEST_REQUIRES_ARM_NEON; |
| 807 | for (size_t elements = 40; elements < 200; elements += 20) { |
| 808 | RAddStoreExpMinusMaxMicrokernelTester() |
| 809 | .elements(elements) |
| 810 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x20); |
| 811 | } |
| 812 | } |
| 813 | |
| 814 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X20, elements_lt_20) { |
| 815 | TEST_REQUIRES_ARM_NEON; |
| 816 | for (size_t elements = 1; elements < 20; elements++) { |
| 817 | RAddStoreExpMinusMaxMicrokernelTester() |
| 818 | .elements(elements) |
| 819 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x20); |
| 820 | } |
| 821 | } |
| 822 | |
| 823 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X20, elements_gt_20) { |
| 824 | TEST_REQUIRES_ARM_NEON; |
| 825 | for (size_t elements = 21; elements < 40; elements++) { |
| 826 | RAddStoreExpMinusMaxMicrokernelTester() |
| 827 | .elements(elements) |
| 828 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x20); |
| 829 | } |
| 830 | } |
| 831 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 832 | |
| 833 | |
| 834 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 835 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X20_ACC2, elements_eq_20) { |
| 836 | TEST_REQUIRES_ARM_NEON; |
| 837 | RAddStoreExpMinusMaxMicrokernelTester() |
| 838 | .elements(20) |
| 839 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x20_acc2); |
| 840 | } |
| 841 | |
| 842 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X20_ACC2, elements_div_20) { |
| 843 | TEST_REQUIRES_ARM_NEON; |
| 844 | for (size_t elements = 40; elements < 200; elements += 20) { |
| 845 | RAddStoreExpMinusMaxMicrokernelTester() |
| 846 | .elements(elements) |
| 847 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x20_acc2); |
| 848 | } |
| 849 | } |
| 850 | |
| 851 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X20_ACC2, elements_lt_20) { |
| 852 | TEST_REQUIRES_ARM_NEON; |
| 853 | for (size_t elements = 1; elements < 20; elements++) { |
| 854 | RAddStoreExpMinusMaxMicrokernelTester() |
| 855 | .elements(elements) |
| 856 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x20_acc2); |
| 857 | } |
| 858 | } |
| 859 | |
| 860 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X20_ACC2, elements_gt_20) { |
| 861 | TEST_REQUIRES_ARM_NEON; |
| 862 | for (size_t elements = 21; elements < 40; elements++) { |
| 863 | RAddStoreExpMinusMaxMicrokernelTester() |
| 864 | .elements(elements) |
| 865 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x20_acc2); |
| 866 | } |
| 867 | } |
| 868 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 869 | |
| 870 | |
| 871 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 872 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X20_ACC5, elements_eq_20) { |
| 873 | TEST_REQUIRES_ARM_NEON; |
| 874 | RAddStoreExpMinusMaxMicrokernelTester() |
| 875 | .elements(20) |
| 876 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x20_acc5); |
| 877 | } |
| 878 | |
| 879 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X20_ACC5, elements_div_20) { |
| 880 | TEST_REQUIRES_ARM_NEON; |
| 881 | for (size_t elements = 40; elements < 200; elements += 20) { |
| 882 | RAddStoreExpMinusMaxMicrokernelTester() |
| 883 | .elements(elements) |
| 884 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x20_acc5); |
| 885 | } |
| 886 | } |
| 887 | |
| 888 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X20_ACC5, elements_lt_20) { |
| 889 | TEST_REQUIRES_ARM_NEON; |
| 890 | for (size_t elements = 1; elements < 20; elements++) { |
| 891 | RAddStoreExpMinusMaxMicrokernelTester() |
| 892 | .elements(elements) |
| 893 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x20_acc5); |
| 894 | } |
| 895 | } |
| 896 | |
| 897 | TEST(F32_RADDSTOREEXPMINUSMAX__NEON_LUT64_P2_X20_ACC5, elements_gt_20) { |
| 898 | TEST_REQUIRES_ARM_NEON; |
| 899 | for (size_t elements = 21; elements < 40; elements++) { |
| 900 | RAddStoreExpMinusMaxMicrokernelTester() |
| 901 | .elements(elements) |
| 902 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neon_lut64_p2_x20_acc5); |
| 903 | } |
| 904 | } |
| 905 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 906 | |
| 907 | |
| 908 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 909 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X4, elements_eq_4) { |
| 910 | TEST_REQUIRES_ARM_NEON_FMA; |
| 911 | RAddStoreExpMinusMaxMicrokernelTester() |
| 912 | .elements(4) |
| 913 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x4); |
| 914 | } |
| 915 | |
| 916 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X4, elements_div_4) { |
| 917 | TEST_REQUIRES_ARM_NEON_FMA; |
| 918 | for (size_t elements = 8; elements < 40; elements += 4) { |
| 919 | RAddStoreExpMinusMaxMicrokernelTester() |
| 920 | .elements(elements) |
| 921 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x4); |
| 922 | } |
| 923 | } |
| 924 | |
| 925 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X4, elements_lt_4) { |
| 926 | TEST_REQUIRES_ARM_NEON_FMA; |
| 927 | for (size_t elements = 1; elements < 4; elements++) { |
| 928 | RAddStoreExpMinusMaxMicrokernelTester() |
| 929 | .elements(elements) |
| 930 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x4); |
| 931 | } |
| 932 | } |
| 933 | |
| 934 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X4, elements_gt_4) { |
| 935 | TEST_REQUIRES_ARM_NEON_FMA; |
| 936 | for (size_t elements = 5; elements < 8; elements++) { |
| 937 | RAddStoreExpMinusMaxMicrokernelTester() |
| 938 | .elements(elements) |
| 939 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x4); |
| 940 | } |
| 941 | } |
| 942 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 943 | |
| 944 | |
| 945 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 946 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X8, elements_eq_8) { |
| 947 | TEST_REQUIRES_ARM_NEON_FMA; |
| 948 | RAddStoreExpMinusMaxMicrokernelTester() |
| 949 | .elements(8) |
| 950 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x8); |
| 951 | } |
| 952 | |
| 953 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X8, elements_div_8) { |
| 954 | TEST_REQUIRES_ARM_NEON_FMA; |
| 955 | for (size_t elements = 16; elements < 80; elements += 8) { |
| 956 | RAddStoreExpMinusMaxMicrokernelTester() |
| 957 | .elements(elements) |
| 958 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x8); |
| 959 | } |
| 960 | } |
| 961 | |
| 962 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X8, elements_lt_8) { |
| 963 | TEST_REQUIRES_ARM_NEON_FMA; |
| 964 | for (size_t elements = 1; elements < 8; elements++) { |
| 965 | RAddStoreExpMinusMaxMicrokernelTester() |
| 966 | .elements(elements) |
| 967 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x8); |
| 968 | } |
| 969 | } |
| 970 | |
| 971 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X8, elements_gt_8) { |
| 972 | TEST_REQUIRES_ARM_NEON_FMA; |
| 973 | for (size_t elements = 9; elements < 16; elements++) { |
| 974 | RAddStoreExpMinusMaxMicrokernelTester() |
| 975 | .elements(elements) |
| 976 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x8); |
| 977 | } |
| 978 | } |
| 979 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 980 | |
| 981 | |
| 982 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 983 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X8_ACC2, elements_eq_8) { |
| 984 | TEST_REQUIRES_ARM_NEON_FMA; |
| 985 | RAddStoreExpMinusMaxMicrokernelTester() |
| 986 | .elements(8) |
| 987 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x8_acc2); |
| 988 | } |
| 989 | |
| 990 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X8_ACC2, elements_div_8) { |
| 991 | TEST_REQUIRES_ARM_NEON_FMA; |
| 992 | for (size_t elements = 16; elements < 80; elements += 8) { |
| 993 | RAddStoreExpMinusMaxMicrokernelTester() |
| 994 | .elements(elements) |
| 995 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x8_acc2); |
| 996 | } |
| 997 | } |
| 998 | |
| 999 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X8_ACC2, elements_lt_8) { |
| 1000 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1001 | for (size_t elements = 1; elements < 8; elements++) { |
| 1002 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1003 | .elements(elements) |
| 1004 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x8_acc2); |
| 1005 | } |
| 1006 | } |
| 1007 | |
| 1008 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X8_ACC2, elements_gt_8) { |
| 1009 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1010 | for (size_t elements = 9; elements < 16; elements++) { |
| 1011 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1012 | .elements(elements) |
| 1013 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x8_acc2); |
| 1014 | } |
| 1015 | } |
| 1016 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1017 | |
| 1018 | |
| 1019 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1020 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X12, elements_eq_12) { |
| 1021 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1022 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1023 | .elements(12) |
| 1024 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x12); |
| 1025 | } |
| 1026 | |
| 1027 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X12, elements_div_12) { |
| 1028 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1029 | for (size_t elements = 24; elements < 120; elements += 12) { |
| 1030 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1031 | .elements(elements) |
| 1032 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x12); |
| 1033 | } |
| 1034 | } |
| 1035 | |
| 1036 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X12, elements_lt_12) { |
| 1037 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1038 | for (size_t elements = 1; elements < 12; elements++) { |
| 1039 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1040 | .elements(elements) |
| 1041 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x12); |
| 1042 | } |
| 1043 | } |
| 1044 | |
| 1045 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X12, elements_gt_12) { |
| 1046 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1047 | for (size_t elements = 13; elements < 24; elements++) { |
| 1048 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1049 | .elements(elements) |
| 1050 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x12); |
| 1051 | } |
| 1052 | } |
| 1053 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1054 | |
| 1055 | |
| 1056 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1057 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X12_ACC2, elements_eq_12) { |
| 1058 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1059 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1060 | .elements(12) |
| 1061 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x12_acc2); |
| 1062 | } |
| 1063 | |
| 1064 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X12_ACC2, elements_div_12) { |
| 1065 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1066 | for (size_t elements = 24; elements < 120; elements += 12) { |
| 1067 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1068 | .elements(elements) |
| 1069 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x12_acc2); |
| 1070 | } |
| 1071 | } |
| 1072 | |
| 1073 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X12_ACC2, elements_lt_12) { |
| 1074 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1075 | for (size_t elements = 1; elements < 12; elements++) { |
| 1076 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1077 | .elements(elements) |
| 1078 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x12_acc2); |
| 1079 | } |
| 1080 | } |
| 1081 | |
| 1082 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X12_ACC2, elements_gt_12) { |
| 1083 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1084 | for (size_t elements = 13; elements < 24; elements++) { |
| 1085 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1086 | .elements(elements) |
| 1087 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x12_acc2); |
| 1088 | } |
| 1089 | } |
| 1090 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1091 | |
| 1092 | |
| 1093 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1094 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X12_ACC3, elements_eq_12) { |
| 1095 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1096 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1097 | .elements(12) |
| 1098 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x12_acc3); |
| 1099 | } |
| 1100 | |
| 1101 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X12_ACC3, elements_div_12) { |
| 1102 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1103 | for (size_t elements = 24; elements < 120; elements += 12) { |
| 1104 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1105 | .elements(elements) |
| 1106 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x12_acc3); |
| 1107 | } |
| 1108 | } |
| 1109 | |
| 1110 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X12_ACC3, elements_lt_12) { |
| 1111 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1112 | for (size_t elements = 1; elements < 12; elements++) { |
| 1113 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1114 | .elements(elements) |
| 1115 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x12_acc3); |
| 1116 | } |
| 1117 | } |
| 1118 | |
| 1119 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X12_ACC3, elements_gt_12) { |
| 1120 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1121 | for (size_t elements = 13; elements < 24; elements++) { |
| 1122 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1123 | .elements(elements) |
| 1124 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x12_acc3); |
| 1125 | } |
| 1126 | } |
| 1127 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1128 | |
| 1129 | |
| 1130 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1131 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X16, elements_eq_16) { |
| 1132 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1133 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1134 | .elements(16) |
| 1135 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x16); |
| 1136 | } |
| 1137 | |
| 1138 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X16, elements_div_16) { |
| 1139 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1140 | for (size_t elements = 32; elements < 160; elements += 16) { |
| 1141 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1142 | .elements(elements) |
| 1143 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x16); |
| 1144 | } |
| 1145 | } |
| 1146 | |
| 1147 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X16, elements_lt_16) { |
| 1148 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1149 | for (size_t elements = 1; elements < 16; elements++) { |
| 1150 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1151 | .elements(elements) |
| 1152 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x16); |
| 1153 | } |
| 1154 | } |
| 1155 | |
| 1156 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X16, elements_gt_16) { |
| 1157 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1158 | for (size_t elements = 17; elements < 32; elements++) { |
| 1159 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1160 | .elements(elements) |
| 1161 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x16); |
| 1162 | } |
| 1163 | } |
| 1164 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1165 | |
| 1166 | |
| 1167 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1168 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X16_ACC2, elements_eq_16) { |
| 1169 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1170 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1171 | .elements(16) |
| 1172 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x16_acc2); |
| 1173 | } |
| 1174 | |
| 1175 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X16_ACC2, elements_div_16) { |
| 1176 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1177 | for (size_t elements = 32; elements < 160; elements += 16) { |
| 1178 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1179 | .elements(elements) |
| 1180 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x16_acc2); |
| 1181 | } |
| 1182 | } |
| 1183 | |
| 1184 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X16_ACC2, elements_lt_16) { |
| 1185 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1186 | for (size_t elements = 1; elements < 16; elements++) { |
| 1187 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1188 | .elements(elements) |
| 1189 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x16_acc2); |
| 1190 | } |
| 1191 | } |
| 1192 | |
| 1193 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X16_ACC2, elements_gt_16) { |
| 1194 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1195 | for (size_t elements = 17; elements < 32; elements++) { |
| 1196 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1197 | .elements(elements) |
| 1198 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x16_acc2); |
| 1199 | } |
| 1200 | } |
| 1201 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1202 | |
| 1203 | |
| 1204 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1205 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X16_ACC4, elements_eq_16) { |
| 1206 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1207 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1208 | .elements(16) |
| 1209 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x16_acc4); |
| 1210 | } |
| 1211 | |
| 1212 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X16_ACC4, elements_div_16) { |
| 1213 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1214 | for (size_t elements = 32; elements < 160; elements += 16) { |
| 1215 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1216 | .elements(elements) |
| 1217 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x16_acc4); |
| 1218 | } |
| 1219 | } |
| 1220 | |
| 1221 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X16_ACC4, elements_lt_16) { |
| 1222 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1223 | for (size_t elements = 1; elements < 16; elements++) { |
| 1224 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1225 | .elements(elements) |
| 1226 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x16_acc4); |
| 1227 | } |
| 1228 | } |
| 1229 | |
| 1230 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X16_ACC4, elements_gt_16) { |
| 1231 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1232 | for (size_t elements = 17; elements < 32; elements++) { |
| 1233 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1234 | .elements(elements) |
| 1235 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x16_acc4); |
| 1236 | } |
| 1237 | } |
| 1238 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1239 | |
| 1240 | |
| 1241 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1242 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X20, elements_eq_20) { |
| 1243 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1244 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1245 | .elements(20) |
| 1246 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x20); |
| 1247 | } |
| 1248 | |
| 1249 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X20, elements_div_20) { |
| 1250 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1251 | for (size_t elements = 40; elements < 200; elements += 20) { |
| 1252 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1253 | .elements(elements) |
| 1254 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x20); |
| 1255 | } |
| 1256 | } |
| 1257 | |
| 1258 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X20, elements_lt_20) { |
| 1259 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1260 | for (size_t elements = 1; elements < 20; elements++) { |
| 1261 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1262 | .elements(elements) |
| 1263 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x20); |
| 1264 | } |
| 1265 | } |
| 1266 | |
| 1267 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X20, elements_gt_20) { |
| 1268 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1269 | for (size_t elements = 21; elements < 40; elements++) { |
| 1270 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1271 | .elements(elements) |
| 1272 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x20); |
| 1273 | } |
| 1274 | } |
| 1275 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1276 | |
| 1277 | |
| 1278 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1279 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X20_ACC2, elements_eq_20) { |
| 1280 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1281 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1282 | .elements(20) |
| 1283 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x20_acc2); |
| 1284 | } |
| 1285 | |
| 1286 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X20_ACC2, elements_div_20) { |
| 1287 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1288 | for (size_t elements = 40; elements < 200; elements += 20) { |
| 1289 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1290 | .elements(elements) |
| 1291 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x20_acc2); |
| 1292 | } |
| 1293 | } |
| 1294 | |
| 1295 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X20_ACC2, elements_lt_20) { |
| 1296 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1297 | for (size_t elements = 1; elements < 20; elements++) { |
| 1298 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1299 | .elements(elements) |
| 1300 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x20_acc2); |
| 1301 | } |
| 1302 | } |
| 1303 | |
| 1304 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X20_ACC2, elements_gt_20) { |
| 1305 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1306 | for (size_t elements = 21; elements < 40; elements++) { |
| 1307 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1308 | .elements(elements) |
| 1309 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x20_acc2); |
| 1310 | } |
| 1311 | } |
| 1312 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1313 | |
| 1314 | |
| 1315 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1316 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X20_ACC5, elements_eq_20) { |
| 1317 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1318 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1319 | .elements(20) |
| 1320 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x20_acc5); |
| 1321 | } |
| 1322 | |
| 1323 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X20_ACC5, elements_div_20) { |
| 1324 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1325 | for (size_t elements = 40; elements < 200; elements += 20) { |
| 1326 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1327 | .elements(elements) |
| 1328 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x20_acc5); |
| 1329 | } |
| 1330 | } |
| 1331 | |
| 1332 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X20_ACC5, elements_lt_20) { |
| 1333 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1334 | for (size_t elements = 1; elements < 20; elements++) { |
| 1335 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1336 | .elements(elements) |
| 1337 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x20_acc5); |
| 1338 | } |
| 1339 | } |
| 1340 | |
| 1341 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_P5_X20_ACC5, elements_gt_20) { |
| 1342 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1343 | for (size_t elements = 21; elements < 40; elements++) { |
| 1344 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1345 | .elements(elements) |
| 1346 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x20_acc5); |
| 1347 | } |
| 1348 | } |
| 1349 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1350 | |
| 1351 | |
| 1352 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1353 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X4, elements_eq_4) { |
| 1354 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1355 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1356 | .elements(4) |
| 1357 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x4); |
| 1358 | } |
| 1359 | |
| 1360 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X4, elements_div_4) { |
| 1361 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1362 | for (size_t elements = 8; elements < 40; elements += 4) { |
| 1363 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1364 | .elements(elements) |
| 1365 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x4); |
| 1366 | } |
| 1367 | } |
| 1368 | |
| 1369 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X4, elements_lt_4) { |
| 1370 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1371 | for (size_t elements = 1; elements < 4; elements++) { |
| 1372 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1373 | .elements(elements) |
| 1374 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x4); |
| 1375 | } |
| 1376 | } |
| 1377 | |
| 1378 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X4, elements_gt_4) { |
| 1379 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1380 | for (size_t elements = 5; elements < 8; elements++) { |
| 1381 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1382 | .elements(elements) |
| 1383 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x4); |
| 1384 | } |
| 1385 | } |
| 1386 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1387 | |
| 1388 | |
| 1389 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1390 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X8, elements_eq_8) { |
| 1391 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1392 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1393 | .elements(8) |
| 1394 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x8); |
| 1395 | } |
| 1396 | |
| 1397 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X8, elements_div_8) { |
| 1398 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1399 | for (size_t elements = 16; elements < 80; elements += 8) { |
| 1400 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1401 | .elements(elements) |
| 1402 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x8); |
| 1403 | } |
| 1404 | } |
| 1405 | |
| 1406 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X8, elements_lt_8) { |
| 1407 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1408 | for (size_t elements = 1; elements < 8; elements++) { |
| 1409 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1410 | .elements(elements) |
| 1411 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x8); |
| 1412 | } |
| 1413 | } |
| 1414 | |
| 1415 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X8, elements_gt_8) { |
| 1416 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1417 | for (size_t elements = 9; elements < 16; elements++) { |
| 1418 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1419 | .elements(elements) |
| 1420 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x8); |
| 1421 | } |
| 1422 | } |
| 1423 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1424 | |
| 1425 | |
| 1426 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1427 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X8_ACC2, elements_eq_8) { |
| 1428 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1429 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1430 | .elements(8) |
| 1431 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x8_acc2); |
| 1432 | } |
| 1433 | |
| 1434 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X8_ACC2, elements_div_8) { |
| 1435 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1436 | for (size_t elements = 16; elements < 80; elements += 8) { |
| 1437 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1438 | .elements(elements) |
| 1439 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x8_acc2); |
| 1440 | } |
| 1441 | } |
| 1442 | |
| 1443 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X8_ACC2, elements_lt_8) { |
| 1444 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1445 | for (size_t elements = 1; elements < 8; elements++) { |
| 1446 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1447 | .elements(elements) |
| 1448 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x8_acc2); |
| 1449 | } |
| 1450 | } |
| 1451 | |
| 1452 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X8_ACC2, elements_gt_8) { |
| 1453 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1454 | for (size_t elements = 9; elements < 16; elements++) { |
| 1455 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1456 | .elements(elements) |
| 1457 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x8_acc2); |
| 1458 | } |
| 1459 | } |
| 1460 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1461 | |
| 1462 | |
| 1463 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1464 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X12, elements_eq_12) { |
| 1465 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1466 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1467 | .elements(12) |
| 1468 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x12); |
| 1469 | } |
| 1470 | |
| 1471 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X12, elements_div_12) { |
| 1472 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1473 | for (size_t elements = 24; elements < 120; elements += 12) { |
| 1474 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1475 | .elements(elements) |
| 1476 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x12); |
| 1477 | } |
| 1478 | } |
| 1479 | |
| 1480 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X12, elements_lt_12) { |
| 1481 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1482 | for (size_t elements = 1; elements < 12; elements++) { |
| 1483 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1484 | .elements(elements) |
| 1485 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x12); |
| 1486 | } |
| 1487 | } |
| 1488 | |
| 1489 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X12, elements_gt_12) { |
| 1490 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1491 | for (size_t elements = 13; elements < 24; elements++) { |
| 1492 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1493 | .elements(elements) |
| 1494 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x12); |
| 1495 | } |
| 1496 | } |
| 1497 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1498 | |
| 1499 | |
| 1500 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1501 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X12_ACC2, elements_eq_12) { |
| 1502 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1503 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1504 | .elements(12) |
| 1505 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x12_acc2); |
| 1506 | } |
| 1507 | |
| 1508 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X12_ACC2, elements_div_12) { |
| 1509 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1510 | for (size_t elements = 24; elements < 120; elements += 12) { |
| 1511 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1512 | .elements(elements) |
| 1513 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x12_acc2); |
| 1514 | } |
| 1515 | } |
| 1516 | |
| 1517 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X12_ACC2, elements_lt_12) { |
| 1518 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1519 | for (size_t elements = 1; elements < 12; elements++) { |
| 1520 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1521 | .elements(elements) |
| 1522 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x12_acc2); |
| 1523 | } |
| 1524 | } |
| 1525 | |
| 1526 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X12_ACC2, elements_gt_12) { |
| 1527 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1528 | for (size_t elements = 13; elements < 24; elements++) { |
| 1529 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1530 | .elements(elements) |
| 1531 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x12_acc2); |
| 1532 | } |
| 1533 | } |
| 1534 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1535 | |
| 1536 | |
| 1537 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1538 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X12_ACC3, elements_eq_12) { |
| 1539 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1540 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1541 | .elements(12) |
| 1542 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x12_acc3); |
| 1543 | } |
| 1544 | |
| 1545 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X12_ACC3, elements_div_12) { |
| 1546 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1547 | for (size_t elements = 24; elements < 120; elements += 12) { |
| 1548 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1549 | .elements(elements) |
| 1550 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x12_acc3); |
| 1551 | } |
| 1552 | } |
| 1553 | |
| 1554 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X12_ACC3, elements_lt_12) { |
| 1555 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1556 | for (size_t elements = 1; elements < 12; elements++) { |
| 1557 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1558 | .elements(elements) |
| 1559 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x12_acc3); |
| 1560 | } |
| 1561 | } |
| 1562 | |
| 1563 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X12_ACC3, elements_gt_12) { |
| 1564 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1565 | for (size_t elements = 13; elements < 24; elements++) { |
| 1566 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1567 | .elements(elements) |
| 1568 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x12_acc3); |
| 1569 | } |
| 1570 | } |
| 1571 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1572 | |
| 1573 | |
| 1574 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1575 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X16, elements_eq_16) { |
| 1576 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1577 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1578 | .elements(16) |
| 1579 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x16); |
| 1580 | } |
| 1581 | |
| 1582 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X16, elements_div_16) { |
| 1583 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1584 | for (size_t elements = 32; elements < 160; elements += 16) { |
| 1585 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1586 | .elements(elements) |
| 1587 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x16); |
| 1588 | } |
| 1589 | } |
| 1590 | |
| 1591 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X16, elements_lt_16) { |
| 1592 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1593 | for (size_t elements = 1; elements < 16; elements++) { |
| 1594 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1595 | .elements(elements) |
| 1596 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x16); |
| 1597 | } |
| 1598 | } |
| 1599 | |
| 1600 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X16, elements_gt_16) { |
| 1601 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1602 | for (size_t elements = 17; elements < 32; elements++) { |
| 1603 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1604 | .elements(elements) |
| 1605 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x16); |
| 1606 | } |
| 1607 | } |
| 1608 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1609 | |
| 1610 | |
| 1611 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1612 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X16_ACC2, elements_eq_16) { |
| 1613 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1614 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1615 | .elements(16) |
| 1616 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x16_acc2); |
| 1617 | } |
| 1618 | |
| 1619 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X16_ACC2, elements_div_16) { |
| 1620 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1621 | for (size_t elements = 32; elements < 160; elements += 16) { |
| 1622 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1623 | .elements(elements) |
| 1624 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x16_acc2); |
| 1625 | } |
| 1626 | } |
| 1627 | |
| 1628 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X16_ACC2, elements_lt_16) { |
| 1629 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1630 | for (size_t elements = 1; elements < 16; elements++) { |
| 1631 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1632 | .elements(elements) |
| 1633 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x16_acc2); |
| 1634 | } |
| 1635 | } |
| 1636 | |
| 1637 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X16_ACC2, elements_gt_16) { |
| 1638 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1639 | for (size_t elements = 17; elements < 32; elements++) { |
| 1640 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1641 | .elements(elements) |
| 1642 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x16_acc2); |
| 1643 | } |
| 1644 | } |
| 1645 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1646 | |
| 1647 | |
| 1648 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1649 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X16_ACC4, elements_eq_16) { |
| 1650 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1651 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1652 | .elements(16) |
| 1653 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x16_acc4); |
| 1654 | } |
| 1655 | |
| 1656 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X16_ACC4, elements_div_16) { |
| 1657 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1658 | for (size_t elements = 32; elements < 160; elements += 16) { |
| 1659 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1660 | .elements(elements) |
| 1661 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x16_acc4); |
| 1662 | } |
| 1663 | } |
| 1664 | |
| 1665 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X16_ACC4, elements_lt_16) { |
| 1666 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1667 | for (size_t elements = 1; elements < 16; elements++) { |
| 1668 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1669 | .elements(elements) |
| 1670 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x16_acc4); |
| 1671 | } |
| 1672 | } |
| 1673 | |
| 1674 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X16_ACC4, elements_gt_16) { |
| 1675 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1676 | for (size_t elements = 17; elements < 32; elements++) { |
| 1677 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1678 | .elements(elements) |
| 1679 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x16_acc4); |
| 1680 | } |
| 1681 | } |
| 1682 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1683 | |
| 1684 | |
| 1685 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1686 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X20, elements_eq_20) { |
| 1687 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1688 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1689 | .elements(20) |
| 1690 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x20); |
| 1691 | } |
| 1692 | |
| 1693 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X20, elements_div_20) { |
| 1694 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1695 | for (size_t elements = 40; elements < 200; elements += 20) { |
| 1696 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1697 | .elements(elements) |
| 1698 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x20); |
| 1699 | } |
| 1700 | } |
| 1701 | |
| 1702 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X20, elements_lt_20) { |
| 1703 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1704 | for (size_t elements = 1; elements < 20; elements++) { |
| 1705 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1706 | .elements(elements) |
| 1707 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x20); |
| 1708 | } |
| 1709 | } |
| 1710 | |
| 1711 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X20, elements_gt_20) { |
| 1712 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1713 | for (size_t elements = 21; elements < 40; elements++) { |
| 1714 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1715 | .elements(elements) |
| 1716 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x20); |
| 1717 | } |
| 1718 | } |
| 1719 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1720 | |
| 1721 | |
| 1722 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1723 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X20_ACC2, elements_eq_20) { |
| 1724 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1725 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1726 | .elements(20) |
| 1727 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x20_acc2); |
| 1728 | } |
| 1729 | |
| 1730 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X20_ACC2, elements_div_20) { |
| 1731 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1732 | for (size_t elements = 40; elements < 200; elements += 20) { |
| 1733 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1734 | .elements(elements) |
| 1735 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x20_acc2); |
| 1736 | } |
| 1737 | } |
| 1738 | |
| 1739 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X20_ACC2, elements_lt_20) { |
| 1740 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1741 | for (size_t elements = 1; elements < 20; elements++) { |
| 1742 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1743 | .elements(elements) |
| 1744 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x20_acc2); |
| 1745 | } |
| 1746 | } |
| 1747 | |
| 1748 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X20_ACC2, elements_gt_20) { |
| 1749 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1750 | for (size_t elements = 21; elements < 40; elements++) { |
| 1751 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1752 | .elements(elements) |
| 1753 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x20_acc2); |
| 1754 | } |
| 1755 | } |
| 1756 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1757 | |
| 1758 | |
| 1759 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1760 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X20_ACC5, elements_eq_20) { |
| 1761 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1762 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1763 | .elements(20) |
| 1764 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x20_acc5); |
| 1765 | } |
| 1766 | |
| 1767 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X20_ACC5, elements_div_20) { |
| 1768 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1769 | for (size_t elements = 40; elements < 200; elements += 20) { |
| 1770 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1771 | .elements(elements) |
| 1772 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x20_acc5); |
| 1773 | } |
| 1774 | } |
| 1775 | |
| 1776 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X20_ACC5, elements_lt_20) { |
| 1777 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1778 | for (size_t elements = 1; elements < 20; elements++) { |
| 1779 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1780 | .elements(elements) |
| 1781 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x20_acc5); |
| 1782 | } |
| 1783 | } |
| 1784 | |
| 1785 | TEST(F32_RADDSTOREEXPMINUSMAX__NEONFMA_LUT64_P2_X20_ACC5, elements_gt_20) { |
| 1786 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1787 | for (size_t elements = 21; elements < 40; elements++) { |
| 1788 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1789 | .elements(elements) |
| 1790 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__neonfma_lut64_p2_x20_acc5); |
| 1791 | } |
| 1792 | } |
| 1793 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1794 | |
| 1795 | |
| Marat Dukhan | 4c4eb00 | 2019-12-08 21:27:49 -0800 | [diff] [blame] | 1796 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| Marat Dukhan | b39689d | 2020-01-24 13:32:20 -0800 | [diff] [blame] | 1797 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X4, elements_eq_4) { |
| 1798 | TEST_REQUIRES_X86_SSE2; |
| 1799 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1800 | .elements(4) |
| 1801 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x4); |
| 1802 | } |
| 1803 | |
| 1804 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X4, elements_div_4) { |
| 1805 | TEST_REQUIRES_X86_SSE2; |
| 1806 | for (size_t elements = 8; elements < 40; elements += 4) { |
| 1807 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1808 | .elements(elements) |
| 1809 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x4); |
| 1810 | } |
| 1811 | } |
| 1812 | |
| 1813 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X4, elements_lt_4) { |
| 1814 | TEST_REQUIRES_X86_SSE2; |
| 1815 | for (size_t elements = 1; elements < 4; elements++) { |
| 1816 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1817 | .elements(elements) |
| 1818 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x4); |
| 1819 | } |
| 1820 | } |
| 1821 | |
| 1822 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X4, elements_gt_4) { |
| 1823 | TEST_REQUIRES_X86_SSE2; |
| 1824 | for (size_t elements = 5; elements < 8; elements++) { |
| 1825 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1826 | .elements(elements) |
| 1827 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x4); |
| 1828 | } |
| 1829 | } |
| 1830 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1831 | |
| 1832 | |
| 1833 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1834 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X8, elements_eq_8) { |
| 1835 | TEST_REQUIRES_X86_SSE2; |
| 1836 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1837 | .elements(8) |
| 1838 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x8); |
| 1839 | } |
| 1840 | |
| 1841 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X8, elements_div_8) { |
| 1842 | TEST_REQUIRES_X86_SSE2; |
| 1843 | for (size_t elements = 16; elements < 80; elements += 8) { |
| 1844 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1845 | .elements(elements) |
| 1846 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x8); |
| 1847 | } |
| 1848 | } |
| 1849 | |
| 1850 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X8, elements_lt_8) { |
| 1851 | TEST_REQUIRES_X86_SSE2; |
| 1852 | for (size_t elements = 1; elements < 8; elements++) { |
| 1853 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1854 | .elements(elements) |
| 1855 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x8); |
| 1856 | } |
| 1857 | } |
| 1858 | |
| 1859 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X8, elements_gt_8) { |
| 1860 | TEST_REQUIRES_X86_SSE2; |
| 1861 | for (size_t elements = 9; elements < 16; elements++) { |
| 1862 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1863 | .elements(elements) |
| 1864 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x8); |
| 1865 | } |
| 1866 | } |
| 1867 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1868 | |
| 1869 | |
| 1870 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1871 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X8_ACC2, elements_eq_8) { |
| 1872 | TEST_REQUIRES_X86_SSE2; |
| 1873 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1874 | .elements(8) |
| 1875 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x8_acc2); |
| 1876 | } |
| 1877 | |
| 1878 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X8_ACC2, elements_div_8) { |
| 1879 | TEST_REQUIRES_X86_SSE2; |
| 1880 | for (size_t elements = 16; elements < 80; elements += 8) { |
| 1881 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1882 | .elements(elements) |
| 1883 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x8_acc2); |
| 1884 | } |
| 1885 | } |
| 1886 | |
| 1887 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X8_ACC2, elements_lt_8) { |
| 1888 | TEST_REQUIRES_X86_SSE2; |
| 1889 | for (size_t elements = 1; elements < 8; elements++) { |
| 1890 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1891 | .elements(elements) |
| 1892 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x8_acc2); |
| 1893 | } |
| 1894 | } |
| 1895 | |
| 1896 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X8_ACC2, elements_gt_8) { |
| 1897 | TEST_REQUIRES_X86_SSE2; |
| 1898 | for (size_t elements = 9; elements < 16; elements++) { |
| 1899 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1900 | .elements(elements) |
| 1901 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x8_acc2); |
| 1902 | } |
| 1903 | } |
| 1904 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1905 | |
| 1906 | |
| 1907 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1908 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X12, elements_eq_12) { |
| 1909 | TEST_REQUIRES_X86_SSE2; |
| 1910 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1911 | .elements(12) |
| 1912 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x12); |
| 1913 | } |
| 1914 | |
| 1915 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X12, elements_div_12) { |
| 1916 | TEST_REQUIRES_X86_SSE2; |
| 1917 | for (size_t elements = 24; elements < 120; elements += 12) { |
| 1918 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1919 | .elements(elements) |
| 1920 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x12); |
| 1921 | } |
| 1922 | } |
| 1923 | |
| 1924 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X12, elements_lt_12) { |
| 1925 | TEST_REQUIRES_X86_SSE2; |
| 1926 | for (size_t elements = 1; elements < 12; elements++) { |
| 1927 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1928 | .elements(elements) |
| 1929 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x12); |
| 1930 | } |
| 1931 | } |
| 1932 | |
| 1933 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X12, elements_gt_12) { |
| 1934 | TEST_REQUIRES_X86_SSE2; |
| 1935 | for (size_t elements = 13; elements < 24; elements++) { |
| 1936 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1937 | .elements(elements) |
| 1938 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x12); |
| 1939 | } |
| 1940 | } |
| 1941 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1942 | |
| 1943 | |
| 1944 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1945 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X12_ACC2, elements_eq_12) { |
| 1946 | TEST_REQUIRES_X86_SSE2; |
| 1947 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1948 | .elements(12) |
| 1949 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x12_acc2); |
| 1950 | } |
| 1951 | |
| 1952 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X12_ACC2, elements_div_12) { |
| 1953 | TEST_REQUIRES_X86_SSE2; |
| 1954 | for (size_t elements = 24; elements < 120; elements += 12) { |
| 1955 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1956 | .elements(elements) |
| 1957 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x12_acc2); |
| 1958 | } |
| 1959 | } |
| 1960 | |
| 1961 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X12_ACC2, elements_lt_12) { |
| 1962 | TEST_REQUIRES_X86_SSE2; |
| 1963 | for (size_t elements = 1; elements < 12; elements++) { |
| 1964 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1965 | .elements(elements) |
| 1966 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x12_acc2); |
| 1967 | } |
| 1968 | } |
| 1969 | |
| 1970 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X12_ACC2, elements_gt_12) { |
| 1971 | TEST_REQUIRES_X86_SSE2; |
| 1972 | for (size_t elements = 13; elements < 24; elements++) { |
| 1973 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1974 | .elements(elements) |
| 1975 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x12_acc2); |
| 1976 | } |
| 1977 | } |
| 1978 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1979 | |
| 1980 | |
| 1981 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1982 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X12_ACC3, elements_eq_12) { |
| 1983 | TEST_REQUIRES_X86_SSE2; |
| 1984 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1985 | .elements(12) |
| 1986 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x12_acc3); |
| 1987 | } |
| 1988 | |
| 1989 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X12_ACC3, elements_div_12) { |
| 1990 | TEST_REQUIRES_X86_SSE2; |
| 1991 | for (size_t elements = 24; elements < 120; elements += 12) { |
| 1992 | RAddStoreExpMinusMaxMicrokernelTester() |
| 1993 | .elements(elements) |
| 1994 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x12_acc3); |
| 1995 | } |
| 1996 | } |
| 1997 | |
| 1998 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X12_ACC3, elements_lt_12) { |
| 1999 | TEST_REQUIRES_X86_SSE2; |
| 2000 | for (size_t elements = 1; elements < 12; elements++) { |
| 2001 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2002 | .elements(elements) |
| 2003 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x12_acc3); |
| 2004 | } |
| 2005 | } |
| 2006 | |
| 2007 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X12_ACC3, elements_gt_12) { |
| 2008 | TEST_REQUIRES_X86_SSE2; |
| 2009 | for (size_t elements = 13; elements < 24; elements++) { |
| 2010 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2011 | .elements(elements) |
| 2012 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x12_acc3); |
| 2013 | } |
| 2014 | } |
| 2015 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2016 | |
| 2017 | |
| 2018 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2019 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X16, elements_eq_16) { |
| 2020 | TEST_REQUIRES_X86_SSE2; |
| 2021 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2022 | .elements(16) |
| 2023 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x16); |
| 2024 | } |
| 2025 | |
| 2026 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X16, elements_div_16) { |
| 2027 | TEST_REQUIRES_X86_SSE2; |
| 2028 | for (size_t elements = 32; elements < 160; elements += 16) { |
| 2029 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2030 | .elements(elements) |
| 2031 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x16); |
| 2032 | } |
| 2033 | } |
| 2034 | |
| 2035 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X16, elements_lt_16) { |
| 2036 | TEST_REQUIRES_X86_SSE2; |
| 2037 | for (size_t elements = 1; elements < 16; elements++) { |
| 2038 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2039 | .elements(elements) |
| 2040 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x16); |
| 2041 | } |
| 2042 | } |
| 2043 | |
| 2044 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X16, elements_gt_16) { |
| 2045 | TEST_REQUIRES_X86_SSE2; |
| 2046 | for (size_t elements = 17; elements < 32; elements++) { |
| 2047 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2048 | .elements(elements) |
| 2049 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x16); |
| 2050 | } |
| 2051 | } |
| 2052 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2053 | |
| 2054 | |
| 2055 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2056 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X16_ACC2, elements_eq_16) { |
| 2057 | TEST_REQUIRES_X86_SSE2; |
| 2058 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2059 | .elements(16) |
| 2060 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x16_acc2); |
| 2061 | } |
| 2062 | |
| 2063 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X16_ACC2, elements_div_16) { |
| 2064 | TEST_REQUIRES_X86_SSE2; |
| 2065 | for (size_t elements = 32; elements < 160; elements += 16) { |
| 2066 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2067 | .elements(elements) |
| 2068 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x16_acc2); |
| 2069 | } |
| 2070 | } |
| 2071 | |
| 2072 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X16_ACC2, elements_lt_16) { |
| 2073 | TEST_REQUIRES_X86_SSE2; |
| 2074 | for (size_t elements = 1; elements < 16; elements++) { |
| 2075 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2076 | .elements(elements) |
| 2077 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x16_acc2); |
| 2078 | } |
| 2079 | } |
| 2080 | |
| 2081 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X16_ACC2, elements_gt_16) { |
| 2082 | TEST_REQUIRES_X86_SSE2; |
| 2083 | for (size_t elements = 17; elements < 32; elements++) { |
| 2084 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2085 | .elements(elements) |
| 2086 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x16_acc2); |
| 2087 | } |
| 2088 | } |
| 2089 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2090 | |
| 2091 | |
| 2092 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2093 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X16_ACC4, elements_eq_16) { |
| 2094 | TEST_REQUIRES_X86_SSE2; |
| 2095 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2096 | .elements(16) |
| 2097 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x16_acc4); |
| 2098 | } |
| 2099 | |
| 2100 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X16_ACC4, elements_div_16) { |
| 2101 | TEST_REQUIRES_X86_SSE2; |
| 2102 | for (size_t elements = 32; elements < 160; elements += 16) { |
| 2103 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2104 | .elements(elements) |
| 2105 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x16_acc4); |
| 2106 | } |
| 2107 | } |
| 2108 | |
| 2109 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X16_ACC4, elements_lt_16) { |
| 2110 | TEST_REQUIRES_X86_SSE2; |
| 2111 | for (size_t elements = 1; elements < 16; elements++) { |
| 2112 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2113 | .elements(elements) |
| 2114 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x16_acc4); |
| 2115 | } |
| 2116 | } |
| 2117 | |
| 2118 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X16_ACC4, elements_gt_16) { |
| 2119 | TEST_REQUIRES_X86_SSE2; |
| 2120 | for (size_t elements = 17; elements < 32; elements++) { |
| 2121 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2122 | .elements(elements) |
| 2123 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x16_acc4); |
| 2124 | } |
| 2125 | } |
| 2126 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2127 | |
| 2128 | |
| 2129 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2130 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X20, elements_eq_20) { |
| 2131 | TEST_REQUIRES_X86_SSE2; |
| 2132 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2133 | .elements(20) |
| 2134 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x20); |
| 2135 | } |
| 2136 | |
| 2137 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X20, elements_div_20) { |
| 2138 | TEST_REQUIRES_X86_SSE2; |
| 2139 | for (size_t elements = 40; elements < 200; elements += 20) { |
| 2140 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2141 | .elements(elements) |
| 2142 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x20); |
| 2143 | } |
| 2144 | } |
| 2145 | |
| 2146 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X20, elements_lt_20) { |
| 2147 | TEST_REQUIRES_X86_SSE2; |
| 2148 | for (size_t elements = 1; elements < 20; elements++) { |
| 2149 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2150 | .elements(elements) |
| 2151 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x20); |
| 2152 | } |
| 2153 | } |
| 2154 | |
| 2155 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X20, elements_gt_20) { |
| 2156 | TEST_REQUIRES_X86_SSE2; |
| 2157 | for (size_t elements = 21; elements < 40; elements++) { |
| 2158 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2159 | .elements(elements) |
| 2160 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x20); |
| 2161 | } |
| 2162 | } |
| 2163 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2164 | |
| 2165 | |
| 2166 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2167 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X20_ACC2, elements_eq_20) { |
| 2168 | TEST_REQUIRES_X86_SSE2; |
| 2169 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2170 | .elements(20) |
| 2171 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x20_acc2); |
| 2172 | } |
| 2173 | |
| 2174 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X20_ACC2, elements_div_20) { |
| 2175 | TEST_REQUIRES_X86_SSE2; |
| 2176 | for (size_t elements = 40; elements < 200; elements += 20) { |
| 2177 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2178 | .elements(elements) |
| 2179 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x20_acc2); |
| 2180 | } |
| 2181 | } |
| 2182 | |
| 2183 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X20_ACC2, elements_lt_20) { |
| 2184 | TEST_REQUIRES_X86_SSE2; |
| 2185 | for (size_t elements = 1; elements < 20; elements++) { |
| 2186 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2187 | .elements(elements) |
| 2188 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x20_acc2); |
| 2189 | } |
| 2190 | } |
| 2191 | |
| 2192 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X20_ACC2, elements_gt_20) { |
| 2193 | TEST_REQUIRES_X86_SSE2; |
| 2194 | for (size_t elements = 21; elements < 40; elements++) { |
| 2195 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2196 | .elements(elements) |
| 2197 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x20_acc2); |
| 2198 | } |
| 2199 | } |
| 2200 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2201 | |
| 2202 | |
| 2203 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2204 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X20_ACC5, elements_eq_20) { |
| 2205 | TEST_REQUIRES_X86_SSE2; |
| 2206 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2207 | .elements(20) |
| 2208 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x20_acc5); |
| 2209 | } |
| 2210 | |
| 2211 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X20_ACC5, elements_div_20) { |
| 2212 | TEST_REQUIRES_X86_SSE2; |
| 2213 | for (size_t elements = 40; elements < 200; elements += 20) { |
| 2214 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2215 | .elements(elements) |
| 2216 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x20_acc5); |
| 2217 | } |
| 2218 | } |
| 2219 | |
| 2220 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X20_ACC5, elements_lt_20) { |
| 2221 | TEST_REQUIRES_X86_SSE2; |
| 2222 | for (size_t elements = 1; elements < 20; elements++) { |
| 2223 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2224 | .elements(elements) |
| 2225 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x20_acc5); |
| 2226 | } |
| 2227 | } |
| 2228 | |
| 2229 | TEST(F32_RADDSTOREEXPMINUSMAX__SSE2_P5_X20_ACC5, elements_gt_20) { |
| 2230 | TEST_REQUIRES_X86_SSE2; |
| 2231 | for (size_t elements = 21; elements < 40; elements++) { |
| 2232 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2233 | .elements(elements) |
| 2234 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__sse2_p5_x20_acc5); |
| 2235 | } |
| 2236 | } |
| 2237 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2238 | |
| 2239 | |
| 2240 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| Marat Dukhan | 4c4eb00 | 2019-12-08 21:27:49 -0800 | [diff] [blame] | 2241 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X64, elements_eq_64) { |
| Marat Dukhan | 9757953 | 2019-10-18 16:40:39 -0700 | [diff] [blame] | 2242 | TEST_REQUIRES_X86_AVX2; |
| 2243 | RAddStoreExpMinusMaxMicrokernelTester() |
| Marat Dukhan | 4c4eb00 | 2019-12-08 21:27:49 -0800 | [diff] [blame] | 2244 | .elements(64) |
| 2245 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x64); |
| Marat Dukhan | 9757953 | 2019-10-18 16:40:39 -0700 | [diff] [blame] | 2246 | } |
| 2247 | |
| Marat Dukhan | 4c4eb00 | 2019-12-08 21:27:49 -0800 | [diff] [blame] | 2248 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X64, elements_div_64) { |
| Marat Dukhan | 9757953 | 2019-10-18 16:40:39 -0700 | [diff] [blame] | 2249 | TEST_REQUIRES_X86_AVX2; |
| Marat Dukhan | 4c4eb00 | 2019-12-08 21:27:49 -0800 | [diff] [blame] | 2250 | for (size_t elements = 128; elements < 640; elements += 64) { |
| Marat Dukhan | 9757953 | 2019-10-18 16:40:39 -0700 | [diff] [blame] | 2251 | RAddStoreExpMinusMaxMicrokernelTester() |
| Marat Dukhan | 4c4eb00 | 2019-12-08 21:27:49 -0800 | [diff] [blame] | 2252 | .elements(elements) |
| 2253 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x64); |
| Marat Dukhan | 9757953 | 2019-10-18 16:40:39 -0700 | [diff] [blame] | 2254 | } |
| 2255 | } |
| 2256 | |
| Marat Dukhan | 4c4eb00 | 2019-12-08 21:27:49 -0800 | [diff] [blame] | 2257 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X64, elements_lt_64) { |
| Marat Dukhan | 9757953 | 2019-10-18 16:40:39 -0700 | [diff] [blame] | 2258 | TEST_REQUIRES_X86_AVX2; |
| Marat Dukhan | 4c4eb00 | 2019-12-08 21:27:49 -0800 | [diff] [blame] | 2259 | for (size_t elements = 1; elements < 64; elements++) { |
| Marat Dukhan | 9757953 | 2019-10-18 16:40:39 -0700 | [diff] [blame] | 2260 | RAddStoreExpMinusMaxMicrokernelTester() |
| Marat Dukhan | 4c4eb00 | 2019-12-08 21:27:49 -0800 | [diff] [blame] | 2261 | .elements(elements) |
| 2262 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x64); |
| Marat Dukhan | 9757953 | 2019-10-18 16:40:39 -0700 | [diff] [blame] | 2263 | } |
| 2264 | } |
| 2265 | |
| Marat Dukhan | 4c4eb00 | 2019-12-08 21:27:49 -0800 | [diff] [blame] | 2266 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X64, elements_gt_64) { |
| 2267 | TEST_REQUIRES_X86_AVX2; |
| 2268 | for (size_t elements = 65; elements < 128; elements++) { |
| 2269 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2270 | .elements(elements) |
| 2271 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x64); |
| 2272 | } |
| 2273 | } |
| 2274 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2275 | |
| 2276 | |
| 2277 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2278 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X64_ACC2, elements_eq_64) { |
| 2279 | TEST_REQUIRES_X86_AVX2; |
| 2280 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2281 | .elements(64) |
| 2282 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x64_acc2); |
| 2283 | } |
| 2284 | |
| 2285 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X64_ACC2, elements_div_64) { |
| 2286 | TEST_REQUIRES_X86_AVX2; |
| 2287 | for (size_t elements = 128; elements < 640; elements += 64) { |
| 2288 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2289 | .elements(elements) |
| 2290 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x64_acc2); |
| 2291 | } |
| 2292 | } |
| 2293 | |
| 2294 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X64_ACC2, elements_lt_64) { |
| 2295 | TEST_REQUIRES_X86_AVX2; |
| 2296 | for (size_t elements = 1; elements < 64; elements++) { |
| 2297 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2298 | .elements(elements) |
| 2299 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x64_acc2); |
| 2300 | } |
| 2301 | } |
| 2302 | |
| 2303 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X64_ACC2, elements_gt_64) { |
| 2304 | TEST_REQUIRES_X86_AVX2; |
| 2305 | for (size_t elements = 65; elements < 128; elements++) { |
| 2306 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2307 | .elements(elements) |
| 2308 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x64_acc2); |
| 2309 | } |
| 2310 | } |
| 2311 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2312 | |
| 2313 | |
| 2314 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2315 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X64_ACC4, elements_eq_64) { |
| 2316 | TEST_REQUIRES_X86_AVX2; |
| 2317 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2318 | .elements(64) |
| 2319 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x64_acc4); |
| 2320 | } |
| 2321 | |
| 2322 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X64_ACC4, elements_div_64) { |
| 2323 | TEST_REQUIRES_X86_AVX2; |
| 2324 | for (size_t elements = 128; elements < 640; elements += 64) { |
| 2325 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2326 | .elements(elements) |
| 2327 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x64_acc4); |
| 2328 | } |
| 2329 | } |
| 2330 | |
| 2331 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X64_ACC4, elements_lt_64) { |
| 2332 | TEST_REQUIRES_X86_AVX2; |
| 2333 | for (size_t elements = 1; elements < 64; elements++) { |
| 2334 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2335 | .elements(elements) |
| 2336 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x64_acc4); |
| 2337 | } |
| 2338 | } |
| 2339 | |
| 2340 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X64_ACC4, elements_gt_64) { |
| 2341 | TEST_REQUIRES_X86_AVX2; |
| 2342 | for (size_t elements = 65; elements < 128; elements++) { |
| 2343 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2344 | .elements(elements) |
| 2345 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x64_acc4); |
| 2346 | } |
| 2347 | } |
| 2348 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2349 | |
| 2350 | |
| 2351 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2352 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X72, elements_eq_72) { |
| 2353 | TEST_REQUIRES_X86_AVX2; |
| 2354 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2355 | .elements(72) |
| 2356 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x72); |
| 2357 | } |
| 2358 | |
| 2359 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X72, elements_div_72) { |
| 2360 | TEST_REQUIRES_X86_AVX2; |
| 2361 | for (size_t elements = 144; elements < 720; elements += 72) { |
| 2362 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2363 | .elements(elements) |
| 2364 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x72); |
| 2365 | } |
| 2366 | } |
| 2367 | |
| 2368 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X72, elements_lt_72) { |
| 2369 | TEST_REQUIRES_X86_AVX2; |
| 2370 | for (size_t elements = 1; elements < 72; elements++) { |
| 2371 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2372 | .elements(elements) |
| 2373 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x72); |
| 2374 | } |
| 2375 | } |
| 2376 | |
| 2377 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X72, elements_gt_72) { |
| 2378 | TEST_REQUIRES_X86_AVX2; |
| 2379 | for (size_t elements = 73; elements < 144; elements++) { |
| 2380 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2381 | .elements(elements) |
| 2382 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x72); |
| 2383 | } |
| 2384 | } |
| 2385 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2386 | |
| 2387 | |
| 2388 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2389 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X72_ACC3, elements_eq_72) { |
| 2390 | TEST_REQUIRES_X86_AVX2; |
| 2391 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2392 | .elements(72) |
| 2393 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x72_acc3); |
| 2394 | } |
| 2395 | |
| 2396 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X72_ACC3, elements_div_72) { |
| 2397 | TEST_REQUIRES_X86_AVX2; |
| 2398 | for (size_t elements = 144; elements < 720; elements += 72) { |
| 2399 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2400 | .elements(elements) |
| 2401 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x72_acc3); |
| 2402 | } |
| 2403 | } |
| 2404 | |
| 2405 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X72_ACC3, elements_lt_72) { |
| 2406 | TEST_REQUIRES_X86_AVX2; |
| 2407 | for (size_t elements = 1; elements < 72; elements++) { |
| 2408 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2409 | .elements(elements) |
| 2410 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x72_acc3); |
| 2411 | } |
| 2412 | } |
| 2413 | |
| 2414 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X72_ACC3, elements_gt_72) { |
| 2415 | TEST_REQUIRES_X86_AVX2; |
| 2416 | for (size_t elements = 73; elements < 144; elements++) { |
| 2417 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2418 | .elements(elements) |
| 2419 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x72_acc3); |
| 2420 | } |
| 2421 | } |
| 2422 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2423 | |
| 2424 | |
| 2425 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2426 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X80, elements_eq_80) { |
| 2427 | TEST_REQUIRES_X86_AVX2; |
| 2428 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2429 | .elements(80) |
| 2430 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x80); |
| 2431 | } |
| 2432 | |
| 2433 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X80, elements_div_80) { |
| 2434 | TEST_REQUIRES_X86_AVX2; |
| 2435 | for (size_t elements = 160; elements < 800; elements += 80) { |
| 2436 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2437 | .elements(elements) |
| 2438 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x80); |
| 2439 | } |
| 2440 | } |
| 2441 | |
| 2442 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X80, elements_lt_80) { |
| 2443 | TEST_REQUIRES_X86_AVX2; |
| 2444 | for (size_t elements = 1; elements < 80; elements++) { |
| 2445 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2446 | .elements(elements) |
| 2447 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x80); |
| 2448 | } |
| 2449 | } |
| 2450 | |
| 2451 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X80, elements_gt_80) { |
| 2452 | TEST_REQUIRES_X86_AVX2; |
| 2453 | for (size_t elements = 81; elements < 160; elements++) { |
| 2454 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2455 | .elements(elements) |
| 2456 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x80); |
| 2457 | } |
| 2458 | } |
| 2459 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2460 | |
| 2461 | |
| 2462 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2463 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X80_ACC2, elements_eq_80) { |
| 2464 | TEST_REQUIRES_X86_AVX2; |
| 2465 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2466 | .elements(80) |
| 2467 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x80_acc2); |
| 2468 | } |
| 2469 | |
| 2470 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X80_ACC2, elements_div_80) { |
| 2471 | TEST_REQUIRES_X86_AVX2; |
| 2472 | for (size_t elements = 160; elements < 800; elements += 80) { |
| 2473 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2474 | .elements(elements) |
| 2475 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x80_acc2); |
| 2476 | } |
| 2477 | } |
| 2478 | |
| 2479 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X80_ACC2, elements_lt_80) { |
| 2480 | TEST_REQUIRES_X86_AVX2; |
| 2481 | for (size_t elements = 1; elements < 80; elements++) { |
| 2482 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2483 | .elements(elements) |
| 2484 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x80_acc2); |
| 2485 | } |
| 2486 | } |
| 2487 | |
| 2488 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X80_ACC2, elements_gt_80) { |
| 2489 | TEST_REQUIRES_X86_AVX2; |
| 2490 | for (size_t elements = 81; elements < 160; elements++) { |
| 2491 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2492 | .elements(elements) |
| 2493 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x80_acc2); |
| 2494 | } |
| 2495 | } |
| 2496 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2497 | |
| 2498 | |
| 2499 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2500 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X80_ACC5, elements_eq_80) { |
| 2501 | TEST_REQUIRES_X86_AVX2; |
| 2502 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2503 | .elements(80) |
| 2504 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x80_acc5); |
| 2505 | } |
| 2506 | |
| 2507 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X80_ACC5, elements_div_80) { |
| 2508 | TEST_REQUIRES_X86_AVX2; |
| 2509 | for (size_t elements = 160; elements < 800; elements += 80) { |
| 2510 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2511 | .elements(elements) |
| 2512 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x80_acc5); |
| 2513 | } |
| 2514 | } |
| 2515 | |
| 2516 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X80_ACC5, elements_lt_80) { |
| 2517 | TEST_REQUIRES_X86_AVX2; |
| 2518 | for (size_t elements = 1; elements < 80; elements++) { |
| 2519 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2520 | .elements(elements) |
| 2521 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x80_acc5); |
| 2522 | } |
| 2523 | } |
| 2524 | |
| 2525 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X80_ACC5, elements_gt_80) { |
| 2526 | TEST_REQUIRES_X86_AVX2; |
| 2527 | for (size_t elements = 81; elements < 160; elements++) { |
| 2528 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2529 | .elements(elements) |
| 2530 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x80_acc5); |
| 2531 | } |
| 2532 | } |
| 2533 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2534 | |
| 2535 | |
| 2536 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2537 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X96, elements_eq_96) { |
| 2538 | TEST_REQUIRES_X86_AVX2; |
| 2539 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2540 | .elements(96) |
| 2541 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x96); |
| 2542 | } |
| 2543 | |
| 2544 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X96, elements_div_96) { |
| 2545 | TEST_REQUIRES_X86_AVX2; |
| 2546 | for (size_t elements = 192; elements < 960; elements += 96) { |
| 2547 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2548 | .elements(elements) |
| 2549 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x96); |
| 2550 | } |
| 2551 | } |
| 2552 | |
| 2553 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X96, elements_lt_96) { |
| 2554 | TEST_REQUIRES_X86_AVX2; |
| 2555 | for (size_t elements = 1; elements < 96; elements++) { |
| 2556 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2557 | .elements(elements) |
| 2558 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x96); |
| 2559 | } |
| 2560 | } |
| 2561 | |
| 2562 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X96, elements_gt_96) { |
| 2563 | TEST_REQUIRES_X86_AVX2; |
| 2564 | for (size_t elements = 97; elements < 192; elements++) { |
| 2565 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2566 | .elements(elements) |
| 2567 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x96); |
| 2568 | } |
| 2569 | } |
| 2570 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2571 | |
| 2572 | |
| 2573 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2574 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X96_ACC2, elements_eq_96) { |
| 2575 | TEST_REQUIRES_X86_AVX2; |
| 2576 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2577 | .elements(96) |
| 2578 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x96_acc2); |
| 2579 | } |
| 2580 | |
| 2581 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X96_ACC2, elements_div_96) { |
| 2582 | TEST_REQUIRES_X86_AVX2; |
| 2583 | for (size_t elements = 192; elements < 960; elements += 96) { |
| 2584 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2585 | .elements(elements) |
| 2586 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x96_acc2); |
| 2587 | } |
| 2588 | } |
| 2589 | |
| 2590 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X96_ACC2, elements_lt_96) { |
| 2591 | TEST_REQUIRES_X86_AVX2; |
| 2592 | for (size_t elements = 1; elements < 96; elements++) { |
| 2593 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2594 | .elements(elements) |
| 2595 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x96_acc2); |
| 2596 | } |
| 2597 | } |
| 2598 | |
| 2599 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X96_ACC2, elements_gt_96) { |
| 2600 | TEST_REQUIRES_X86_AVX2; |
| 2601 | for (size_t elements = 97; elements < 192; elements++) { |
| 2602 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2603 | .elements(elements) |
| 2604 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x96_acc2); |
| 2605 | } |
| 2606 | } |
| 2607 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2608 | |
| 2609 | |
| 2610 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2611 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X96_ACC3, elements_eq_96) { |
| 2612 | TEST_REQUIRES_X86_AVX2; |
| 2613 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2614 | .elements(96) |
| 2615 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x96_acc3); |
| 2616 | } |
| 2617 | |
| 2618 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X96_ACC3, elements_div_96) { |
| 2619 | TEST_REQUIRES_X86_AVX2; |
| 2620 | for (size_t elements = 192; elements < 960; elements += 96) { |
| 2621 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2622 | .elements(elements) |
| 2623 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x96_acc3); |
| 2624 | } |
| 2625 | } |
| 2626 | |
| 2627 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X96_ACC3, elements_lt_96) { |
| 2628 | TEST_REQUIRES_X86_AVX2; |
| 2629 | for (size_t elements = 1; elements < 96; elements++) { |
| 2630 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2631 | .elements(elements) |
| 2632 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x96_acc3); |
| 2633 | } |
| 2634 | } |
| 2635 | |
| 2636 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X96_ACC3, elements_gt_96) { |
| 2637 | TEST_REQUIRES_X86_AVX2; |
| 2638 | for (size_t elements = 97; elements < 192; elements++) { |
| 2639 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2640 | .elements(elements) |
| 2641 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x96_acc3); |
| 2642 | } |
| 2643 | } |
| 2644 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2645 | |
| 2646 | |
| 2647 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2648 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X96_ACC6, elements_eq_96) { |
| 2649 | TEST_REQUIRES_X86_AVX2; |
| 2650 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2651 | .elements(96) |
| 2652 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x96_acc6); |
| 2653 | } |
| 2654 | |
| 2655 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X96_ACC6, elements_div_96) { |
| 2656 | TEST_REQUIRES_X86_AVX2; |
| 2657 | for (size_t elements = 192; elements < 960; elements += 96) { |
| 2658 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2659 | .elements(elements) |
| 2660 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x96_acc6); |
| 2661 | } |
| 2662 | } |
| 2663 | |
| 2664 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X96_ACC6, elements_lt_96) { |
| 2665 | TEST_REQUIRES_X86_AVX2; |
| 2666 | for (size_t elements = 1; elements < 96; elements++) { |
| 2667 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2668 | .elements(elements) |
| 2669 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x96_acc6); |
| 2670 | } |
| 2671 | } |
| 2672 | |
| 2673 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX2_P5_X96_ACC6, elements_gt_96) { |
| 2674 | TEST_REQUIRES_X86_AVX2; |
| 2675 | for (size_t elements = 97; elements < 192; elements++) { |
| 2676 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2677 | .elements(elements) |
| 2678 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx2_p5_x96_acc6); |
| 2679 | } |
| 2680 | } |
| 2681 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2682 | |
| 2683 | |
| 2684 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2685 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X128, elements_eq_128) { |
| Marat Dukhan | 9757953 | 2019-10-18 16:40:39 -0700 | [diff] [blame] | 2686 | TEST_REQUIRES_X86_AVX512F; |
| 2687 | RAddStoreExpMinusMaxMicrokernelTester() |
| Marat Dukhan | 4c4eb00 | 2019-12-08 21:27:49 -0800 | [diff] [blame] | 2688 | .elements(128) |
| 2689 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x128); |
| Marat Dukhan | 9757953 | 2019-10-18 16:40:39 -0700 | [diff] [blame] | 2690 | } |
| 2691 | |
| Marat Dukhan | 4c4eb00 | 2019-12-08 21:27:49 -0800 | [diff] [blame] | 2692 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X128, elements_div_128) { |
| Marat Dukhan | 9757953 | 2019-10-18 16:40:39 -0700 | [diff] [blame] | 2693 | TEST_REQUIRES_X86_AVX512F; |
| Marat Dukhan | 4c4eb00 | 2019-12-08 21:27:49 -0800 | [diff] [blame] | 2694 | for (size_t elements = 256; elements < 1280; elements += 128) { |
| Marat Dukhan | 9757953 | 2019-10-18 16:40:39 -0700 | [diff] [blame] | 2695 | RAddStoreExpMinusMaxMicrokernelTester() |
| Marat Dukhan | 4c4eb00 | 2019-12-08 21:27:49 -0800 | [diff] [blame] | 2696 | .elements(elements) |
| 2697 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x128); |
| Marat Dukhan | 9757953 | 2019-10-18 16:40:39 -0700 | [diff] [blame] | 2698 | } |
| 2699 | } |
| 2700 | |
| Marat Dukhan | 4c4eb00 | 2019-12-08 21:27:49 -0800 | [diff] [blame] | 2701 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X128, elements_lt_128) { |
| Marat Dukhan | 9757953 | 2019-10-18 16:40:39 -0700 | [diff] [blame] | 2702 | TEST_REQUIRES_X86_AVX512F; |
| Marat Dukhan | 4c4eb00 | 2019-12-08 21:27:49 -0800 | [diff] [blame] | 2703 | for (size_t elements = 1; elements < 128; elements++) { |
| Marat Dukhan | 9757953 | 2019-10-18 16:40:39 -0700 | [diff] [blame] | 2704 | RAddStoreExpMinusMaxMicrokernelTester() |
| Marat Dukhan | 4c4eb00 | 2019-12-08 21:27:49 -0800 | [diff] [blame] | 2705 | .elements(elements) |
| 2706 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x128); |
| Marat Dukhan | 9757953 | 2019-10-18 16:40:39 -0700 | [diff] [blame] | 2707 | } |
| 2708 | } |
| Marat Dukhan | 4c4eb00 | 2019-12-08 21:27:49 -0800 | [diff] [blame] | 2709 | |
| 2710 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X128, elements_gt_128) { |
| 2711 | TEST_REQUIRES_X86_AVX512F; |
| 2712 | for (size_t elements = 129; elements < 256; elements++) { |
| 2713 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2714 | .elements(elements) |
| 2715 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x128); |
| 2716 | } |
| 2717 | } |
| 2718 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2719 | |
| 2720 | |
| 2721 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2722 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X128_ACC2, elements_eq_128) { |
| 2723 | TEST_REQUIRES_X86_AVX512F; |
| 2724 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2725 | .elements(128) |
| 2726 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x128_acc2); |
| 2727 | } |
| 2728 | |
| 2729 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X128_ACC2, elements_div_128) { |
| 2730 | TEST_REQUIRES_X86_AVX512F; |
| 2731 | for (size_t elements = 256; elements < 1280; elements += 128) { |
| 2732 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2733 | .elements(elements) |
| 2734 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x128_acc2); |
| 2735 | } |
| 2736 | } |
| 2737 | |
| 2738 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X128_ACC2, elements_lt_128) { |
| 2739 | TEST_REQUIRES_X86_AVX512F; |
| 2740 | for (size_t elements = 1; elements < 128; elements++) { |
| 2741 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2742 | .elements(elements) |
| 2743 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x128_acc2); |
| 2744 | } |
| 2745 | } |
| 2746 | |
| 2747 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X128_ACC2, elements_gt_128) { |
| 2748 | TEST_REQUIRES_X86_AVX512F; |
| 2749 | for (size_t elements = 129; elements < 256; elements++) { |
| 2750 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2751 | .elements(elements) |
| 2752 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x128_acc2); |
| 2753 | } |
| 2754 | } |
| 2755 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2756 | |
| 2757 | |
| 2758 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2759 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X128_ACC4, elements_eq_128) { |
| 2760 | TEST_REQUIRES_X86_AVX512F; |
| 2761 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2762 | .elements(128) |
| 2763 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x128_acc4); |
| 2764 | } |
| 2765 | |
| 2766 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X128_ACC4, elements_div_128) { |
| 2767 | TEST_REQUIRES_X86_AVX512F; |
| 2768 | for (size_t elements = 256; elements < 1280; elements += 128) { |
| 2769 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2770 | .elements(elements) |
| 2771 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x128_acc4); |
| 2772 | } |
| 2773 | } |
| 2774 | |
| 2775 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X128_ACC4, elements_lt_128) { |
| 2776 | TEST_REQUIRES_X86_AVX512F; |
| 2777 | for (size_t elements = 1; elements < 128; elements++) { |
| 2778 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2779 | .elements(elements) |
| 2780 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x128_acc4); |
| 2781 | } |
| 2782 | } |
| 2783 | |
| 2784 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X128_ACC4, elements_gt_128) { |
| 2785 | TEST_REQUIRES_X86_AVX512F; |
| 2786 | for (size_t elements = 129; elements < 256; elements++) { |
| 2787 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2788 | .elements(elements) |
| 2789 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x128_acc4); |
| 2790 | } |
| 2791 | } |
| 2792 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2793 | |
| 2794 | |
| 2795 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2796 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X144, elements_eq_144) { |
| 2797 | TEST_REQUIRES_X86_AVX512F; |
| 2798 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2799 | .elements(144) |
| 2800 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x144); |
| 2801 | } |
| 2802 | |
| 2803 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X144, elements_div_144) { |
| 2804 | TEST_REQUIRES_X86_AVX512F; |
| 2805 | for (size_t elements = 288; elements < 1440; elements += 144) { |
| 2806 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2807 | .elements(elements) |
| 2808 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x144); |
| 2809 | } |
| 2810 | } |
| 2811 | |
| 2812 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X144, elements_lt_144) { |
| 2813 | TEST_REQUIRES_X86_AVX512F; |
| 2814 | for (size_t elements = 1; elements < 144; elements++) { |
| 2815 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2816 | .elements(elements) |
| 2817 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x144); |
| 2818 | } |
| 2819 | } |
| 2820 | |
| 2821 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X144, elements_gt_144) { |
| 2822 | TEST_REQUIRES_X86_AVX512F; |
| 2823 | for (size_t elements = 145; elements < 288; elements++) { |
| 2824 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2825 | .elements(elements) |
| 2826 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x144); |
| 2827 | } |
| 2828 | } |
| 2829 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2830 | |
| 2831 | |
| 2832 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2833 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X144_ACC3, elements_eq_144) { |
| 2834 | TEST_REQUIRES_X86_AVX512F; |
| 2835 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2836 | .elements(144) |
| 2837 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x144_acc3); |
| 2838 | } |
| 2839 | |
| 2840 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X144_ACC3, elements_div_144) { |
| 2841 | TEST_REQUIRES_X86_AVX512F; |
| 2842 | for (size_t elements = 288; elements < 1440; elements += 144) { |
| 2843 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2844 | .elements(elements) |
| 2845 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x144_acc3); |
| 2846 | } |
| 2847 | } |
| 2848 | |
| 2849 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X144_ACC3, elements_lt_144) { |
| 2850 | TEST_REQUIRES_X86_AVX512F; |
| 2851 | for (size_t elements = 1; elements < 144; elements++) { |
| 2852 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2853 | .elements(elements) |
| 2854 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x144_acc3); |
| 2855 | } |
| 2856 | } |
| 2857 | |
| 2858 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X144_ACC3, elements_gt_144) { |
| 2859 | TEST_REQUIRES_X86_AVX512F; |
| 2860 | for (size_t elements = 145; elements < 288; elements++) { |
| 2861 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2862 | .elements(elements) |
| 2863 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x144_acc3); |
| 2864 | } |
| 2865 | } |
| 2866 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2867 | |
| 2868 | |
| 2869 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2870 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X160, elements_eq_160) { |
| 2871 | TEST_REQUIRES_X86_AVX512F; |
| 2872 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2873 | .elements(160) |
| 2874 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x160); |
| 2875 | } |
| 2876 | |
| 2877 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X160, elements_div_160) { |
| 2878 | TEST_REQUIRES_X86_AVX512F; |
| 2879 | for (size_t elements = 320; elements < 1600; elements += 160) { |
| 2880 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2881 | .elements(elements) |
| 2882 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x160); |
| 2883 | } |
| 2884 | } |
| 2885 | |
| 2886 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X160, elements_lt_160) { |
| 2887 | TEST_REQUIRES_X86_AVX512F; |
| 2888 | for (size_t elements = 1; elements < 160; elements++) { |
| 2889 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2890 | .elements(elements) |
| 2891 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x160); |
| 2892 | } |
| 2893 | } |
| 2894 | |
| 2895 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X160, elements_gt_160) { |
| 2896 | TEST_REQUIRES_X86_AVX512F; |
| 2897 | for (size_t elements = 161; elements < 320; elements++) { |
| 2898 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2899 | .elements(elements) |
| 2900 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x160); |
| 2901 | } |
| 2902 | } |
| 2903 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2904 | |
| 2905 | |
| 2906 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2907 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X160_ACC2, elements_eq_160) { |
| 2908 | TEST_REQUIRES_X86_AVX512F; |
| 2909 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2910 | .elements(160) |
| 2911 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x160_acc2); |
| 2912 | } |
| 2913 | |
| 2914 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X160_ACC2, elements_div_160) { |
| 2915 | TEST_REQUIRES_X86_AVX512F; |
| 2916 | for (size_t elements = 320; elements < 1600; elements += 160) { |
| 2917 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2918 | .elements(elements) |
| 2919 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x160_acc2); |
| 2920 | } |
| 2921 | } |
| 2922 | |
| 2923 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X160_ACC2, elements_lt_160) { |
| 2924 | TEST_REQUIRES_X86_AVX512F; |
| 2925 | for (size_t elements = 1; elements < 160; elements++) { |
| 2926 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2927 | .elements(elements) |
| 2928 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x160_acc2); |
| 2929 | } |
| 2930 | } |
| 2931 | |
| 2932 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X160_ACC2, elements_gt_160) { |
| 2933 | TEST_REQUIRES_X86_AVX512F; |
| 2934 | for (size_t elements = 161; elements < 320; elements++) { |
| 2935 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2936 | .elements(elements) |
| 2937 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x160_acc2); |
| 2938 | } |
| 2939 | } |
| 2940 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2941 | |
| 2942 | |
| 2943 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2944 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X160_ACC5, elements_eq_160) { |
| 2945 | TEST_REQUIRES_X86_AVX512F; |
| 2946 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2947 | .elements(160) |
| 2948 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x160_acc5); |
| 2949 | } |
| 2950 | |
| 2951 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X160_ACC5, elements_div_160) { |
| 2952 | TEST_REQUIRES_X86_AVX512F; |
| 2953 | for (size_t elements = 320; elements < 1600; elements += 160) { |
| 2954 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2955 | .elements(elements) |
| 2956 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x160_acc5); |
| 2957 | } |
| 2958 | } |
| 2959 | |
| 2960 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X160_ACC5, elements_lt_160) { |
| 2961 | TEST_REQUIRES_X86_AVX512F; |
| 2962 | for (size_t elements = 1; elements < 160; elements++) { |
| 2963 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2964 | .elements(elements) |
| 2965 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x160_acc5); |
| 2966 | } |
| 2967 | } |
| 2968 | |
| 2969 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X160_ACC5, elements_gt_160) { |
| 2970 | TEST_REQUIRES_X86_AVX512F; |
| 2971 | for (size_t elements = 161; elements < 320; elements++) { |
| 2972 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2973 | .elements(elements) |
| 2974 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x160_acc5); |
| 2975 | } |
| 2976 | } |
| 2977 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2978 | |
| 2979 | |
| 2980 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2981 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X192, elements_eq_192) { |
| 2982 | TEST_REQUIRES_X86_AVX512F; |
| 2983 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2984 | .elements(192) |
| 2985 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x192); |
| 2986 | } |
| 2987 | |
| 2988 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X192, elements_div_192) { |
| 2989 | TEST_REQUIRES_X86_AVX512F; |
| 2990 | for (size_t elements = 384; elements < 1920; elements += 192) { |
| 2991 | RAddStoreExpMinusMaxMicrokernelTester() |
| 2992 | .elements(elements) |
| 2993 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x192); |
| 2994 | } |
| 2995 | } |
| 2996 | |
| 2997 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X192, elements_lt_192) { |
| 2998 | TEST_REQUIRES_X86_AVX512F; |
| 2999 | for (size_t elements = 1; elements < 192; elements++) { |
| 3000 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3001 | .elements(elements) |
| 3002 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x192); |
| 3003 | } |
| 3004 | } |
| 3005 | |
| 3006 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X192, elements_gt_192) { |
| 3007 | TEST_REQUIRES_X86_AVX512F; |
| 3008 | for (size_t elements = 193; elements < 384; elements++) { |
| 3009 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3010 | .elements(elements) |
| 3011 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x192); |
| 3012 | } |
| 3013 | } |
| 3014 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 3015 | |
| 3016 | |
| 3017 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 3018 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X192_ACC2, elements_eq_192) { |
| 3019 | TEST_REQUIRES_X86_AVX512F; |
| 3020 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3021 | .elements(192) |
| 3022 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x192_acc2); |
| 3023 | } |
| 3024 | |
| 3025 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X192_ACC2, elements_div_192) { |
| 3026 | TEST_REQUIRES_X86_AVX512F; |
| 3027 | for (size_t elements = 384; elements < 1920; elements += 192) { |
| 3028 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3029 | .elements(elements) |
| 3030 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x192_acc2); |
| 3031 | } |
| 3032 | } |
| 3033 | |
| 3034 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X192_ACC2, elements_lt_192) { |
| 3035 | TEST_REQUIRES_X86_AVX512F; |
| 3036 | for (size_t elements = 1; elements < 192; elements++) { |
| 3037 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3038 | .elements(elements) |
| 3039 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x192_acc2); |
| 3040 | } |
| 3041 | } |
| 3042 | |
| 3043 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X192_ACC2, elements_gt_192) { |
| 3044 | TEST_REQUIRES_X86_AVX512F; |
| 3045 | for (size_t elements = 193; elements < 384; elements++) { |
| 3046 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3047 | .elements(elements) |
| 3048 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x192_acc2); |
| 3049 | } |
| 3050 | } |
| 3051 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 3052 | |
| 3053 | |
| 3054 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 3055 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X192_ACC3, elements_eq_192) { |
| 3056 | TEST_REQUIRES_X86_AVX512F; |
| 3057 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3058 | .elements(192) |
| 3059 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x192_acc3); |
| 3060 | } |
| 3061 | |
| 3062 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X192_ACC3, elements_div_192) { |
| 3063 | TEST_REQUIRES_X86_AVX512F; |
| 3064 | for (size_t elements = 384; elements < 1920; elements += 192) { |
| 3065 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3066 | .elements(elements) |
| 3067 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x192_acc3); |
| 3068 | } |
| 3069 | } |
| 3070 | |
| 3071 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X192_ACC3, elements_lt_192) { |
| 3072 | TEST_REQUIRES_X86_AVX512F; |
| 3073 | for (size_t elements = 1; elements < 192; elements++) { |
| 3074 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3075 | .elements(elements) |
| 3076 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x192_acc3); |
| 3077 | } |
| 3078 | } |
| 3079 | |
| 3080 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X192_ACC3, elements_gt_192) { |
| 3081 | TEST_REQUIRES_X86_AVX512F; |
| 3082 | for (size_t elements = 193; elements < 384; elements++) { |
| 3083 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3084 | .elements(elements) |
| 3085 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x192_acc3); |
| 3086 | } |
| 3087 | } |
| 3088 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 3089 | |
| 3090 | |
| 3091 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 3092 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X192_ACC6, elements_eq_192) { |
| 3093 | TEST_REQUIRES_X86_AVX512F; |
| 3094 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3095 | .elements(192) |
| 3096 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x192_acc6); |
| 3097 | } |
| 3098 | |
| 3099 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X192_ACC6, elements_div_192) { |
| 3100 | TEST_REQUIRES_X86_AVX512F; |
| 3101 | for (size_t elements = 384; elements < 1920; elements += 192) { |
| 3102 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3103 | .elements(elements) |
| 3104 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x192_acc6); |
| 3105 | } |
| 3106 | } |
| 3107 | |
| 3108 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X192_ACC6, elements_lt_192) { |
| 3109 | TEST_REQUIRES_X86_AVX512F; |
| 3110 | for (size_t elements = 1; elements < 192; elements++) { |
| 3111 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3112 | .elements(elements) |
| 3113 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x192_acc6); |
| 3114 | } |
| 3115 | } |
| 3116 | |
| 3117 | TEST(F32_RADDSTOREEXPMINUSMAX__AVX512F_P5_SCALEF_X192_ACC6, elements_gt_192) { |
| 3118 | TEST_REQUIRES_X86_AVX512F; |
| 3119 | for (size_t elements = 193; elements < 384; elements++) { |
| 3120 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3121 | .elements(elements) |
| 3122 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__avx512f_p5_scalef_x192_acc6); |
| 3123 | } |
| 3124 | } |
| 3125 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| Marat Dukhan | f46f675 | 2020-01-21 11:03:49 -0800 | [diff] [blame] | 3126 | |
| 3127 | |
| Marat Dukhan | 52238f0 | 2020-07-16 15:30:28 -0700 | [diff] [blame] | 3128 | #if XNN_ARCH_WASMSIMD |
| 3129 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X4, elements_eq_4) { |
| 3130 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3131 | .elements(4) |
| 3132 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x4); |
| 3133 | } |
| 3134 | |
| 3135 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X4, elements_div_4) { |
| 3136 | for (size_t elements = 8; elements < 40; elements += 4) { |
| 3137 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3138 | .elements(elements) |
| 3139 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x4); |
| 3140 | } |
| 3141 | } |
| 3142 | |
| 3143 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X4, elements_lt_4) { |
| 3144 | for (size_t elements = 1; elements < 4; elements++) { |
| 3145 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3146 | .elements(elements) |
| 3147 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x4); |
| 3148 | } |
| 3149 | } |
| 3150 | |
| 3151 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X4, elements_gt_4) { |
| 3152 | for (size_t elements = 5; elements < 8; elements++) { |
| 3153 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3154 | .elements(elements) |
| 3155 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x4); |
| 3156 | } |
| 3157 | } |
| 3158 | #endif // XNN_ARCH_WASMSIMD |
| 3159 | |
| 3160 | |
| 3161 | #if XNN_ARCH_WASMSIMD |
| 3162 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X8, elements_eq_8) { |
| 3163 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3164 | .elements(8) |
| 3165 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x8); |
| 3166 | } |
| 3167 | |
| 3168 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X8, elements_div_8) { |
| 3169 | for (size_t elements = 16; elements < 80; elements += 8) { |
| 3170 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3171 | .elements(elements) |
| 3172 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x8); |
| 3173 | } |
| 3174 | } |
| 3175 | |
| 3176 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X8, elements_lt_8) { |
| 3177 | for (size_t elements = 1; elements < 8; elements++) { |
| 3178 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3179 | .elements(elements) |
| 3180 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x8); |
| 3181 | } |
| 3182 | } |
| 3183 | |
| 3184 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X8, elements_gt_8) { |
| 3185 | for (size_t elements = 9; elements < 16; elements++) { |
| 3186 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3187 | .elements(elements) |
| 3188 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x8); |
| 3189 | } |
| 3190 | } |
| 3191 | #endif // XNN_ARCH_WASMSIMD |
| 3192 | |
| 3193 | |
| 3194 | #if XNN_ARCH_WASMSIMD |
| 3195 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X8_ACC2, elements_eq_8) { |
| 3196 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3197 | .elements(8) |
| 3198 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x8_acc2); |
| 3199 | } |
| 3200 | |
| 3201 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X8_ACC2, elements_div_8) { |
| 3202 | for (size_t elements = 16; elements < 80; elements += 8) { |
| 3203 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3204 | .elements(elements) |
| 3205 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x8_acc2); |
| 3206 | } |
| 3207 | } |
| 3208 | |
| 3209 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X8_ACC2, elements_lt_8) { |
| 3210 | for (size_t elements = 1; elements < 8; elements++) { |
| 3211 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3212 | .elements(elements) |
| 3213 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x8_acc2); |
| 3214 | } |
| 3215 | } |
| 3216 | |
| 3217 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X8_ACC2, elements_gt_8) { |
| 3218 | for (size_t elements = 9; elements < 16; elements++) { |
| 3219 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3220 | .elements(elements) |
| 3221 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x8_acc2); |
| 3222 | } |
| 3223 | } |
| 3224 | #endif // XNN_ARCH_WASMSIMD |
| 3225 | |
| 3226 | |
| 3227 | #if XNN_ARCH_WASMSIMD |
| 3228 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X12, elements_eq_12) { |
| 3229 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3230 | .elements(12) |
| 3231 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x12); |
| 3232 | } |
| 3233 | |
| 3234 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X12, elements_div_12) { |
| 3235 | for (size_t elements = 24; elements < 120; elements += 12) { |
| 3236 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3237 | .elements(elements) |
| 3238 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x12); |
| 3239 | } |
| 3240 | } |
| 3241 | |
| 3242 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X12, elements_lt_12) { |
| 3243 | for (size_t elements = 1; elements < 12; elements++) { |
| 3244 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3245 | .elements(elements) |
| 3246 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x12); |
| 3247 | } |
| 3248 | } |
| 3249 | |
| 3250 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X12, elements_gt_12) { |
| 3251 | for (size_t elements = 13; elements < 24; elements++) { |
| 3252 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3253 | .elements(elements) |
| 3254 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x12); |
| 3255 | } |
| 3256 | } |
| 3257 | #endif // XNN_ARCH_WASMSIMD |
| 3258 | |
| 3259 | |
| 3260 | #if XNN_ARCH_WASMSIMD |
| 3261 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X12_ACC2, elements_eq_12) { |
| 3262 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3263 | .elements(12) |
| 3264 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x12_acc2); |
| 3265 | } |
| 3266 | |
| 3267 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X12_ACC2, elements_div_12) { |
| 3268 | for (size_t elements = 24; elements < 120; elements += 12) { |
| 3269 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3270 | .elements(elements) |
| 3271 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x12_acc2); |
| 3272 | } |
| 3273 | } |
| 3274 | |
| 3275 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X12_ACC2, elements_lt_12) { |
| 3276 | for (size_t elements = 1; elements < 12; elements++) { |
| 3277 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3278 | .elements(elements) |
| 3279 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x12_acc2); |
| 3280 | } |
| 3281 | } |
| 3282 | |
| 3283 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X12_ACC2, elements_gt_12) { |
| 3284 | for (size_t elements = 13; elements < 24; elements++) { |
| 3285 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3286 | .elements(elements) |
| 3287 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x12_acc2); |
| 3288 | } |
| 3289 | } |
| 3290 | #endif // XNN_ARCH_WASMSIMD |
| 3291 | |
| 3292 | |
| 3293 | #if XNN_ARCH_WASMSIMD |
| 3294 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X12_ACC3, elements_eq_12) { |
| 3295 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3296 | .elements(12) |
| 3297 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x12_acc3); |
| 3298 | } |
| 3299 | |
| 3300 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X12_ACC3, elements_div_12) { |
| 3301 | for (size_t elements = 24; elements < 120; elements += 12) { |
| 3302 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3303 | .elements(elements) |
| 3304 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x12_acc3); |
| 3305 | } |
| 3306 | } |
| 3307 | |
| 3308 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X12_ACC3, elements_lt_12) { |
| 3309 | for (size_t elements = 1; elements < 12; elements++) { |
| 3310 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3311 | .elements(elements) |
| 3312 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x12_acc3); |
| 3313 | } |
| 3314 | } |
| 3315 | |
| 3316 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X12_ACC3, elements_gt_12) { |
| 3317 | for (size_t elements = 13; elements < 24; elements++) { |
| 3318 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3319 | .elements(elements) |
| 3320 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x12_acc3); |
| 3321 | } |
| 3322 | } |
| 3323 | #endif // XNN_ARCH_WASMSIMD |
| 3324 | |
| 3325 | |
| 3326 | #if XNN_ARCH_WASMSIMD |
| 3327 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X16, elements_eq_16) { |
| 3328 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3329 | .elements(16) |
| 3330 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x16); |
| 3331 | } |
| 3332 | |
| 3333 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X16, elements_div_16) { |
| 3334 | for (size_t elements = 32; elements < 160; elements += 16) { |
| 3335 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3336 | .elements(elements) |
| 3337 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x16); |
| 3338 | } |
| 3339 | } |
| 3340 | |
| 3341 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X16, elements_lt_16) { |
| 3342 | for (size_t elements = 1; elements < 16; elements++) { |
| 3343 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3344 | .elements(elements) |
| 3345 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x16); |
| 3346 | } |
| 3347 | } |
| 3348 | |
| 3349 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X16, elements_gt_16) { |
| 3350 | for (size_t elements = 17; elements < 32; elements++) { |
| 3351 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3352 | .elements(elements) |
| 3353 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x16); |
| 3354 | } |
| 3355 | } |
| 3356 | #endif // XNN_ARCH_WASMSIMD |
| 3357 | |
| 3358 | |
| 3359 | #if XNN_ARCH_WASMSIMD |
| 3360 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X16_ACC2, elements_eq_16) { |
| 3361 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3362 | .elements(16) |
| 3363 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x16_acc2); |
| 3364 | } |
| 3365 | |
| 3366 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X16_ACC2, elements_div_16) { |
| 3367 | for (size_t elements = 32; elements < 160; elements += 16) { |
| 3368 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3369 | .elements(elements) |
| 3370 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x16_acc2); |
| 3371 | } |
| 3372 | } |
| 3373 | |
| 3374 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X16_ACC2, elements_lt_16) { |
| 3375 | for (size_t elements = 1; elements < 16; elements++) { |
| 3376 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3377 | .elements(elements) |
| 3378 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x16_acc2); |
| 3379 | } |
| 3380 | } |
| 3381 | |
| 3382 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X16_ACC2, elements_gt_16) { |
| 3383 | for (size_t elements = 17; elements < 32; elements++) { |
| 3384 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3385 | .elements(elements) |
| 3386 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x16_acc2); |
| 3387 | } |
| 3388 | } |
| 3389 | #endif // XNN_ARCH_WASMSIMD |
| 3390 | |
| 3391 | |
| 3392 | #if XNN_ARCH_WASMSIMD |
| 3393 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X16_ACC4, elements_eq_16) { |
| 3394 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3395 | .elements(16) |
| 3396 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x16_acc4); |
| 3397 | } |
| 3398 | |
| 3399 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X16_ACC4, elements_div_16) { |
| 3400 | for (size_t elements = 32; elements < 160; elements += 16) { |
| 3401 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3402 | .elements(elements) |
| 3403 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x16_acc4); |
| 3404 | } |
| 3405 | } |
| 3406 | |
| 3407 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X16_ACC4, elements_lt_16) { |
| 3408 | for (size_t elements = 1; elements < 16; elements++) { |
| 3409 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3410 | .elements(elements) |
| 3411 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x16_acc4); |
| 3412 | } |
| 3413 | } |
| 3414 | |
| 3415 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X16_ACC4, elements_gt_16) { |
| 3416 | for (size_t elements = 17; elements < 32; elements++) { |
| 3417 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3418 | .elements(elements) |
| 3419 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x16_acc4); |
| 3420 | } |
| 3421 | } |
| 3422 | #endif // XNN_ARCH_WASMSIMD |
| 3423 | |
| 3424 | |
| 3425 | #if XNN_ARCH_WASMSIMD |
| 3426 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X20, elements_eq_20) { |
| 3427 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3428 | .elements(20) |
| 3429 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x20); |
| 3430 | } |
| 3431 | |
| 3432 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X20, elements_div_20) { |
| 3433 | for (size_t elements = 40; elements < 200; elements += 20) { |
| 3434 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3435 | .elements(elements) |
| 3436 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x20); |
| 3437 | } |
| 3438 | } |
| 3439 | |
| 3440 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X20, elements_lt_20) { |
| 3441 | for (size_t elements = 1; elements < 20; elements++) { |
| 3442 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3443 | .elements(elements) |
| 3444 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x20); |
| 3445 | } |
| 3446 | } |
| 3447 | |
| 3448 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X20, elements_gt_20) { |
| 3449 | for (size_t elements = 21; elements < 40; elements++) { |
| 3450 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3451 | .elements(elements) |
| 3452 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x20); |
| 3453 | } |
| 3454 | } |
| 3455 | #endif // XNN_ARCH_WASMSIMD |
| 3456 | |
| 3457 | |
| 3458 | #if XNN_ARCH_WASMSIMD |
| 3459 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X20_ACC2, elements_eq_20) { |
| 3460 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3461 | .elements(20) |
| 3462 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x20_acc2); |
| 3463 | } |
| 3464 | |
| 3465 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X20_ACC2, elements_div_20) { |
| 3466 | for (size_t elements = 40; elements < 200; elements += 20) { |
| 3467 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3468 | .elements(elements) |
| 3469 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x20_acc2); |
| 3470 | } |
| 3471 | } |
| 3472 | |
| 3473 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X20_ACC2, elements_lt_20) { |
| 3474 | for (size_t elements = 1; elements < 20; elements++) { |
| 3475 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3476 | .elements(elements) |
| 3477 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x20_acc2); |
| 3478 | } |
| 3479 | } |
| 3480 | |
| 3481 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X20_ACC2, elements_gt_20) { |
| 3482 | for (size_t elements = 21; elements < 40; elements++) { |
| 3483 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3484 | .elements(elements) |
| 3485 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x20_acc2); |
| 3486 | } |
| 3487 | } |
| 3488 | #endif // XNN_ARCH_WASMSIMD |
| 3489 | |
| 3490 | |
| 3491 | #if XNN_ARCH_WASMSIMD |
| 3492 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X20_ACC5, elements_eq_20) { |
| 3493 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3494 | .elements(20) |
| 3495 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x20_acc5); |
| 3496 | } |
| 3497 | |
| 3498 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X20_ACC5, elements_div_20) { |
| 3499 | for (size_t elements = 40; elements < 200; elements += 20) { |
| 3500 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3501 | .elements(elements) |
| 3502 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x20_acc5); |
| 3503 | } |
| 3504 | } |
| 3505 | |
| 3506 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X20_ACC5, elements_lt_20) { |
| 3507 | for (size_t elements = 1; elements < 20; elements++) { |
| 3508 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3509 | .elements(elements) |
| 3510 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x20_acc5); |
| 3511 | } |
| 3512 | } |
| 3513 | |
| 3514 | TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X20_ACC5, elements_gt_20) { |
| 3515 | for (size_t elements = 21; elements < 40; elements++) { |
| 3516 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3517 | .elements(elements) |
| 3518 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x20_acc5); |
| 3519 | } |
| 3520 | } |
| 3521 | #endif // XNN_ARCH_WASMSIMD |
| 3522 | |
| 3523 | |
| Marat Dukhan | f46f675 | 2020-01-21 11:03:49 -0800 | [diff] [blame] | 3524 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_P5_X1, elements_eq_1) { |
| 3525 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3526 | .elements(1) |
| 3527 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_p5_x1); |
| 3528 | } |
| 3529 | |
| 3530 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_P5_X1, elements_gt_1) { |
| 3531 | for (size_t elements = 2; elements < 10; elements++) { |
| 3532 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3533 | .elements(elements) |
| 3534 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_p5_x1); |
| 3535 | } |
| 3536 | } |
| 3537 | |
| 3538 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_P5_X2, elements_eq_2) { |
| 3539 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3540 | .elements(2) |
| 3541 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_p5_x2); |
| 3542 | } |
| 3543 | |
| 3544 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_P5_X2, elements_div_2) { |
| 3545 | for (size_t elements = 4; elements < 20; elements += 2) { |
| 3546 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3547 | .elements(elements) |
| 3548 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_p5_x2); |
| 3549 | } |
| 3550 | } |
| 3551 | |
| 3552 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_P5_X2, elements_lt_2) { |
| 3553 | for (size_t elements = 1; elements < 2; elements++) { |
| 3554 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3555 | .elements(elements) |
| 3556 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_p5_x2); |
| 3557 | } |
| 3558 | } |
| 3559 | |
| 3560 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_P5_X2, elements_gt_2) { |
| 3561 | for (size_t elements = 3; elements < 4; elements++) { |
| 3562 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3563 | .elements(elements) |
| 3564 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_p5_x2); |
| 3565 | } |
| 3566 | } |
| 3567 | |
| 3568 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_P5_X2_ACC2, elements_eq_2) { |
| 3569 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3570 | .elements(2) |
| 3571 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_p5_x2_acc2); |
| 3572 | } |
| 3573 | |
| 3574 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_P5_X2_ACC2, elements_div_2) { |
| 3575 | for (size_t elements = 4; elements < 20; elements += 2) { |
| 3576 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3577 | .elements(elements) |
| 3578 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_p5_x2_acc2); |
| 3579 | } |
| 3580 | } |
| 3581 | |
| 3582 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_P5_X2_ACC2, elements_lt_2) { |
| 3583 | for (size_t elements = 1; elements < 2; elements++) { |
| 3584 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3585 | .elements(elements) |
| 3586 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_p5_x2_acc2); |
| 3587 | } |
| 3588 | } |
| 3589 | |
| 3590 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_P5_X2_ACC2, elements_gt_2) { |
| 3591 | for (size_t elements = 3; elements < 4; elements++) { |
| 3592 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3593 | .elements(elements) |
| 3594 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_p5_x2_acc2); |
| 3595 | } |
| 3596 | } |
| 3597 | |
| 3598 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_P5_X4, elements_eq_4) { |
| 3599 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3600 | .elements(4) |
| 3601 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_p5_x4); |
| 3602 | } |
| 3603 | |
| 3604 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_P5_X4, elements_div_4) { |
| 3605 | for (size_t elements = 8; elements < 40; elements += 4) { |
| 3606 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3607 | .elements(elements) |
| 3608 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_p5_x4); |
| 3609 | } |
| 3610 | } |
| 3611 | |
| 3612 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_P5_X4, elements_lt_4) { |
| 3613 | for (size_t elements = 1; elements < 4; elements++) { |
| 3614 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3615 | .elements(elements) |
| 3616 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_p5_x4); |
| 3617 | } |
| 3618 | } |
| 3619 | |
| 3620 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_P5_X4, elements_gt_4) { |
| 3621 | for (size_t elements = 5; elements < 8; elements++) { |
| 3622 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3623 | .elements(elements) |
| 3624 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_p5_x4); |
| 3625 | } |
| 3626 | } |
| 3627 | |
| 3628 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_P5_X4_ACC2, elements_eq_4) { |
| 3629 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3630 | .elements(4) |
| 3631 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_p5_x4_acc2); |
| 3632 | } |
| 3633 | |
| 3634 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_P5_X4_ACC2, elements_div_4) { |
| 3635 | for (size_t elements = 8; elements < 40; elements += 4) { |
| 3636 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3637 | .elements(elements) |
| 3638 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_p5_x4_acc2); |
| 3639 | } |
| 3640 | } |
| 3641 | |
| 3642 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_P5_X4_ACC2, elements_lt_4) { |
| 3643 | for (size_t elements = 1; elements < 4; elements++) { |
| 3644 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3645 | .elements(elements) |
| 3646 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_p5_x4_acc2); |
| 3647 | } |
| 3648 | } |
| 3649 | |
| 3650 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_P5_X4_ACC2, elements_gt_4) { |
| 3651 | for (size_t elements = 5; elements < 8; elements++) { |
| 3652 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3653 | .elements(elements) |
| 3654 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_p5_x4_acc2); |
| 3655 | } |
| 3656 | } |
| 3657 | |
| 3658 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_P5_X4_ACC4, elements_eq_4) { |
| 3659 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3660 | .elements(4) |
| 3661 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_p5_x4_acc4); |
| 3662 | } |
| 3663 | |
| 3664 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_P5_X4_ACC4, elements_div_4) { |
| 3665 | for (size_t elements = 8; elements < 40; elements += 4) { |
| 3666 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3667 | .elements(elements) |
| 3668 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_p5_x4_acc4); |
| 3669 | } |
| 3670 | } |
| 3671 | |
| 3672 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_P5_X4_ACC4, elements_lt_4) { |
| 3673 | for (size_t elements = 1; elements < 4; elements++) { |
| 3674 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3675 | .elements(elements) |
| 3676 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_p5_x4_acc4); |
| 3677 | } |
| 3678 | } |
| 3679 | |
| 3680 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_P5_X4_ACC4, elements_gt_4) { |
| 3681 | for (size_t elements = 5; elements < 8; elements++) { |
| 3682 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3683 | .elements(elements) |
| 3684 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_p5_x4_acc4); |
| 3685 | } |
| 3686 | } |
| 3687 | |
| 3688 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_LUT64_P2_X1, elements_eq_1) { |
| 3689 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3690 | .elements(1) |
| 3691 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_lut64_p2_x1); |
| 3692 | } |
| 3693 | |
| 3694 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_LUT64_P2_X1, elements_gt_1) { |
| 3695 | for (size_t elements = 2; elements < 10; elements++) { |
| 3696 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3697 | .elements(elements) |
| 3698 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_lut64_p2_x1); |
| 3699 | } |
| 3700 | } |
| 3701 | |
| 3702 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_LUT64_P2_X2, elements_eq_2) { |
| 3703 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3704 | .elements(2) |
| 3705 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_lut64_p2_x2); |
| 3706 | } |
| 3707 | |
| 3708 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_LUT64_P2_X2, elements_div_2) { |
| 3709 | for (size_t elements = 4; elements < 20; elements += 2) { |
| 3710 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3711 | .elements(elements) |
| 3712 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_lut64_p2_x2); |
| 3713 | } |
| 3714 | } |
| 3715 | |
| 3716 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_LUT64_P2_X2, elements_lt_2) { |
| 3717 | for (size_t elements = 1; elements < 2; elements++) { |
| 3718 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3719 | .elements(elements) |
| 3720 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_lut64_p2_x2); |
| 3721 | } |
| 3722 | } |
| 3723 | |
| 3724 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_LUT64_P2_X2, elements_gt_2) { |
| 3725 | for (size_t elements = 3; elements < 4; elements++) { |
| 3726 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3727 | .elements(elements) |
| 3728 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_lut64_p2_x2); |
| 3729 | } |
| 3730 | } |
| 3731 | |
| 3732 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_LUT64_P2_X2_ACC2, elements_eq_2) { |
| 3733 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3734 | .elements(2) |
| 3735 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_lut64_p2_x2_acc2); |
| 3736 | } |
| 3737 | |
| 3738 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_LUT64_P2_X2_ACC2, elements_div_2) { |
| 3739 | for (size_t elements = 4; elements < 20; elements += 2) { |
| 3740 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3741 | .elements(elements) |
| 3742 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_lut64_p2_x2_acc2); |
| 3743 | } |
| 3744 | } |
| 3745 | |
| 3746 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_LUT64_P2_X2_ACC2, elements_lt_2) { |
| 3747 | for (size_t elements = 1; elements < 2; elements++) { |
| 3748 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3749 | .elements(elements) |
| 3750 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_lut64_p2_x2_acc2); |
| 3751 | } |
| 3752 | } |
| 3753 | |
| 3754 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_LUT64_P2_X2_ACC2, elements_gt_2) { |
| 3755 | for (size_t elements = 3; elements < 4; elements++) { |
| 3756 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3757 | .elements(elements) |
| 3758 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_lut64_p2_x2_acc2); |
| 3759 | } |
| 3760 | } |
| 3761 | |
| 3762 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_LUT64_P2_X4, elements_eq_4) { |
| 3763 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3764 | .elements(4) |
| 3765 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_lut64_p2_x4); |
| 3766 | } |
| 3767 | |
| 3768 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_LUT64_P2_X4, elements_div_4) { |
| 3769 | for (size_t elements = 8; elements < 40; elements += 4) { |
| 3770 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3771 | .elements(elements) |
| 3772 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_lut64_p2_x4); |
| 3773 | } |
| 3774 | } |
| 3775 | |
| 3776 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_LUT64_P2_X4, elements_lt_4) { |
| 3777 | for (size_t elements = 1; elements < 4; elements++) { |
| 3778 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3779 | .elements(elements) |
| 3780 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_lut64_p2_x4); |
| 3781 | } |
| 3782 | } |
| 3783 | |
| 3784 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_LUT64_P2_X4, elements_gt_4) { |
| 3785 | for (size_t elements = 5; elements < 8; elements++) { |
| 3786 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3787 | .elements(elements) |
| 3788 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_lut64_p2_x4); |
| 3789 | } |
| 3790 | } |
| 3791 | |
| 3792 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_LUT64_P2_X4_ACC2, elements_eq_4) { |
| 3793 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3794 | .elements(4) |
| 3795 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_lut64_p2_x4_acc2); |
| 3796 | } |
| 3797 | |
| 3798 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_LUT64_P2_X4_ACC2, elements_div_4) { |
| 3799 | for (size_t elements = 8; elements < 40; elements += 4) { |
| 3800 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3801 | .elements(elements) |
| 3802 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_lut64_p2_x4_acc2); |
| 3803 | } |
| 3804 | } |
| 3805 | |
| 3806 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_LUT64_P2_X4_ACC2, elements_lt_4) { |
| 3807 | for (size_t elements = 1; elements < 4; elements++) { |
| 3808 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3809 | .elements(elements) |
| 3810 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_lut64_p2_x4_acc2); |
| 3811 | } |
| 3812 | } |
| 3813 | |
| 3814 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_LUT64_P2_X4_ACC2, elements_gt_4) { |
| 3815 | for (size_t elements = 5; elements < 8; elements++) { |
| 3816 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3817 | .elements(elements) |
| 3818 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_lut64_p2_x4_acc2); |
| 3819 | } |
| 3820 | } |
| 3821 | |
| 3822 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_LUT64_P2_X4_ACC4, elements_eq_4) { |
| 3823 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3824 | .elements(4) |
| 3825 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_lut64_p2_x4_acc4); |
| 3826 | } |
| 3827 | |
| 3828 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_LUT64_P2_X4_ACC4, elements_div_4) { |
| 3829 | for (size_t elements = 8; elements < 40; elements += 4) { |
| 3830 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3831 | .elements(elements) |
| 3832 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_lut64_p2_x4_acc4); |
| 3833 | } |
| 3834 | } |
| 3835 | |
| 3836 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_LUT64_P2_X4_ACC4, elements_lt_4) { |
| 3837 | for (size_t elements = 1; elements < 4; elements++) { |
| 3838 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3839 | .elements(elements) |
| 3840 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_lut64_p2_x4_acc4); |
| 3841 | } |
| 3842 | } |
| 3843 | |
| 3844 | TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_LUT64_P2_X4_ACC4, elements_gt_4) { |
| 3845 | for (size_t elements = 5; elements < 8; elements++) { |
| 3846 | RAddStoreExpMinusMaxMicrokernelTester() |
| 3847 | .elements(elements) |
| 3848 | .Test(xnn_f32_raddstoreexpminusmax_ukernel__scalar_lut64_p2_x4_acc4); |
| 3849 | } |
| 3850 | } |