XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1 | // Copyright 2019 Google LLC |
| 2 | // |
| 3 | // This source code is licensed under the BSD-style license found in the |
| 4 | // LICENSE file in the root directory of this source tree. |
| 5 | // |
| 6 | // Auto-generated file. Do not edit! |
Marat Dukhan | b2217dd | 2020-05-28 17:30:28 -0700 | [diff] [blame] | 7 | // Specification: test/f32-vmulcaddc-minmax.yaml |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 8 | // Generator: tools/generate-vmulcaddc-test.py |
| 9 | |
| 10 | |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 11 | #include <gtest/gtest.h> |
| 12 | |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 13 | #include <xnnpack/common.h> |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 14 | #include <xnnpack/isa-checks.h> |
| 15 | |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 16 | #include <xnnpack/vmulcaddc.h> |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 17 | #include "vmulcaddc-microkernel-tester.h" |
| 18 | |
| 19 | |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 20 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 21 | TEST(F32_VMULCADDC_MINMAX_C4__NEONFMA_2X, channels_eq_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 22 | TEST_REQUIRES_ARM_NEON_FMA; |
| 23 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 24 | .channel_tile(4) |
| 25 | .channels(4) |
| 26 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 27 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neonfma_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 28 | } |
| 29 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 30 | TEST(F32_VMULCADDC_MINMAX_C4__NEONFMA_2X, channels_div_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 31 | TEST_REQUIRES_ARM_NEON_FMA; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 32 | for (size_t channels = 8; channels < 40; channels += 4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 33 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 34 | .channel_tile(4) |
| 35 | .channels(channels) |
| 36 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 37 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neonfma_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 38 | } |
| 39 | } |
| 40 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 41 | TEST(F32_VMULCADDC_MINMAX_C4__NEONFMA_2X, channels_lt_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 42 | TEST_REQUIRES_ARM_NEON_FMA; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 43 | for (size_t channels = 1; channels < 4; channels++) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 44 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 45 | .channel_tile(4) |
| 46 | .channels(channels) |
| 47 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 48 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neonfma_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 49 | } |
| 50 | } |
| 51 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 52 | TEST(F32_VMULCADDC_MINMAX_C4__NEONFMA_2X, channels_gt_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 53 | TEST_REQUIRES_ARM_NEON_FMA; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 54 | for (size_t channels = 5; channels < 8; channels++) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 55 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 56 | .channel_tile(4) |
| 57 | .channels(channels) |
| 58 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 59 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neonfma_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 60 | } |
| 61 | } |
| 62 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 63 | TEST(F32_VMULCADDC_MINMAX_C4__NEONFMA_2X, rows_lt_2) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 64 | TEST_REQUIRES_ARM_NEON_FMA; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 65 | for (size_t rows = 1; rows < 2; rows++) { |
| 66 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 67 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 68 | .channel_tile(4) |
| 69 | .channels(channels) |
| 70 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 71 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neonfma_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 72 | } |
| 73 | } |
| 74 | } |
| 75 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 76 | TEST(F32_VMULCADDC_MINMAX_C4__NEONFMA_2X, rows_div_2) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 77 | TEST_REQUIRES_ARM_NEON_FMA; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 78 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 79 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 80 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 81 | .channel_tile(4) |
| 82 | .channels(channels) |
| 83 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 84 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neonfma_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 85 | } |
| 86 | } |
| 87 | } |
| 88 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 89 | TEST(F32_VMULCADDC_MINMAX_C4__NEONFMA_2X, rows_gt_2) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 90 | TEST_REQUIRES_ARM_NEON_FMA; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 91 | for (size_t rows = 3; rows < 4; rows++) { |
| 92 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 93 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 94 | .channel_tile(4) |
| 95 | .channels(channels) |
| 96 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 97 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neonfma_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 98 | } |
| 99 | } |
| 100 | } |
| 101 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 102 | TEST(F32_VMULCADDC_MINMAX_C4__NEONFMA_2X, input_stride) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 103 | TEST_REQUIRES_ARM_NEON_FMA; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 104 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 105 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 106 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 107 | .channel_tile(4) |
| 108 | .channels(channels) |
| 109 | .rows(rows) |
| 110 | .input_stride(23) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 111 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neonfma_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 112 | } |
| 113 | } |
| 114 | } |
| 115 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 116 | TEST(F32_VMULCADDC_MINMAX_C4__NEONFMA_2X, output_stride) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 117 | TEST_REQUIRES_ARM_NEON_FMA; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 118 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 119 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 120 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 121 | .channel_tile(4) |
| 122 | .channels(channels) |
| 123 | .rows(rows) |
| 124 | .output_stride(23) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 125 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neonfma_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 126 | } |
| 127 | } |
| 128 | } |
| 129 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 130 | TEST(F32_VMULCADDC_MINMAX_C4__NEONFMA_2X, inplace) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 131 | TEST_REQUIRES_ARM_NEON_FMA; |
| 132 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 133 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 134 | VMulCAddCMicrokernelTester() |
| 135 | .channel_tile(4) |
| 136 | .channels(channels) |
| 137 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 138 | .inplace(true) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 139 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neonfma_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 140 | } |
| 141 | } |
| 142 | } |
| 143 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 144 | TEST(F32_VMULCADDC_MINMAX_C4__NEONFMA_2X, qmin) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 145 | TEST_REQUIRES_ARM_NEON_FMA; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 146 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 147 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 148 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 149 | .channel_tile(4) |
| 150 | .channels(channels) |
| 151 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 152 | .qmin(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 153 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neonfma_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 154 | } |
| 155 | } |
| 156 | } |
| 157 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 158 | TEST(F32_VMULCADDC_MINMAX_C4__NEONFMA_2X, qmax) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 159 | TEST_REQUIRES_ARM_NEON_FMA; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 160 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 161 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 162 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 163 | .channel_tile(4) |
| 164 | .channels(channels) |
| 165 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 166 | .qmax(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 167 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neonfma_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 168 | } |
| 169 | } |
| 170 | } |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 171 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 172 | |
| 173 | |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 174 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 175 | TEST(F32_VMULCADDC_MINMAX_C8__NEONFMA_2X, channels_eq_8) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 176 | TEST_REQUIRES_ARM_NEON_FMA; |
| 177 | VMulCAddCMicrokernelTester() |
| 178 | .channel_tile(8) |
| 179 | .channels(8) |
| 180 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 181 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neonfma_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 182 | } |
| 183 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 184 | TEST(F32_VMULCADDC_MINMAX_C8__NEONFMA_2X, channels_div_8) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 185 | TEST_REQUIRES_ARM_NEON_FMA; |
| 186 | for (size_t channels = 16; channels < 80; channels += 8) { |
| 187 | VMulCAddCMicrokernelTester() |
| 188 | .channel_tile(8) |
| 189 | .channels(channels) |
| 190 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 191 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neonfma_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 192 | } |
| 193 | } |
| 194 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 195 | TEST(F32_VMULCADDC_MINMAX_C8__NEONFMA_2X, channels_lt_8) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 196 | TEST_REQUIRES_ARM_NEON_FMA; |
| 197 | for (size_t channels = 1; channels < 8; channels++) { |
| 198 | VMulCAddCMicrokernelTester() |
| 199 | .channel_tile(8) |
| 200 | .channels(channels) |
| 201 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 202 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neonfma_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 203 | } |
| 204 | } |
| 205 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 206 | TEST(F32_VMULCADDC_MINMAX_C8__NEONFMA_2X, channels_gt_8) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 207 | TEST_REQUIRES_ARM_NEON_FMA; |
| 208 | for (size_t channels = 9; channels < 16; channels++) { |
| 209 | VMulCAddCMicrokernelTester() |
| 210 | .channel_tile(8) |
| 211 | .channels(channels) |
| 212 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 213 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neonfma_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 214 | } |
| 215 | } |
| 216 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 217 | TEST(F32_VMULCADDC_MINMAX_C8__NEONFMA_2X, rows_lt_2) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 218 | TEST_REQUIRES_ARM_NEON_FMA; |
| 219 | for (size_t rows = 1; rows < 2; rows++) { |
| 220 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 221 | VMulCAddCMicrokernelTester() |
| 222 | .channel_tile(8) |
| 223 | .channels(channels) |
| 224 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 225 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neonfma_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 226 | } |
| 227 | } |
| 228 | } |
| 229 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 230 | TEST(F32_VMULCADDC_MINMAX_C8__NEONFMA_2X, rows_div_2) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 231 | TEST_REQUIRES_ARM_NEON_FMA; |
| 232 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 233 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 234 | VMulCAddCMicrokernelTester() |
| 235 | .channel_tile(8) |
| 236 | .channels(channels) |
| 237 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 238 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neonfma_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 239 | } |
| 240 | } |
| 241 | } |
| 242 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 243 | TEST(F32_VMULCADDC_MINMAX_C8__NEONFMA_2X, rows_gt_2) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 244 | TEST_REQUIRES_ARM_NEON_FMA; |
| 245 | for (size_t rows = 3; rows < 4; rows++) { |
| 246 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 247 | VMulCAddCMicrokernelTester() |
| 248 | .channel_tile(8) |
| 249 | .channels(channels) |
| 250 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 251 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neonfma_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 252 | } |
| 253 | } |
| 254 | } |
| 255 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 256 | TEST(F32_VMULCADDC_MINMAX_C8__NEONFMA_2X, input_stride) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 257 | TEST_REQUIRES_ARM_NEON_FMA; |
| 258 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 259 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 260 | VMulCAddCMicrokernelTester() |
| 261 | .channel_tile(8) |
| 262 | .channels(channels) |
| 263 | .rows(rows) |
| 264 | .input_stride(43) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 265 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neonfma_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 266 | } |
| 267 | } |
| 268 | } |
| 269 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 270 | TEST(F32_VMULCADDC_MINMAX_C8__NEONFMA_2X, output_stride) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 271 | TEST_REQUIRES_ARM_NEON_FMA; |
| 272 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 273 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 274 | VMulCAddCMicrokernelTester() |
| 275 | .channel_tile(8) |
| 276 | .channels(channels) |
| 277 | .rows(rows) |
| 278 | .output_stride(43) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 279 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neonfma_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 280 | } |
| 281 | } |
| 282 | } |
| 283 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 284 | TEST(F32_VMULCADDC_MINMAX_C8__NEONFMA_2X, inplace) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 285 | TEST_REQUIRES_ARM_NEON_FMA; |
| 286 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 287 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 288 | VMulCAddCMicrokernelTester() |
| 289 | .channel_tile(8) |
| 290 | .channels(channels) |
| 291 | .rows(rows) |
| 292 | .inplace(true) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 293 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neonfma_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 294 | } |
| 295 | } |
| 296 | } |
| 297 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 298 | TEST(F32_VMULCADDC_MINMAX_C8__NEONFMA_2X, qmin) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 299 | TEST_REQUIRES_ARM_NEON_FMA; |
| 300 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 301 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 302 | VMulCAddCMicrokernelTester() |
| 303 | .channel_tile(8) |
| 304 | .channels(channels) |
| 305 | .rows(rows) |
| 306 | .qmin(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 307 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neonfma_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 308 | } |
| 309 | } |
| 310 | } |
| 311 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 312 | TEST(F32_VMULCADDC_MINMAX_C8__NEONFMA_2X, qmax) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 313 | TEST_REQUIRES_ARM_NEON_FMA; |
| 314 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 315 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 316 | VMulCAddCMicrokernelTester() |
| 317 | .channel_tile(8) |
| 318 | .channels(channels) |
| 319 | .rows(rows) |
| 320 | .qmax(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 321 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neonfma_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 322 | } |
| 323 | } |
| 324 | } |
| 325 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 326 | |
| 327 | |
| 328 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 329 | TEST(F32_VMULCADDC_MINMAX_C4__NEON_2X, channels_eq_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 330 | TEST_REQUIRES_ARM_NEON; |
| 331 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 332 | .channel_tile(4) |
| 333 | .channels(4) |
| 334 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 335 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neon_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 336 | } |
| 337 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 338 | TEST(F32_VMULCADDC_MINMAX_C4__NEON_2X, channels_div_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 339 | TEST_REQUIRES_ARM_NEON; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 340 | for (size_t channels = 8; channels < 40; channels += 4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 341 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 342 | .channel_tile(4) |
| 343 | .channels(channels) |
| 344 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 345 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neon_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 346 | } |
| 347 | } |
| 348 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 349 | TEST(F32_VMULCADDC_MINMAX_C4__NEON_2X, channels_lt_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 350 | TEST_REQUIRES_ARM_NEON; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 351 | for (size_t channels = 1; channels < 4; channels++) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 352 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 353 | .channel_tile(4) |
| 354 | .channels(channels) |
| 355 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 356 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neon_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 357 | } |
| 358 | } |
| 359 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 360 | TEST(F32_VMULCADDC_MINMAX_C4__NEON_2X, channels_gt_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 361 | TEST_REQUIRES_ARM_NEON; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 362 | for (size_t channels = 5; channels < 8; channels++) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 363 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 364 | .channel_tile(4) |
| 365 | .channels(channels) |
| 366 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 367 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neon_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 368 | } |
| 369 | } |
| 370 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 371 | TEST(F32_VMULCADDC_MINMAX_C4__NEON_2X, rows_lt_2) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 372 | TEST_REQUIRES_ARM_NEON; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 373 | for (size_t rows = 1; rows < 2; rows++) { |
| 374 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 375 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 376 | .channel_tile(4) |
| 377 | .channels(channels) |
| 378 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 379 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neon_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 380 | } |
| 381 | } |
| 382 | } |
| 383 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 384 | TEST(F32_VMULCADDC_MINMAX_C4__NEON_2X, rows_div_2) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 385 | TEST_REQUIRES_ARM_NEON; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 386 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 387 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 388 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 389 | .channel_tile(4) |
| 390 | .channels(channels) |
| 391 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 392 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neon_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 393 | } |
| 394 | } |
| 395 | } |
| 396 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 397 | TEST(F32_VMULCADDC_MINMAX_C4__NEON_2X, rows_gt_2) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 398 | TEST_REQUIRES_ARM_NEON; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 399 | for (size_t rows = 3; rows < 4; rows++) { |
| 400 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 401 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 402 | .channel_tile(4) |
| 403 | .channels(channels) |
| 404 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 405 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neon_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 406 | } |
| 407 | } |
| 408 | } |
| 409 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 410 | TEST(F32_VMULCADDC_MINMAX_C4__NEON_2X, input_stride) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 411 | TEST_REQUIRES_ARM_NEON; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 412 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 413 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 414 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 415 | .channel_tile(4) |
| 416 | .channels(channels) |
| 417 | .rows(rows) |
| 418 | .input_stride(23) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 419 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neon_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 420 | } |
| 421 | } |
| 422 | } |
| 423 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 424 | TEST(F32_VMULCADDC_MINMAX_C4__NEON_2X, output_stride) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 425 | TEST_REQUIRES_ARM_NEON; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 426 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 427 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 428 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 429 | .channel_tile(4) |
| 430 | .channels(channels) |
| 431 | .rows(rows) |
| 432 | .output_stride(23) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 433 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neon_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 434 | } |
| 435 | } |
| 436 | } |
| 437 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 438 | TEST(F32_VMULCADDC_MINMAX_C4__NEON_2X, inplace) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 439 | TEST_REQUIRES_ARM_NEON; |
| 440 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 441 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 442 | VMulCAddCMicrokernelTester() |
| 443 | .channel_tile(4) |
| 444 | .channels(channels) |
| 445 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 446 | .inplace(true) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 447 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neon_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 448 | } |
| 449 | } |
| 450 | } |
| 451 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 452 | TEST(F32_VMULCADDC_MINMAX_C4__NEON_2X, qmin) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 453 | TEST_REQUIRES_ARM_NEON; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 454 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 455 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 456 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 457 | .channel_tile(4) |
| 458 | .channels(channels) |
| 459 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 460 | .qmin(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 461 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neon_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 462 | } |
| 463 | } |
| 464 | } |
| 465 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 466 | TEST(F32_VMULCADDC_MINMAX_C4__NEON_2X, qmax) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 467 | TEST_REQUIRES_ARM_NEON; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 468 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 469 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 470 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 471 | .channel_tile(4) |
| 472 | .channels(channels) |
| 473 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 474 | .qmax(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 475 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__neon_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 476 | } |
| 477 | } |
| 478 | } |
| 479 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 480 | |
| 481 | |
| 482 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 483 | TEST(F32_VMULCADDC_MINMAX_C8__NEON_2X, channels_eq_8) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 484 | TEST_REQUIRES_ARM_NEON; |
| 485 | VMulCAddCMicrokernelTester() |
| 486 | .channel_tile(8) |
| 487 | .channels(8) |
| 488 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 489 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neon_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 490 | } |
| 491 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 492 | TEST(F32_VMULCADDC_MINMAX_C8__NEON_2X, channels_div_8) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 493 | TEST_REQUIRES_ARM_NEON; |
| 494 | for (size_t channels = 16; channels < 80; channels += 8) { |
| 495 | VMulCAddCMicrokernelTester() |
| 496 | .channel_tile(8) |
| 497 | .channels(channels) |
| 498 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 499 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neon_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 500 | } |
| 501 | } |
| 502 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 503 | TEST(F32_VMULCADDC_MINMAX_C8__NEON_2X, channels_lt_8) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 504 | TEST_REQUIRES_ARM_NEON; |
| 505 | for (size_t channels = 1; channels < 8; channels++) { |
| 506 | VMulCAddCMicrokernelTester() |
| 507 | .channel_tile(8) |
| 508 | .channels(channels) |
| 509 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 510 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neon_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 511 | } |
| 512 | } |
| 513 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 514 | TEST(F32_VMULCADDC_MINMAX_C8__NEON_2X, channels_gt_8) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 515 | TEST_REQUIRES_ARM_NEON; |
| 516 | for (size_t channels = 9; channels < 16; channels++) { |
| 517 | VMulCAddCMicrokernelTester() |
| 518 | .channel_tile(8) |
| 519 | .channels(channels) |
| 520 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 521 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neon_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 522 | } |
| 523 | } |
| 524 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 525 | TEST(F32_VMULCADDC_MINMAX_C8__NEON_2X, rows_lt_2) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 526 | TEST_REQUIRES_ARM_NEON; |
| 527 | for (size_t rows = 1; rows < 2; rows++) { |
| 528 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 529 | VMulCAddCMicrokernelTester() |
| 530 | .channel_tile(8) |
| 531 | .channels(channels) |
| 532 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 533 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neon_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 534 | } |
| 535 | } |
| 536 | } |
| 537 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 538 | TEST(F32_VMULCADDC_MINMAX_C8__NEON_2X, rows_div_2) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 539 | TEST_REQUIRES_ARM_NEON; |
| 540 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 541 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 542 | VMulCAddCMicrokernelTester() |
| 543 | .channel_tile(8) |
| 544 | .channels(channels) |
| 545 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 546 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neon_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 547 | } |
| 548 | } |
| 549 | } |
| 550 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 551 | TEST(F32_VMULCADDC_MINMAX_C8__NEON_2X, rows_gt_2) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 552 | TEST_REQUIRES_ARM_NEON; |
| 553 | for (size_t rows = 3; rows < 4; rows++) { |
| 554 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 555 | VMulCAddCMicrokernelTester() |
| 556 | .channel_tile(8) |
| 557 | .channels(channels) |
| 558 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 559 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neon_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 560 | } |
| 561 | } |
| 562 | } |
| 563 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 564 | TEST(F32_VMULCADDC_MINMAX_C8__NEON_2X, input_stride) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 565 | TEST_REQUIRES_ARM_NEON; |
| 566 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 567 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 568 | VMulCAddCMicrokernelTester() |
| 569 | .channel_tile(8) |
| 570 | .channels(channels) |
| 571 | .rows(rows) |
| 572 | .input_stride(43) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 573 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neon_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 574 | } |
| 575 | } |
| 576 | } |
| 577 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 578 | TEST(F32_VMULCADDC_MINMAX_C8__NEON_2X, output_stride) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 579 | TEST_REQUIRES_ARM_NEON; |
| 580 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 581 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 582 | VMulCAddCMicrokernelTester() |
| 583 | .channel_tile(8) |
| 584 | .channels(channels) |
| 585 | .rows(rows) |
| 586 | .output_stride(43) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 587 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neon_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 588 | } |
| 589 | } |
| 590 | } |
| 591 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 592 | TEST(F32_VMULCADDC_MINMAX_C8__NEON_2X, inplace) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 593 | TEST_REQUIRES_ARM_NEON; |
| 594 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 595 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 596 | VMulCAddCMicrokernelTester() |
| 597 | .channel_tile(8) |
| 598 | .channels(channels) |
| 599 | .rows(rows) |
| 600 | .inplace(true) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 601 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neon_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 602 | } |
| 603 | } |
| 604 | } |
| 605 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 606 | TEST(F32_VMULCADDC_MINMAX_C8__NEON_2X, qmin) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 607 | TEST_REQUIRES_ARM_NEON; |
| 608 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 609 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 610 | VMulCAddCMicrokernelTester() |
| 611 | .channel_tile(8) |
| 612 | .channels(channels) |
| 613 | .rows(rows) |
| 614 | .qmin(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 615 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neon_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 616 | } |
| 617 | } |
| 618 | } |
| 619 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 620 | TEST(F32_VMULCADDC_MINMAX_C8__NEON_2X, qmax) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 621 | TEST_REQUIRES_ARM_NEON; |
| 622 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 623 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 624 | VMulCAddCMicrokernelTester() |
| 625 | .channel_tile(8) |
| 626 | .channels(channels) |
| 627 | .rows(rows) |
| 628 | .qmax(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 629 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__neon_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 630 | } |
| 631 | } |
| 632 | } |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 633 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 634 | |
| 635 | |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 636 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 637 | TEST(F32_VMULCADDC_MINMAX_C4__SSE_2X, channels_eq_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 638 | TEST_REQUIRES_X86_SSE; |
| 639 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 640 | .channel_tile(4) |
| 641 | .channels(4) |
| 642 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 643 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__sse_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 644 | } |
| 645 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 646 | TEST(F32_VMULCADDC_MINMAX_C4__SSE_2X, channels_div_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 647 | TEST_REQUIRES_X86_SSE; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 648 | for (size_t channels = 8; channels < 40; channels += 4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 649 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 650 | .channel_tile(4) |
| 651 | .channels(channels) |
| 652 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 653 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__sse_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 654 | } |
| 655 | } |
| 656 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 657 | TEST(F32_VMULCADDC_MINMAX_C4__SSE_2X, channels_lt_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 658 | TEST_REQUIRES_X86_SSE; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 659 | for (size_t channels = 1; channels < 4; channels++) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 660 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 661 | .channel_tile(4) |
| 662 | .channels(channels) |
| 663 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 664 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__sse_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 665 | } |
| 666 | } |
| 667 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 668 | TEST(F32_VMULCADDC_MINMAX_C4__SSE_2X, channels_gt_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 669 | TEST_REQUIRES_X86_SSE; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 670 | for (size_t channels = 5; channels < 8; channels++) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 671 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 672 | .channel_tile(4) |
| 673 | .channels(channels) |
| 674 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 675 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__sse_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 676 | } |
| 677 | } |
| 678 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 679 | TEST(F32_VMULCADDC_MINMAX_C4__SSE_2X, rows_lt_2) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 680 | TEST_REQUIRES_X86_SSE; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 681 | for (size_t rows = 1; rows < 2; rows++) { |
| 682 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 683 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 684 | .channel_tile(4) |
| 685 | .channels(channels) |
| 686 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 687 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__sse_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 688 | } |
| 689 | } |
| 690 | } |
| 691 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 692 | TEST(F32_VMULCADDC_MINMAX_C4__SSE_2X, rows_div_2) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 693 | TEST_REQUIRES_X86_SSE; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 694 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 695 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 696 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 697 | .channel_tile(4) |
| 698 | .channels(channels) |
| 699 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 700 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__sse_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 701 | } |
| 702 | } |
| 703 | } |
| 704 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 705 | TEST(F32_VMULCADDC_MINMAX_C4__SSE_2X, rows_gt_2) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 706 | TEST_REQUIRES_X86_SSE; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 707 | for (size_t rows = 3; rows < 4; rows++) { |
| 708 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 709 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 710 | .channel_tile(4) |
| 711 | .channels(channels) |
| 712 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 713 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__sse_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 714 | } |
| 715 | } |
| 716 | } |
| 717 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 718 | TEST(F32_VMULCADDC_MINMAX_C4__SSE_2X, input_stride) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 719 | TEST_REQUIRES_X86_SSE; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 720 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 721 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 722 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 723 | .channel_tile(4) |
| 724 | .channels(channels) |
| 725 | .rows(rows) |
| 726 | .input_stride(23) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 727 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__sse_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 728 | } |
| 729 | } |
| 730 | } |
| 731 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 732 | TEST(F32_VMULCADDC_MINMAX_C4__SSE_2X, output_stride) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 733 | TEST_REQUIRES_X86_SSE; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 734 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 735 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 736 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 737 | .channel_tile(4) |
| 738 | .channels(channels) |
| 739 | .rows(rows) |
| 740 | .output_stride(23) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 741 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__sse_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 742 | } |
| 743 | } |
| 744 | } |
| 745 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 746 | TEST(F32_VMULCADDC_MINMAX_C4__SSE_2X, inplace) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 747 | TEST_REQUIRES_X86_SSE; |
| 748 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 749 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 750 | VMulCAddCMicrokernelTester() |
| 751 | .channel_tile(4) |
| 752 | .channels(channels) |
| 753 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 754 | .inplace(true) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 755 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__sse_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 756 | } |
| 757 | } |
| 758 | } |
| 759 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 760 | TEST(F32_VMULCADDC_MINMAX_C4__SSE_2X, qmin) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 761 | TEST_REQUIRES_X86_SSE; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 762 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 763 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 764 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 765 | .channel_tile(4) |
| 766 | .channels(channels) |
| 767 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 768 | .qmin(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 769 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__sse_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 770 | } |
| 771 | } |
| 772 | } |
| 773 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 774 | TEST(F32_VMULCADDC_MINMAX_C4__SSE_2X, qmax) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 775 | TEST_REQUIRES_X86_SSE; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 776 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 777 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 778 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 779 | .channel_tile(4) |
| 780 | .channels(channels) |
| 781 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 782 | .qmax(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 783 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__sse_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 784 | } |
| 785 | } |
| 786 | } |
| 787 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 788 | |
| 789 | |
| 790 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 791 | TEST(F32_VMULCADDC_MINMAX_C8__SSE_2X, channels_eq_8) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 792 | TEST_REQUIRES_X86_SSE; |
| 793 | VMulCAddCMicrokernelTester() |
| 794 | .channel_tile(8) |
| 795 | .channels(8) |
| 796 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 797 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__sse_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 798 | } |
| 799 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 800 | TEST(F32_VMULCADDC_MINMAX_C8__SSE_2X, channels_div_8) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 801 | TEST_REQUIRES_X86_SSE; |
| 802 | for (size_t channels = 16; channels < 80; channels += 8) { |
| 803 | VMulCAddCMicrokernelTester() |
| 804 | .channel_tile(8) |
| 805 | .channels(channels) |
| 806 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 807 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__sse_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 808 | } |
| 809 | } |
| 810 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 811 | TEST(F32_VMULCADDC_MINMAX_C8__SSE_2X, channels_lt_8) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 812 | TEST_REQUIRES_X86_SSE; |
| 813 | for (size_t channels = 1; channels < 8; channels++) { |
| 814 | VMulCAddCMicrokernelTester() |
| 815 | .channel_tile(8) |
| 816 | .channels(channels) |
| 817 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 818 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__sse_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 819 | } |
| 820 | } |
| 821 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 822 | TEST(F32_VMULCADDC_MINMAX_C8__SSE_2X, channels_gt_8) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 823 | TEST_REQUIRES_X86_SSE; |
| 824 | for (size_t channels = 9; channels < 16; channels++) { |
| 825 | VMulCAddCMicrokernelTester() |
| 826 | .channel_tile(8) |
| 827 | .channels(channels) |
| 828 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 829 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__sse_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 830 | } |
| 831 | } |
| 832 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 833 | TEST(F32_VMULCADDC_MINMAX_C8__SSE_2X, rows_lt_2) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 834 | TEST_REQUIRES_X86_SSE; |
| 835 | for (size_t rows = 1; rows < 2; rows++) { |
| 836 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 837 | VMulCAddCMicrokernelTester() |
| 838 | .channel_tile(8) |
| 839 | .channels(channels) |
| 840 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 841 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__sse_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 842 | } |
| 843 | } |
| 844 | } |
| 845 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 846 | TEST(F32_VMULCADDC_MINMAX_C8__SSE_2X, rows_div_2) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 847 | TEST_REQUIRES_X86_SSE; |
| 848 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 849 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 850 | VMulCAddCMicrokernelTester() |
| 851 | .channel_tile(8) |
| 852 | .channels(channels) |
| 853 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 854 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__sse_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 855 | } |
| 856 | } |
| 857 | } |
| 858 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 859 | TEST(F32_VMULCADDC_MINMAX_C8__SSE_2X, rows_gt_2) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 860 | TEST_REQUIRES_X86_SSE; |
| 861 | for (size_t rows = 3; rows < 4; rows++) { |
| 862 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 863 | VMulCAddCMicrokernelTester() |
| 864 | .channel_tile(8) |
| 865 | .channels(channels) |
| 866 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 867 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__sse_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 868 | } |
| 869 | } |
| 870 | } |
| 871 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 872 | TEST(F32_VMULCADDC_MINMAX_C8__SSE_2X, input_stride) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 873 | TEST_REQUIRES_X86_SSE; |
| 874 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 875 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 876 | VMulCAddCMicrokernelTester() |
| 877 | .channel_tile(8) |
| 878 | .channels(channels) |
| 879 | .rows(rows) |
| 880 | .input_stride(43) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 881 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__sse_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 882 | } |
| 883 | } |
| 884 | } |
| 885 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 886 | TEST(F32_VMULCADDC_MINMAX_C8__SSE_2X, output_stride) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 887 | TEST_REQUIRES_X86_SSE; |
| 888 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 889 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 890 | VMulCAddCMicrokernelTester() |
| 891 | .channel_tile(8) |
| 892 | .channels(channels) |
| 893 | .rows(rows) |
| 894 | .output_stride(43) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 895 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__sse_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 896 | } |
| 897 | } |
| 898 | } |
| 899 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 900 | TEST(F32_VMULCADDC_MINMAX_C8__SSE_2X, inplace) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 901 | TEST_REQUIRES_X86_SSE; |
| 902 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 903 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 904 | VMulCAddCMicrokernelTester() |
| 905 | .channel_tile(8) |
| 906 | .channels(channels) |
| 907 | .rows(rows) |
| 908 | .inplace(true) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 909 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__sse_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 910 | } |
| 911 | } |
| 912 | } |
| 913 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 914 | TEST(F32_VMULCADDC_MINMAX_C8__SSE_2X, qmin) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 915 | TEST_REQUIRES_X86_SSE; |
| 916 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 917 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 918 | VMulCAddCMicrokernelTester() |
| 919 | .channel_tile(8) |
| 920 | .channels(channels) |
| 921 | .rows(rows) |
| 922 | .qmin(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 923 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__sse_2x); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 924 | } |
| 925 | } |
| 926 | } |
| 927 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 928 | TEST(F32_VMULCADDC_MINMAX_C8__SSE_2X, qmax) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 929 | TEST_REQUIRES_X86_SSE; |
| 930 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 931 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 932 | VMulCAddCMicrokernelTester() |
| 933 | .channel_tile(8) |
| 934 | .channels(channels) |
| 935 | .rows(rows) |
| 936 | .qmax(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 937 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__sse_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 938 | } |
| 939 | } |
| 940 | } |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 941 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 942 | |
| 943 | |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 944 | #if XNN_ARCH_WASMSIMD |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 945 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_ARM_2X, channels_eq_4) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 946 | VMulCAddCMicrokernelTester() |
| 947 | .channel_tile(4) |
| 948 | .channels(4) |
| 949 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 950 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 951 | } |
| 952 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 953 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_ARM_2X, channels_div_4) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 954 | for (size_t channels = 8; channels < 40; channels += 4) { |
| 955 | VMulCAddCMicrokernelTester() |
| 956 | .channel_tile(4) |
| 957 | .channels(channels) |
| 958 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 959 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 960 | } |
| 961 | } |
| 962 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 963 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_ARM_2X, channels_lt_4) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 964 | for (size_t channels = 1; channels < 4; channels++) { |
| 965 | VMulCAddCMicrokernelTester() |
| 966 | .channel_tile(4) |
| 967 | .channels(channels) |
| 968 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 969 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 970 | } |
| 971 | } |
| 972 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 973 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_ARM_2X, channels_gt_4) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 974 | for (size_t channels = 5; channels < 8; channels++) { |
| 975 | VMulCAddCMicrokernelTester() |
| 976 | .channel_tile(4) |
| 977 | .channels(channels) |
| 978 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 979 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 980 | } |
| 981 | } |
| 982 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 983 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_ARM_2X, rows_lt_2) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 984 | for (size_t rows = 1; rows < 2; rows++) { |
| 985 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 986 | VMulCAddCMicrokernelTester() |
| 987 | .channel_tile(4) |
| 988 | .channels(channels) |
| 989 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 990 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 991 | } |
| 992 | } |
| 993 | } |
| 994 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 995 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_ARM_2X, rows_div_2) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 996 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 997 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 998 | VMulCAddCMicrokernelTester() |
| 999 | .channel_tile(4) |
| 1000 | .channels(channels) |
| 1001 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1002 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1003 | } |
| 1004 | } |
| 1005 | } |
| 1006 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1007 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_ARM_2X, rows_gt_2) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1008 | for (size_t rows = 3; rows < 4; rows++) { |
| 1009 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1010 | VMulCAddCMicrokernelTester() |
| 1011 | .channel_tile(4) |
| 1012 | .channels(channels) |
| 1013 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1014 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1015 | } |
| 1016 | } |
| 1017 | } |
| 1018 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1019 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_ARM_2X, input_stride) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1020 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1021 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1022 | VMulCAddCMicrokernelTester() |
| 1023 | .channel_tile(4) |
| 1024 | .channels(channels) |
| 1025 | .rows(rows) |
| 1026 | .input_stride(23) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1027 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1028 | } |
| 1029 | } |
| 1030 | } |
| 1031 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1032 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_ARM_2X, output_stride) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1033 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1034 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1035 | VMulCAddCMicrokernelTester() |
| 1036 | .channel_tile(4) |
| 1037 | .channels(channels) |
| 1038 | .rows(rows) |
| 1039 | .output_stride(23) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1040 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1041 | } |
| 1042 | } |
| 1043 | } |
| 1044 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1045 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_ARM_2X, inplace) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1046 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1047 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1048 | VMulCAddCMicrokernelTester() |
| 1049 | .channel_tile(4) |
| 1050 | .channels(channels) |
| 1051 | .rows(rows) |
| 1052 | .inplace(true) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1053 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1054 | } |
| 1055 | } |
| 1056 | } |
| 1057 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1058 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_ARM_2X, qmin) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1059 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1060 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1061 | VMulCAddCMicrokernelTester() |
| 1062 | .channel_tile(4) |
| 1063 | .channels(channels) |
| 1064 | .rows(rows) |
| 1065 | .qmin(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1066 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1067 | } |
| 1068 | } |
| 1069 | } |
| 1070 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1071 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_ARM_2X, qmax) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1072 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1073 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1074 | VMulCAddCMicrokernelTester() |
| 1075 | .channel_tile(4) |
| 1076 | .channels(channels) |
| 1077 | .rows(rows) |
| 1078 | .qmax(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1079 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1080 | } |
| 1081 | } |
| 1082 | } |
| 1083 | #endif // XNN_ARCH_WASMSIMD |
| 1084 | |
| 1085 | |
| 1086 | #if XNN_ARCH_WASMSIMD |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1087 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_ARM_2X, channels_eq_8) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1088 | VMulCAddCMicrokernelTester() |
| 1089 | .channel_tile(8) |
| 1090 | .channels(8) |
| 1091 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1092 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1093 | } |
| 1094 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1095 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_ARM_2X, channels_div_8) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1096 | for (size_t channels = 16; channels < 80; channels += 8) { |
| 1097 | VMulCAddCMicrokernelTester() |
| 1098 | .channel_tile(8) |
| 1099 | .channels(channels) |
| 1100 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1101 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1102 | } |
| 1103 | } |
| 1104 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1105 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_ARM_2X, channels_lt_8) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1106 | for (size_t channels = 1; channels < 8; channels++) { |
| 1107 | VMulCAddCMicrokernelTester() |
| 1108 | .channel_tile(8) |
| 1109 | .channels(channels) |
| 1110 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1111 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1112 | } |
| 1113 | } |
| 1114 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1115 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_ARM_2X, channels_gt_8) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1116 | for (size_t channels = 9; channels < 16; channels++) { |
| 1117 | VMulCAddCMicrokernelTester() |
| 1118 | .channel_tile(8) |
| 1119 | .channels(channels) |
| 1120 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1121 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1122 | } |
| 1123 | } |
| 1124 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1125 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_ARM_2X, rows_lt_2) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1126 | for (size_t rows = 1; rows < 2; rows++) { |
| 1127 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1128 | VMulCAddCMicrokernelTester() |
| 1129 | .channel_tile(8) |
| 1130 | .channels(channels) |
| 1131 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1132 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1133 | } |
| 1134 | } |
| 1135 | } |
| 1136 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1137 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_ARM_2X, rows_div_2) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1138 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 1139 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1140 | VMulCAddCMicrokernelTester() |
| 1141 | .channel_tile(8) |
| 1142 | .channels(channels) |
| 1143 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1144 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1145 | } |
| 1146 | } |
| 1147 | } |
| 1148 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1149 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_ARM_2X, rows_gt_2) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1150 | for (size_t rows = 3; rows < 4; rows++) { |
| 1151 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1152 | VMulCAddCMicrokernelTester() |
| 1153 | .channel_tile(8) |
| 1154 | .channels(channels) |
| 1155 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1156 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1157 | } |
| 1158 | } |
| 1159 | } |
| 1160 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1161 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_ARM_2X, input_stride) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1162 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1163 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1164 | VMulCAddCMicrokernelTester() |
| 1165 | .channel_tile(8) |
| 1166 | .channels(channels) |
| 1167 | .rows(rows) |
| 1168 | .input_stride(43) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1169 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1170 | } |
| 1171 | } |
| 1172 | } |
| 1173 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1174 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_ARM_2X, output_stride) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1175 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1176 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1177 | VMulCAddCMicrokernelTester() |
| 1178 | .channel_tile(8) |
| 1179 | .channels(channels) |
| 1180 | .rows(rows) |
| 1181 | .output_stride(43) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1182 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1183 | } |
| 1184 | } |
| 1185 | } |
| 1186 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1187 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_ARM_2X, inplace) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1188 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1189 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1190 | VMulCAddCMicrokernelTester() |
| 1191 | .channel_tile(8) |
| 1192 | .channels(channels) |
| 1193 | .rows(rows) |
| 1194 | .inplace(true) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1195 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1196 | } |
| 1197 | } |
| 1198 | } |
| 1199 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1200 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_ARM_2X, qmin) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1201 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1202 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1203 | VMulCAddCMicrokernelTester() |
| 1204 | .channel_tile(8) |
| 1205 | .channels(channels) |
| 1206 | .rows(rows) |
| 1207 | .qmin(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1208 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1209 | } |
| 1210 | } |
| 1211 | } |
| 1212 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1213 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_ARM_2X, qmax) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1214 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1215 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1216 | VMulCAddCMicrokernelTester() |
| 1217 | .channel_tile(8) |
| 1218 | .channels(channels) |
| 1219 | .rows(rows) |
| 1220 | .qmax(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1221 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_arm_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1222 | } |
| 1223 | } |
| 1224 | } |
| 1225 | #endif // XNN_ARCH_WASMSIMD |
| 1226 | |
| 1227 | |
| 1228 | #if XNN_ARCH_WASMSIMD |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1229 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_X86_2X, channels_eq_4) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1230 | VMulCAddCMicrokernelTester() |
| 1231 | .channel_tile(4) |
| 1232 | .channels(4) |
| 1233 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1234 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1235 | } |
| 1236 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1237 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_X86_2X, channels_div_4) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1238 | for (size_t channels = 8; channels < 40; channels += 4) { |
| 1239 | VMulCAddCMicrokernelTester() |
| 1240 | .channel_tile(4) |
| 1241 | .channels(channels) |
| 1242 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1243 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1244 | } |
| 1245 | } |
| 1246 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1247 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_X86_2X, channels_lt_4) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1248 | for (size_t channels = 1; channels < 4; channels++) { |
| 1249 | VMulCAddCMicrokernelTester() |
| 1250 | .channel_tile(4) |
| 1251 | .channels(channels) |
| 1252 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1253 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1254 | } |
| 1255 | } |
| 1256 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1257 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_X86_2X, channels_gt_4) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1258 | for (size_t channels = 5; channels < 8; channels++) { |
| 1259 | VMulCAddCMicrokernelTester() |
| 1260 | .channel_tile(4) |
| 1261 | .channels(channels) |
| 1262 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1263 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1264 | } |
| 1265 | } |
| 1266 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1267 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_X86_2X, rows_lt_2) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1268 | for (size_t rows = 1; rows < 2; rows++) { |
| 1269 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1270 | VMulCAddCMicrokernelTester() |
| 1271 | .channel_tile(4) |
| 1272 | .channels(channels) |
| 1273 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1274 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1275 | } |
| 1276 | } |
| 1277 | } |
| 1278 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1279 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_X86_2X, rows_div_2) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1280 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 1281 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1282 | VMulCAddCMicrokernelTester() |
| 1283 | .channel_tile(4) |
| 1284 | .channels(channels) |
| 1285 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1286 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1287 | } |
| 1288 | } |
| 1289 | } |
| 1290 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1291 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_X86_2X, rows_gt_2) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1292 | for (size_t rows = 3; rows < 4; rows++) { |
| 1293 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1294 | VMulCAddCMicrokernelTester() |
| 1295 | .channel_tile(4) |
| 1296 | .channels(channels) |
| 1297 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1298 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1299 | } |
| 1300 | } |
| 1301 | } |
| 1302 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1303 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_X86_2X, input_stride) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1304 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1305 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1306 | VMulCAddCMicrokernelTester() |
| 1307 | .channel_tile(4) |
| 1308 | .channels(channels) |
| 1309 | .rows(rows) |
| 1310 | .input_stride(23) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1311 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1312 | } |
| 1313 | } |
| 1314 | } |
| 1315 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1316 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_X86_2X, output_stride) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1317 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1318 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1319 | VMulCAddCMicrokernelTester() |
| 1320 | .channel_tile(4) |
| 1321 | .channels(channels) |
| 1322 | .rows(rows) |
| 1323 | .output_stride(23) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1324 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1325 | } |
| 1326 | } |
| 1327 | } |
| 1328 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1329 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_X86_2X, inplace) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1330 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1331 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1332 | VMulCAddCMicrokernelTester() |
| 1333 | .channel_tile(4) |
| 1334 | .channels(channels) |
| 1335 | .rows(rows) |
| 1336 | .inplace(true) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1337 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1338 | } |
| 1339 | } |
| 1340 | } |
| 1341 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1342 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_X86_2X, qmin) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1343 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1344 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1345 | VMulCAddCMicrokernelTester() |
| 1346 | .channel_tile(4) |
| 1347 | .channels(channels) |
| 1348 | .rows(rows) |
| 1349 | .qmin(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1350 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1351 | } |
| 1352 | } |
| 1353 | } |
| 1354 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1355 | TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_X86_2X, qmax) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1356 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1357 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1358 | VMulCAddCMicrokernelTester() |
| 1359 | .channel_tile(4) |
| 1360 | .channels(channels) |
| 1361 | .rows(rows) |
| 1362 | .qmax(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1363 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1364 | } |
| 1365 | } |
| 1366 | } |
| 1367 | #endif // XNN_ARCH_WASMSIMD |
| 1368 | |
| 1369 | |
| 1370 | #if XNN_ARCH_WASMSIMD |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1371 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_X86_2X, channels_eq_8) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1372 | VMulCAddCMicrokernelTester() |
| 1373 | .channel_tile(8) |
| 1374 | .channels(8) |
| 1375 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1376 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1377 | } |
| 1378 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1379 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_X86_2X, channels_div_8) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1380 | for (size_t channels = 16; channels < 80; channels += 8) { |
| 1381 | VMulCAddCMicrokernelTester() |
| 1382 | .channel_tile(8) |
| 1383 | .channels(channels) |
| 1384 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1385 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1386 | } |
| 1387 | } |
| 1388 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1389 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_X86_2X, channels_lt_8) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1390 | for (size_t channels = 1; channels < 8; channels++) { |
| 1391 | VMulCAddCMicrokernelTester() |
| 1392 | .channel_tile(8) |
| 1393 | .channels(channels) |
| 1394 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1395 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1396 | } |
| 1397 | } |
| 1398 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1399 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_X86_2X, channels_gt_8) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1400 | for (size_t channels = 9; channels < 16; channels++) { |
| 1401 | VMulCAddCMicrokernelTester() |
| 1402 | .channel_tile(8) |
| 1403 | .channels(channels) |
| 1404 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1405 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1406 | } |
| 1407 | } |
| 1408 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1409 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_X86_2X, rows_lt_2) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1410 | for (size_t rows = 1; rows < 2; rows++) { |
| 1411 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1412 | VMulCAddCMicrokernelTester() |
| 1413 | .channel_tile(8) |
| 1414 | .channels(channels) |
| 1415 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1416 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1417 | } |
| 1418 | } |
| 1419 | } |
| 1420 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1421 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_X86_2X, rows_div_2) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1422 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 1423 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1424 | VMulCAddCMicrokernelTester() |
| 1425 | .channel_tile(8) |
| 1426 | .channels(channels) |
| 1427 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1428 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1429 | } |
| 1430 | } |
| 1431 | } |
| 1432 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1433 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_X86_2X, rows_gt_2) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1434 | for (size_t rows = 3; rows < 4; rows++) { |
| 1435 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1436 | VMulCAddCMicrokernelTester() |
| 1437 | .channel_tile(8) |
| 1438 | .channels(channels) |
| 1439 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1440 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1441 | } |
| 1442 | } |
| 1443 | } |
| 1444 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1445 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_X86_2X, input_stride) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1446 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1447 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1448 | VMulCAddCMicrokernelTester() |
| 1449 | .channel_tile(8) |
| 1450 | .channels(channels) |
| 1451 | .rows(rows) |
| 1452 | .input_stride(43) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1453 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1454 | } |
| 1455 | } |
| 1456 | } |
| 1457 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1458 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_X86_2X, output_stride) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1459 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1460 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1461 | VMulCAddCMicrokernelTester() |
| 1462 | .channel_tile(8) |
| 1463 | .channels(channels) |
| 1464 | .rows(rows) |
| 1465 | .output_stride(43) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1466 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1467 | } |
| 1468 | } |
| 1469 | } |
| 1470 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1471 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_X86_2X, inplace) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1472 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1473 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1474 | VMulCAddCMicrokernelTester() |
| 1475 | .channel_tile(8) |
| 1476 | .channels(channels) |
| 1477 | .rows(rows) |
| 1478 | .inplace(true) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1479 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1480 | } |
| 1481 | } |
| 1482 | } |
| 1483 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1484 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_X86_2X, qmin) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1485 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1486 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1487 | VMulCAddCMicrokernelTester() |
| 1488 | .channel_tile(8) |
| 1489 | .channels(channels) |
| 1490 | .rows(rows) |
| 1491 | .qmin(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1492 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1493 | } |
| 1494 | } |
| 1495 | } |
| 1496 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1497 | TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_X86_2X, qmax) { |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1498 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1499 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1500 | VMulCAddCMicrokernelTester() |
| 1501 | .channel_tile(8) |
| 1502 | .channels(channels) |
| 1503 | .rows(rows) |
| 1504 | .qmax(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1505 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c8__wasmsimd_x86_2x); |
Marat Dukhan | d816f62 | 2020-07-15 10:14:39 -0700 | [diff] [blame] | 1506 | } |
| 1507 | } |
| 1508 | } |
| 1509 | #endif // XNN_ARCH_WASMSIMD |
| 1510 | |
| 1511 | |
Marat Dukhan | fb5b20a | 2020-06-26 13:14:50 -0700 | [diff] [blame] | 1512 | #if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1513 | TEST(F32_VMULCADDC_MINMAX_C1__WASM_2X, channels_eq_1) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1514 | VMulCAddCMicrokernelTester() |
| 1515 | .channel_tile(1) |
| 1516 | .channels(1) |
| 1517 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1518 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c1__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1519 | } |
| 1520 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1521 | TEST(F32_VMULCADDC_MINMAX_C1__WASM_2X, channels_gt_1) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1522 | for (size_t channels = 2; channels < 10; channels++) { |
| 1523 | VMulCAddCMicrokernelTester() |
| 1524 | .channel_tile(1) |
| 1525 | .channels(channels) |
| 1526 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1527 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c1__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1528 | } |
| 1529 | } |
| 1530 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1531 | TEST(F32_VMULCADDC_MINMAX_C1__WASM_2X, rows_lt_2) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1532 | for (size_t rows = 1; rows < 2; rows++) { |
| 1533 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 1534 | VMulCAddCMicrokernelTester() |
| 1535 | .channel_tile(1) |
| 1536 | .channels(channels) |
| 1537 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1538 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c1__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1539 | } |
| 1540 | } |
| 1541 | } |
| 1542 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1543 | TEST(F32_VMULCADDC_MINMAX_C1__WASM_2X, rows_div_2) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1544 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 1545 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 1546 | VMulCAddCMicrokernelTester() |
| 1547 | .channel_tile(1) |
| 1548 | .channels(channels) |
| 1549 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1550 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c1__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1551 | } |
| 1552 | } |
| 1553 | } |
| 1554 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1555 | TEST(F32_VMULCADDC_MINMAX_C1__WASM_2X, rows_gt_2) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1556 | for (size_t rows = 3; rows < 4; rows++) { |
| 1557 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 1558 | VMulCAddCMicrokernelTester() |
| 1559 | .channel_tile(1) |
| 1560 | .channels(channels) |
| 1561 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1562 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c1__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1563 | } |
| 1564 | } |
| 1565 | } |
| 1566 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1567 | TEST(F32_VMULCADDC_MINMAX_C1__WASM_2X, input_stride) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1568 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1569 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 1570 | VMulCAddCMicrokernelTester() |
| 1571 | .channel_tile(1) |
| 1572 | .channels(channels) |
| 1573 | .rows(rows) |
| 1574 | .input_stride(7) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1575 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c1__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1576 | } |
| 1577 | } |
| 1578 | } |
| 1579 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1580 | TEST(F32_VMULCADDC_MINMAX_C1__WASM_2X, output_stride) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1581 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1582 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 1583 | VMulCAddCMicrokernelTester() |
| 1584 | .channel_tile(1) |
| 1585 | .channels(channels) |
| 1586 | .rows(rows) |
| 1587 | .output_stride(7) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1588 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c1__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1589 | } |
| 1590 | } |
| 1591 | } |
| 1592 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1593 | TEST(F32_VMULCADDC_MINMAX_C1__WASM_2X, inplace) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1594 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1595 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 1596 | VMulCAddCMicrokernelTester() |
| 1597 | .channel_tile(1) |
| 1598 | .channels(channels) |
| 1599 | .rows(rows) |
| 1600 | .inplace(true) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1601 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c1__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1602 | } |
| 1603 | } |
| 1604 | } |
| 1605 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1606 | TEST(F32_VMULCADDC_MINMAX_C1__WASM_2X, qmin) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1607 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1608 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 1609 | VMulCAddCMicrokernelTester() |
| 1610 | .channel_tile(1) |
| 1611 | .channels(channels) |
| 1612 | .rows(rows) |
| 1613 | .qmin(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1614 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c1__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1615 | } |
| 1616 | } |
| 1617 | } |
| 1618 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1619 | TEST(F32_VMULCADDC_MINMAX_C1__WASM_2X, qmax) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1620 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1621 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 1622 | VMulCAddCMicrokernelTester() |
| 1623 | .channel_tile(1) |
| 1624 | .channels(channels) |
| 1625 | .rows(rows) |
| 1626 | .qmax(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1627 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c1__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1628 | } |
| 1629 | } |
| 1630 | } |
Marat Dukhan | fb5b20a | 2020-06-26 13:14:50 -0700 | [diff] [blame] | 1631 | #endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1632 | |
| 1633 | |
Marat Dukhan | fb5b20a | 2020-06-26 13:14:50 -0700 | [diff] [blame] | 1634 | #if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1635 | TEST(F32_VMULCADDC_MINMAX_C2__WASM_2X, channels_eq_2) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1636 | VMulCAddCMicrokernelTester() |
| 1637 | .channel_tile(2) |
| 1638 | .channels(2) |
| 1639 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1640 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1641 | } |
| 1642 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1643 | TEST(F32_VMULCADDC_MINMAX_C2__WASM_2X, channels_div_2) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1644 | for (size_t channels = 4; channels < 20; channels += 2) { |
| 1645 | VMulCAddCMicrokernelTester() |
| 1646 | .channel_tile(2) |
| 1647 | .channels(channels) |
| 1648 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1649 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1650 | } |
| 1651 | } |
| 1652 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1653 | TEST(F32_VMULCADDC_MINMAX_C2__WASM_2X, channels_lt_2) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1654 | for (size_t channels = 1; channels < 2; channels++) { |
| 1655 | VMulCAddCMicrokernelTester() |
| 1656 | .channel_tile(2) |
| 1657 | .channels(channels) |
| 1658 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1659 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1660 | } |
| 1661 | } |
| 1662 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1663 | TEST(F32_VMULCADDC_MINMAX_C2__WASM_2X, channels_gt_2) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1664 | for (size_t channels = 3; channels < 4; channels++) { |
| 1665 | VMulCAddCMicrokernelTester() |
| 1666 | .channel_tile(2) |
| 1667 | .channels(channels) |
| 1668 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1669 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1670 | } |
| 1671 | } |
| 1672 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1673 | TEST(F32_VMULCADDC_MINMAX_C2__WASM_2X, rows_lt_2) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1674 | for (size_t rows = 1; rows < 2; rows++) { |
| 1675 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1676 | VMulCAddCMicrokernelTester() |
| 1677 | .channel_tile(2) |
| 1678 | .channels(channels) |
| 1679 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1680 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1681 | } |
| 1682 | } |
| 1683 | } |
| 1684 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1685 | TEST(F32_VMULCADDC_MINMAX_C2__WASM_2X, rows_div_2) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1686 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 1687 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1688 | VMulCAddCMicrokernelTester() |
| 1689 | .channel_tile(2) |
| 1690 | .channels(channels) |
| 1691 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1692 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1693 | } |
| 1694 | } |
| 1695 | } |
| 1696 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1697 | TEST(F32_VMULCADDC_MINMAX_C2__WASM_2X, rows_gt_2) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1698 | for (size_t rows = 3; rows < 4; rows++) { |
| 1699 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1700 | VMulCAddCMicrokernelTester() |
| 1701 | .channel_tile(2) |
| 1702 | .channels(channels) |
| 1703 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1704 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1705 | } |
| 1706 | } |
| 1707 | } |
| 1708 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1709 | TEST(F32_VMULCADDC_MINMAX_C2__WASM_2X, input_stride) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1710 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1711 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1712 | VMulCAddCMicrokernelTester() |
| 1713 | .channel_tile(2) |
| 1714 | .channels(channels) |
| 1715 | .rows(rows) |
| 1716 | .input_stride(13) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1717 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1718 | } |
| 1719 | } |
| 1720 | } |
| 1721 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1722 | TEST(F32_VMULCADDC_MINMAX_C2__WASM_2X, output_stride) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1723 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1724 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1725 | VMulCAddCMicrokernelTester() |
| 1726 | .channel_tile(2) |
| 1727 | .channels(channels) |
| 1728 | .rows(rows) |
| 1729 | .output_stride(13) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1730 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1731 | } |
| 1732 | } |
| 1733 | } |
| 1734 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1735 | TEST(F32_VMULCADDC_MINMAX_C2__WASM_2X, inplace) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1736 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1737 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1738 | VMulCAddCMicrokernelTester() |
| 1739 | .channel_tile(2) |
| 1740 | .channels(channels) |
| 1741 | .rows(rows) |
| 1742 | .inplace(true) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1743 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1744 | } |
| 1745 | } |
| 1746 | } |
| 1747 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1748 | TEST(F32_VMULCADDC_MINMAX_C2__WASM_2X, qmin) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1749 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1750 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1751 | VMulCAddCMicrokernelTester() |
| 1752 | .channel_tile(2) |
| 1753 | .channels(channels) |
| 1754 | .rows(rows) |
| 1755 | .qmin(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1756 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1757 | } |
| 1758 | } |
| 1759 | } |
| 1760 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1761 | TEST(F32_VMULCADDC_MINMAX_C2__WASM_2X, qmax) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1762 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1763 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1764 | VMulCAddCMicrokernelTester() |
| 1765 | .channel_tile(2) |
| 1766 | .channels(channels) |
| 1767 | .rows(rows) |
| 1768 | .qmax(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1769 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1770 | } |
| 1771 | } |
| 1772 | } |
Marat Dukhan | fb5b20a | 2020-06-26 13:14:50 -0700 | [diff] [blame] | 1773 | #endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1774 | |
| 1775 | |
Marat Dukhan | fb5b20a | 2020-06-26 13:14:50 -0700 | [diff] [blame] | 1776 | #if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1777 | TEST(F32_VMULCADDC_MINMAX_C4__WASM_2X, channels_eq_4) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1778 | VMulCAddCMicrokernelTester() |
| 1779 | .channel_tile(4) |
| 1780 | .channels(4) |
| 1781 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1782 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1783 | } |
| 1784 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1785 | TEST(F32_VMULCADDC_MINMAX_C4__WASM_2X, channels_div_4) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1786 | for (size_t channels = 8; channels < 40; channels += 4) { |
| 1787 | VMulCAddCMicrokernelTester() |
| 1788 | .channel_tile(4) |
| 1789 | .channels(channels) |
| 1790 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1791 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1792 | } |
| 1793 | } |
| 1794 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1795 | TEST(F32_VMULCADDC_MINMAX_C4__WASM_2X, channels_lt_4) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1796 | for (size_t channels = 1; channels < 4; channels++) { |
| 1797 | VMulCAddCMicrokernelTester() |
| 1798 | .channel_tile(4) |
| 1799 | .channels(channels) |
| 1800 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1801 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1802 | } |
| 1803 | } |
| 1804 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1805 | TEST(F32_VMULCADDC_MINMAX_C4__WASM_2X, channels_gt_4) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1806 | for (size_t channels = 5; channels < 8; channels++) { |
| 1807 | VMulCAddCMicrokernelTester() |
| 1808 | .channel_tile(4) |
| 1809 | .channels(channels) |
| 1810 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1811 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1812 | } |
| 1813 | } |
| 1814 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1815 | TEST(F32_VMULCADDC_MINMAX_C4__WASM_2X, rows_lt_2) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1816 | for (size_t rows = 1; rows < 2; rows++) { |
| 1817 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1818 | VMulCAddCMicrokernelTester() |
| 1819 | .channel_tile(4) |
| 1820 | .channels(channels) |
| 1821 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1822 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1823 | } |
| 1824 | } |
| 1825 | } |
| 1826 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1827 | TEST(F32_VMULCADDC_MINMAX_C4__WASM_2X, rows_div_2) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1828 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 1829 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1830 | VMulCAddCMicrokernelTester() |
| 1831 | .channel_tile(4) |
| 1832 | .channels(channels) |
| 1833 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1834 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1835 | } |
| 1836 | } |
| 1837 | } |
| 1838 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1839 | TEST(F32_VMULCADDC_MINMAX_C4__WASM_2X, rows_gt_2) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1840 | for (size_t rows = 3; rows < 4; rows++) { |
| 1841 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1842 | VMulCAddCMicrokernelTester() |
| 1843 | .channel_tile(4) |
| 1844 | .channels(channels) |
| 1845 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1846 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1847 | } |
| 1848 | } |
| 1849 | } |
| 1850 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1851 | TEST(F32_VMULCADDC_MINMAX_C4__WASM_2X, input_stride) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1852 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1853 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1854 | VMulCAddCMicrokernelTester() |
| 1855 | .channel_tile(4) |
| 1856 | .channels(channels) |
| 1857 | .rows(rows) |
| 1858 | .input_stride(23) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1859 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1860 | } |
| 1861 | } |
| 1862 | } |
| 1863 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1864 | TEST(F32_VMULCADDC_MINMAX_C4__WASM_2X, output_stride) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1865 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1866 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1867 | VMulCAddCMicrokernelTester() |
| 1868 | .channel_tile(4) |
| 1869 | .channels(channels) |
| 1870 | .rows(rows) |
| 1871 | .output_stride(23) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1872 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1873 | } |
| 1874 | } |
| 1875 | } |
| 1876 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1877 | TEST(F32_VMULCADDC_MINMAX_C4__WASM_2X, inplace) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1878 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1879 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1880 | VMulCAddCMicrokernelTester() |
| 1881 | .channel_tile(4) |
| 1882 | .channels(channels) |
| 1883 | .rows(rows) |
| 1884 | .inplace(true) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1885 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1886 | } |
| 1887 | } |
| 1888 | } |
| 1889 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1890 | TEST(F32_VMULCADDC_MINMAX_C4__WASM_2X, qmin) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1891 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1892 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1893 | VMulCAddCMicrokernelTester() |
| 1894 | .channel_tile(4) |
| 1895 | .channels(channels) |
| 1896 | .rows(rows) |
| 1897 | .qmin(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1898 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1899 | } |
| 1900 | } |
| 1901 | } |
| 1902 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1903 | TEST(F32_VMULCADDC_MINMAX_C4__WASM_2X, qmax) { |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1904 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1905 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1906 | VMulCAddCMicrokernelTester() |
| 1907 | .channel_tile(4) |
| 1908 | .channels(channels) |
| 1909 | .rows(rows) |
| 1910 | .qmax(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1911 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__wasm_2x); |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1912 | } |
| 1913 | } |
| 1914 | } |
Marat Dukhan | fb5b20a | 2020-06-26 13:14:50 -0700 | [diff] [blame] | 1915 | #endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1916 | |
| 1917 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1918 | TEST(F32_VMULCADDC_MINMAX_C1__SCALAR_2X, channels_eq_1) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1919 | VMulCAddCMicrokernelTester() |
| 1920 | .channel_tile(1) |
| 1921 | .channels(1) |
| 1922 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1923 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c1__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1924 | } |
| 1925 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1926 | TEST(F32_VMULCADDC_MINMAX_C1__SCALAR_2X, channels_gt_1) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1927 | for (size_t channels = 2; channels < 10; channels++) { |
| 1928 | VMulCAddCMicrokernelTester() |
| 1929 | .channel_tile(1) |
| 1930 | .channels(channels) |
| 1931 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1932 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c1__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1933 | } |
| 1934 | } |
| 1935 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1936 | TEST(F32_VMULCADDC_MINMAX_C1__SCALAR_2X, rows_lt_2) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1937 | for (size_t rows = 1; rows < 2; rows++) { |
| 1938 | for (size_t channels = 1; channels <= 5; channels += 1) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1939 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1940 | .channel_tile(1) |
| 1941 | .channels(channels) |
| 1942 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1943 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c1__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1944 | } |
| 1945 | } |
| 1946 | } |
| 1947 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1948 | TEST(F32_VMULCADDC_MINMAX_C1__SCALAR_2X, rows_div_2) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1949 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 1950 | for (size_t channels = 1; channels <= 5; channels += 1) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1951 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1952 | .channel_tile(1) |
| 1953 | .channels(channels) |
| 1954 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1955 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c1__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1956 | } |
| 1957 | } |
| 1958 | } |
| 1959 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1960 | TEST(F32_VMULCADDC_MINMAX_C1__SCALAR_2X, rows_gt_2) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1961 | for (size_t rows = 3; rows < 4; rows++) { |
| 1962 | for (size_t channels = 1; channels <= 5; channels += 1) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1963 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1964 | .channel_tile(1) |
| 1965 | .channels(channels) |
| 1966 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1967 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c1__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1968 | } |
| 1969 | } |
| 1970 | } |
| 1971 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1972 | TEST(F32_VMULCADDC_MINMAX_C1__SCALAR_2X, input_stride) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1973 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1974 | for (size_t channels = 1; channels <= 5; channels += 1) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1975 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1976 | .channel_tile(1) |
| 1977 | .channels(channels) |
| 1978 | .rows(rows) |
| 1979 | .input_stride(7) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1980 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c1__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1981 | } |
| 1982 | } |
| 1983 | } |
| 1984 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1985 | TEST(F32_VMULCADDC_MINMAX_C1__SCALAR_2X, output_stride) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1986 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1987 | for (size_t channels = 1; channels <= 5; channels += 1) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1988 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1989 | .channel_tile(1) |
| 1990 | .channels(channels) |
| 1991 | .rows(rows) |
| 1992 | .output_stride(7) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1993 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c1__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1994 | } |
| 1995 | } |
| 1996 | } |
| 1997 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 1998 | TEST(F32_VMULCADDC_MINMAX_C1__SCALAR_2X, inplace) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1999 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 2000 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 2001 | VMulCAddCMicrokernelTester() |
| 2002 | .channel_tile(1) |
| 2003 | .channels(channels) |
| 2004 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 2005 | .inplace(true) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2006 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c1__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 2007 | } |
| 2008 | } |
| 2009 | } |
| 2010 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2011 | TEST(F32_VMULCADDC_MINMAX_C1__SCALAR_2X, qmin) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2012 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 2013 | for (size_t channels = 1; channels <= 5; channels += 1) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 2014 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2015 | .channel_tile(1) |
| 2016 | .channels(channels) |
| 2017 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 2018 | .qmin(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2019 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c1__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 2020 | } |
| 2021 | } |
| 2022 | } |
| 2023 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2024 | TEST(F32_VMULCADDC_MINMAX_C1__SCALAR_2X, qmax) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2025 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 2026 | for (size_t channels = 1; channels <= 5; channels += 1) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 2027 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2028 | .channel_tile(1) |
| 2029 | .channels(channels) |
| 2030 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 2031 | .qmax(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2032 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c1__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2033 | } |
| 2034 | } |
| 2035 | } |
| 2036 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2037 | TEST(F32_VMULCADDC_MINMAX_C2__SCALAR_2X, channels_eq_2) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2038 | VMulCAddCMicrokernelTester() |
| 2039 | .channel_tile(2) |
| 2040 | .channels(2) |
| 2041 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2042 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2043 | } |
| 2044 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2045 | TEST(F32_VMULCADDC_MINMAX_C2__SCALAR_2X, channels_div_2) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2046 | for (size_t channels = 4; channels < 20; channels += 2) { |
| 2047 | VMulCAddCMicrokernelTester() |
| 2048 | .channel_tile(2) |
| 2049 | .channels(channels) |
| 2050 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2051 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2052 | } |
| 2053 | } |
| 2054 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2055 | TEST(F32_VMULCADDC_MINMAX_C2__SCALAR_2X, channels_lt_2) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2056 | for (size_t channels = 1; channels < 2; channels++) { |
| 2057 | VMulCAddCMicrokernelTester() |
| 2058 | .channel_tile(2) |
| 2059 | .channels(channels) |
| 2060 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2061 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2062 | } |
| 2063 | } |
| 2064 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2065 | TEST(F32_VMULCADDC_MINMAX_C2__SCALAR_2X, channels_gt_2) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2066 | for (size_t channels = 3; channels < 4; channels++) { |
| 2067 | VMulCAddCMicrokernelTester() |
| 2068 | .channel_tile(2) |
| 2069 | .channels(channels) |
| 2070 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2071 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2072 | } |
| 2073 | } |
| 2074 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2075 | TEST(F32_VMULCADDC_MINMAX_C2__SCALAR_2X, rows_lt_2) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2076 | for (size_t rows = 1; rows < 2; rows++) { |
| 2077 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 2078 | VMulCAddCMicrokernelTester() |
| 2079 | .channel_tile(2) |
| 2080 | .channels(channels) |
| 2081 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2082 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2083 | } |
| 2084 | } |
| 2085 | } |
| 2086 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2087 | TEST(F32_VMULCADDC_MINMAX_C2__SCALAR_2X, rows_div_2) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2088 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 2089 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 2090 | VMulCAddCMicrokernelTester() |
| 2091 | .channel_tile(2) |
| 2092 | .channels(channels) |
| 2093 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2094 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2095 | } |
| 2096 | } |
| 2097 | } |
| 2098 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2099 | TEST(F32_VMULCADDC_MINMAX_C2__SCALAR_2X, rows_gt_2) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2100 | for (size_t rows = 3; rows < 4; rows++) { |
| 2101 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 2102 | VMulCAddCMicrokernelTester() |
| 2103 | .channel_tile(2) |
| 2104 | .channels(channels) |
| 2105 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2106 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2107 | } |
| 2108 | } |
| 2109 | } |
| 2110 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2111 | TEST(F32_VMULCADDC_MINMAX_C2__SCALAR_2X, input_stride) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2112 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 2113 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 2114 | VMulCAddCMicrokernelTester() |
| 2115 | .channel_tile(2) |
| 2116 | .channels(channels) |
| 2117 | .rows(rows) |
| 2118 | .input_stride(13) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2119 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2120 | } |
| 2121 | } |
| 2122 | } |
| 2123 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2124 | TEST(F32_VMULCADDC_MINMAX_C2__SCALAR_2X, output_stride) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2125 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 2126 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 2127 | VMulCAddCMicrokernelTester() |
| 2128 | .channel_tile(2) |
| 2129 | .channels(channels) |
| 2130 | .rows(rows) |
| 2131 | .output_stride(13) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2132 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2133 | } |
| 2134 | } |
| 2135 | } |
| 2136 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2137 | TEST(F32_VMULCADDC_MINMAX_C2__SCALAR_2X, inplace) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2138 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 2139 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 2140 | VMulCAddCMicrokernelTester() |
| 2141 | .channel_tile(2) |
| 2142 | .channels(channels) |
| 2143 | .rows(rows) |
| 2144 | .inplace(true) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2145 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2146 | } |
| 2147 | } |
| 2148 | } |
| 2149 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2150 | TEST(F32_VMULCADDC_MINMAX_C2__SCALAR_2X, qmin) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2151 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 2152 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 2153 | VMulCAddCMicrokernelTester() |
| 2154 | .channel_tile(2) |
| 2155 | .channels(channels) |
| 2156 | .rows(rows) |
| 2157 | .qmin(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2158 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2159 | } |
| 2160 | } |
| 2161 | } |
| 2162 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2163 | TEST(F32_VMULCADDC_MINMAX_C2__SCALAR_2X, qmax) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2164 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 2165 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 2166 | VMulCAddCMicrokernelTester() |
| 2167 | .channel_tile(2) |
| 2168 | .channels(channels) |
| 2169 | .rows(rows) |
| 2170 | .qmax(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2171 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2172 | } |
| 2173 | } |
| 2174 | } |
| 2175 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2176 | TEST(F32_VMULCADDC_MINMAX_C4__SCALAR_2X, channels_eq_4) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2177 | VMulCAddCMicrokernelTester() |
| 2178 | .channel_tile(4) |
| 2179 | .channels(4) |
| 2180 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2181 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2182 | } |
| 2183 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2184 | TEST(F32_VMULCADDC_MINMAX_C4__SCALAR_2X, channels_div_4) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2185 | for (size_t channels = 8; channels < 40; channels += 4) { |
| 2186 | VMulCAddCMicrokernelTester() |
| 2187 | .channel_tile(4) |
| 2188 | .channels(channels) |
| 2189 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2190 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2191 | } |
| 2192 | } |
| 2193 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2194 | TEST(F32_VMULCADDC_MINMAX_C4__SCALAR_2X, channels_lt_4) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2195 | for (size_t channels = 1; channels < 4; channels++) { |
| 2196 | VMulCAddCMicrokernelTester() |
| 2197 | .channel_tile(4) |
| 2198 | .channels(channels) |
| 2199 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2200 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2201 | } |
| 2202 | } |
| 2203 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2204 | TEST(F32_VMULCADDC_MINMAX_C4__SCALAR_2X, channels_gt_4) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2205 | for (size_t channels = 5; channels < 8; channels++) { |
| 2206 | VMulCAddCMicrokernelTester() |
| 2207 | .channel_tile(4) |
| 2208 | .channels(channels) |
| 2209 | .rows(2) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2210 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2211 | } |
| 2212 | } |
| 2213 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2214 | TEST(F32_VMULCADDC_MINMAX_C4__SCALAR_2X, rows_lt_2) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2215 | for (size_t rows = 1; rows < 2; rows++) { |
| 2216 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2217 | VMulCAddCMicrokernelTester() |
| 2218 | .channel_tile(4) |
| 2219 | .channels(channels) |
| 2220 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2221 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2222 | } |
| 2223 | } |
| 2224 | } |
| 2225 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2226 | TEST(F32_VMULCADDC_MINMAX_C4__SCALAR_2X, rows_div_2) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2227 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 2228 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2229 | VMulCAddCMicrokernelTester() |
| 2230 | .channel_tile(4) |
| 2231 | .channels(channels) |
| 2232 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2233 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2234 | } |
| 2235 | } |
| 2236 | } |
| 2237 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2238 | TEST(F32_VMULCADDC_MINMAX_C4__SCALAR_2X, rows_gt_2) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2239 | for (size_t rows = 3; rows < 4; rows++) { |
| 2240 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2241 | VMulCAddCMicrokernelTester() |
| 2242 | .channel_tile(4) |
| 2243 | .channels(channels) |
| 2244 | .rows(rows) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2245 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2246 | } |
| 2247 | } |
| 2248 | } |
| 2249 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2250 | TEST(F32_VMULCADDC_MINMAX_C4__SCALAR_2X, input_stride) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2251 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 2252 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2253 | VMulCAddCMicrokernelTester() |
| 2254 | .channel_tile(4) |
| 2255 | .channels(channels) |
| 2256 | .rows(rows) |
| 2257 | .input_stride(23) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2258 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2259 | } |
| 2260 | } |
| 2261 | } |
| 2262 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2263 | TEST(F32_VMULCADDC_MINMAX_C4__SCALAR_2X, output_stride) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2264 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 2265 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2266 | VMulCAddCMicrokernelTester() |
| 2267 | .channel_tile(4) |
| 2268 | .channels(channels) |
| 2269 | .rows(rows) |
| 2270 | .output_stride(23) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2271 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2272 | } |
| 2273 | } |
| 2274 | } |
| 2275 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2276 | TEST(F32_VMULCADDC_MINMAX_C4__SCALAR_2X, inplace) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2277 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 2278 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2279 | VMulCAddCMicrokernelTester() |
| 2280 | .channel_tile(4) |
| 2281 | .channels(channels) |
| 2282 | .rows(rows) |
| 2283 | .inplace(true) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2284 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2285 | } |
| 2286 | } |
| 2287 | } |
| 2288 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2289 | TEST(F32_VMULCADDC_MINMAX_C4__SCALAR_2X, qmin) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2290 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 2291 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2292 | VMulCAddCMicrokernelTester() |
| 2293 | .channel_tile(4) |
| 2294 | .channels(channels) |
| 2295 | .rows(rows) |
| 2296 | .qmin(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2297 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2298 | } |
| 2299 | } |
| 2300 | } |
| 2301 | |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2302 | TEST(F32_VMULCADDC_MINMAX_C4__SCALAR_2X, qmax) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 2303 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 2304 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2305 | VMulCAddCMicrokernelTester() |
| 2306 | .channel_tile(4) |
| 2307 | .channels(channels) |
| 2308 | .rows(rows) |
| 2309 | .qmax(128) |
Marat Dukhan | 9531e9f | 2020-07-24 15:25:02 -0700 | [diff] [blame] | 2310 | .Test(xnn_f32_vmulcaddc_minmax_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 2311 | } |
| 2312 | } |
| 2313 | } |