blob: 9ad71fbca930c302ba75ecf1c8e4e447a2dcd52f [file] [log] [blame]
XNNPACK Teamb455b122019-09-27 18:10:33 -07001// Copyright 2019 Google LLC
2//
3// This source code is licensed under the BSD-style license found in the
4// LICENSE file in the root directory of this source tree.
5
6#include <gtest/gtest.h>
7
Marat Dukhan1dadbf72019-10-01 10:46:20 -07008#include <xnnpack/common.h>
XNNPACK Teamb455b122019-09-27 18:10:33 -07009#include <xnnpack/isa-checks.h>
XNNPACK Teamb455b122019-09-27 18:10:33 -070010
Marat Dukhan1dadbf72019-10-01 10:46:20 -070011#include <xnnpack/pad.h>
XNNPACK Teamb455b122019-09-27 18:10:33 -070012#include "pad-microkernel-tester.h"
13
14
Marat Dukhan1dadbf72019-10-01 10:46:20 -070015#if XNN_ARCH_ARM || XNN_ARCH_ARM64
Marat Dukhan63523d42020-05-22 17:07:33 -070016 TEST(X32_PAD__NEON, fulltile_copy_channels_eq_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070017 TEST_REQUIRES_ARM_NEON;
18 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -070019 .rows(1)
20 .input_channels(4)
21 .Test(xnn_x32_pad_ukernel__neon);
XNNPACK Teamb455b122019-09-27 18:10:33 -070022 }
23
Marat Dukhan63523d42020-05-22 17:07:33 -070024 TEST(X32_PAD__NEON, fulltile_copy_channels_div_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070025 TEST_REQUIRES_ARM_NEON;
Marat Dukhan63523d42020-05-22 17:07:33 -070026 for (size_t channels = 8; channels < 32; channels += 4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070027 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -070028 .rows(1)
29 .input_channels(channels)
30 .Test(xnn_x32_pad_ukernel__neon);
XNNPACK Teamb455b122019-09-27 18:10:33 -070031 }
32 }
33
Marat Dukhan63523d42020-05-22 17:07:33 -070034 TEST(X32_PAD__NEON, fulltile_copy_channels_lt_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070035 TEST_REQUIRES_ARM_NEON;
Marat Dukhan63523d42020-05-22 17:07:33 -070036 for (size_t channels = 1; channels < 4; channels++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070037 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -070038 .rows(1)
39 .input_channels(channels)
40 .Test(xnn_x32_pad_ukernel__neon);
XNNPACK Teamb455b122019-09-27 18:10:33 -070041 }
42 }
43
Marat Dukhan63523d42020-05-22 17:07:33 -070044 TEST(X32_PAD__NEON, fulltile_copy_channels_gt_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070045 TEST_REQUIRES_ARM_NEON;
Marat Dukhan63523d42020-05-22 17:07:33 -070046 for (size_t channels = 5; channels < 8; channels++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070047 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -070048 .rows(1)
49 .input_channels(4)
50 .Test(xnn_x32_pad_ukernel__neon);
XNNPACK Teamb455b122019-09-27 18:10:33 -070051 }
52 }
53
Marat Dukhan63523d42020-05-22 17:07:33 -070054 TEST(X32_PAD__NEON, fulltile_pre_padding_eq_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070055 TEST_REQUIRES_ARM_NEON;
56 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -070057 .rows(1)
58 .input_channels(1)
59 .pre_padding(4)
60 .Test(xnn_x32_pad_ukernel__neon);
XNNPACK Teamb455b122019-09-27 18:10:33 -070061 }
62
Marat Dukhan63523d42020-05-22 17:07:33 -070063 TEST(X32_PAD__NEON, fulltile_pre_padding_div_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070064 TEST_REQUIRES_ARM_NEON;
Marat Dukhan63523d42020-05-22 17:07:33 -070065 for (size_t pre_padding = 8; pre_padding < 32; pre_padding += 4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070066 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -070067 .rows(1)
68 .input_channels(1)
69 .pre_padding(pre_padding)
70 .Test(xnn_x32_pad_ukernel__neon);
XNNPACK Teamb455b122019-09-27 18:10:33 -070071 }
72 }
73
Marat Dukhan63523d42020-05-22 17:07:33 -070074 TEST(X32_PAD__NEON, fulltile_pre_padding_lt_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070075 TEST_REQUIRES_ARM_NEON;
Marat Dukhan63523d42020-05-22 17:07:33 -070076 for (size_t pre_padding = 1; pre_padding < 4; pre_padding++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070077 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -070078 .rows(1)
79 .input_channels(1)
80 .pre_padding(pre_padding)
81 .Test(xnn_x32_pad_ukernel__neon);
XNNPACK Teamb455b122019-09-27 18:10:33 -070082 }
83 }
84
Marat Dukhan63523d42020-05-22 17:07:33 -070085 TEST(X32_PAD__NEON, fulltile_pre_padding_gt_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070086 TEST_REQUIRES_ARM_NEON;
Marat Dukhan63523d42020-05-22 17:07:33 -070087 for (size_t pre_padding = 5; pre_padding < 8; pre_padding++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070088 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -070089 .rows(1)
90 .input_channels(1)
91 .pre_padding(pre_padding)
92 .Test(xnn_x32_pad_ukernel__neon);
XNNPACK Teamb455b122019-09-27 18:10:33 -070093 }
94 }
95
Marat Dukhan63523d42020-05-22 17:07:33 -070096 TEST(X32_PAD__NEON, fulltile_post_padding_eq_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070097 TEST_REQUIRES_ARM_NEON;
98 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -070099 .rows(1)
100 .input_channels(1)
101 .post_padding(4)
102 .Test(xnn_x32_pad_ukernel__neon);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700103 }
104
Marat Dukhan63523d42020-05-22 17:07:33 -0700105 TEST(X32_PAD__NEON, fulltile_post_padding_div_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700106 TEST_REQUIRES_ARM_NEON;
Marat Dukhan63523d42020-05-22 17:07:33 -0700107 for (size_t post_padding = 8; post_padding < 32; post_padding += 4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700108 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700109 .rows(1)
110 .input_channels(1)
111 .post_padding(post_padding)
112 .Test(xnn_x32_pad_ukernel__neon);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700113 }
114 }
115
Marat Dukhan63523d42020-05-22 17:07:33 -0700116 TEST(X32_PAD__NEON, fulltile_post_padding_lt_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700117 TEST_REQUIRES_ARM_NEON;
Marat Dukhan63523d42020-05-22 17:07:33 -0700118 for (size_t post_padding = 1; post_padding < 4; post_padding++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700119 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700120 .rows(1)
121 .input_channels(1)
122 .post_padding(post_padding)
123 .Test(xnn_x32_pad_ukernel__neon);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700124 }
125 }
126
Marat Dukhan63523d42020-05-22 17:07:33 -0700127 TEST(X32_PAD__NEON, fulltile_post_padding_gt_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700128 TEST_REQUIRES_ARM_NEON;
Marat Dukhan63523d42020-05-22 17:07:33 -0700129 for (size_t post_padding = 5; post_padding < 8; post_padding++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700130 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700131 .rows(1)
132 .input_channels(1)
133 .pre_padding(post_padding)
134 .Test(xnn_x32_pad_ukernel__neon);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700135 }
136 }
137
Marat Dukhan63523d42020-05-22 17:07:33 -0700138 TEST(X32_PAD__NEON, multitile) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700139 TEST_REQUIRES_ARM_NEON;
Marat Dukhan63523d42020-05-22 17:07:33 -0700140 for (size_t rows = 2; rows <= 5; rows++) {
141 for (size_t channels = 1; channels < 10; channels++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700142 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700143 .rows(rows)
144 .input_channels(channels)
145 .pre_padding(channels)
146 .post_padding(channels)
147 .Test(xnn_x32_pad_ukernel__neon);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700148 }
149 }
150 }
151
Marat Dukhan63523d42020-05-22 17:07:33 -0700152 TEST(X32_PAD__NEON, multitile_with_input_stride) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700153 TEST_REQUIRES_ARM_NEON;
Marat Dukhan63523d42020-05-22 17:07:33 -0700154 for (size_t rows = 2; rows <= 5; rows++) {
155 for (size_t channels = 1; channels < 10; channels++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700156 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700157 .rows(rows)
158 .input_channels(channels)
159 .pre_padding(channels)
160 .post_padding(channels)
161 .input_stride(2 * channels + 1)
162 .Test(xnn_x32_pad_ukernel__neon);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700163 }
164 }
165 }
166
Marat Dukhan63523d42020-05-22 17:07:33 -0700167 TEST(X32_PAD__NEON, multitile_with_output_stride) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700168 TEST_REQUIRES_ARM_NEON;
Marat Dukhan63523d42020-05-22 17:07:33 -0700169 for (size_t rows = 2; rows <= 5; rows++) {
170 for (size_t channels = 1; channels < 10; channels++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700171 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700172 .rows(rows)
173 .input_channels(2 * channels)
174 .pre_padding(channels)
175 .post_padding(channels)
176 .output_stride(5 * channels + 3)
177 .Test(xnn_x32_pad_ukernel__neon);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700178 }
179 }
180 }
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700181#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
XNNPACK Teamb455b122019-09-27 18:10:33 -0700182
183
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700184#if XNN_ARCH_X86 || XNN_ARCH_X86_64
Marat Dukhan63523d42020-05-22 17:07:33 -0700185 TEST(X32_PAD__SSE, fulltile_copy_channels_eq_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700186 TEST_REQUIRES_X86_SSE2;
187 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700188 .rows(1)
189 .input_channels(4)
190 .Test(xnn_x32_pad_ukernel__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700191 }
192
Marat Dukhan63523d42020-05-22 17:07:33 -0700193 TEST(X32_PAD__SSE, fulltile_copy_channels_div_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700194 TEST_REQUIRES_X86_SSE2;
Marat Dukhan63523d42020-05-22 17:07:33 -0700195 for (size_t channels = 8; channels < 32; channels += 4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700196 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700197 .rows(1)
198 .input_channels(channels)
199 .Test(xnn_x32_pad_ukernel__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700200 }
201 }
202
Marat Dukhan63523d42020-05-22 17:07:33 -0700203 TEST(X32_PAD__SSE, fulltile_copy_channels_lt_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700204 TEST_REQUIRES_X86_SSE2;
Marat Dukhan63523d42020-05-22 17:07:33 -0700205 for (size_t channels = 1; channels < 4; channels++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700206 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700207 .rows(1)
208 .input_channels(channels)
209 .Test(xnn_x32_pad_ukernel__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700210 }
211 }
212
Marat Dukhan63523d42020-05-22 17:07:33 -0700213 TEST(X32_PAD__SSE, fulltile_copy_channels_gt_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700214 TEST_REQUIRES_X86_SSE2;
Marat Dukhan63523d42020-05-22 17:07:33 -0700215 for (size_t channels = 5; channels < 8; channels++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700216 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700217 .rows(1)
218 .input_channels(4)
219 .Test(xnn_x32_pad_ukernel__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700220 }
221 }
222
Marat Dukhan63523d42020-05-22 17:07:33 -0700223 TEST(X32_PAD__SSE, fulltile_pre_padding_eq_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700224 TEST_REQUIRES_X86_SSE2;
225 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700226 .rows(1)
227 .input_channels(1)
228 .pre_padding(4)
229 .Test(xnn_x32_pad_ukernel__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700230 }
231
Marat Dukhan63523d42020-05-22 17:07:33 -0700232 TEST(X32_PAD__SSE, fulltile_pre_padding_div_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700233 TEST_REQUIRES_X86_SSE2;
Marat Dukhan63523d42020-05-22 17:07:33 -0700234 for (size_t pre_padding = 8; pre_padding < 32; pre_padding += 4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700235 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700236 .rows(1)
237 .input_channels(1)
238 .pre_padding(pre_padding)
239 .Test(xnn_x32_pad_ukernel__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700240 }
241 }
242
Marat Dukhan63523d42020-05-22 17:07:33 -0700243 TEST(X32_PAD__SSE, fulltile_pre_padding_lt_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700244 TEST_REQUIRES_X86_SSE2;
Marat Dukhan63523d42020-05-22 17:07:33 -0700245 for (size_t pre_padding = 1; pre_padding < 4; pre_padding++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700246 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700247 .rows(1)
248 .input_channels(1)
249 .pre_padding(pre_padding)
250 .Test(xnn_x32_pad_ukernel__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700251 }
252 }
253
Marat Dukhan63523d42020-05-22 17:07:33 -0700254 TEST(X32_PAD__SSE, fulltile_pre_padding_gt_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700255 TEST_REQUIRES_X86_SSE2;
Marat Dukhan63523d42020-05-22 17:07:33 -0700256 for (size_t pre_padding = 5; pre_padding < 8; pre_padding++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700257 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700258 .rows(1)
259 .input_channels(1)
260 .pre_padding(pre_padding)
261 .Test(xnn_x32_pad_ukernel__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700262 }
263 }
264
Marat Dukhan63523d42020-05-22 17:07:33 -0700265 TEST(X32_PAD__SSE, fulltile_post_padding_eq_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700266 TEST_REQUIRES_X86_SSE2;
267 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700268 .rows(1)
269 .input_channels(1)
270 .post_padding(4)
271 .Test(xnn_x32_pad_ukernel__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700272 }
273
Marat Dukhan63523d42020-05-22 17:07:33 -0700274 TEST(X32_PAD__SSE, fulltile_post_padding_div_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700275 TEST_REQUIRES_X86_SSE2;
Marat Dukhan63523d42020-05-22 17:07:33 -0700276 for (size_t post_padding = 8; post_padding < 32; post_padding += 4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700277 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700278 .rows(1)
279 .input_channels(1)
280 .post_padding(post_padding)
281 .Test(xnn_x32_pad_ukernel__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700282 }
283 }
284
Marat Dukhan63523d42020-05-22 17:07:33 -0700285 TEST(X32_PAD__SSE, fulltile_post_padding_lt_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700286 TEST_REQUIRES_X86_SSE2;
Marat Dukhan63523d42020-05-22 17:07:33 -0700287 for (size_t post_padding = 1; post_padding < 4; post_padding++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700288 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700289 .rows(1)
290 .input_channels(1)
291 .post_padding(post_padding)
292 .Test(xnn_x32_pad_ukernel__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700293 }
294 }
295
Marat Dukhan63523d42020-05-22 17:07:33 -0700296 TEST(X32_PAD__SSE, fulltile_post_padding_gt_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700297 TEST_REQUIRES_X86_SSE2;
Marat Dukhan63523d42020-05-22 17:07:33 -0700298 for (size_t post_padding = 5; post_padding < 8; post_padding++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700299 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700300 .rows(1)
301 .input_channels(1)
302 .pre_padding(post_padding)
303 .Test(xnn_x32_pad_ukernel__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700304 }
305 }
306
Marat Dukhan63523d42020-05-22 17:07:33 -0700307 TEST(X32_PAD__SSE, multitile) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700308 TEST_REQUIRES_X86_SSE2;
Marat Dukhan63523d42020-05-22 17:07:33 -0700309 for (size_t rows = 2; rows <= 5; rows++) {
310 for (size_t channels = 1; channels < 10; channels++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700311 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700312 .rows(rows)
313 .input_channels(channels)
314 .pre_padding(channels)
315 .post_padding(channels)
316 .Test(xnn_x32_pad_ukernel__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700317 }
318 }
319 }
320
Marat Dukhan63523d42020-05-22 17:07:33 -0700321 TEST(X32_PAD__SSE, multitile_with_input_stride) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700322 TEST_REQUIRES_X86_SSE2;
Marat Dukhan63523d42020-05-22 17:07:33 -0700323 for (size_t rows = 2; rows <= 5; rows++) {
324 for (size_t channels = 1; channels < 10; channels++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700325 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700326 .rows(rows)
327 .input_channels(channels)
328 .pre_padding(channels)
329 .post_padding(channels)
330 .input_stride(2 * channels + 1)
331 .Test(xnn_x32_pad_ukernel__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700332 }
333 }
334 }
335
Marat Dukhan63523d42020-05-22 17:07:33 -0700336 TEST(X32_PAD__SSE, multitile_with_output_stride) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700337 TEST_REQUIRES_X86_SSE2;
Marat Dukhan63523d42020-05-22 17:07:33 -0700338 for (size_t rows = 2; rows <= 5; rows++) {
339 for (size_t channels = 1; channels < 10; channels++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700340 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700341 .rows(rows)
342 .input_channels(2 * channels)
343 .pre_padding(channels)
344 .post_padding(channels)
345 .output_stride(5 * channels + 3)
346 .Test(xnn_x32_pad_ukernel__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700347 }
348 }
349 }
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700350#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
XNNPACK Teamb455b122019-09-27 18:10:33 -0700351
352
Marat Dukhan9306ae02020-07-16 15:51:13 -0700353#if XNN_ARCH_WASMSIMD
354 TEST(X32_PAD__WASMSIMD, fulltile_copy_channels_eq_4) {
355 PadMicrokernelTester()
356 .rows(1)
357 .input_channels(4)
358 .Test(xnn_x32_pad_ukernel__wasmsimd);
359 }
360
361 TEST(X32_PAD__WASMSIMD, fulltile_copy_channels_div_4) {
362 for (size_t channels = 8; channels < 32; channels += 4) {
363 PadMicrokernelTester()
364 .rows(1)
365 .input_channels(channels)
366 .Test(xnn_x32_pad_ukernel__wasmsimd);
367 }
368 }
369
370 TEST(X32_PAD__WASMSIMD, fulltile_copy_channels_lt_4) {
371 for (size_t channels = 1; channels < 4; channels++) {
372 PadMicrokernelTester()
373 .rows(1)
374 .input_channels(channels)
375 .Test(xnn_x32_pad_ukernel__wasmsimd);
376 }
377 }
378
379 TEST(X32_PAD__WASMSIMD, fulltile_copy_channels_gt_4) {
380 for (size_t channels = 5; channels < 8; channels++) {
381 PadMicrokernelTester()
382 .rows(1)
383 .input_channels(4)
384 .Test(xnn_x32_pad_ukernel__wasmsimd);
385 }
386 }
387
388 TEST(X32_PAD__WASMSIMD, fulltile_pre_padding_eq_4) {
389 PadMicrokernelTester()
390 .rows(1)
391 .input_channels(1)
392 .pre_padding(4)
393 .Test(xnn_x32_pad_ukernel__wasmsimd);
394 }
395
396 TEST(X32_PAD__WASMSIMD, fulltile_pre_padding_div_4) {
397 for (size_t pre_padding = 8; pre_padding < 32; pre_padding += 4) {
398 PadMicrokernelTester()
399 .rows(1)
400 .input_channels(1)
401 .pre_padding(pre_padding)
402 .Test(xnn_x32_pad_ukernel__wasmsimd);
403 }
404 }
405
406 TEST(X32_PAD__WASMSIMD, fulltile_pre_padding_lt_4) {
407 for (size_t pre_padding = 1; pre_padding < 4; pre_padding++) {
408 PadMicrokernelTester()
409 .rows(1)
410 .input_channels(1)
411 .pre_padding(pre_padding)
412 .Test(xnn_x32_pad_ukernel__wasmsimd);
413 }
414 }
415
416 TEST(X32_PAD__WASMSIMD, fulltile_pre_padding_gt_4) {
417 for (size_t pre_padding = 5; pre_padding < 8; pre_padding++) {
418 PadMicrokernelTester()
419 .rows(1)
420 .input_channels(1)
421 .pre_padding(pre_padding)
422 .Test(xnn_x32_pad_ukernel__wasmsimd);
423 }
424 }
425
426 TEST(X32_PAD__WASMSIMD, fulltile_post_padding_eq_4) {
427 PadMicrokernelTester()
428 .rows(1)
429 .input_channels(1)
430 .post_padding(4)
431 .Test(xnn_x32_pad_ukernel__wasmsimd);
432 }
433
434 TEST(X32_PAD__WASMSIMD, fulltile_post_padding_div_4) {
435 for (size_t post_padding = 8; post_padding < 32; post_padding += 4) {
436 PadMicrokernelTester()
437 .rows(1)
438 .input_channels(1)
439 .post_padding(post_padding)
440 .Test(xnn_x32_pad_ukernel__wasmsimd);
441 }
442 }
443
444 TEST(X32_PAD__WASMSIMD, fulltile_post_padding_lt_4) {
445 for (size_t post_padding = 1; post_padding < 4; post_padding++) {
446 PadMicrokernelTester()
447 .rows(1)
448 .input_channels(1)
449 .post_padding(post_padding)
450 .Test(xnn_x32_pad_ukernel__wasmsimd);
451 }
452 }
453
454 TEST(X32_PAD__WASMSIMD, fulltile_post_padding_gt_4) {
455 for (size_t post_padding = 5; post_padding < 8; post_padding++) {
456 PadMicrokernelTester()
457 .rows(1)
458 .input_channels(1)
459 .pre_padding(post_padding)
460 .Test(xnn_x32_pad_ukernel__wasmsimd);
461 }
462 }
463
464 TEST(X32_PAD__WASMSIMD, multitile) {
465 for (size_t rows = 2; rows <= 5; rows++) {
466 for (size_t channels = 1; channels < 10; channels++) {
467 PadMicrokernelTester()
468 .rows(rows)
469 .input_channels(channels)
470 .pre_padding(channels)
471 .post_padding(channels)
472 .Test(xnn_x32_pad_ukernel__wasmsimd);
473 }
474 }
475 }
476
477 TEST(X32_PAD__WASMSIMD, multitile_with_input_stride) {
478 for (size_t rows = 2; rows <= 5; rows++) {
479 for (size_t channels = 1; channels < 10; channels++) {
480 PadMicrokernelTester()
481 .rows(rows)
482 .input_channels(channels)
483 .pre_padding(channels)
484 .post_padding(channels)
485 .input_stride(2 * channels + 1)
486 .Test(xnn_x32_pad_ukernel__wasmsimd);
487 }
488 }
489 }
490
491 TEST(X32_PAD__WASMSIMD, multitile_with_output_stride) {
492 for (size_t rows = 2; rows <= 5; rows++) {
493 for (size_t channels = 1; channels < 10; channels++) {
494 PadMicrokernelTester()
495 .rows(rows)
496 .input_channels(2 * channels)
497 .pre_padding(channels)
498 .post_padding(channels)
499 .output_stride(5 * channels + 3)
500 .Test(xnn_x32_pad_ukernel__wasmsimd);
501 }
502 }
503 }
504#endif // XNN_ARCH_WASMSIMD
505
506
Marat Dukhan63523d42020-05-22 17:07:33 -0700507TEST(X32_PAD__SCALAR_INT, fulltile_copy_channels_eq_1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700508 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700509 .rows(1)
510 .input_channels(1)
511 .Test(xnn_x32_pad_ukernel__scalar_int);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700512}
513
Marat Dukhan63523d42020-05-22 17:07:33 -0700514TEST(X32_PAD__SCALAR_INT, fulltile_copy_channels_gt_1) {
515 for (size_t channels = 2; channels < 8; channels++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700516 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700517 .rows(1)
518 .input_channels(channels)
519 .Test(xnn_x32_pad_ukernel__scalar_int);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700520 }
521}
522
Marat Dukhan63523d42020-05-22 17:07:33 -0700523TEST(X32_PAD__SCALAR_INT, fulltile_pre_padding_eq_1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700524 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700525 .rows(1)
526 .input_channels(1)
527 .pre_padding(1)
528 .Test(xnn_x32_pad_ukernel__scalar_int);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700529}
530
Marat Dukhan63523d42020-05-22 17:07:33 -0700531TEST(X32_PAD__SCALAR_INT, fulltile_pre_padding_gt_1) {
532 for (size_t pre_padding = 2; pre_padding < 8; pre_padding++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700533 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700534 .rows(1)
535 .input_channels(1)
536 .pre_padding(pre_padding)
537 .Test(xnn_x32_pad_ukernel__scalar_int);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700538 }
539}
540
Marat Dukhan63523d42020-05-22 17:07:33 -0700541TEST(X32_PAD__SCALAR_INT, fulltile_post_padding_eq_1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700542 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700543 .rows(1)
544 .input_channels(1)
545 .post_padding(1)
546 .Test(xnn_x32_pad_ukernel__scalar_int);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700547}
548
Marat Dukhan63523d42020-05-22 17:07:33 -0700549TEST(X32_PAD__SCALAR_INT, fulltile_post_padding_gt_1) {
550 for (size_t post_padding = 1; post_padding < 8; post_padding++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700551 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700552 .rows(1)
553 .input_channels(1)
554 .pre_padding(post_padding)
555 .Test(xnn_x32_pad_ukernel__scalar_int);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700556 }
557}
558
Marat Dukhan63523d42020-05-22 17:07:33 -0700559TEST(X32_PAD__SCALAR_INT, multitile) {
560 for (size_t rows = 2; rows <= 5; rows++) {
561 for (size_t channels = 1; channels < 10; channels++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700562 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700563 .rows(rows)
564 .input_channels(channels)
565 .pre_padding(channels)
566 .post_padding(channels)
567 .Test(xnn_x32_pad_ukernel__scalar_int);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700568 }
569 }
570}
571
Marat Dukhan63523d42020-05-22 17:07:33 -0700572TEST(X32_PAD__SCALAR_INT, multitile_with_input_stride) {
573 for (size_t rows = 2; rows <= 5; rows++) {
574 for (size_t channels = 1; channels < 10; channels++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700575 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700576 .rows(rows)
577 .input_channels(channels)
578 .pre_padding(channels)
579 .post_padding(channels)
580 .input_stride(2 * channels + 1)
581 .Test(xnn_x32_pad_ukernel__scalar_int);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700582 }
583 }
584}
585
Marat Dukhan63523d42020-05-22 17:07:33 -0700586TEST(X32_PAD__SCALAR_INT, multitile_with_output_stride) {
587 for (size_t rows = 2; rows <= 5; rows++) {
588 for (size_t channels = 1; channels < 10; channels++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700589 PadMicrokernelTester()
Marat Dukhan63523d42020-05-22 17:07:33 -0700590 .rows(rows)
591 .input_channels(2 * channels)
592 .pre_padding(channels)
593 .post_padding(channels)
594 .output_stride(5 * channels + 3)
595 .Test(xnn_x32_pad_ukernel__scalar_int);
596 }
597 }
598}
599
600
601TEST(X32_PAD__SCALAR_FLOAT, fulltile_copy_channels_eq_1) {
602 PadMicrokernelTester()
603 .rows(1)
604 .input_channels(1)
605 .Test(xnn_x32_pad_ukernel__scalar_float);
606}
607
608TEST(X32_PAD__SCALAR_FLOAT, fulltile_copy_channels_gt_1) {
609 for (size_t channels = 2; channels < 8; channels++) {
610 PadMicrokernelTester()
611 .rows(1)
612 .input_channels(channels)
613 .Test(xnn_x32_pad_ukernel__scalar_float);
614 }
615}
616
617TEST(X32_PAD__SCALAR_FLOAT, fulltile_pre_padding_eq_1) {
618 PadMicrokernelTester()
619 .rows(1)
620 .input_channels(1)
621 .pre_padding(1)
622 .Test(xnn_x32_pad_ukernel__scalar_float);
623}
624
625TEST(X32_PAD__SCALAR_FLOAT, fulltile_pre_padding_gt_1) {
626 for (size_t pre_padding = 2; pre_padding < 8; pre_padding++) {
627 PadMicrokernelTester()
628 .rows(1)
629 .input_channels(1)
630 .pre_padding(pre_padding)
631 .Test(xnn_x32_pad_ukernel__scalar_float);
632 }
633}
634
635TEST(X32_PAD__SCALAR_FLOAT, fulltile_post_padding_eq_1) {
636 PadMicrokernelTester()
637 .rows(1)
638 .input_channels(1)
639 .post_padding(1)
640 .Test(xnn_x32_pad_ukernel__scalar_float);
641}
642
643TEST(X32_PAD__SCALAR_FLOAT, fulltile_post_padding_gt_1) {
644 for (size_t post_padding = 1; post_padding < 8; post_padding++) {
645 PadMicrokernelTester()
646 .rows(1)
647 .input_channels(1)
648 .pre_padding(post_padding)
649 .Test(xnn_x32_pad_ukernel__scalar_float);
650 }
651}
652
653TEST(X32_PAD__SCALAR_FLOAT, multitile) {
654 for (size_t rows = 2; rows <= 5; rows++) {
655 for (size_t channels = 1; channels < 10; channels++) {
656 PadMicrokernelTester()
657 .rows(rows)
658 .input_channels(channels)
659 .pre_padding(channels)
660 .post_padding(channels)
661 .Test(xnn_x32_pad_ukernel__scalar_float);
662 }
663 }
664}
665
666TEST(X32_PAD__SCALAR_FLOAT, multitile_with_input_stride) {
667 for (size_t rows = 2; rows <= 5; rows++) {
668 for (size_t channels = 1; channels < 10; channels++) {
669 PadMicrokernelTester()
670 .rows(rows)
671 .input_channels(channels)
672 .pre_padding(channels)
673 .post_padding(channels)
674 .input_stride(2 * channels + 1)
675 .Test(xnn_x32_pad_ukernel__scalar_float);
676 }
677 }
678}
679
680TEST(X32_PAD__SCALAR_FLOAT, multitile_with_output_stride) {
681 for (size_t rows = 2; rows <= 5; rows++) {
682 for (size_t channels = 1; channels < 10; channels++) {
683 PadMicrokernelTester()
684 .rows(rows)
685 .input_channels(2 * channels)
686 .pre_padding(channels)
687 .post_padding(channels)
688 .output_stride(5 * channels + 3)
689 .Test(xnn_x32_pad_ukernel__scalar_float);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700690 }
691 }
692}