XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1 | // Copyright 2019 Google LLC |
| 2 | // |
| 3 | // This source code is licensed under the BSD-style license found in the |
| 4 | // LICENSE file in the root directory of this source tree. |
| 5 | // |
| 6 | // Auto-generated file. Do not edit! |
| 7 | // Specification: test/f32-vmulcaddc.yaml |
| 8 | // Generator: tools/generate-vmulcaddc-test.py |
| 9 | |
| 10 | |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 11 | #include <gtest/gtest.h> |
| 12 | |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 13 | #include <xnnpack/common.h> |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 14 | #include <xnnpack/isa-checks.h> |
| 15 | |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 16 | #include <xnnpack/vmulcaddc.h> |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 17 | #include "vmulcaddc-microkernel-tester.h" |
| 18 | |
| 19 | |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 20 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 21 | TEST(F32_VMULCADDC_C4__NEONFMA_2X, channels_eq_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 22 | TEST_REQUIRES_ARM_NEON_FMA; |
| 23 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 24 | .channel_tile(4) |
| 25 | .channels(4) |
| 26 | .rows(2) |
| 27 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neonfma_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 28 | } |
| 29 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 30 | TEST(F32_VMULCADDC_C4__NEONFMA_2X, channels_div_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 31 | TEST_REQUIRES_ARM_NEON_FMA; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 32 | for (size_t channels = 8; channels < 40; channels += 4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 33 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 34 | .channel_tile(4) |
| 35 | .channels(channels) |
| 36 | .rows(2) |
| 37 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neonfma_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 38 | } |
| 39 | } |
| 40 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 41 | TEST(F32_VMULCADDC_C4__NEONFMA_2X, channels_lt_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 42 | TEST_REQUIRES_ARM_NEON_FMA; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 43 | for (size_t channels = 1; channels < 4; channels++) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 44 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 45 | .channel_tile(4) |
| 46 | .channels(channels) |
| 47 | .rows(2) |
| 48 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neonfma_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 49 | } |
| 50 | } |
| 51 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 52 | TEST(F32_VMULCADDC_C4__NEONFMA_2X, channels_gt_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 53 | TEST_REQUIRES_ARM_NEON_FMA; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 54 | for (size_t channels = 5; channels < 8; channels++) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 55 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 56 | .channel_tile(4) |
| 57 | .channels(channels) |
| 58 | .rows(2) |
| 59 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neonfma_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 60 | } |
| 61 | } |
| 62 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 63 | TEST(F32_VMULCADDC_C4__NEONFMA_2X, rows_lt_2) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 64 | TEST_REQUIRES_ARM_NEON_FMA; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 65 | for (size_t rows = 1; rows < 2; rows++) { |
| 66 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 67 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 68 | .channel_tile(4) |
| 69 | .channels(channels) |
| 70 | .rows(rows) |
| 71 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neonfma_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 72 | } |
| 73 | } |
| 74 | } |
| 75 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 76 | TEST(F32_VMULCADDC_C4__NEONFMA_2X, rows_div_2) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 77 | TEST_REQUIRES_ARM_NEON_FMA; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 78 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 79 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 80 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 81 | .channel_tile(4) |
| 82 | .channels(channels) |
| 83 | .rows(rows) |
| 84 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neonfma_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 85 | } |
| 86 | } |
| 87 | } |
| 88 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 89 | TEST(F32_VMULCADDC_C4__NEONFMA_2X, rows_gt_2) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 90 | TEST_REQUIRES_ARM_NEON_FMA; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 91 | for (size_t rows = 3; rows < 4; rows++) { |
| 92 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 93 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 94 | .channel_tile(4) |
| 95 | .channels(channels) |
| 96 | .rows(rows) |
| 97 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neonfma_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 98 | } |
| 99 | } |
| 100 | } |
| 101 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 102 | TEST(F32_VMULCADDC_C4__NEONFMA_2X, input_stride) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 103 | TEST_REQUIRES_ARM_NEON_FMA; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 104 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 105 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 106 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 107 | .channel_tile(4) |
| 108 | .channels(channels) |
| 109 | .rows(rows) |
| 110 | .input_stride(23) |
| 111 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neonfma_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 112 | } |
| 113 | } |
| 114 | } |
| 115 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 116 | TEST(F32_VMULCADDC_C4__NEONFMA_2X, output_stride) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 117 | TEST_REQUIRES_ARM_NEON_FMA; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 118 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 119 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 120 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 121 | .channel_tile(4) |
| 122 | .channels(channels) |
| 123 | .rows(rows) |
| 124 | .output_stride(23) |
| 125 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neonfma_2x); |
| 126 | } |
| 127 | } |
| 128 | } |
| 129 | |
| 130 | TEST(F32_VMULCADDC_C4__NEONFMA_2X, inplace) { |
| 131 | TEST_REQUIRES_ARM_NEON_FMA; |
| 132 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 133 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 134 | VMulCAddCMicrokernelTester() |
| 135 | .channel_tile(4) |
| 136 | .channels(channels) |
| 137 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 138 | .inplace(true) |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 139 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neonfma_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 140 | } |
| 141 | } |
| 142 | } |
| 143 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 144 | TEST(F32_VMULCADDC_C4__NEONFMA_2X, qmin) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 145 | TEST_REQUIRES_ARM_NEON_FMA; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 146 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 147 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 148 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 149 | .channel_tile(4) |
| 150 | .channels(channels) |
| 151 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 152 | .qmin(128) |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 153 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neonfma_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 154 | } |
| 155 | } |
| 156 | } |
| 157 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 158 | TEST(F32_VMULCADDC_C4__NEONFMA_2X, qmax) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 159 | TEST_REQUIRES_ARM_NEON_FMA; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 160 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 161 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 162 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 163 | .channel_tile(4) |
| 164 | .channels(channels) |
| 165 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 166 | .qmax(128) |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 167 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neonfma_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 168 | } |
| 169 | } |
| 170 | } |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 171 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 172 | |
| 173 | |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 174 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 175 | TEST(F32_VMULCADDC_C8__NEONFMA_2X, channels_eq_8) { |
| 176 | TEST_REQUIRES_ARM_NEON_FMA; |
| 177 | VMulCAddCMicrokernelTester() |
| 178 | .channel_tile(8) |
| 179 | .channels(8) |
| 180 | .rows(2) |
| 181 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neonfma_2x); |
| 182 | } |
| 183 | |
| 184 | TEST(F32_VMULCADDC_C8__NEONFMA_2X, channels_div_8) { |
| 185 | TEST_REQUIRES_ARM_NEON_FMA; |
| 186 | for (size_t channels = 16; channels < 80; channels += 8) { |
| 187 | VMulCAddCMicrokernelTester() |
| 188 | .channel_tile(8) |
| 189 | .channels(channels) |
| 190 | .rows(2) |
| 191 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neonfma_2x); |
| 192 | } |
| 193 | } |
| 194 | |
| 195 | TEST(F32_VMULCADDC_C8__NEONFMA_2X, channels_lt_8) { |
| 196 | TEST_REQUIRES_ARM_NEON_FMA; |
| 197 | for (size_t channels = 1; channels < 8; channels++) { |
| 198 | VMulCAddCMicrokernelTester() |
| 199 | .channel_tile(8) |
| 200 | .channels(channels) |
| 201 | .rows(2) |
| 202 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neonfma_2x); |
| 203 | } |
| 204 | } |
| 205 | |
| 206 | TEST(F32_VMULCADDC_C8__NEONFMA_2X, channels_gt_8) { |
| 207 | TEST_REQUIRES_ARM_NEON_FMA; |
| 208 | for (size_t channels = 9; channels < 16; channels++) { |
| 209 | VMulCAddCMicrokernelTester() |
| 210 | .channel_tile(8) |
| 211 | .channels(channels) |
| 212 | .rows(2) |
| 213 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neonfma_2x); |
| 214 | } |
| 215 | } |
| 216 | |
| 217 | TEST(F32_VMULCADDC_C8__NEONFMA_2X, rows_lt_2) { |
| 218 | TEST_REQUIRES_ARM_NEON_FMA; |
| 219 | for (size_t rows = 1; rows < 2; rows++) { |
| 220 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 221 | VMulCAddCMicrokernelTester() |
| 222 | .channel_tile(8) |
| 223 | .channels(channels) |
| 224 | .rows(rows) |
| 225 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neonfma_2x); |
| 226 | } |
| 227 | } |
| 228 | } |
| 229 | |
| 230 | TEST(F32_VMULCADDC_C8__NEONFMA_2X, rows_div_2) { |
| 231 | TEST_REQUIRES_ARM_NEON_FMA; |
| 232 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 233 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 234 | VMulCAddCMicrokernelTester() |
| 235 | .channel_tile(8) |
| 236 | .channels(channels) |
| 237 | .rows(rows) |
| 238 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neonfma_2x); |
| 239 | } |
| 240 | } |
| 241 | } |
| 242 | |
| 243 | TEST(F32_VMULCADDC_C8__NEONFMA_2X, rows_gt_2) { |
| 244 | TEST_REQUIRES_ARM_NEON_FMA; |
| 245 | for (size_t rows = 3; rows < 4; rows++) { |
| 246 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 247 | VMulCAddCMicrokernelTester() |
| 248 | .channel_tile(8) |
| 249 | .channels(channels) |
| 250 | .rows(rows) |
| 251 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neonfma_2x); |
| 252 | } |
| 253 | } |
| 254 | } |
| 255 | |
| 256 | TEST(F32_VMULCADDC_C8__NEONFMA_2X, input_stride) { |
| 257 | TEST_REQUIRES_ARM_NEON_FMA; |
| 258 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 259 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 260 | VMulCAddCMicrokernelTester() |
| 261 | .channel_tile(8) |
| 262 | .channels(channels) |
| 263 | .rows(rows) |
| 264 | .input_stride(43) |
| 265 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neonfma_2x); |
| 266 | } |
| 267 | } |
| 268 | } |
| 269 | |
| 270 | TEST(F32_VMULCADDC_C8__NEONFMA_2X, output_stride) { |
| 271 | TEST_REQUIRES_ARM_NEON_FMA; |
| 272 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 273 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 274 | VMulCAddCMicrokernelTester() |
| 275 | .channel_tile(8) |
| 276 | .channels(channels) |
| 277 | .rows(rows) |
| 278 | .output_stride(43) |
| 279 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neonfma_2x); |
| 280 | } |
| 281 | } |
| 282 | } |
| 283 | |
| 284 | TEST(F32_VMULCADDC_C8__NEONFMA_2X, inplace) { |
| 285 | TEST_REQUIRES_ARM_NEON_FMA; |
| 286 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 287 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 288 | VMulCAddCMicrokernelTester() |
| 289 | .channel_tile(8) |
| 290 | .channels(channels) |
| 291 | .rows(rows) |
| 292 | .inplace(true) |
| 293 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neonfma_2x); |
| 294 | } |
| 295 | } |
| 296 | } |
| 297 | |
| 298 | TEST(F32_VMULCADDC_C8__NEONFMA_2X, qmin) { |
| 299 | TEST_REQUIRES_ARM_NEON_FMA; |
| 300 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 301 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 302 | VMulCAddCMicrokernelTester() |
| 303 | .channel_tile(8) |
| 304 | .channels(channels) |
| 305 | .rows(rows) |
| 306 | .qmin(128) |
| 307 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neonfma_2x); |
| 308 | } |
| 309 | } |
| 310 | } |
| 311 | |
| 312 | TEST(F32_VMULCADDC_C8__NEONFMA_2X, qmax) { |
| 313 | TEST_REQUIRES_ARM_NEON_FMA; |
| 314 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 315 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 316 | VMulCAddCMicrokernelTester() |
| 317 | .channel_tile(8) |
| 318 | .channels(channels) |
| 319 | .rows(rows) |
| 320 | .qmax(128) |
| 321 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neonfma_2x); |
| 322 | } |
| 323 | } |
| 324 | } |
| 325 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 326 | |
| 327 | |
| 328 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 329 | TEST(F32_VMULCADDC_C4__NEON_2X, channels_eq_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 330 | TEST_REQUIRES_ARM_NEON; |
| 331 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 332 | .channel_tile(4) |
| 333 | .channels(4) |
| 334 | .rows(2) |
| 335 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neon_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 336 | } |
| 337 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 338 | TEST(F32_VMULCADDC_C4__NEON_2X, channels_div_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 339 | TEST_REQUIRES_ARM_NEON; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 340 | for (size_t channels = 8; channels < 40; channels += 4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 341 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 342 | .channel_tile(4) |
| 343 | .channels(channels) |
| 344 | .rows(2) |
| 345 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neon_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 346 | } |
| 347 | } |
| 348 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 349 | TEST(F32_VMULCADDC_C4__NEON_2X, channels_lt_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 350 | TEST_REQUIRES_ARM_NEON; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 351 | for (size_t channels = 1; channels < 4; channels++) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 352 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 353 | .channel_tile(4) |
| 354 | .channels(channels) |
| 355 | .rows(2) |
| 356 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neon_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 357 | } |
| 358 | } |
| 359 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 360 | TEST(F32_VMULCADDC_C4__NEON_2X, channels_gt_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 361 | TEST_REQUIRES_ARM_NEON; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 362 | for (size_t channels = 5; channels < 8; channels++) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 363 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 364 | .channel_tile(4) |
| 365 | .channels(channels) |
| 366 | .rows(2) |
| 367 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neon_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 368 | } |
| 369 | } |
| 370 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 371 | TEST(F32_VMULCADDC_C4__NEON_2X, rows_lt_2) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 372 | TEST_REQUIRES_ARM_NEON; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 373 | for (size_t rows = 1; rows < 2; rows++) { |
| 374 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 375 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 376 | .channel_tile(4) |
| 377 | .channels(channels) |
| 378 | .rows(rows) |
| 379 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neon_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 380 | } |
| 381 | } |
| 382 | } |
| 383 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 384 | TEST(F32_VMULCADDC_C4__NEON_2X, rows_div_2) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 385 | TEST_REQUIRES_ARM_NEON; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 386 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 387 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 388 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 389 | .channel_tile(4) |
| 390 | .channels(channels) |
| 391 | .rows(rows) |
| 392 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neon_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 393 | } |
| 394 | } |
| 395 | } |
| 396 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 397 | TEST(F32_VMULCADDC_C4__NEON_2X, rows_gt_2) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 398 | TEST_REQUIRES_ARM_NEON; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 399 | for (size_t rows = 3; rows < 4; rows++) { |
| 400 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 401 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 402 | .channel_tile(4) |
| 403 | .channels(channels) |
| 404 | .rows(rows) |
| 405 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neon_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 406 | } |
| 407 | } |
| 408 | } |
| 409 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 410 | TEST(F32_VMULCADDC_C4__NEON_2X, input_stride) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 411 | TEST_REQUIRES_ARM_NEON; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 412 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 413 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 414 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 415 | .channel_tile(4) |
| 416 | .channels(channels) |
| 417 | .rows(rows) |
| 418 | .input_stride(23) |
| 419 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neon_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 420 | } |
| 421 | } |
| 422 | } |
| 423 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 424 | TEST(F32_VMULCADDC_C4__NEON_2X, output_stride) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 425 | TEST_REQUIRES_ARM_NEON; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 426 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 427 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 428 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 429 | .channel_tile(4) |
| 430 | .channels(channels) |
| 431 | .rows(rows) |
| 432 | .output_stride(23) |
| 433 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neon_2x); |
| 434 | } |
| 435 | } |
| 436 | } |
| 437 | |
| 438 | TEST(F32_VMULCADDC_C4__NEON_2X, inplace) { |
| 439 | TEST_REQUIRES_ARM_NEON; |
| 440 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 441 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 442 | VMulCAddCMicrokernelTester() |
| 443 | .channel_tile(4) |
| 444 | .channels(channels) |
| 445 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 446 | .inplace(true) |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 447 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neon_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 448 | } |
| 449 | } |
| 450 | } |
| 451 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 452 | TEST(F32_VMULCADDC_C4__NEON_2X, qmin) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 453 | TEST_REQUIRES_ARM_NEON; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 454 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 455 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 456 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 457 | .channel_tile(4) |
| 458 | .channels(channels) |
| 459 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 460 | .qmin(128) |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 461 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neon_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 462 | } |
| 463 | } |
| 464 | } |
| 465 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 466 | TEST(F32_VMULCADDC_C4__NEON_2X, qmax) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 467 | TEST_REQUIRES_ARM_NEON; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 468 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 469 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 470 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 471 | .channel_tile(4) |
| 472 | .channels(channels) |
| 473 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 474 | .qmax(128) |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 475 | .Test(xnn_f32_vmulcaddc_ukernel_c4__neon_2x); |
| 476 | } |
| 477 | } |
| 478 | } |
| 479 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 480 | |
| 481 | |
| 482 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 483 | TEST(F32_VMULCADDC_C8__NEON_2X, channels_eq_8) { |
| 484 | TEST_REQUIRES_ARM_NEON; |
| 485 | VMulCAddCMicrokernelTester() |
| 486 | .channel_tile(8) |
| 487 | .channels(8) |
| 488 | .rows(2) |
| 489 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neon_2x); |
| 490 | } |
| 491 | |
| 492 | TEST(F32_VMULCADDC_C8__NEON_2X, channels_div_8) { |
| 493 | TEST_REQUIRES_ARM_NEON; |
| 494 | for (size_t channels = 16; channels < 80; channels += 8) { |
| 495 | VMulCAddCMicrokernelTester() |
| 496 | .channel_tile(8) |
| 497 | .channels(channels) |
| 498 | .rows(2) |
| 499 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neon_2x); |
| 500 | } |
| 501 | } |
| 502 | |
| 503 | TEST(F32_VMULCADDC_C8__NEON_2X, channels_lt_8) { |
| 504 | TEST_REQUIRES_ARM_NEON; |
| 505 | for (size_t channels = 1; channels < 8; channels++) { |
| 506 | VMulCAddCMicrokernelTester() |
| 507 | .channel_tile(8) |
| 508 | .channels(channels) |
| 509 | .rows(2) |
| 510 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neon_2x); |
| 511 | } |
| 512 | } |
| 513 | |
| 514 | TEST(F32_VMULCADDC_C8__NEON_2X, channels_gt_8) { |
| 515 | TEST_REQUIRES_ARM_NEON; |
| 516 | for (size_t channels = 9; channels < 16; channels++) { |
| 517 | VMulCAddCMicrokernelTester() |
| 518 | .channel_tile(8) |
| 519 | .channels(channels) |
| 520 | .rows(2) |
| 521 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neon_2x); |
| 522 | } |
| 523 | } |
| 524 | |
| 525 | TEST(F32_VMULCADDC_C8__NEON_2X, rows_lt_2) { |
| 526 | TEST_REQUIRES_ARM_NEON; |
| 527 | for (size_t rows = 1; rows < 2; rows++) { |
| 528 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 529 | VMulCAddCMicrokernelTester() |
| 530 | .channel_tile(8) |
| 531 | .channels(channels) |
| 532 | .rows(rows) |
| 533 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neon_2x); |
| 534 | } |
| 535 | } |
| 536 | } |
| 537 | |
| 538 | TEST(F32_VMULCADDC_C8__NEON_2X, rows_div_2) { |
| 539 | TEST_REQUIRES_ARM_NEON; |
| 540 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 541 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 542 | VMulCAddCMicrokernelTester() |
| 543 | .channel_tile(8) |
| 544 | .channels(channels) |
| 545 | .rows(rows) |
| 546 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neon_2x); |
| 547 | } |
| 548 | } |
| 549 | } |
| 550 | |
| 551 | TEST(F32_VMULCADDC_C8__NEON_2X, rows_gt_2) { |
| 552 | TEST_REQUIRES_ARM_NEON; |
| 553 | for (size_t rows = 3; rows < 4; rows++) { |
| 554 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 555 | VMulCAddCMicrokernelTester() |
| 556 | .channel_tile(8) |
| 557 | .channels(channels) |
| 558 | .rows(rows) |
| 559 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neon_2x); |
| 560 | } |
| 561 | } |
| 562 | } |
| 563 | |
| 564 | TEST(F32_VMULCADDC_C8__NEON_2X, input_stride) { |
| 565 | TEST_REQUIRES_ARM_NEON; |
| 566 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 567 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 568 | VMulCAddCMicrokernelTester() |
| 569 | .channel_tile(8) |
| 570 | .channels(channels) |
| 571 | .rows(rows) |
| 572 | .input_stride(43) |
| 573 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neon_2x); |
| 574 | } |
| 575 | } |
| 576 | } |
| 577 | |
| 578 | TEST(F32_VMULCADDC_C8__NEON_2X, output_stride) { |
| 579 | TEST_REQUIRES_ARM_NEON; |
| 580 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 581 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 582 | VMulCAddCMicrokernelTester() |
| 583 | .channel_tile(8) |
| 584 | .channels(channels) |
| 585 | .rows(rows) |
| 586 | .output_stride(43) |
| 587 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neon_2x); |
| 588 | } |
| 589 | } |
| 590 | } |
| 591 | |
| 592 | TEST(F32_VMULCADDC_C8__NEON_2X, inplace) { |
| 593 | TEST_REQUIRES_ARM_NEON; |
| 594 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 595 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 596 | VMulCAddCMicrokernelTester() |
| 597 | .channel_tile(8) |
| 598 | .channels(channels) |
| 599 | .rows(rows) |
| 600 | .inplace(true) |
| 601 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neon_2x); |
| 602 | } |
| 603 | } |
| 604 | } |
| 605 | |
| 606 | TEST(F32_VMULCADDC_C8__NEON_2X, qmin) { |
| 607 | TEST_REQUIRES_ARM_NEON; |
| 608 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 609 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 610 | VMulCAddCMicrokernelTester() |
| 611 | .channel_tile(8) |
| 612 | .channels(channels) |
| 613 | .rows(rows) |
| 614 | .qmin(128) |
| 615 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neon_2x); |
| 616 | } |
| 617 | } |
| 618 | } |
| 619 | |
| 620 | TEST(F32_VMULCADDC_C8__NEON_2X, qmax) { |
| 621 | TEST_REQUIRES_ARM_NEON; |
| 622 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 623 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 624 | VMulCAddCMicrokernelTester() |
| 625 | .channel_tile(8) |
| 626 | .channels(channels) |
| 627 | .rows(rows) |
| 628 | .qmax(128) |
| 629 | .Test(xnn_f32_vmulcaddc_ukernel_c8__neon_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 630 | } |
| 631 | } |
| 632 | } |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 633 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 634 | |
| 635 | |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 636 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 637 | TEST(F32_VMULCADDC_C4__SSE_2X, channels_eq_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 638 | TEST_REQUIRES_X86_SSE; |
| 639 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 640 | .channel_tile(4) |
| 641 | .channels(4) |
| 642 | .rows(2) |
| 643 | .Test(xnn_f32_vmulcaddc_ukernel_c4__sse_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 644 | } |
| 645 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 646 | TEST(F32_VMULCADDC_C4__SSE_2X, channels_div_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 647 | TEST_REQUIRES_X86_SSE; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 648 | for (size_t channels = 8; channels < 40; channels += 4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 649 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 650 | .channel_tile(4) |
| 651 | .channels(channels) |
| 652 | .rows(2) |
| 653 | .Test(xnn_f32_vmulcaddc_ukernel_c4__sse_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 654 | } |
| 655 | } |
| 656 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 657 | TEST(F32_VMULCADDC_C4__SSE_2X, channels_lt_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 658 | TEST_REQUIRES_X86_SSE; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 659 | for (size_t channels = 1; channels < 4; channels++) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 660 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 661 | .channel_tile(4) |
| 662 | .channels(channels) |
| 663 | .rows(2) |
| 664 | .Test(xnn_f32_vmulcaddc_ukernel_c4__sse_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 665 | } |
| 666 | } |
| 667 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 668 | TEST(F32_VMULCADDC_C4__SSE_2X, channels_gt_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 669 | TEST_REQUIRES_X86_SSE; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 670 | for (size_t channels = 5; channels < 8; channels++) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 671 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 672 | .channel_tile(4) |
| 673 | .channels(channels) |
| 674 | .rows(2) |
| 675 | .Test(xnn_f32_vmulcaddc_ukernel_c4__sse_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 676 | } |
| 677 | } |
| 678 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 679 | TEST(F32_VMULCADDC_C4__SSE_2X, rows_lt_2) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 680 | TEST_REQUIRES_X86_SSE; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 681 | for (size_t rows = 1; rows < 2; rows++) { |
| 682 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 683 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 684 | .channel_tile(4) |
| 685 | .channels(channels) |
| 686 | .rows(rows) |
| 687 | .Test(xnn_f32_vmulcaddc_ukernel_c4__sse_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 688 | } |
| 689 | } |
| 690 | } |
| 691 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 692 | TEST(F32_VMULCADDC_C4__SSE_2X, rows_div_2) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 693 | TEST_REQUIRES_X86_SSE; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 694 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 695 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 696 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 697 | .channel_tile(4) |
| 698 | .channels(channels) |
| 699 | .rows(rows) |
| 700 | .Test(xnn_f32_vmulcaddc_ukernel_c4__sse_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 701 | } |
| 702 | } |
| 703 | } |
| 704 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 705 | TEST(F32_VMULCADDC_C4__SSE_2X, rows_gt_2) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 706 | TEST_REQUIRES_X86_SSE; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 707 | for (size_t rows = 3; rows < 4; rows++) { |
| 708 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 709 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 710 | .channel_tile(4) |
| 711 | .channels(channels) |
| 712 | .rows(rows) |
| 713 | .Test(xnn_f32_vmulcaddc_ukernel_c4__sse_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 714 | } |
| 715 | } |
| 716 | } |
| 717 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 718 | TEST(F32_VMULCADDC_C4__SSE_2X, input_stride) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 719 | TEST_REQUIRES_X86_SSE; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 720 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 721 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 722 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 723 | .channel_tile(4) |
| 724 | .channels(channels) |
| 725 | .rows(rows) |
| 726 | .input_stride(23) |
| 727 | .Test(xnn_f32_vmulcaddc_ukernel_c4__sse_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 728 | } |
| 729 | } |
| 730 | } |
| 731 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 732 | TEST(F32_VMULCADDC_C4__SSE_2X, output_stride) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 733 | TEST_REQUIRES_X86_SSE; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 734 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 735 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 736 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 737 | .channel_tile(4) |
| 738 | .channels(channels) |
| 739 | .rows(rows) |
| 740 | .output_stride(23) |
| 741 | .Test(xnn_f32_vmulcaddc_ukernel_c4__sse_2x); |
| 742 | } |
| 743 | } |
| 744 | } |
| 745 | |
| 746 | TEST(F32_VMULCADDC_C4__SSE_2X, inplace) { |
| 747 | TEST_REQUIRES_X86_SSE; |
| 748 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 749 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 750 | VMulCAddCMicrokernelTester() |
| 751 | .channel_tile(4) |
| 752 | .channels(channels) |
| 753 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 754 | .inplace(true) |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 755 | .Test(xnn_f32_vmulcaddc_ukernel_c4__sse_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 756 | } |
| 757 | } |
| 758 | } |
| 759 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 760 | TEST(F32_VMULCADDC_C4__SSE_2X, qmin) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 761 | TEST_REQUIRES_X86_SSE; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 762 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 763 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 764 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 765 | .channel_tile(4) |
| 766 | .channels(channels) |
| 767 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 768 | .qmin(128) |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 769 | .Test(xnn_f32_vmulcaddc_ukernel_c4__sse_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 770 | } |
| 771 | } |
| 772 | } |
| 773 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 774 | TEST(F32_VMULCADDC_C4__SSE_2X, qmax) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 775 | TEST_REQUIRES_X86_SSE; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 776 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 777 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 778 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 779 | .channel_tile(4) |
| 780 | .channels(channels) |
| 781 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 782 | .qmax(128) |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 783 | .Test(xnn_f32_vmulcaddc_ukernel_c4__sse_2x); |
| 784 | } |
| 785 | } |
| 786 | } |
| 787 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 788 | |
| 789 | |
| 790 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 791 | TEST(F32_VMULCADDC_C8__SSE_2X, channels_eq_8) { |
| 792 | TEST_REQUIRES_X86_SSE; |
| 793 | VMulCAddCMicrokernelTester() |
| 794 | .channel_tile(8) |
| 795 | .channels(8) |
| 796 | .rows(2) |
| 797 | .Test(xnn_f32_vmulcaddc_ukernel_c8__sse_2x); |
| 798 | } |
| 799 | |
| 800 | TEST(F32_VMULCADDC_C8__SSE_2X, channels_div_8) { |
| 801 | TEST_REQUIRES_X86_SSE; |
| 802 | for (size_t channels = 16; channels < 80; channels += 8) { |
| 803 | VMulCAddCMicrokernelTester() |
| 804 | .channel_tile(8) |
| 805 | .channels(channels) |
| 806 | .rows(2) |
| 807 | .Test(xnn_f32_vmulcaddc_ukernel_c8__sse_2x); |
| 808 | } |
| 809 | } |
| 810 | |
| 811 | TEST(F32_VMULCADDC_C8__SSE_2X, channels_lt_8) { |
| 812 | TEST_REQUIRES_X86_SSE; |
| 813 | for (size_t channels = 1; channels < 8; channels++) { |
| 814 | VMulCAddCMicrokernelTester() |
| 815 | .channel_tile(8) |
| 816 | .channels(channels) |
| 817 | .rows(2) |
| 818 | .Test(xnn_f32_vmulcaddc_ukernel_c8__sse_2x); |
| 819 | } |
| 820 | } |
| 821 | |
| 822 | TEST(F32_VMULCADDC_C8__SSE_2X, channels_gt_8) { |
| 823 | TEST_REQUIRES_X86_SSE; |
| 824 | for (size_t channels = 9; channels < 16; channels++) { |
| 825 | VMulCAddCMicrokernelTester() |
| 826 | .channel_tile(8) |
| 827 | .channels(channels) |
| 828 | .rows(2) |
| 829 | .Test(xnn_f32_vmulcaddc_ukernel_c8__sse_2x); |
| 830 | } |
| 831 | } |
| 832 | |
| 833 | TEST(F32_VMULCADDC_C8__SSE_2X, rows_lt_2) { |
| 834 | TEST_REQUIRES_X86_SSE; |
| 835 | for (size_t rows = 1; rows < 2; rows++) { |
| 836 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 837 | VMulCAddCMicrokernelTester() |
| 838 | .channel_tile(8) |
| 839 | .channels(channels) |
| 840 | .rows(rows) |
| 841 | .Test(xnn_f32_vmulcaddc_ukernel_c8__sse_2x); |
| 842 | } |
| 843 | } |
| 844 | } |
| 845 | |
| 846 | TEST(F32_VMULCADDC_C8__SSE_2X, rows_div_2) { |
| 847 | TEST_REQUIRES_X86_SSE; |
| 848 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 849 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 850 | VMulCAddCMicrokernelTester() |
| 851 | .channel_tile(8) |
| 852 | .channels(channels) |
| 853 | .rows(rows) |
| 854 | .Test(xnn_f32_vmulcaddc_ukernel_c8__sse_2x); |
| 855 | } |
| 856 | } |
| 857 | } |
| 858 | |
| 859 | TEST(F32_VMULCADDC_C8__SSE_2X, rows_gt_2) { |
| 860 | TEST_REQUIRES_X86_SSE; |
| 861 | for (size_t rows = 3; rows < 4; rows++) { |
| 862 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 863 | VMulCAddCMicrokernelTester() |
| 864 | .channel_tile(8) |
| 865 | .channels(channels) |
| 866 | .rows(rows) |
| 867 | .Test(xnn_f32_vmulcaddc_ukernel_c8__sse_2x); |
| 868 | } |
| 869 | } |
| 870 | } |
| 871 | |
| 872 | TEST(F32_VMULCADDC_C8__SSE_2X, input_stride) { |
| 873 | TEST_REQUIRES_X86_SSE; |
| 874 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 875 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 876 | VMulCAddCMicrokernelTester() |
| 877 | .channel_tile(8) |
| 878 | .channels(channels) |
| 879 | .rows(rows) |
| 880 | .input_stride(43) |
| 881 | .Test(xnn_f32_vmulcaddc_ukernel_c8__sse_2x); |
| 882 | } |
| 883 | } |
| 884 | } |
| 885 | |
| 886 | TEST(F32_VMULCADDC_C8__SSE_2X, output_stride) { |
| 887 | TEST_REQUIRES_X86_SSE; |
| 888 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 889 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 890 | VMulCAddCMicrokernelTester() |
| 891 | .channel_tile(8) |
| 892 | .channels(channels) |
| 893 | .rows(rows) |
| 894 | .output_stride(43) |
| 895 | .Test(xnn_f32_vmulcaddc_ukernel_c8__sse_2x); |
| 896 | } |
| 897 | } |
| 898 | } |
| 899 | |
| 900 | TEST(F32_VMULCADDC_C8__SSE_2X, inplace) { |
| 901 | TEST_REQUIRES_X86_SSE; |
| 902 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 903 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 904 | VMulCAddCMicrokernelTester() |
| 905 | .channel_tile(8) |
| 906 | .channels(channels) |
| 907 | .rows(rows) |
| 908 | .inplace(true) |
| 909 | .Test(xnn_f32_vmulcaddc_ukernel_c8__sse_2x); |
| 910 | } |
| 911 | } |
| 912 | } |
| 913 | |
| 914 | TEST(F32_VMULCADDC_C8__SSE_2X, qmin) { |
| 915 | TEST_REQUIRES_X86_SSE; |
| 916 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 917 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 918 | VMulCAddCMicrokernelTester() |
| 919 | .channel_tile(8) |
| 920 | .channels(channels) |
| 921 | .rows(rows) |
| 922 | .qmin(128) |
| 923 | .Test(xnn_f32_vmulcaddc_ukernel_c8__sse_2x); |
| 924 | } |
| 925 | } |
| 926 | } |
| 927 | |
| 928 | TEST(F32_VMULCADDC_C8__SSE_2X, qmax) { |
| 929 | TEST_REQUIRES_X86_SSE; |
| 930 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 931 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 932 | VMulCAddCMicrokernelTester() |
| 933 | .channel_tile(8) |
| 934 | .channels(channels) |
| 935 | .rows(rows) |
| 936 | .qmax(128) |
| 937 | .Test(xnn_f32_vmulcaddc_ukernel_c8__sse_2x); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 938 | } |
| 939 | } |
| 940 | } |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 941 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 942 | |
| 943 | |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 944 | #if !XNN_ARCH_ASMJS && !XNN_ARCH_WASM |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 945 | TEST(F32_VMULCADDC_C4__PSIMD_2X, channels_eq_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 946 | TEST_REQUIRES_PSIMD; |
| 947 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 948 | .channel_tile(4) |
| 949 | .channels(4) |
| 950 | .rows(2) |
| 951 | .Test(xnn_f32_vmulcaddc_ukernel_c4__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 952 | } |
| 953 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 954 | TEST(F32_VMULCADDC_C4__PSIMD_2X, channels_div_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 955 | TEST_REQUIRES_PSIMD; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 956 | for (size_t channels = 8; channels < 40; channels += 4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 957 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 958 | .channel_tile(4) |
| 959 | .channels(channels) |
| 960 | .rows(2) |
| 961 | .Test(xnn_f32_vmulcaddc_ukernel_c4__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 962 | } |
| 963 | } |
| 964 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 965 | TEST(F32_VMULCADDC_C4__PSIMD_2X, channels_lt_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 966 | TEST_REQUIRES_PSIMD; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 967 | for (size_t channels = 1; channels < 4; channels++) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 968 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 969 | .channel_tile(4) |
| 970 | .channels(channels) |
| 971 | .rows(2) |
| 972 | .Test(xnn_f32_vmulcaddc_ukernel_c4__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 973 | } |
| 974 | } |
| 975 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 976 | TEST(F32_VMULCADDC_C4__PSIMD_2X, channels_gt_4) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 977 | TEST_REQUIRES_PSIMD; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 978 | for (size_t channels = 5; channels < 8; channels++) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 979 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 980 | .channel_tile(4) |
| 981 | .channels(channels) |
| 982 | .rows(2) |
| 983 | .Test(xnn_f32_vmulcaddc_ukernel_c4__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 984 | } |
| 985 | } |
| 986 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 987 | TEST(F32_VMULCADDC_C4__PSIMD_2X, rows_lt_2) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 988 | TEST_REQUIRES_PSIMD; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 989 | for (size_t rows = 1; rows < 2; rows++) { |
| 990 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 991 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 992 | .channel_tile(4) |
| 993 | .channels(channels) |
| 994 | .rows(rows) |
| 995 | .Test(xnn_f32_vmulcaddc_ukernel_c4__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 996 | } |
| 997 | } |
| 998 | } |
| 999 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1000 | TEST(F32_VMULCADDC_C4__PSIMD_2X, rows_div_2) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1001 | TEST_REQUIRES_PSIMD; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1002 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 1003 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1004 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1005 | .channel_tile(4) |
| 1006 | .channels(channels) |
| 1007 | .rows(rows) |
| 1008 | .Test(xnn_f32_vmulcaddc_ukernel_c4__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1009 | } |
| 1010 | } |
| 1011 | } |
| 1012 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1013 | TEST(F32_VMULCADDC_C4__PSIMD_2X, rows_gt_2) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1014 | TEST_REQUIRES_PSIMD; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1015 | for (size_t rows = 3; rows < 4; rows++) { |
| 1016 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1017 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1018 | .channel_tile(4) |
| 1019 | .channels(channels) |
| 1020 | .rows(rows) |
| 1021 | .Test(xnn_f32_vmulcaddc_ukernel_c4__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1022 | } |
| 1023 | } |
| 1024 | } |
| 1025 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1026 | TEST(F32_VMULCADDC_C4__PSIMD_2X, input_stride) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1027 | TEST_REQUIRES_PSIMD; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1028 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1029 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1030 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1031 | .channel_tile(4) |
| 1032 | .channels(channels) |
| 1033 | .rows(rows) |
| 1034 | .input_stride(23) |
| 1035 | .Test(xnn_f32_vmulcaddc_ukernel_c4__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1036 | } |
| 1037 | } |
| 1038 | } |
| 1039 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1040 | TEST(F32_VMULCADDC_C4__PSIMD_2X, output_stride) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1041 | TEST_REQUIRES_PSIMD; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1042 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1043 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1044 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1045 | .channel_tile(4) |
| 1046 | .channels(channels) |
| 1047 | .rows(rows) |
| 1048 | .output_stride(23) |
| 1049 | .Test(xnn_f32_vmulcaddc_ukernel_c4__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1050 | } |
| 1051 | } |
| 1052 | } |
| 1053 | |
| 1054 | TEST(F32_VMULCADDC_C4__PSIMD_2X, inplace) { |
| 1055 | TEST_REQUIRES_PSIMD; |
| 1056 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1057 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1058 | VMulCAddCMicrokernelTester() |
| 1059 | .channel_tile(4) |
| 1060 | .channels(channels) |
| 1061 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1062 | .inplace(true) |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1063 | .Test(xnn_f32_vmulcaddc_ukernel_c4__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1064 | } |
| 1065 | } |
| 1066 | } |
| 1067 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1068 | TEST(F32_VMULCADDC_C4__PSIMD_2X, qmin) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1069 | TEST_REQUIRES_PSIMD; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1070 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1071 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1072 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1073 | .channel_tile(4) |
| 1074 | .channels(channels) |
| 1075 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1076 | .qmin(128) |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1077 | .Test(xnn_f32_vmulcaddc_ukernel_c4__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1078 | } |
| 1079 | } |
| 1080 | } |
| 1081 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1082 | TEST(F32_VMULCADDC_C4__PSIMD_2X, qmax) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1083 | TEST_REQUIRES_PSIMD; |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1084 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1085 | for (size_t channels = 1; channels <= 20; channels += 3) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1086 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1087 | .channel_tile(4) |
| 1088 | .channels(channels) |
| 1089 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1090 | .qmax(128) |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1091 | .Test(xnn_f32_vmulcaddc_ukernel_c4__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1092 | } |
| 1093 | } |
| 1094 | } |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 1095 | #endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1096 | |
| 1097 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1098 | #if !XNN_ARCH_ASMJS && !XNN_ARCH_WASM |
| 1099 | TEST(F32_VMULCADDC_C8__PSIMD_2X, channels_eq_8) { |
| 1100 | TEST_REQUIRES_PSIMD; |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1101 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1102 | .channel_tile(8) |
| 1103 | .channels(8) |
| 1104 | .rows(2) |
| 1105 | .Test(xnn_f32_vmulcaddc_ukernel_c8__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1106 | } |
| 1107 | |
| 1108 | TEST(F32_VMULCADDC_C8__PSIMD_2X, channels_div_8) { |
| 1109 | TEST_REQUIRES_PSIMD; |
| 1110 | for (size_t channels = 16; channels < 80; channels += 8) { |
| 1111 | VMulCAddCMicrokernelTester() |
| 1112 | .channel_tile(8) |
| 1113 | .channels(channels) |
| 1114 | .rows(2) |
| 1115 | .Test(xnn_f32_vmulcaddc_ukernel_c8__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1116 | } |
| 1117 | } |
| 1118 | |
| 1119 | TEST(F32_VMULCADDC_C8__PSIMD_2X, channels_lt_8) { |
| 1120 | TEST_REQUIRES_PSIMD; |
| 1121 | for (size_t channels = 1; channels < 8; channels++) { |
| 1122 | VMulCAddCMicrokernelTester() |
| 1123 | .channel_tile(8) |
| 1124 | .channels(channels) |
| 1125 | .rows(2) |
| 1126 | .Test(xnn_f32_vmulcaddc_ukernel_c8__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1127 | } |
| 1128 | } |
| 1129 | |
| 1130 | TEST(F32_VMULCADDC_C8__PSIMD_2X, channels_gt_8) { |
| 1131 | TEST_REQUIRES_PSIMD; |
| 1132 | for (size_t channels = 9; channels < 16; channels++) { |
| 1133 | VMulCAddCMicrokernelTester() |
| 1134 | .channel_tile(8) |
| 1135 | .channels(channels) |
| 1136 | .rows(2) |
| 1137 | .Test(xnn_f32_vmulcaddc_ukernel_c8__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1138 | } |
| 1139 | } |
| 1140 | |
| 1141 | TEST(F32_VMULCADDC_C8__PSIMD_2X, rows_lt_2) { |
| 1142 | TEST_REQUIRES_PSIMD; |
| 1143 | for (size_t rows = 1; rows < 2; rows++) { |
| 1144 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1145 | VMulCAddCMicrokernelTester() |
| 1146 | .channel_tile(8) |
| 1147 | .channels(channels) |
| 1148 | .rows(rows) |
| 1149 | .Test(xnn_f32_vmulcaddc_ukernel_c8__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1150 | } |
| 1151 | } |
| 1152 | } |
| 1153 | |
| 1154 | TEST(F32_VMULCADDC_C8__PSIMD_2X, rows_div_2) { |
| 1155 | TEST_REQUIRES_PSIMD; |
| 1156 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 1157 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1158 | VMulCAddCMicrokernelTester() |
| 1159 | .channel_tile(8) |
| 1160 | .channels(channels) |
| 1161 | .rows(rows) |
| 1162 | .Test(xnn_f32_vmulcaddc_ukernel_c8__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1163 | } |
| 1164 | } |
| 1165 | } |
| 1166 | |
| 1167 | TEST(F32_VMULCADDC_C8__PSIMD_2X, rows_gt_2) { |
| 1168 | TEST_REQUIRES_PSIMD; |
| 1169 | for (size_t rows = 3; rows < 4; rows++) { |
| 1170 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1171 | VMulCAddCMicrokernelTester() |
| 1172 | .channel_tile(8) |
| 1173 | .channels(channels) |
| 1174 | .rows(rows) |
| 1175 | .Test(xnn_f32_vmulcaddc_ukernel_c8__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1176 | } |
| 1177 | } |
| 1178 | } |
| 1179 | |
| 1180 | TEST(F32_VMULCADDC_C8__PSIMD_2X, input_stride) { |
| 1181 | TEST_REQUIRES_PSIMD; |
| 1182 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1183 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1184 | VMulCAddCMicrokernelTester() |
| 1185 | .channel_tile(8) |
| 1186 | .channels(channels) |
| 1187 | .rows(rows) |
| 1188 | .input_stride(43) |
| 1189 | .Test(xnn_f32_vmulcaddc_ukernel_c8__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1190 | } |
| 1191 | } |
| 1192 | } |
| 1193 | |
| 1194 | TEST(F32_VMULCADDC_C8__PSIMD_2X, output_stride) { |
| 1195 | TEST_REQUIRES_PSIMD; |
| 1196 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1197 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1198 | VMulCAddCMicrokernelTester() |
| 1199 | .channel_tile(8) |
| 1200 | .channels(channels) |
| 1201 | .rows(rows) |
| 1202 | .output_stride(43) |
| 1203 | .Test(xnn_f32_vmulcaddc_ukernel_c8__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1204 | } |
| 1205 | } |
| 1206 | } |
| 1207 | |
| 1208 | TEST(F32_VMULCADDC_C8__PSIMD_2X, inplace) { |
| 1209 | TEST_REQUIRES_PSIMD; |
| 1210 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1211 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1212 | VMulCAddCMicrokernelTester() |
| 1213 | .channel_tile(8) |
| 1214 | .channels(channels) |
| 1215 | .rows(rows) |
| 1216 | .inplace(true) |
| 1217 | .Test(xnn_f32_vmulcaddc_ukernel_c8__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1218 | } |
| 1219 | } |
| 1220 | } |
| 1221 | |
| 1222 | TEST(F32_VMULCADDC_C8__PSIMD_2X, qmin) { |
| 1223 | TEST_REQUIRES_PSIMD; |
| 1224 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1225 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1226 | VMulCAddCMicrokernelTester() |
| 1227 | .channel_tile(8) |
| 1228 | .channels(channels) |
| 1229 | .rows(rows) |
| 1230 | .qmin(128) |
| 1231 | .Test(xnn_f32_vmulcaddc_ukernel_c8__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1232 | } |
| 1233 | } |
| 1234 | } |
| 1235 | |
| 1236 | TEST(F32_VMULCADDC_C8__PSIMD_2X, qmax) { |
| 1237 | TEST_REQUIRES_PSIMD; |
| 1238 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1239 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1240 | VMulCAddCMicrokernelTester() |
| 1241 | .channel_tile(8) |
| 1242 | .channels(channels) |
| 1243 | .rows(rows) |
| 1244 | .qmax(128) |
| 1245 | .Test(xnn_f32_vmulcaddc_ukernel_c8__psimd_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1246 | } |
| 1247 | } |
| 1248 | } |
| 1249 | #endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM |
| 1250 | |
| 1251 | |
Marat Dukhan | 436ebe6 | 2019-12-04 15:10:12 -0800 | [diff] [blame] | 1252 | #if XNN_ARCH_WASM |
| 1253 | TEST(F32_VMULCADDC_C1__WASM_2X, channels_eq_1) { |
| 1254 | VMulCAddCMicrokernelTester() |
| 1255 | .channel_tile(1) |
| 1256 | .channels(1) |
| 1257 | .rows(2) |
| 1258 | .Test(xnn_f32_vmulcaddc_ukernel_c1__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1259 | } |
| 1260 | |
| 1261 | TEST(F32_VMULCADDC_C1__WASM_2X, channels_gt_1) { |
| 1262 | for (size_t channels = 2; channels < 10; channels++) { |
| 1263 | VMulCAddCMicrokernelTester() |
| 1264 | .channel_tile(1) |
| 1265 | .channels(channels) |
| 1266 | .rows(2) |
| 1267 | .Test(xnn_f32_vmulcaddc_ukernel_c1__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1268 | } |
| 1269 | } |
| 1270 | |
| 1271 | TEST(F32_VMULCADDC_C1__WASM_2X, rows_lt_2) { |
| 1272 | for (size_t rows = 1; rows < 2; rows++) { |
| 1273 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 1274 | VMulCAddCMicrokernelTester() |
| 1275 | .channel_tile(1) |
| 1276 | .channels(channels) |
| 1277 | .rows(rows) |
| 1278 | .Test(xnn_f32_vmulcaddc_ukernel_c1__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1279 | } |
| 1280 | } |
| 1281 | } |
| 1282 | |
| 1283 | TEST(F32_VMULCADDC_C1__WASM_2X, rows_div_2) { |
| 1284 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 1285 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 1286 | VMulCAddCMicrokernelTester() |
| 1287 | .channel_tile(1) |
| 1288 | .channels(channels) |
| 1289 | .rows(rows) |
| 1290 | .Test(xnn_f32_vmulcaddc_ukernel_c1__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1291 | } |
| 1292 | } |
| 1293 | } |
| 1294 | |
| 1295 | TEST(F32_VMULCADDC_C1__WASM_2X, rows_gt_2) { |
| 1296 | for (size_t rows = 3; rows < 4; rows++) { |
| 1297 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 1298 | VMulCAddCMicrokernelTester() |
| 1299 | .channel_tile(1) |
| 1300 | .channels(channels) |
| 1301 | .rows(rows) |
| 1302 | .Test(xnn_f32_vmulcaddc_ukernel_c1__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1303 | } |
| 1304 | } |
| 1305 | } |
| 1306 | |
| 1307 | TEST(F32_VMULCADDC_C1__WASM_2X, input_stride) { |
| 1308 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1309 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 1310 | VMulCAddCMicrokernelTester() |
| 1311 | .channel_tile(1) |
| 1312 | .channels(channels) |
| 1313 | .rows(rows) |
| 1314 | .input_stride(7) |
| 1315 | .Test(xnn_f32_vmulcaddc_ukernel_c1__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1316 | } |
| 1317 | } |
| 1318 | } |
| 1319 | |
| 1320 | TEST(F32_VMULCADDC_C1__WASM_2X, output_stride) { |
| 1321 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1322 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 1323 | VMulCAddCMicrokernelTester() |
| 1324 | .channel_tile(1) |
| 1325 | .channels(channels) |
| 1326 | .rows(rows) |
| 1327 | .output_stride(7) |
| 1328 | .Test(xnn_f32_vmulcaddc_ukernel_c1__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1329 | } |
| 1330 | } |
| 1331 | } |
| 1332 | |
| 1333 | TEST(F32_VMULCADDC_C1__WASM_2X, inplace) { |
| 1334 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1335 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 1336 | VMulCAddCMicrokernelTester() |
| 1337 | .channel_tile(1) |
| 1338 | .channels(channels) |
| 1339 | .rows(rows) |
| 1340 | .inplace(true) |
| 1341 | .Test(xnn_f32_vmulcaddc_ukernel_c1__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1342 | } |
| 1343 | } |
| 1344 | } |
| 1345 | |
| 1346 | TEST(F32_VMULCADDC_C1__WASM_2X, qmin) { |
| 1347 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1348 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 1349 | VMulCAddCMicrokernelTester() |
| 1350 | .channel_tile(1) |
| 1351 | .channels(channels) |
| 1352 | .rows(rows) |
| 1353 | .qmin(128) |
| 1354 | .Test(xnn_f32_vmulcaddc_ukernel_c1__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1355 | } |
| 1356 | } |
| 1357 | } |
| 1358 | |
| 1359 | TEST(F32_VMULCADDC_C1__WASM_2X, qmax) { |
| 1360 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1361 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 1362 | VMulCAddCMicrokernelTester() |
| 1363 | .channel_tile(1) |
| 1364 | .channels(channels) |
| 1365 | .rows(rows) |
| 1366 | .qmax(128) |
| 1367 | .Test(xnn_f32_vmulcaddc_ukernel_c1__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1368 | } |
| 1369 | } |
| 1370 | } |
| 1371 | #endif // XNN_ARCH_WASM |
| 1372 | |
| 1373 | |
| 1374 | #if XNN_ARCH_WASM |
| 1375 | TEST(F32_VMULCADDC_C2__WASM_2X, channels_eq_2) { |
| 1376 | VMulCAddCMicrokernelTester() |
| 1377 | .channel_tile(2) |
| 1378 | .channels(2) |
| 1379 | .rows(2) |
| 1380 | .Test(xnn_f32_vmulcaddc_ukernel_c2__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1381 | } |
| 1382 | |
| 1383 | TEST(F32_VMULCADDC_C2__WASM_2X, channels_div_2) { |
| 1384 | for (size_t channels = 4; channels < 20; channels += 2) { |
| 1385 | VMulCAddCMicrokernelTester() |
| 1386 | .channel_tile(2) |
| 1387 | .channels(channels) |
| 1388 | .rows(2) |
| 1389 | .Test(xnn_f32_vmulcaddc_ukernel_c2__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1390 | } |
| 1391 | } |
| 1392 | |
| 1393 | TEST(F32_VMULCADDC_C2__WASM_2X, channels_lt_2) { |
| 1394 | for (size_t channels = 1; channels < 2; channels++) { |
| 1395 | VMulCAddCMicrokernelTester() |
| 1396 | .channel_tile(2) |
| 1397 | .channels(channels) |
| 1398 | .rows(2) |
| 1399 | .Test(xnn_f32_vmulcaddc_ukernel_c2__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1400 | } |
| 1401 | } |
| 1402 | |
| 1403 | TEST(F32_VMULCADDC_C2__WASM_2X, channels_gt_2) { |
| 1404 | for (size_t channels = 3; channels < 4; channels++) { |
| 1405 | VMulCAddCMicrokernelTester() |
| 1406 | .channel_tile(2) |
| 1407 | .channels(channels) |
| 1408 | .rows(2) |
| 1409 | .Test(xnn_f32_vmulcaddc_ukernel_c2__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1410 | } |
| 1411 | } |
| 1412 | |
| 1413 | TEST(F32_VMULCADDC_C2__WASM_2X, rows_lt_2) { |
| 1414 | for (size_t rows = 1; rows < 2; rows++) { |
| 1415 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1416 | VMulCAddCMicrokernelTester() |
| 1417 | .channel_tile(2) |
| 1418 | .channels(channels) |
| 1419 | .rows(rows) |
| 1420 | .Test(xnn_f32_vmulcaddc_ukernel_c2__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1421 | } |
| 1422 | } |
| 1423 | } |
| 1424 | |
| 1425 | TEST(F32_VMULCADDC_C2__WASM_2X, rows_div_2) { |
| 1426 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 1427 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1428 | VMulCAddCMicrokernelTester() |
| 1429 | .channel_tile(2) |
| 1430 | .channels(channels) |
| 1431 | .rows(rows) |
| 1432 | .Test(xnn_f32_vmulcaddc_ukernel_c2__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1433 | } |
| 1434 | } |
| 1435 | } |
| 1436 | |
| 1437 | TEST(F32_VMULCADDC_C2__WASM_2X, rows_gt_2) { |
| 1438 | for (size_t rows = 3; rows < 4; rows++) { |
| 1439 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1440 | VMulCAddCMicrokernelTester() |
| 1441 | .channel_tile(2) |
| 1442 | .channels(channels) |
| 1443 | .rows(rows) |
| 1444 | .Test(xnn_f32_vmulcaddc_ukernel_c2__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1445 | } |
| 1446 | } |
| 1447 | } |
| 1448 | |
| 1449 | TEST(F32_VMULCADDC_C2__WASM_2X, input_stride) { |
| 1450 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1451 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1452 | VMulCAddCMicrokernelTester() |
| 1453 | .channel_tile(2) |
| 1454 | .channels(channels) |
| 1455 | .rows(rows) |
| 1456 | .input_stride(13) |
| 1457 | .Test(xnn_f32_vmulcaddc_ukernel_c2__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1458 | } |
| 1459 | } |
| 1460 | } |
| 1461 | |
| 1462 | TEST(F32_VMULCADDC_C2__WASM_2X, output_stride) { |
| 1463 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1464 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1465 | VMulCAddCMicrokernelTester() |
| 1466 | .channel_tile(2) |
| 1467 | .channels(channels) |
| 1468 | .rows(rows) |
| 1469 | .output_stride(13) |
| 1470 | .Test(xnn_f32_vmulcaddc_ukernel_c2__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1471 | } |
| 1472 | } |
| 1473 | } |
| 1474 | |
| 1475 | TEST(F32_VMULCADDC_C2__WASM_2X, inplace) { |
| 1476 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1477 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1478 | VMulCAddCMicrokernelTester() |
| 1479 | .channel_tile(2) |
| 1480 | .channels(channels) |
| 1481 | .rows(rows) |
| 1482 | .inplace(true) |
| 1483 | .Test(xnn_f32_vmulcaddc_ukernel_c2__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1484 | } |
| 1485 | } |
| 1486 | } |
| 1487 | |
| 1488 | TEST(F32_VMULCADDC_C2__WASM_2X, qmin) { |
| 1489 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1490 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1491 | VMulCAddCMicrokernelTester() |
| 1492 | .channel_tile(2) |
| 1493 | .channels(channels) |
| 1494 | .rows(rows) |
| 1495 | .qmin(128) |
| 1496 | .Test(xnn_f32_vmulcaddc_ukernel_c2__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1497 | } |
| 1498 | } |
| 1499 | } |
| 1500 | |
| 1501 | TEST(F32_VMULCADDC_C2__WASM_2X, qmax) { |
| 1502 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1503 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1504 | VMulCAddCMicrokernelTester() |
| 1505 | .channel_tile(2) |
| 1506 | .channels(channels) |
| 1507 | .rows(rows) |
| 1508 | .qmax(128) |
| 1509 | .Test(xnn_f32_vmulcaddc_ukernel_c2__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1510 | } |
| 1511 | } |
| 1512 | } |
| 1513 | #endif // XNN_ARCH_WASM |
| 1514 | |
| 1515 | |
| 1516 | #if XNN_ARCH_WASM |
| 1517 | TEST(F32_VMULCADDC_C4__WASM_2X, channels_eq_4) { |
| 1518 | VMulCAddCMicrokernelTester() |
| 1519 | .channel_tile(4) |
| 1520 | .channels(4) |
| 1521 | .rows(2) |
| 1522 | .Test(xnn_f32_vmulcaddc_ukernel_c4__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1523 | } |
| 1524 | |
| 1525 | TEST(F32_VMULCADDC_C4__WASM_2X, channels_div_4) { |
| 1526 | for (size_t channels = 8; channels < 40; channels += 4) { |
| 1527 | VMulCAddCMicrokernelTester() |
| 1528 | .channel_tile(4) |
| 1529 | .channels(channels) |
| 1530 | .rows(2) |
| 1531 | .Test(xnn_f32_vmulcaddc_ukernel_c4__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1532 | } |
| 1533 | } |
| 1534 | |
| 1535 | TEST(F32_VMULCADDC_C4__WASM_2X, channels_lt_4) { |
| 1536 | for (size_t channels = 1; channels < 4; channels++) { |
| 1537 | VMulCAddCMicrokernelTester() |
| 1538 | .channel_tile(4) |
| 1539 | .channels(channels) |
| 1540 | .rows(2) |
| 1541 | .Test(xnn_f32_vmulcaddc_ukernel_c4__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1542 | } |
| 1543 | } |
| 1544 | |
| 1545 | TEST(F32_VMULCADDC_C4__WASM_2X, channels_gt_4) { |
| 1546 | for (size_t channels = 5; channels < 8; channels++) { |
| 1547 | VMulCAddCMicrokernelTester() |
| 1548 | .channel_tile(4) |
| 1549 | .channels(channels) |
| 1550 | .rows(2) |
| 1551 | .Test(xnn_f32_vmulcaddc_ukernel_c4__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1552 | } |
| 1553 | } |
| 1554 | |
| 1555 | TEST(F32_VMULCADDC_C4__WASM_2X, rows_lt_2) { |
| 1556 | for (size_t rows = 1; rows < 2; rows++) { |
| 1557 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1558 | VMulCAddCMicrokernelTester() |
| 1559 | .channel_tile(4) |
| 1560 | .channels(channels) |
| 1561 | .rows(rows) |
| 1562 | .Test(xnn_f32_vmulcaddc_ukernel_c4__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1563 | } |
| 1564 | } |
| 1565 | } |
| 1566 | |
| 1567 | TEST(F32_VMULCADDC_C4__WASM_2X, rows_div_2) { |
| 1568 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 1569 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1570 | VMulCAddCMicrokernelTester() |
| 1571 | .channel_tile(4) |
| 1572 | .channels(channels) |
| 1573 | .rows(rows) |
| 1574 | .Test(xnn_f32_vmulcaddc_ukernel_c4__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1575 | } |
| 1576 | } |
| 1577 | } |
| 1578 | |
| 1579 | TEST(F32_VMULCADDC_C4__WASM_2X, rows_gt_2) { |
| 1580 | for (size_t rows = 3; rows < 4; rows++) { |
| 1581 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1582 | VMulCAddCMicrokernelTester() |
| 1583 | .channel_tile(4) |
| 1584 | .channels(channels) |
| 1585 | .rows(rows) |
| 1586 | .Test(xnn_f32_vmulcaddc_ukernel_c4__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1587 | } |
| 1588 | } |
| 1589 | } |
| 1590 | |
| 1591 | TEST(F32_VMULCADDC_C4__WASM_2X, input_stride) { |
| 1592 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1593 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1594 | VMulCAddCMicrokernelTester() |
| 1595 | .channel_tile(4) |
| 1596 | .channels(channels) |
| 1597 | .rows(rows) |
| 1598 | .input_stride(23) |
| 1599 | .Test(xnn_f32_vmulcaddc_ukernel_c4__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1600 | } |
| 1601 | } |
| 1602 | } |
| 1603 | |
| 1604 | TEST(F32_VMULCADDC_C4__WASM_2X, output_stride) { |
| 1605 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1606 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1607 | VMulCAddCMicrokernelTester() |
| 1608 | .channel_tile(4) |
| 1609 | .channels(channels) |
| 1610 | .rows(rows) |
| 1611 | .output_stride(23) |
| 1612 | .Test(xnn_f32_vmulcaddc_ukernel_c4__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1613 | } |
| 1614 | } |
| 1615 | } |
| 1616 | |
| 1617 | TEST(F32_VMULCADDC_C4__WASM_2X, inplace) { |
| 1618 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1619 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1620 | VMulCAddCMicrokernelTester() |
| 1621 | .channel_tile(4) |
| 1622 | .channels(channels) |
| 1623 | .rows(rows) |
| 1624 | .inplace(true) |
| 1625 | .Test(xnn_f32_vmulcaddc_ukernel_c4__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1626 | } |
| 1627 | } |
| 1628 | } |
| 1629 | |
| 1630 | TEST(F32_VMULCADDC_C4__WASM_2X, qmin) { |
| 1631 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1632 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1633 | VMulCAddCMicrokernelTester() |
| 1634 | .channel_tile(4) |
| 1635 | .channels(channels) |
| 1636 | .rows(rows) |
| 1637 | .qmin(128) |
| 1638 | .Test(xnn_f32_vmulcaddc_ukernel_c4__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1639 | } |
| 1640 | } |
| 1641 | } |
| 1642 | |
| 1643 | TEST(F32_VMULCADDC_C4__WASM_2X, qmax) { |
| 1644 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1645 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1646 | VMulCAddCMicrokernelTester() |
| 1647 | .channel_tile(4) |
| 1648 | .channels(channels) |
| 1649 | .rows(rows) |
| 1650 | .qmax(128) |
| 1651 | .Test(xnn_f32_vmulcaddc_ukernel_c4__wasm_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1652 | } |
| 1653 | } |
| 1654 | } |
| 1655 | #endif // XNN_ARCH_WASM |
| 1656 | |
| 1657 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1658 | TEST(F32_VMULCADDC_C1__SCALAR_2X, channels_eq_1) { |
| 1659 | VMulCAddCMicrokernelTester() |
| 1660 | .channel_tile(1) |
| 1661 | .channels(1) |
| 1662 | .rows(2) |
| 1663 | .Test(xnn_f32_vmulcaddc_ukernel_c1__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1664 | } |
| 1665 | |
| 1666 | TEST(F32_VMULCADDC_C1__SCALAR_2X, channels_gt_1) { |
| 1667 | for (size_t channels = 2; channels < 10; channels++) { |
| 1668 | VMulCAddCMicrokernelTester() |
| 1669 | .channel_tile(1) |
| 1670 | .channels(channels) |
| 1671 | .rows(2) |
| 1672 | .Test(xnn_f32_vmulcaddc_ukernel_c1__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1673 | } |
| 1674 | } |
| 1675 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1676 | TEST(F32_VMULCADDC_C1__SCALAR_2X, rows_lt_2) { |
| 1677 | for (size_t rows = 1; rows < 2; rows++) { |
| 1678 | for (size_t channels = 1; channels <= 5; channels += 1) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1679 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1680 | .channel_tile(1) |
| 1681 | .channels(channels) |
| 1682 | .rows(rows) |
| 1683 | .Test(xnn_f32_vmulcaddc_ukernel_c1__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1684 | } |
| 1685 | } |
| 1686 | } |
| 1687 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1688 | TEST(F32_VMULCADDC_C1__SCALAR_2X, rows_div_2) { |
| 1689 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 1690 | for (size_t channels = 1; channels <= 5; channels += 1) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1691 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1692 | .channel_tile(1) |
| 1693 | .channels(channels) |
| 1694 | .rows(rows) |
| 1695 | .Test(xnn_f32_vmulcaddc_ukernel_c1__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1696 | } |
| 1697 | } |
| 1698 | } |
| 1699 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1700 | TEST(F32_VMULCADDC_C1__SCALAR_2X, rows_gt_2) { |
| 1701 | for (size_t rows = 3; rows < 4; rows++) { |
| 1702 | for (size_t channels = 1; channels <= 5; channels += 1) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1703 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1704 | .channel_tile(1) |
| 1705 | .channels(channels) |
| 1706 | .rows(rows) |
| 1707 | .Test(xnn_f32_vmulcaddc_ukernel_c1__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1708 | } |
| 1709 | } |
| 1710 | } |
| 1711 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1712 | TEST(F32_VMULCADDC_C1__SCALAR_2X, input_stride) { |
| 1713 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1714 | for (size_t channels = 1; channels <= 5; channels += 1) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1715 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1716 | .channel_tile(1) |
| 1717 | .channels(channels) |
| 1718 | .rows(rows) |
| 1719 | .input_stride(7) |
| 1720 | .Test(xnn_f32_vmulcaddc_ukernel_c1__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1721 | } |
| 1722 | } |
| 1723 | } |
| 1724 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1725 | TEST(F32_VMULCADDC_C1__SCALAR_2X, output_stride) { |
| 1726 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1727 | for (size_t channels = 1; channels <= 5; channels += 1) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1728 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1729 | .channel_tile(1) |
| 1730 | .channels(channels) |
| 1731 | .rows(rows) |
| 1732 | .output_stride(7) |
| 1733 | .Test(xnn_f32_vmulcaddc_ukernel_c1__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1734 | } |
| 1735 | } |
| 1736 | } |
| 1737 | |
| 1738 | TEST(F32_VMULCADDC_C1__SCALAR_2X, inplace) { |
| 1739 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1740 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 1741 | VMulCAddCMicrokernelTester() |
| 1742 | .channel_tile(1) |
| 1743 | .channels(channels) |
| 1744 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1745 | .inplace(true) |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1746 | .Test(xnn_f32_vmulcaddc_ukernel_c1__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1747 | } |
| 1748 | } |
| 1749 | } |
| 1750 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1751 | TEST(F32_VMULCADDC_C1__SCALAR_2X, qmin) { |
| 1752 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1753 | for (size_t channels = 1; channels <= 5; channels += 1) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1754 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1755 | .channel_tile(1) |
| 1756 | .channels(channels) |
| 1757 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1758 | .qmin(128) |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1759 | .Test(xnn_f32_vmulcaddc_ukernel_c1__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1760 | } |
| 1761 | } |
| 1762 | } |
| 1763 | |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1764 | TEST(F32_VMULCADDC_C1__SCALAR_2X, qmax) { |
| 1765 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1766 | for (size_t channels = 1; channels <= 5; channels += 1) { |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1767 | VMulCAddCMicrokernelTester() |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1768 | .channel_tile(1) |
| 1769 | .channels(channels) |
| 1770 | .rows(rows) |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1771 | .qmax(128) |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1772 | .Test(xnn_f32_vmulcaddc_ukernel_c1__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1773 | } |
| 1774 | } |
| 1775 | } |
| 1776 | |
| 1777 | TEST(F32_VMULCADDC_C2__SCALAR_2X, channels_eq_2) { |
| 1778 | VMulCAddCMicrokernelTester() |
| 1779 | .channel_tile(2) |
| 1780 | .channels(2) |
| 1781 | .rows(2) |
| 1782 | .Test(xnn_f32_vmulcaddc_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1783 | } |
| 1784 | |
| 1785 | TEST(F32_VMULCADDC_C2__SCALAR_2X, channels_div_2) { |
| 1786 | for (size_t channels = 4; channels < 20; channels += 2) { |
| 1787 | VMulCAddCMicrokernelTester() |
| 1788 | .channel_tile(2) |
| 1789 | .channels(channels) |
| 1790 | .rows(2) |
| 1791 | .Test(xnn_f32_vmulcaddc_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1792 | } |
| 1793 | } |
| 1794 | |
| 1795 | TEST(F32_VMULCADDC_C2__SCALAR_2X, channels_lt_2) { |
| 1796 | for (size_t channels = 1; channels < 2; channels++) { |
| 1797 | VMulCAddCMicrokernelTester() |
| 1798 | .channel_tile(2) |
| 1799 | .channels(channels) |
| 1800 | .rows(2) |
| 1801 | .Test(xnn_f32_vmulcaddc_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1802 | } |
| 1803 | } |
| 1804 | |
| 1805 | TEST(F32_VMULCADDC_C2__SCALAR_2X, channels_gt_2) { |
| 1806 | for (size_t channels = 3; channels < 4; channels++) { |
| 1807 | VMulCAddCMicrokernelTester() |
| 1808 | .channel_tile(2) |
| 1809 | .channels(channels) |
| 1810 | .rows(2) |
| 1811 | .Test(xnn_f32_vmulcaddc_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1812 | } |
| 1813 | } |
| 1814 | |
| 1815 | TEST(F32_VMULCADDC_C2__SCALAR_2X, rows_lt_2) { |
| 1816 | for (size_t rows = 1; rows < 2; rows++) { |
| 1817 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1818 | VMulCAddCMicrokernelTester() |
| 1819 | .channel_tile(2) |
| 1820 | .channels(channels) |
| 1821 | .rows(rows) |
| 1822 | .Test(xnn_f32_vmulcaddc_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1823 | } |
| 1824 | } |
| 1825 | } |
| 1826 | |
| 1827 | TEST(F32_VMULCADDC_C2__SCALAR_2X, rows_div_2) { |
| 1828 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 1829 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1830 | VMulCAddCMicrokernelTester() |
| 1831 | .channel_tile(2) |
| 1832 | .channels(channels) |
| 1833 | .rows(rows) |
| 1834 | .Test(xnn_f32_vmulcaddc_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1835 | } |
| 1836 | } |
| 1837 | } |
| 1838 | |
| 1839 | TEST(F32_VMULCADDC_C2__SCALAR_2X, rows_gt_2) { |
| 1840 | for (size_t rows = 3; rows < 4; rows++) { |
| 1841 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1842 | VMulCAddCMicrokernelTester() |
| 1843 | .channel_tile(2) |
| 1844 | .channels(channels) |
| 1845 | .rows(rows) |
| 1846 | .Test(xnn_f32_vmulcaddc_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1847 | } |
| 1848 | } |
| 1849 | } |
| 1850 | |
| 1851 | TEST(F32_VMULCADDC_C2__SCALAR_2X, input_stride) { |
| 1852 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1853 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1854 | VMulCAddCMicrokernelTester() |
| 1855 | .channel_tile(2) |
| 1856 | .channels(channels) |
| 1857 | .rows(rows) |
| 1858 | .input_stride(13) |
| 1859 | .Test(xnn_f32_vmulcaddc_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1860 | } |
| 1861 | } |
| 1862 | } |
| 1863 | |
| 1864 | TEST(F32_VMULCADDC_C2__SCALAR_2X, output_stride) { |
| 1865 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1866 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1867 | VMulCAddCMicrokernelTester() |
| 1868 | .channel_tile(2) |
| 1869 | .channels(channels) |
| 1870 | .rows(rows) |
| 1871 | .output_stride(13) |
| 1872 | .Test(xnn_f32_vmulcaddc_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1873 | } |
| 1874 | } |
| 1875 | } |
| 1876 | |
| 1877 | TEST(F32_VMULCADDC_C2__SCALAR_2X, inplace) { |
| 1878 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1879 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1880 | VMulCAddCMicrokernelTester() |
| 1881 | .channel_tile(2) |
| 1882 | .channels(channels) |
| 1883 | .rows(rows) |
| 1884 | .inplace(true) |
| 1885 | .Test(xnn_f32_vmulcaddc_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1886 | } |
| 1887 | } |
| 1888 | } |
| 1889 | |
| 1890 | TEST(F32_VMULCADDC_C2__SCALAR_2X, qmin) { |
| 1891 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1892 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1893 | VMulCAddCMicrokernelTester() |
| 1894 | .channel_tile(2) |
| 1895 | .channels(channels) |
| 1896 | .rows(rows) |
| 1897 | .qmin(128) |
| 1898 | .Test(xnn_f32_vmulcaddc_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1899 | } |
| 1900 | } |
| 1901 | } |
| 1902 | |
| 1903 | TEST(F32_VMULCADDC_C2__SCALAR_2X, qmax) { |
| 1904 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1905 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 1906 | VMulCAddCMicrokernelTester() |
| 1907 | .channel_tile(2) |
| 1908 | .channels(channels) |
| 1909 | .rows(rows) |
| 1910 | .qmax(128) |
| 1911 | .Test(xnn_f32_vmulcaddc_ukernel_c2__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1912 | } |
| 1913 | } |
| 1914 | } |
| 1915 | |
| 1916 | TEST(F32_VMULCADDC_C4__SCALAR_2X, channels_eq_4) { |
| 1917 | VMulCAddCMicrokernelTester() |
| 1918 | .channel_tile(4) |
| 1919 | .channels(4) |
| 1920 | .rows(2) |
| 1921 | .Test(xnn_f32_vmulcaddc_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1922 | } |
| 1923 | |
| 1924 | TEST(F32_VMULCADDC_C4__SCALAR_2X, channels_div_4) { |
| 1925 | for (size_t channels = 8; channels < 40; channels += 4) { |
| 1926 | VMulCAddCMicrokernelTester() |
| 1927 | .channel_tile(4) |
| 1928 | .channels(channels) |
| 1929 | .rows(2) |
| 1930 | .Test(xnn_f32_vmulcaddc_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1931 | } |
| 1932 | } |
| 1933 | |
| 1934 | TEST(F32_VMULCADDC_C4__SCALAR_2X, channels_lt_4) { |
| 1935 | for (size_t channels = 1; channels < 4; channels++) { |
| 1936 | VMulCAddCMicrokernelTester() |
| 1937 | .channel_tile(4) |
| 1938 | .channels(channels) |
| 1939 | .rows(2) |
| 1940 | .Test(xnn_f32_vmulcaddc_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1941 | } |
| 1942 | } |
| 1943 | |
| 1944 | TEST(F32_VMULCADDC_C4__SCALAR_2X, channels_gt_4) { |
| 1945 | for (size_t channels = 5; channels < 8; channels++) { |
| 1946 | VMulCAddCMicrokernelTester() |
| 1947 | .channel_tile(4) |
| 1948 | .channels(channels) |
| 1949 | .rows(2) |
| 1950 | .Test(xnn_f32_vmulcaddc_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1951 | } |
| 1952 | } |
| 1953 | |
| 1954 | TEST(F32_VMULCADDC_C4__SCALAR_2X, rows_lt_2) { |
| 1955 | for (size_t rows = 1; rows < 2; rows++) { |
| 1956 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1957 | VMulCAddCMicrokernelTester() |
| 1958 | .channel_tile(4) |
| 1959 | .channels(channels) |
| 1960 | .rows(rows) |
| 1961 | .Test(xnn_f32_vmulcaddc_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1962 | } |
| 1963 | } |
| 1964 | } |
| 1965 | |
| 1966 | TEST(F32_VMULCADDC_C4__SCALAR_2X, rows_div_2) { |
| 1967 | for (size_t rows = 4; rows <= 8; rows += 2) { |
| 1968 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1969 | VMulCAddCMicrokernelTester() |
| 1970 | .channel_tile(4) |
| 1971 | .channels(channels) |
| 1972 | .rows(rows) |
| 1973 | .Test(xnn_f32_vmulcaddc_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1974 | } |
| 1975 | } |
| 1976 | } |
| 1977 | |
| 1978 | TEST(F32_VMULCADDC_C4__SCALAR_2X, rows_gt_2) { |
| 1979 | for (size_t rows = 3; rows < 4; rows++) { |
| 1980 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1981 | VMulCAddCMicrokernelTester() |
| 1982 | .channel_tile(4) |
| 1983 | .channels(channels) |
| 1984 | .rows(rows) |
| 1985 | .Test(xnn_f32_vmulcaddc_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1986 | } |
| 1987 | } |
| 1988 | } |
| 1989 | |
| 1990 | TEST(F32_VMULCADDC_C4__SCALAR_2X, input_stride) { |
| 1991 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 1992 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1993 | VMulCAddCMicrokernelTester() |
| 1994 | .channel_tile(4) |
| 1995 | .channels(channels) |
| 1996 | .rows(rows) |
| 1997 | .input_stride(23) |
| 1998 | .Test(xnn_f32_vmulcaddc_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 1999 | } |
| 2000 | } |
| 2001 | } |
| 2002 | |
| 2003 | TEST(F32_VMULCADDC_C4__SCALAR_2X, output_stride) { |
| 2004 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 2005 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2006 | VMulCAddCMicrokernelTester() |
| 2007 | .channel_tile(4) |
| 2008 | .channels(channels) |
| 2009 | .rows(rows) |
| 2010 | .output_stride(23) |
| 2011 | .Test(xnn_f32_vmulcaddc_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 2012 | } |
| 2013 | } |
| 2014 | } |
| 2015 | |
| 2016 | TEST(F32_VMULCADDC_C4__SCALAR_2X, inplace) { |
| 2017 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 2018 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2019 | VMulCAddCMicrokernelTester() |
| 2020 | .channel_tile(4) |
| 2021 | .channels(channels) |
| 2022 | .rows(rows) |
| 2023 | .inplace(true) |
| 2024 | .Test(xnn_f32_vmulcaddc_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 2025 | } |
| 2026 | } |
| 2027 | } |
| 2028 | |
| 2029 | TEST(F32_VMULCADDC_C4__SCALAR_2X, qmin) { |
| 2030 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 2031 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2032 | VMulCAddCMicrokernelTester() |
| 2033 | .channel_tile(4) |
| 2034 | .channels(channels) |
| 2035 | .rows(rows) |
| 2036 | .qmin(128) |
| 2037 | .Test(xnn_f32_vmulcaddc_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
| 2038 | } |
| 2039 | } |
| 2040 | } |
| 2041 | |
| 2042 | TEST(F32_VMULCADDC_C4__SCALAR_2X, qmax) { |
| 2043 | for (size_t rows = 1; rows <= 6; rows += 1) { |
| 2044 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2045 | VMulCAddCMicrokernelTester() |
| 2046 | .channel_tile(4) |
| 2047 | .channels(channels) |
| 2048 | .rows(rows) |
| 2049 | .qmax(128) |
| 2050 | .Test(xnn_f32_vmulcaddc_ukernel_c4__scalar_2x, VMulCAddCMicrokernelTester::Variant::Scalar); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 2051 | } |
| 2052 | } |
| 2053 | } |