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Marat Dukhan6f8d4d32019-10-25 17:07:09 -07001// Copyright 2019 Google LLC
2//
3// This source code is licensed under the BSD-style license found in the
4// LICENSE file in the root directory of this source tree.
Marat Dukhan4c4eb002019-12-08 21:27:49 -08005//
6// Auto-generated file. Do not edit!
7// Specification: test/f32-raddextexp.yaml
8// Generator: tools/generate-raddextexp-test.py
9
Marat Dukhan6f8d4d32019-10-25 17:07:09 -070010
11#include <gtest/gtest.h>
12
13#include <xnnpack/common.h>
14#include <xnnpack/isa-checks.h>
15
16#include <xnnpack/raddextexp.h>
17#include "raddextexp-microkernel-tester.h"
18
19
20#if XNN_ARCH_X86 || XNN_ARCH_X86_64
Marat Dukhan4c4eb002019-12-08 21:27:49 -080021 TEST(F32_RADDEXTEXP__AVX2_P5_X64, elements_eq_64) {
22 TEST_REQUIRES_X86_AVX2;
Marat Dukhan6f8d4d32019-10-25 17:07:09 -070023 RAddExtExpMicrokernelTester()
Marat Dukhan4c4eb002019-12-08 21:27:49 -080024 .elements(64)
25 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x64);
Marat Dukhan6f8d4d32019-10-25 17:07:09 -070026 }
27
Marat Dukhan4c4eb002019-12-08 21:27:49 -080028 TEST(F32_RADDEXTEXP__AVX2_P5_X64, elements_div_64) {
29 TEST_REQUIRES_X86_AVX2;
30 for (size_t elements = 128; elements < 640; elements += 64) {
Marat Dukhan6f8d4d32019-10-25 17:07:09 -070031 RAddExtExpMicrokernelTester()
Marat Dukhan4c4eb002019-12-08 21:27:49 -080032 .elements(elements)
33 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x64);
Marat Dukhan6f8d4d32019-10-25 17:07:09 -070034 }
35 }
36
Marat Dukhan4c4eb002019-12-08 21:27:49 -080037 TEST(F32_RADDEXTEXP__AVX2_P5_X64, elements_lt_64) {
38 TEST_REQUIRES_X86_AVX2;
39 for (size_t elements = 1; elements < 64; elements++) {
Marat Dukhan6f8d4d32019-10-25 17:07:09 -070040 RAddExtExpMicrokernelTester()
Marat Dukhan4c4eb002019-12-08 21:27:49 -080041 .elements(elements)
42 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x64);
43 }
44 }
45
46 TEST(F32_RADDEXTEXP__AVX2_P5_X64, elements_gt_64) {
47 TEST_REQUIRES_X86_AVX2;
48 for (size_t elements = 65; elements < 128; elements++) {
49 RAddExtExpMicrokernelTester()
50 .elements(elements)
51 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x64);
Marat Dukhan6f8d4d32019-10-25 17:07:09 -070052 }
53 }
54#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
55
Marat Dukhan6f8d4d32019-10-25 17:07:09 -070056
Marat Dukhan4c4eb002019-12-08 21:27:49 -080057#if XNN_ARCH_X86 || XNN_ARCH_X86_64
58 TEST(F32_RADDEXTEXP__AVX2_P5_X64_ACC2, elements_eq_64) {
Marat Dukhan6f8d4d32019-10-25 17:07:09 -070059 TEST_REQUIRES_X86_AVX2;
60 RAddExtExpMicrokernelTester()
Marat Dukhan4c4eb002019-12-08 21:27:49 -080061 .elements(64)
62 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x64_acc2);
Marat Dukhan6f8d4d32019-10-25 17:07:09 -070063 }
64
Marat Dukhan4c4eb002019-12-08 21:27:49 -080065 TEST(F32_RADDEXTEXP__AVX2_P5_X64_ACC2, elements_div_64) {
Marat Dukhan6f8d4d32019-10-25 17:07:09 -070066 TEST_REQUIRES_X86_AVX2;
Marat Dukhan4c4eb002019-12-08 21:27:49 -080067 for (size_t elements = 128; elements < 640; elements += 64) {
Marat Dukhan6f8d4d32019-10-25 17:07:09 -070068 RAddExtExpMicrokernelTester()
Marat Dukhan4c4eb002019-12-08 21:27:49 -080069 .elements(elements)
70 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x64_acc2);
Marat Dukhan6f8d4d32019-10-25 17:07:09 -070071 }
72 }
73
Marat Dukhan4c4eb002019-12-08 21:27:49 -080074 TEST(F32_RADDEXTEXP__AVX2_P5_X64_ACC2, elements_lt_64) {
Marat Dukhan6f8d4d32019-10-25 17:07:09 -070075 TEST_REQUIRES_X86_AVX2;
Marat Dukhan4c4eb002019-12-08 21:27:49 -080076 for (size_t elements = 1; elements < 64; elements++) {
Marat Dukhan6f8d4d32019-10-25 17:07:09 -070077 RAddExtExpMicrokernelTester()
Marat Dukhan4c4eb002019-12-08 21:27:49 -080078 .elements(elements)
79 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x64_acc2);
80 }
81 }
82
83 TEST(F32_RADDEXTEXP__AVX2_P5_X64_ACC2, elements_gt_64) {
84 TEST_REQUIRES_X86_AVX2;
85 for (size_t elements = 65; elements < 128; elements++) {
86 RAddExtExpMicrokernelTester()
87 .elements(elements)
88 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x64_acc2);
89 }
90 }
91#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
92
93
94#if XNN_ARCH_X86 || XNN_ARCH_X86_64
95 TEST(F32_RADDEXTEXP__AVX2_P5_X64_ACC4, elements_eq_64) {
96 TEST_REQUIRES_X86_AVX2;
97 RAddExtExpMicrokernelTester()
98 .elements(64)
99 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x64_acc4);
100 }
101
102 TEST(F32_RADDEXTEXP__AVX2_P5_X64_ACC4, elements_div_64) {
103 TEST_REQUIRES_X86_AVX2;
104 for (size_t elements = 128; elements < 640; elements += 64) {
105 RAddExtExpMicrokernelTester()
106 .elements(elements)
107 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x64_acc4);
108 }
109 }
110
111 TEST(F32_RADDEXTEXP__AVX2_P5_X64_ACC4, elements_lt_64) {
112 TEST_REQUIRES_X86_AVX2;
113 for (size_t elements = 1; elements < 64; elements++) {
114 RAddExtExpMicrokernelTester()
115 .elements(elements)
116 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x64_acc4);
117 }
118 }
119
120 TEST(F32_RADDEXTEXP__AVX2_P5_X64_ACC4, elements_gt_64) {
121 TEST_REQUIRES_X86_AVX2;
122 for (size_t elements = 65; elements < 128; elements++) {
123 RAddExtExpMicrokernelTester()
124 .elements(elements)
125 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x64_acc4);
126 }
127 }
128#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
129
130
131#if XNN_ARCH_X86 || XNN_ARCH_X86_64
132 TEST(F32_RADDEXTEXP__AVX2_P5_X72, elements_eq_72) {
133 TEST_REQUIRES_X86_AVX2;
134 RAddExtExpMicrokernelTester()
135 .elements(72)
136 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x72);
137 }
138
139 TEST(F32_RADDEXTEXP__AVX2_P5_X72, elements_div_72) {
140 TEST_REQUIRES_X86_AVX2;
141 for (size_t elements = 144; elements < 720; elements += 72) {
142 RAddExtExpMicrokernelTester()
143 .elements(elements)
144 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x72);
145 }
146 }
147
148 TEST(F32_RADDEXTEXP__AVX2_P5_X72, elements_lt_72) {
149 TEST_REQUIRES_X86_AVX2;
150 for (size_t elements = 1; elements < 72; elements++) {
151 RAddExtExpMicrokernelTester()
152 .elements(elements)
153 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x72);
154 }
155 }
156
157 TEST(F32_RADDEXTEXP__AVX2_P5_X72, elements_gt_72) {
158 TEST_REQUIRES_X86_AVX2;
159 for (size_t elements = 73; elements < 144; elements++) {
160 RAddExtExpMicrokernelTester()
161 .elements(elements)
162 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x72);
163 }
164 }
165#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
166
167
168#if XNN_ARCH_X86 || XNN_ARCH_X86_64
169 TEST(F32_RADDEXTEXP__AVX2_P5_X72_ACC3, elements_eq_72) {
170 TEST_REQUIRES_X86_AVX2;
171 RAddExtExpMicrokernelTester()
172 .elements(72)
173 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x72_acc3);
174 }
175
176 TEST(F32_RADDEXTEXP__AVX2_P5_X72_ACC3, elements_div_72) {
177 TEST_REQUIRES_X86_AVX2;
178 for (size_t elements = 144; elements < 720; elements += 72) {
179 RAddExtExpMicrokernelTester()
180 .elements(elements)
181 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x72_acc3);
182 }
183 }
184
185 TEST(F32_RADDEXTEXP__AVX2_P5_X72_ACC3, elements_lt_72) {
186 TEST_REQUIRES_X86_AVX2;
187 for (size_t elements = 1; elements < 72; elements++) {
188 RAddExtExpMicrokernelTester()
189 .elements(elements)
190 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x72_acc3);
191 }
192 }
193
194 TEST(F32_RADDEXTEXP__AVX2_P5_X72_ACC3, elements_gt_72) {
195 TEST_REQUIRES_X86_AVX2;
196 for (size_t elements = 73; elements < 144; elements++) {
197 RAddExtExpMicrokernelTester()
198 .elements(elements)
199 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x72_acc3);
200 }
201 }
202#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
203
204
205#if XNN_ARCH_X86 || XNN_ARCH_X86_64
206 TEST(F32_RADDEXTEXP__AVX2_P5_X80, elements_eq_80) {
207 TEST_REQUIRES_X86_AVX2;
208 RAddExtExpMicrokernelTester()
209 .elements(80)
210 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x80);
211 }
212
213 TEST(F32_RADDEXTEXP__AVX2_P5_X80, elements_div_80) {
214 TEST_REQUIRES_X86_AVX2;
215 for (size_t elements = 160; elements < 800; elements += 80) {
216 RAddExtExpMicrokernelTester()
217 .elements(elements)
218 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x80);
219 }
220 }
221
222 TEST(F32_RADDEXTEXP__AVX2_P5_X80, elements_lt_80) {
223 TEST_REQUIRES_X86_AVX2;
224 for (size_t elements = 1; elements < 80; elements++) {
225 RAddExtExpMicrokernelTester()
226 .elements(elements)
227 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x80);
228 }
229 }
230
231 TEST(F32_RADDEXTEXP__AVX2_P5_X80, elements_gt_80) {
232 TEST_REQUIRES_X86_AVX2;
233 for (size_t elements = 81; elements < 160; elements++) {
234 RAddExtExpMicrokernelTester()
235 .elements(elements)
236 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x80);
237 }
238 }
239#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
240
241
242#if XNN_ARCH_X86 || XNN_ARCH_X86_64
243 TEST(F32_RADDEXTEXP__AVX2_P5_X80_ACC2, elements_eq_80) {
244 TEST_REQUIRES_X86_AVX2;
245 RAddExtExpMicrokernelTester()
246 .elements(80)
247 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x80_acc2);
248 }
249
250 TEST(F32_RADDEXTEXP__AVX2_P5_X80_ACC2, elements_div_80) {
251 TEST_REQUIRES_X86_AVX2;
252 for (size_t elements = 160; elements < 800; elements += 80) {
253 RAddExtExpMicrokernelTester()
254 .elements(elements)
255 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x80_acc2);
256 }
257 }
258
259 TEST(F32_RADDEXTEXP__AVX2_P5_X80_ACC2, elements_lt_80) {
260 TEST_REQUIRES_X86_AVX2;
261 for (size_t elements = 1; elements < 80; elements++) {
262 RAddExtExpMicrokernelTester()
263 .elements(elements)
264 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x80_acc2);
265 }
266 }
267
268 TEST(F32_RADDEXTEXP__AVX2_P5_X80_ACC2, elements_gt_80) {
269 TEST_REQUIRES_X86_AVX2;
270 for (size_t elements = 81; elements < 160; elements++) {
271 RAddExtExpMicrokernelTester()
272 .elements(elements)
273 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x80_acc2);
274 }
275 }
276#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
277
278
279#if XNN_ARCH_X86 || XNN_ARCH_X86_64
280 TEST(F32_RADDEXTEXP__AVX2_P5_X80_ACC5, elements_eq_80) {
281 TEST_REQUIRES_X86_AVX2;
282 RAddExtExpMicrokernelTester()
283 .elements(80)
284 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x80_acc5);
285 }
286
287 TEST(F32_RADDEXTEXP__AVX2_P5_X80_ACC5, elements_div_80) {
288 TEST_REQUIRES_X86_AVX2;
289 for (size_t elements = 160; elements < 800; elements += 80) {
290 RAddExtExpMicrokernelTester()
291 .elements(elements)
292 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x80_acc5);
293 }
294 }
295
296 TEST(F32_RADDEXTEXP__AVX2_P5_X80_ACC5, elements_lt_80) {
297 TEST_REQUIRES_X86_AVX2;
298 for (size_t elements = 1; elements < 80; elements++) {
299 RAddExtExpMicrokernelTester()
300 .elements(elements)
301 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x80_acc5);
302 }
303 }
304
305 TEST(F32_RADDEXTEXP__AVX2_P5_X80_ACC5, elements_gt_80) {
306 TEST_REQUIRES_X86_AVX2;
307 for (size_t elements = 81; elements < 160; elements++) {
308 RAddExtExpMicrokernelTester()
309 .elements(elements)
310 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x80_acc5);
311 }
312 }
313#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
314
315
316#if XNN_ARCH_X86 || XNN_ARCH_X86_64
317 TEST(F32_RADDEXTEXP__AVX2_P5_X96, elements_eq_96) {
318 TEST_REQUIRES_X86_AVX2;
319 RAddExtExpMicrokernelTester()
320 .elements(96)
321 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x96);
322 }
323
324 TEST(F32_RADDEXTEXP__AVX2_P5_X96, elements_div_96) {
325 TEST_REQUIRES_X86_AVX2;
326 for (size_t elements = 192; elements < 960; elements += 96) {
327 RAddExtExpMicrokernelTester()
328 .elements(elements)
329 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x96);
330 }
331 }
332
333 TEST(F32_RADDEXTEXP__AVX2_P5_X96, elements_lt_96) {
334 TEST_REQUIRES_X86_AVX2;
335 for (size_t elements = 1; elements < 96; elements++) {
336 RAddExtExpMicrokernelTester()
337 .elements(elements)
338 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x96);
339 }
340 }
341
342 TEST(F32_RADDEXTEXP__AVX2_P5_X96, elements_gt_96) {
343 TEST_REQUIRES_X86_AVX2;
344 for (size_t elements = 97; elements < 192; elements++) {
345 RAddExtExpMicrokernelTester()
346 .elements(elements)
347 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x96);
348 }
349 }
350#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
351
352
353#if XNN_ARCH_X86 || XNN_ARCH_X86_64
354 TEST(F32_RADDEXTEXP__AVX2_P5_X96_ACC2, elements_eq_96) {
355 TEST_REQUIRES_X86_AVX2;
356 RAddExtExpMicrokernelTester()
357 .elements(96)
358 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x96_acc2);
359 }
360
361 TEST(F32_RADDEXTEXP__AVX2_P5_X96_ACC2, elements_div_96) {
362 TEST_REQUIRES_X86_AVX2;
363 for (size_t elements = 192; elements < 960; elements += 96) {
364 RAddExtExpMicrokernelTester()
365 .elements(elements)
366 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x96_acc2);
367 }
368 }
369
370 TEST(F32_RADDEXTEXP__AVX2_P5_X96_ACC2, elements_lt_96) {
371 TEST_REQUIRES_X86_AVX2;
372 for (size_t elements = 1; elements < 96; elements++) {
373 RAddExtExpMicrokernelTester()
374 .elements(elements)
375 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x96_acc2);
376 }
377 }
378
379 TEST(F32_RADDEXTEXP__AVX2_P5_X96_ACC2, elements_gt_96) {
380 TEST_REQUIRES_X86_AVX2;
381 for (size_t elements = 97; elements < 192; elements++) {
382 RAddExtExpMicrokernelTester()
383 .elements(elements)
384 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x96_acc2);
385 }
386 }
387#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
388
389
390#if XNN_ARCH_X86 || XNN_ARCH_X86_64
391 TEST(F32_RADDEXTEXP__AVX2_P5_X96_ACC3, elements_eq_96) {
392 TEST_REQUIRES_X86_AVX2;
393 RAddExtExpMicrokernelTester()
394 .elements(96)
395 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x96_acc3);
396 }
397
398 TEST(F32_RADDEXTEXP__AVX2_P5_X96_ACC3, elements_div_96) {
399 TEST_REQUIRES_X86_AVX2;
400 for (size_t elements = 192; elements < 960; elements += 96) {
401 RAddExtExpMicrokernelTester()
402 .elements(elements)
403 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x96_acc3);
404 }
405 }
406
407 TEST(F32_RADDEXTEXP__AVX2_P5_X96_ACC3, elements_lt_96) {
408 TEST_REQUIRES_X86_AVX2;
409 for (size_t elements = 1; elements < 96; elements++) {
410 RAddExtExpMicrokernelTester()
411 .elements(elements)
412 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x96_acc3);
413 }
414 }
415
416 TEST(F32_RADDEXTEXP__AVX2_P5_X96_ACC3, elements_gt_96) {
417 TEST_REQUIRES_X86_AVX2;
418 for (size_t elements = 97; elements < 192; elements++) {
419 RAddExtExpMicrokernelTester()
420 .elements(elements)
421 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x96_acc3);
422 }
423 }
424#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
425
426
427#if XNN_ARCH_X86 || XNN_ARCH_X86_64
428 TEST(F32_RADDEXTEXP__AVX2_P5_X96_ACC6, elements_eq_96) {
429 TEST_REQUIRES_X86_AVX2;
430 RAddExtExpMicrokernelTester()
431 .elements(96)
432 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x96_acc6);
433 }
434
435 TEST(F32_RADDEXTEXP__AVX2_P5_X96_ACC6, elements_div_96) {
436 TEST_REQUIRES_X86_AVX2;
437 for (size_t elements = 192; elements < 960; elements += 96) {
438 RAddExtExpMicrokernelTester()
439 .elements(elements)
440 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x96_acc6);
441 }
442 }
443
444 TEST(F32_RADDEXTEXP__AVX2_P5_X96_ACC6, elements_lt_96) {
445 TEST_REQUIRES_X86_AVX2;
446 for (size_t elements = 1; elements < 96; elements++) {
447 RAddExtExpMicrokernelTester()
448 .elements(elements)
449 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x96_acc6);
450 }
451 }
452
453 TEST(F32_RADDEXTEXP__AVX2_P5_X96_ACC6, elements_gt_96) {
454 TEST_REQUIRES_X86_AVX2;
455 for (size_t elements = 97; elements < 192; elements++) {
456 RAddExtExpMicrokernelTester()
457 .elements(elements)
458 .Test(xnn_f32_raddextexp_ukernel__avx2_p5_x96_acc6);
459 }
460 }
461#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
462
463
464#if XNN_ARCH_X86 || XNN_ARCH_X86_64
465 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X128, elements_eq_128) {
466 TEST_REQUIRES_X86_AVX512F;
467 RAddExtExpMicrokernelTester()
468 .elements(128)
469 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x128);
470 }
471
472 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X128, elements_div_128) {
473 TEST_REQUIRES_X86_AVX512F;
474 for (size_t elements = 256; elements < 1280; elements += 128) {
475 RAddExtExpMicrokernelTester()
476 .elements(elements)
477 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x128);
478 }
479 }
480
481 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X128, elements_lt_128) {
482 TEST_REQUIRES_X86_AVX512F;
483 for (size_t elements = 1; elements < 128; elements++) {
484 RAddExtExpMicrokernelTester()
485 .elements(elements)
486 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x128);
487 }
488 }
489
490 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X128, elements_gt_128) {
491 TEST_REQUIRES_X86_AVX512F;
492 for (size_t elements = 129; elements < 256; elements++) {
493 RAddExtExpMicrokernelTester()
494 .elements(elements)
495 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x128);
496 }
497 }
498#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
499
500
501#if XNN_ARCH_X86 || XNN_ARCH_X86_64
502 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X128_ACC2, elements_eq_128) {
503 TEST_REQUIRES_X86_AVX512F;
504 RAddExtExpMicrokernelTester()
505 .elements(128)
506 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x128_acc2);
507 }
508
509 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X128_ACC2, elements_div_128) {
510 TEST_REQUIRES_X86_AVX512F;
511 for (size_t elements = 256; elements < 1280; elements += 128) {
512 RAddExtExpMicrokernelTester()
513 .elements(elements)
514 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x128_acc2);
515 }
516 }
517
518 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X128_ACC2, elements_lt_128) {
519 TEST_REQUIRES_X86_AVX512F;
520 for (size_t elements = 1; elements < 128; elements++) {
521 RAddExtExpMicrokernelTester()
522 .elements(elements)
523 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x128_acc2);
524 }
525 }
526
527 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X128_ACC2, elements_gt_128) {
528 TEST_REQUIRES_X86_AVX512F;
529 for (size_t elements = 129; elements < 256; elements++) {
530 RAddExtExpMicrokernelTester()
531 .elements(elements)
532 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x128_acc2);
533 }
534 }
535#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
536
537
538#if XNN_ARCH_X86 || XNN_ARCH_X86_64
539 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X128_ACC4, elements_eq_128) {
540 TEST_REQUIRES_X86_AVX512F;
541 RAddExtExpMicrokernelTester()
542 .elements(128)
543 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x128_acc4);
544 }
545
546 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X128_ACC4, elements_div_128) {
547 TEST_REQUIRES_X86_AVX512F;
548 for (size_t elements = 256; elements < 1280; elements += 128) {
549 RAddExtExpMicrokernelTester()
550 .elements(elements)
551 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x128_acc4);
552 }
553 }
554
555 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X128_ACC4, elements_lt_128) {
556 TEST_REQUIRES_X86_AVX512F;
557 for (size_t elements = 1; elements < 128; elements++) {
558 RAddExtExpMicrokernelTester()
559 .elements(elements)
560 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x128_acc4);
561 }
562 }
563
564 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X128_ACC4, elements_gt_128) {
565 TEST_REQUIRES_X86_AVX512F;
566 for (size_t elements = 129; elements < 256; elements++) {
567 RAddExtExpMicrokernelTester()
568 .elements(elements)
569 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x128_acc4);
570 }
571 }
572#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
573
574
575#if XNN_ARCH_X86 || XNN_ARCH_X86_64
576 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X144, elements_eq_144) {
577 TEST_REQUIRES_X86_AVX512F;
578 RAddExtExpMicrokernelTester()
579 .elements(144)
580 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x144);
581 }
582
583 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X144, elements_div_144) {
584 TEST_REQUIRES_X86_AVX512F;
585 for (size_t elements = 288; elements < 1440; elements += 144) {
586 RAddExtExpMicrokernelTester()
587 .elements(elements)
588 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x144);
589 }
590 }
591
592 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X144, elements_lt_144) {
593 TEST_REQUIRES_X86_AVX512F;
594 for (size_t elements = 1; elements < 144; elements++) {
595 RAddExtExpMicrokernelTester()
596 .elements(elements)
597 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x144);
598 }
599 }
600
601 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X144, elements_gt_144) {
602 TEST_REQUIRES_X86_AVX512F;
603 for (size_t elements = 145; elements < 288; elements++) {
604 RAddExtExpMicrokernelTester()
605 .elements(elements)
606 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x144);
607 }
608 }
609#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
610
611
612#if XNN_ARCH_X86 || XNN_ARCH_X86_64
613 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X144_ACC3, elements_eq_144) {
614 TEST_REQUIRES_X86_AVX512F;
615 RAddExtExpMicrokernelTester()
616 .elements(144)
617 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x144_acc3);
618 }
619
620 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X144_ACC3, elements_div_144) {
621 TEST_REQUIRES_X86_AVX512F;
622 for (size_t elements = 288; elements < 1440; elements += 144) {
623 RAddExtExpMicrokernelTester()
624 .elements(elements)
625 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x144_acc3);
626 }
627 }
628
629 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X144_ACC3, elements_lt_144) {
630 TEST_REQUIRES_X86_AVX512F;
631 for (size_t elements = 1; elements < 144; elements++) {
632 RAddExtExpMicrokernelTester()
633 .elements(elements)
634 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x144_acc3);
635 }
636 }
637
638 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X144_ACC3, elements_gt_144) {
639 TEST_REQUIRES_X86_AVX512F;
640 for (size_t elements = 145; elements < 288; elements++) {
641 RAddExtExpMicrokernelTester()
642 .elements(elements)
643 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x144_acc3);
644 }
645 }
646#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
647
648
649#if XNN_ARCH_X86 || XNN_ARCH_X86_64
650 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X160, elements_eq_160) {
651 TEST_REQUIRES_X86_AVX512F;
652 RAddExtExpMicrokernelTester()
653 .elements(160)
654 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x160);
655 }
656
657 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X160, elements_div_160) {
658 TEST_REQUIRES_X86_AVX512F;
659 for (size_t elements = 320; elements < 1600; elements += 160) {
660 RAddExtExpMicrokernelTester()
661 .elements(elements)
662 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x160);
663 }
664 }
665
666 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X160, elements_lt_160) {
667 TEST_REQUIRES_X86_AVX512F;
668 for (size_t elements = 1; elements < 160; elements++) {
669 RAddExtExpMicrokernelTester()
670 .elements(elements)
671 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x160);
672 }
673 }
674
675 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X160, elements_gt_160) {
676 TEST_REQUIRES_X86_AVX512F;
677 for (size_t elements = 161; elements < 320; elements++) {
678 RAddExtExpMicrokernelTester()
679 .elements(elements)
680 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x160);
681 }
682 }
683#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
684
685
686#if XNN_ARCH_X86 || XNN_ARCH_X86_64
687 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X160_ACC2, elements_eq_160) {
688 TEST_REQUIRES_X86_AVX512F;
689 RAddExtExpMicrokernelTester()
690 .elements(160)
691 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x160_acc2);
692 }
693
694 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X160_ACC2, elements_div_160) {
695 TEST_REQUIRES_X86_AVX512F;
696 for (size_t elements = 320; elements < 1600; elements += 160) {
697 RAddExtExpMicrokernelTester()
698 .elements(elements)
699 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x160_acc2);
700 }
701 }
702
703 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X160_ACC2, elements_lt_160) {
704 TEST_REQUIRES_X86_AVX512F;
705 for (size_t elements = 1; elements < 160; elements++) {
706 RAddExtExpMicrokernelTester()
707 .elements(elements)
708 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x160_acc2);
709 }
710 }
711
712 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X160_ACC2, elements_gt_160) {
713 TEST_REQUIRES_X86_AVX512F;
714 for (size_t elements = 161; elements < 320; elements++) {
715 RAddExtExpMicrokernelTester()
716 .elements(elements)
717 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x160_acc2);
718 }
719 }
720#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
721
722
723#if XNN_ARCH_X86 || XNN_ARCH_X86_64
724 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X160_ACC5, elements_eq_160) {
725 TEST_REQUIRES_X86_AVX512F;
726 RAddExtExpMicrokernelTester()
727 .elements(160)
728 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x160_acc5);
729 }
730
731 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X160_ACC5, elements_div_160) {
732 TEST_REQUIRES_X86_AVX512F;
733 for (size_t elements = 320; elements < 1600; elements += 160) {
734 RAddExtExpMicrokernelTester()
735 .elements(elements)
736 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x160_acc5);
737 }
738 }
739
740 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X160_ACC5, elements_lt_160) {
741 TEST_REQUIRES_X86_AVX512F;
742 for (size_t elements = 1; elements < 160; elements++) {
743 RAddExtExpMicrokernelTester()
744 .elements(elements)
745 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x160_acc5);
746 }
747 }
748
749 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X160_ACC5, elements_gt_160) {
750 TEST_REQUIRES_X86_AVX512F;
751 for (size_t elements = 161; elements < 320; elements++) {
752 RAddExtExpMicrokernelTester()
753 .elements(elements)
754 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x160_acc5);
755 }
756 }
757#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
758
759
760#if XNN_ARCH_X86 || XNN_ARCH_X86_64
761 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X192, elements_eq_192) {
762 TEST_REQUIRES_X86_AVX512F;
763 RAddExtExpMicrokernelTester()
764 .elements(192)
765 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x192);
766 }
767
768 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X192, elements_div_192) {
769 TEST_REQUIRES_X86_AVX512F;
770 for (size_t elements = 384; elements < 1920; elements += 192) {
771 RAddExtExpMicrokernelTester()
772 .elements(elements)
773 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x192);
774 }
775 }
776
777 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X192, elements_lt_192) {
778 TEST_REQUIRES_X86_AVX512F;
779 for (size_t elements = 1; elements < 192; elements++) {
780 RAddExtExpMicrokernelTester()
781 .elements(elements)
782 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x192);
783 }
784 }
785
786 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X192, elements_gt_192) {
787 TEST_REQUIRES_X86_AVX512F;
788 for (size_t elements = 193; elements < 384; elements++) {
789 RAddExtExpMicrokernelTester()
790 .elements(elements)
791 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x192);
792 }
793 }
794#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
795
796
797#if XNN_ARCH_X86 || XNN_ARCH_X86_64
798 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X192_ACC2, elements_eq_192) {
799 TEST_REQUIRES_X86_AVX512F;
800 RAddExtExpMicrokernelTester()
801 .elements(192)
802 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x192_acc2);
803 }
804
805 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X192_ACC2, elements_div_192) {
806 TEST_REQUIRES_X86_AVX512F;
807 for (size_t elements = 384; elements < 1920; elements += 192) {
808 RAddExtExpMicrokernelTester()
809 .elements(elements)
810 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x192_acc2);
811 }
812 }
813
814 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X192_ACC2, elements_lt_192) {
815 TEST_REQUIRES_X86_AVX512F;
816 for (size_t elements = 1; elements < 192; elements++) {
817 RAddExtExpMicrokernelTester()
818 .elements(elements)
819 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x192_acc2);
820 }
821 }
822
823 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X192_ACC2, elements_gt_192) {
824 TEST_REQUIRES_X86_AVX512F;
825 for (size_t elements = 193; elements < 384; elements++) {
826 RAddExtExpMicrokernelTester()
827 .elements(elements)
828 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x192_acc2);
829 }
830 }
831#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
832
833
834#if XNN_ARCH_X86 || XNN_ARCH_X86_64
835 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X192_ACC3, elements_eq_192) {
836 TEST_REQUIRES_X86_AVX512F;
837 RAddExtExpMicrokernelTester()
838 .elements(192)
839 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x192_acc3);
840 }
841
842 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X192_ACC3, elements_div_192) {
843 TEST_REQUIRES_X86_AVX512F;
844 for (size_t elements = 384; elements < 1920; elements += 192) {
845 RAddExtExpMicrokernelTester()
846 .elements(elements)
847 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x192_acc3);
848 }
849 }
850
851 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X192_ACC3, elements_lt_192) {
852 TEST_REQUIRES_X86_AVX512F;
853 for (size_t elements = 1; elements < 192; elements++) {
854 RAddExtExpMicrokernelTester()
855 .elements(elements)
856 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x192_acc3);
857 }
858 }
859
860 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X192_ACC3, elements_gt_192) {
861 TEST_REQUIRES_X86_AVX512F;
862 for (size_t elements = 193; elements < 384; elements++) {
863 RAddExtExpMicrokernelTester()
864 .elements(elements)
865 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x192_acc3);
866 }
867 }
868#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
869
870
871#if XNN_ARCH_X86 || XNN_ARCH_X86_64
872 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X192_ACC6, elements_eq_192) {
873 TEST_REQUIRES_X86_AVX512F;
874 RAddExtExpMicrokernelTester()
875 .elements(192)
876 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x192_acc6);
877 }
878
879 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X192_ACC6, elements_div_192) {
880 TEST_REQUIRES_X86_AVX512F;
881 for (size_t elements = 384; elements < 1920; elements += 192) {
882 RAddExtExpMicrokernelTester()
883 .elements(elements)
884 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x192_acc6);
885 }
886 }
887
888 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X192_ACC6, elements_lt_192) {
889 TEST_REQUIRES_X86_AVX512F;
890 for (size_t elements = 1; elements < 192; elements++) {
891 RAddExtExpMicrokernelTester()
892 .elements(elements)
893 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x192_acc6);
894 }
895 }
896
897 TEST(F32_RADDEXTEXP__AVX512F_P5_SCALEF_X192_ACC6, elements_gt_192) {
898 TEST_REQUIRES_X86_AVX512F;
899 for (size_t elements = 193; elements < 384; elements++) {
900 RAddExtExpMicrokernelTester()
901 .elements(elements)
902 .Test(xnn_f32_raddextexp_ukernel__avx512f_p5_scalef_x192_acc6);
Marat Dukhan6f8d4d32019-10-25 17:07:09 -0700903 }
904 }
905#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64