Marat Dukhan | 346a9e5 | 2019-11-15 09:06:30 -0800 | [diff] [blame] | 1 | // Copyright 2019 Google LLC |
| 2 | // |
| 3 | // This source code is licensed under the BSD-style license found in the |
| 4 | // LICENSE file in the root directory of this source tree. |
| 5 | // |
| 6 | // Auto-generated file. Do not edit! |
| 7 | // Specification: test/f32-sigmoid.yaml |
Marat Dukhan | 1e782c4 | 2019-11-21 17:02:40 -0800 | [diff] [blame] | 8 | // Generator: tools/generate-vunary-test.py |
Marat Dukhan | 346a9e5 | 2019-11-15 09:06:30 -0800 | [diff] [blame] | 9 | |
| 10 | |
| 11 | #include <gtest/gtest.h> |
| 12 | |
| 13 | #include <xnnpack/common.h> |
| 14 | #include <xnnpack/isa-checks.h> |
| 15 | |
Marat Dukhan | 1e782c4 | 2019-11-21 17:02:40 -0800 | [diff] [blame] | 16 | #include <xnnpack/vunary.h> |
| 17 | #include "vunary-microkernel-tester.h" |
Marat Dukhan | 346a9e5 | 2019-11-15 09:06:30 -0800 | [diff] [blame] | 18 | |
| 19 | |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 20 | #if XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 21 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X4, batch_eq_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 22 | TEST_REQUIRES_ARM_NEON_FMA; |
| 23 | VUnOpMicrokernelTester() |
| 24 | .batch_size(4) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 25 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 26 | } |
| 27 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 28 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X4, batch_div_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 29 | TEST_REQUIRES_ARM_NEON_FMA; |
| 30 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 31 | VUnOpMicrokernelTester() |
| 32 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 33 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 34 | } |
| 35 | } |
| 36 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 37 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X4, batch_lt_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 38 | TEST_REQUIRES_ARM_NEON_FMA; |
| 39 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 40 | VUnOpMicrokernelTester() |
| 41 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 42 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 43 | } |
| 44 | } |
| 45 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 46 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X4, batch_gt_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 47 | TEST_REQUIRES_ARM_NEON_FMA; |
| 48 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 49 | VUnOpMicrokernelTester() |
| 50 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 51 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 52 | } |
| 53 | } |
| 54 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 55 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X4, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 56 | TEST_REQUIRES_ARM_NEON_FMA; |
| 57 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 58 | VUnOpMicrokernelTester() |
| 59 | .batch_size(batch_size) |
| 60 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 61 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 62 | } |
| 63 | } |
| 64 | #endif // XNN_ARCH_ARM64 |
| 65 | |
| 66 | |
| 67 | #if XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 68 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X8, batch_eq_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 69 | TEST_REQUIRES_ARM_NEON_FMA; |
| 70 | VUnOpMicrokernelTester() |
| 71 | .batch_size(8) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 72 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 73 | } |
| 74 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 75 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X8, batch_div_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 76 | TEST_REQUIRES_ARM_NEON_FMA; |
| 77 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 78 | VUnOpMicrokernelTester() |
| 79 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 80 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 81 | } |
| 82 | } |
| 83 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 84 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X8, batch_lt_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 85 | TEST_REQUIRES_ARM_NEON_FMA; |
| 86 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 87 | VUnOpMicrokernelTester() |
| 88 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 89 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 90 | } |
| 91 | } |
| 92 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 93 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X8, batch_gt_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 94 | TEST_REQUIRES_ARM_NEON_FMA; |
| 95 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 96 | VUnOpMicrokernelTester() |
| 97 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 98 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 99 | } |
| 100 | } |
| 101 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 102 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X8, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 103 | TEST_REQUIRES_ARM_NEON_FMA; |
| 104 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 105 | VUnOpMicrokernelTester() |
| 106 | .batch_size(batch_size) |
| 107 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 108 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 109 | } |
| 110 | } |
| 111 | #endif // XNN_ARCH_ARM64 |
| 112 | |
| 113 | |
| 114 | #if XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 115 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X12, batch_eq_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 116 | TEST_REQUIRES_ARM_NEON_FMA; |
| 117 | VUnOpMicrokernelTester() |
| 118 | .batch_size(12) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 119 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 120 | } |
| 121 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 122 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X12, batch_div_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 123 | TEST_REQUIRES_ARM_NEON_FMA; |
| 124 | for (size_t batch_size = 24; batch_size < 120; batch_size += 12) { |
| 125 | VUnOpMicrokernelTester() |
| 126 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 127 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 128 | } |
| 129 | } |
| 130 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 131 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X12, batch_lt_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 132 | TEST_REQUIRES_ARM_NEON_FMA; |
| 133 | for (size_t batch_size = 1; batch_size < 12; batch_size++) { |
| 134 | VUnOpMicrokernelTester() |
| 135 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 136 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 137 | } |
| 138 | } |
| 139 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 140 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X12, batch_gt_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 141 | TEST_REQUIRES_ARM_NEON_FMA; |
| 142 | for (size_t batch_size = 13; batch_size < 24; batch_size++) { |
| 143 | VUnOpMicrokernelTester() |
| 144 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 145 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 146 | } |
| 147 | } |
| 148 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 149 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X12, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 150 | TEST_REQUIRES_ARM_NEON_FMA; |
| 151 | for (size_t batch_size = 1; batch_size <= 60; batch_size += 11) { |
| 152 | VUnOpMicrokernelTester() |
| 153 | .batch_size(batch_size) |
| 154 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 155 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 156 | } |
| 157 | } |
| 158 | #endif // XNN_ARCH_ARM64 |
| 159 | |
| 160 | |
| 161 | #if XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 162 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X16, batch_eq_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 163 | TEST_REQUIRES_ARM_NEON_FMA; |
| 164 | VUnOpMicrokernelTester() |
| 165 | .batch_size(16) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 166 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 167 | } |
| 168 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 169 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X16, batch_div_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 170 | TEST_REQUIRES_ARM_NEON_FMA; |
| 171 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 172 | VUnOpMicrokernelTester() |
| 173 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 174 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 175 | } |
| 176 | } |
| 177 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 178 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X16, batch_lt_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 179 | TEST_REQUIRES_ARM_NEON_FMA; |
| 180 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 181 | VUnOpMicrokernelTester() |
| 182 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 183 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 184 | } |
| 185 | } |
| 186 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 187 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X16, batch_gt_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 188 | TEST_REQUIRES_ARM_NEON_FMA; |
| 189 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 190 | VUnOpMicrokernelTester() |
| 191 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 192 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 193 | } |
| 194 | } |
| 195 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 196 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X16, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 197 | TEST_REQUIRES_ARM_NEON_FMA; |
| 198 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 199 | VUnOpMicrokernelTester() |
| 200 | .batch_size(batch_size) |
| 201 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 202 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 203 | } |
| 204 | } |
| 205 | #endif // XNN_ARCH_ARM64 |
| 206 | |
| 207 | |
| 208 | #if XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 209 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X20, batch_eq_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 210 | TEST_REQUIRES_ARM_NEON_FMA; |
| 211 | VUnOpMicrokernelTester() |
| 212 | .batch_size(20) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 213 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 214 | } |
| 215 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 216 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X20, batch_div_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 217 | TEST_REQUIRES_ARM_NEON_FMA; |
| 218 | for (size_t batch_size = 40; batch_size < 200; batch_size += 20) { |
| 219 | VUnOpMicrokernelTester() |
| 220 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 221 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 222 | } |
| 223 | } |
| 224 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 225 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X20, batch_lt_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 226 | TEST_REQUIRES_ARM_NEON_FMA; |
| 227 | for (size_t batch_size = 1; batch_size < 20; batch_size++) { |
| 228 | VUnOpMicrokernelTester() |
| 229 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 230 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 231 | } |
| 232 | } |
| 233 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 234 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X20, batch_gt_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 235 | TEST_REQUIRES_ARM_NEON_FMA; |
| 236 | for (size_t batch_size = 21; batch_size < 40; batch_size++) { |
| 237 | VUnOpMicrokernelTester() |
| 238 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 239 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 240 | } |
| 241 | } |
| 242 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 243 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X20, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 244 | TEST_REQUIRES_ARM_NEON_FMA; |
| 245 | for (size_t batch_size = 1; batch_size <= 100; batch_size += 19) { |
| 246 | VUnOpMicrokernelTester() |
| 247 | .batch_size(batch_size) |
| 248 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 249 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 250 | } |
| 251 | } |
| 252 | #endif // XNN_ARCH_ARM64 |
| 253 | |
| 254 | |
| 255 | #if XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 256 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X24, batch_eq_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 257 | TEST_REQUIRES_ARM_NEON_FMA; |
| 258 | VUnOpMicrokernelTester() |
| 259 | .batch_size(24) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 260 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 261 | } |
| 262 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 263 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X24, batch_div_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 264 | TEST_REQUIRES_ARM_NEON_FMA; |
| 265 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 266 | VUnOpMicrokernelTester() |
| 267 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 268 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 269 | } |
| 270 | } |
| 271 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 272 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X24, batch_lt_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 273 | TEST_REQUIRES_ARM_NEON_FMA; |
| 274 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 275 | VUnOpMicrokernelTester() |
| 276 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 277 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 278 | } |
| 279 | } |
| 280 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 281 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X24, batch_gt_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 282 | TEST_REQUIRES_ARM_NEON_FMA; |
| 283 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 284 | VUnOpMicrokernelTester() |
| 285 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 286 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 287 | } |
| 288 | } |
| 289 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 290 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_DIV_X24, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 291 | TEST_REQUIRES_ARM_NEON_FMA; |
| 292 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 293 | VUnOpMicrokernelTester() |
| 294 | .batch_size(batch_size) |
| 295 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 296 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 297 | } |
| 298 | } |
| 299 | #endif // XNN_ARCH_ARM64 |
| 300 | |
| 301 | |
| 302 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 303 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X4, batch_eq_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 304 | TEST_REQUIRES_ARM_NEON_FMA; |
| 305 | VUnOpMicrokernelTester() |
| 306 | .batch_size(4) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 307 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 308 | } |
| 309 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 310 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X4, batch_div_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 311 | TEST_REQUIRES_ARM_NEON_FMA; |
| 312 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 313 | VUnOpMicrokernelTester() |
| 314 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 315 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 316 | } |
| 317 | } |
| 318 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 319 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X4, batch_lt_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 320 | TEST_REQUIRES_ARM_NEON_FMA; |
| 321 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 322 | VUnOpMicrokernelTester() |
| 323 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 324 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 325 | } |
| 326 | } |
| 327 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 328 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X4, batch_gt_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 329 | TEST_REQUIRES_ARM_NEON_FMA; |
| 330 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 331 | VUnOpMicrokernelTester() |
| 332 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 333 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 334 | } |
| 335 | } |
| 336 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 337 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X4, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 338 | TEST_REQUIRES_ARM_NEON_FMA; |
| 339 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 340 | VUnOpMicrokernelTester() |
| 341 | .batch_size(batch_size) |
| 342 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 343 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 344 | } |
| 345 | } |
| 346 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 347 | |
| 348 | |
| 349 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 350 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X8, batch_eq_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 351 | TEST_REQUIRES_ARM_NEON_FMA; |
| 352 | VUnOpMicrokernelTester() |
| 353 | .batch_size(8) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 354 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 355 | } |
| 356 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 357 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X8, batch_div_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 358 | TEST_REQUIRES_ARM_NEON_FMA; |
| 359 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 360 | VUnOpMicrokernelTester() |
| 361 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 362 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 363 | } |
| 364 | } |
| 365 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 366 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X8, batch_lt_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 367 | TEST_REQUIRES_ARM_NEON_FMA; |
| 368 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 369 | VUnOpMicrokernelTester() |
| 370 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 371 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 372 | } |
| 373 | } |
| 374 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 375 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X8, batch_gt_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 376 | TEST_REQUIRES_ARM_NEON_FMA; |
| 377 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 378 | VUnOpMicrokernelTester() |
| 379 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 380 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 381 | } |
| 382 | } |
| 383 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 384 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X8, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 385 | TEST_REQUIRES_ARM_NEON_FMA; |
| 386 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 387 | VUnOpMicrokernelTester() |
| 388 | .batch_size(batch_size) |
| 389 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 390 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 391 | } |
| 392 | } |
| 393 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 394 | |
| 395 | |
| 396 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 397 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X12, batch_eq_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 398 | TEST_REQUIRES_ARM_NEON_FMA; |
| 399 | VUnOpMicrokernelTester() |
| 400 | .batch_size(12) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 401 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 402 | } |
| 403 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 404 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X12, batch_div_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 405 | TEST_REQUIRES_ARM_NEON_FMA; |
| 406 | for (size_t batch_size = 24; batch_size < 120; batch_size += 12) { |
| 407 | VUnOpMicrokernelTester() |
| 408 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 409 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 410 | } |
| 411 | } |
| 412 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 413 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X12, batch_lt_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 414 | TEST_REQUIRES_ARM_NEON_FMA; |
| 415 | for (size_t batch_size = 1; batch_size < 12; batch_size++) { |
| 416 | VUnOpMicrokernelTester() |
| 417 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 418 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 419 | } |
| 420 | } |
| 421 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 422 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X12, batch_gt_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 423 | TEST_REQUIRES_ARM_NEON_FMA; |
| 424 | for (size_t batch_size = 13; batch_size < 24; batch_size++) { |
| 425 | VUnOpMicrokernelTester() |
| 426 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 427 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 428 | } |
| 429 | } |
| 430 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 431 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X12, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 432 | TEST_REQUIRES_ARM_NEON_FMA; |
| 433 | for (size_t batch_size = 1; batch_size <= 60; batch_size += 11) { |
| 434 | VUnOpMicrokernelTester() |
| 435 | .batch_size(batch_size) |
| 436 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 437 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 438 | } |
| 439 | } |
| 440 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 441 | |
| 442 | |
Marat Dukhan | 346a9e5 | 2019-11-15 09:06:30 -0800 | [diff] [blame] | 443 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 444 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X16, batch_eq_16) { |
Marat Dukhan | 346a9e5 | 2019-11-15 09:06:30 -0800 | [diff] [blame] | 445 | TEST_REQUIRES_ARM_NEON_FMA; |
| 446 | VUnOpMicrokernelTester() |
| 447 | .batch_size(16) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 448 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 346a9e5 | 2019-11-15 09:06:30 -0800 | [diff] [blame] | 449 | } |
| 450 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 451 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X16, batch_div_16) { |
Marat Dukhan | 346a9e5 | 2019-11-15 09:06:30 -0800 | [diff] [blame] | 452 | TEST_REQUIRES_ARM_NEON_FMA; |
| 453 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 454 | VUnOpMicrokernelTester() |
| 455 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 456 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 346a9e5 | 2019-11-15 09:06:30 -0800 | [diff] [blame] | 457 | } |
| 458 | } |
| 459 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 460 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X16, batch_lt_16) { |
Marat Dukhan | 346a9e5 | 2019-11-15 09:06:30 -0800 | [diff] [blame] | 461 | TEST_REQUIRES_ARM_NEON_FMA; |
| 462 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 463 | VUnOpMicrokernelTester() |
| 464 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 465 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 346a9e5 | 2019-11-15 09:06:30 -0800 | [diff] [blame] | 466 | } |
| 467 | } |
| 468 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 469 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X16, batch_gt_16) { |
Marat Dukhan | 346a9e5 | 2019-11-15 09:06:30 -0800 | [diff] [blame] | 470 | TEST_REQUIRES_ARM_NEON_FMA; |
| 471 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 472 | VUnOpMicrokernelTester() |
| 473 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 474 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 346a9e5 | 2019-11-15 09:06:30 -0800 | [diff] [blame] | 475 | } |
| 476 | } |
| 477 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 478 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X16, inplace) { |
Marat Dukhan | 346a9e5 | 2019-11-15 09:06:30 -0800 | [diff] [blame] | 479 | TEST_REQUIRES_ARM_NEON_FMA; |
| 480 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 481 | VUnOpMicrokernelTester() |
| 482 | .batch_size(batch_size) |
| 483 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 484 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 346a9e5 | 2019-11-15 09:06:30 -0800 | [diff] [blame] | 485 | } |
| 486 | } |
| 487 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Erich Elsen | 8fd7b5f | 2019-11-18 10:50:41 -0800 | [diff] [blame] | 488 | |
| 489 | |
| 490 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 491 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X20, batch_eq_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 492 | TEST_REQUIRES_ARM_NEON_FMA; |
| 493 | VUnOpMicrokernelTester() |
| 494 | .batch_size(20) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 495 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 496 | } |
| 497 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 498 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X20, batch_div_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 499 | TEST_REQUIRES_ARM_NEON_FMA; |
| 500 | for (size_t batch_size = 40; batch_size < 200; batch_size += 20) { |
| 501 | VUnOpMicrokernelTester() |
| 502 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 503 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 504 | } |
| 505 | } |
| 506 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 507 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X20, batch_lt_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 508 | TEST_REQUIRES_ARM_NEON_FMA; |
| 509 | for (size_t batch_size = 1; batch_size < 20; batch_size++) { |
| 510 | VUnOpMicrokernelTester() |
| 511 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 512 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 513 | } |
| 514 | } |
| 515 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 516 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X20, batch_gt_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 517 | TEST_REQUIRES_ARM_NEON_FMA; |
| 518 | for (size_t batch_size = 21; batch_size < 40; batch_size++) { |
| 519 | VUnOpMicrokernelTester() |
| 520 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 521 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 522 | } |
| 523 | } |
| 524 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 525 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X20, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 526 | TEST_REQUIRES_ARM_NEON_FMA; |
| 527 | for (size_t batch_size = 1; batch_size <= 100; batch_size += 19) { |
| 528 | VUnOpMicrokernelTester() |
| 529 | .batch_size(batch_size) |
| 530 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 531 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 532 | } |
| 533 | } |
| 534 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 535 | |
| 536 | |
| 537 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 538 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X24, batch_eq_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 539 | TEST_REQUIRES_ARM_NEON_FMA; |
| 540 | VUnOpMicrokernelTester() |
| 541 | .batch_size(24) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 542 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 543 | } |
| 544 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 545 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X24, batch_div_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 546 | TEST_REQUIRES_ARM_NEON_FMA; |
| 547 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 548 | VUnOpMicrokernelTester() |
| 549 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 550 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 551 | } |
| 552 | } |
| 553 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 554 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X24, batch_lt_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 555 | TEST_REQUIRES_ARM_NEON_FMA; |
| 556 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 557 | VUnOpMicrokernelTester() |
| 558 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 559 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 560 | } |
| 561 | } |
| 562 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 563 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X24, batch_gt_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 564 | TEST_REQUIRES_ARM_NEON_FMA; |
| 565 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 566 | VUnOpMicrokernelTester() |
| 567 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 568 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 569 | } |
| 570 | } |
| 571 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 572 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2FMA_X24, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 573 | TEST_REQUIRES_ARM_NEON_FMA; |
| 574 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 575 | VUnOpMicrokernelTester() |
| 576 | .batch_size(batch_size) |
| 577 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 578 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 579 | } |
| 580 | } |
| 581 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 582 | |
| 583 | |
| 584 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 585 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X4, batch_eq_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 586 | TEST_REQUIRES_ARM_NEON_FMA; |
| 587 | VUnOpMicrokernelTester() |
| 588 | .batch_size(4) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 589 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 590 | } |
| 591 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 592 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X4, batch_div_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 593 | TEST_REQUIRES_ARM_NEON_FMA; |
| 594 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 595 | VUnOpMicrokernelTester() |
| 596 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 597 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 598 | } |
| 599 | } |
| 600 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 601 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X4, batch_lt_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 602 | TEST_REQUIRES_ARM_NEON_FMA; |
| 603 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 604 | VUnOpMicrokernelTester() |
| 605 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 606 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 607 | } |
| 608 | } |
| 609 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 610 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X4, batch_gt_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 611 | TEST_REQUIRES_ARM_NEON_FMA; |
| 612 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 613 | VUnOpMicrokernelTester() |
| 614 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 615 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 616 | } |
| 617 | } |
| 618 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 619 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X4, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 620 | TEST_REQUIRES_ARM_NEON_FMA; |
| 621 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 622 | VUnOpMicrokernelTester() |
| 623 | .batch_size(batch_size) |
| 624 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 625 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 626 | } |
| 627 | } |
| 628 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 629 | |
| 630 | |
| 631 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 632 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X8, batch_eq_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 633 | TEST_REQUIRES_ARM_NEON_FMA; |
| 634 | VUnOpMicrokernelTester() |
| 635 | .batch_size(8) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 636 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 637 | } |
| 638 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 639 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X8, batch_div_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 640 | TEST_REQUIRES_ARM_NEON_FMA; |
| 641 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 642 | VUnOpMicrokernelTester() |
| 643 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 644 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 645 | } |
| 646 | } |
| 647 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 648 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X8, batch_lt_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 649 | TEST_REQUIRES_ARM_NEON_FMA; |
| 650 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 651 | VUnOpMicrokernelTester() |
| 652 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 653 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 654 | } |
| 655 | } |
| 656 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 657 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X8, batch_gt_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 658 | TEST_REQUIRES_ARM_NEON_FMA; |
| 659 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 660 | VUnOpMicrokernelTester() |
| 661 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 662 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 663 | } |
| 664 | } |
| 665 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 666 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X8, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 667 | TEST_REQUIRES_ARM_NEON_FMA; |
| 668 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 669 | VUnOpMicrokernelTester() |
| 670 | .batch_size(batch_size) |
| 671 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 672 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 673 | } |
| 674 | } |
| 675 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 676 | |
| 677 | |
| 678 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 679 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X12, batch_eq_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 680 | TEST_REQUIRES_ARM_NEON_FMA; |
| 681 | VUnOpMicrokernelTester() |
| 682 | .batch_size(12) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 683 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 684 | } |
| 685 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 686 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X12, batch_div_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 687 | TEST_REQUIRES_ARM_NEON_FMA; |
| 688 | for (size_t batch_size = 24; batch_size < 120; batch_size += 12) { |
| 689 | VUnOpMicrokernelTester() |
| 690 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 691 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 692 | } |
| 693 | } |
| 694 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 695 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X12, batch_lt_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 696 | TEST_REQUIRES_ARM_NEON_FMA; |
| 697 | for (size_t batch_size = 1; batch_size < 12; batch_size++) { |
| 698 | VUnOpMicrokernelTester() |
| 699 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 700 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 701 | } |
| 702 | } |
| 703 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 704 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X12, batch_gt_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 705 | TEST_REQUIRES_ARM_NEON_FMA; |
| 706 | for (size_t batch_size = 13; batch_size < 24; batch_size++) { |
| 707 | VUnOpMicrokernelTester() |
| 708 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 709 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 710 | } |
| 711 | } |
| 712 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 713 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X12, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 714 | TEST_REQUIRES_ARM_NEON_FMA; |
| 715 | for (size_t batch_size = 1; batch_size <= 60; batch_size += 11) { |
| 716 | VUnOpMicrokernelTester() |
| 717 | .batch_size(batch_size) |
| 718 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 719 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 720 | } |
| 721 | } |
| 722 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 723 | |
| 724 | |
| 725 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 726 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X16, batch_eq_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 727 | TEST_REQUIRES_ARM_NEON_FMA; |
| 728 | VUnOpMicrokernelTester() |
| 729 | .batch_size(16) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 730 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 731 | } |
| 732 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 733 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X16, batch_div_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 734 | TEST_REQUIRES_ARM_NEON_FMA; |
| 735 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 736 | VUnOpMicrokernelTester() |
| 737 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 738 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 739 | } |
| 740 | } |
| 741 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 742 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X16, batch_lt_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 743 | TEST_REQUIRES_ARM_NEON_FMA; |
| 744 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 745 | VUnOpMicrokernelTester() |
| 746 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 747 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 748 | } |
| 749 | } |
| 750 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 751 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X16, batch_gt_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 752 | TEST_REQUIRES_ARM_NEON_FMA; |
| 753 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 754 | VUnOpMicrokernelTester() |
| 755 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 756 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 757 | } |
| 758 | } |
| 759 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 760 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X16, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 761 | TEST_REQUIRES_ARM_NEON_FMA; |
| 762 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 763 | VUnOpMicrokernelTester() |
| 764 | .batch_size(batch_size) |
| 765 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 766 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 767 | } |
| 768 | } |
| 769 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 770 | |
| 771 | |
| 772 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 773 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X20, batch_eq_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 774 | TEST_REQUIRES_ARM_NEON_FMA; |
| 775 | VUnOpMicrokernelTester() |
| 776 | .batch_size(20) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 777 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 778 | } |
| 779 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 780 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X20, batch_div_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 781 | TEST_REQUIRES_ARM_NEON_FMA; |
| 782 | for (size_t batch_size = 40; batch_size < 200; batch_size += 20) { |
| 783 | VUnOpMicrokernelTester() |
| 784 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 785 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 786 | } |
| 787 | } |
| 788 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 789 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X20, batch_lt_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 790 | TEST_REQUIRES_ARM_NEON_FMA; |
| 791 | for (size_t batch_size = 1; batch_size < 20; batch_size++) { |
| 792 | VUnOpMicrokernelTester() |
| 793 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 794 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 795 | } |
| 796 | } |
| 797 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 798 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X20, batch_gt_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 799 | TEST_REQUIRES_ARM_NEON_FMA; |
| 800 | for (size_t batch_size = 21; batch_size < 40; batch_size++) { |
| 801 | VUnOpMicrokernelTester() |
| 802 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 803 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 804 | } |
| 805 | } |
| 806 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 807 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X20, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 808 | TEST_REQUIRES_ARM_NEON_FMA; |
| 809 | for (size_t batch_size = 1; batch_size <= 100; batch_size += 19) { |
| 810 | VUnOpMicrokernelTester() |
| 811 | .batch_size(batch_size) |
| 812 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 813 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 814 | } |
| 815 | } |
| 816 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 817 | |
| 818 | |
| 819 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 820 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X24, batch_eq_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 821 | TEST_REQUIRES_ARM_NEON_FMA; |
| 822 | VUnOpMicrokernelTester() |
| 823 | .batch_size(24) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 824 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 825 | } |
| 826 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 827 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X24, batch_div_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 828 | TEST_REQUIRES_ARM_NEON_FMA; |
| 829 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 830 | VUnOpMicrokernelTester() |
| 831 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 832 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 833 | } |
| 834 | } |
| 835 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 836 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X24, batch_lt_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 837 | TEST_REQUIRES_ARM_NEON_FMA; |
| 838 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 839 | VUnOpMicrokernelTester() |
| 840 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 841 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 842 | } |
| 843 | } |
| 844 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 845 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X24, batch_gt_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 846 | TEST_REQUIRES_ARM_NEON_FMA; |
| 847 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 848 | VUnOpMicrokernelTester() |
| 849 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 850 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 851 | } |
| 852 | } |
| 853 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 854 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR1RECPS1FMA_X24, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 855 | TEST_REQUIRES_ARM_NEON_FMA; |
| 856 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 857 | VUnOpMicrokernelTester() |
| 858 | .batch_size(batch_size) |
| 859 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 860 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr1recps1fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 861 | } |
| 862 | } |
| 863 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 864 | |
| 865 | |
| 866 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 867 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X4, batch_eq_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 868 | TEST_REQUIRES_ARM_NEON_FMA; |
| 869 | VUnOpMicrokernelTester() |
| 870 | .batch_size(4) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 871 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 872 | } |
| 873 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 874 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X4, batch_div_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 875 | TEST_REQUIRES_ARM_NEON_FMA; |
| 876 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 877 | VUnOpMicrokernelTester() |
| 878 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 879 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 880 | } |
| 881 | } |
| 882 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 883 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X4, batch_lt_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 884 | TEST_REQUIRES_ARM_NEON_FMA; |
| 885 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 886 | VUnOpMicrokernelTester() |
| 887 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 888 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 889 | } |
| 890 | } |
| 891 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 892 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X4, batch_gt_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 893 | TEST_REQUIRES_ARM_NEON_FMA; |
| 894 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 895 | VUnOpMicrokernelTester() |
| 896 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 897 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 898 | } |
| 899 | } |
| 900 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 901 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X4, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 902 | TEST_REQUIRES_ARM_NEON_FMA; |
| 903 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 904 | VUnOpMicrokernelTester() |
| 905 | .batch_size(batch_size) |
| 906 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 907 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 908 | } |
| 909 | } |
| 910 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 911 | |
| 912 | |
| 913 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 914 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X8, batch_eq_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 915 | TEST_REQUIRES_ARM_NEON_FMA; |
| 916 | VUnOpMicrokernelTester() |
| 917 | .batch_size(8) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 918 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 919 | } |
| 920 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 921 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X8, batch_div_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 922 | TEST_REQUIRES_ARM_NEON_FMA; |
| 923 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 924 | VUnOpMicrokernelTester() |
| 925 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 926 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 927 | } |
| 928 | } |
| 929 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 930 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X8, batch_lt_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 931 | TEST_REQUIRES_ARM_NEON_FMA; |
| 932 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 933 | VUnOpMicrokernelTester() |
| 934 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 935 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 936 | } |
| 937 | } |
| 938 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 939 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X8, batch_gt_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 940 | TEST_REQUIRES_ARM_NEON_FMA; |
| 941 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 942 | VUnOpMicrokernelTester() |
| 943 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 944 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 945 | } |
| 946 | } |
| 947 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 948 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X8, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 949 | TEST_REQUIRES_ARM_NEON_FMA; |
| 950 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 951 | VUnOpMicrokernelTester() |
| 952 | .batch_size(batch_size) |
| 953 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 954 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 955 | } |
| 956 | } |
| 957 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 958 | |
| 959 | |
| 960 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 961 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X12, batch_eq_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 962 | TEST_REQUIRES_ARM_NEON_FMA; |
| 963 | VUnOpMicrokernelTester() |
| 964 | .batch_size(12) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 965 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 966 | } |
| 967 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 968 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X12, batch_div_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 969 | TEST_REQUIRES_ARM_NEON_FMA; |
| 970 | for (size_t batch_size = 24; batch_size < 120; batch_size += 12) { |
| 971 | VUnOpMicrokernelTester() |
| 972 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 973 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 974 | } |
| 975 | } |
| 976 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 977 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X12, batch_lt_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 978 | TEST_REQUIRES_ARM_NEON_FMA; |
| 979 | for (size_t batch_size = 1; batch_size < 12; batch_size++) { |
| 980 | VUnOpMicrokernelTester() |
| 981 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 982 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 983 | } |
| 984 | } |
| 985 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 986 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X12, batch_gt_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 987 | TEST_REQUIRES_ARM_NEON_FMA; |
| 988 | for (size_t batch_size = 13; batch_size < 24; batch_size++) { |
| 989 | VUnOpMicrokernelTester() |
| 990 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 991 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 992 | } |
| 993 | } |
| 994 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 995 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X12, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 996 | TEST_REQUIRES_ARM_NEON_FMA; |
| 997 | for (size_t batch_size = 1; batch_size <= 60; batch_size += 11) { |
| 998 | VUnOpMicrokernelTester() |
| 999 | .batch_size(batch_size) |
| 1000 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1001 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1002 | } |
| 1003 | } |
| 1004 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1005 | |
| 1006 | |
| 1007 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1008 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X16, batch_eq_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1009 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1010 | VUnOpMicrokernelTester() |
| 1011 | .batch_size(16) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1012 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1013 | } |
| 1014 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1015 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X16, batch_div_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1016 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1017 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 1018 | VUnOpMicrokernelTester() |
| 1019 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1020 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1021 | } |
| 1022 | } |
| 1023 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1024 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X16, batch_lt_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1025 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1026 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 1027 | VUnOpMicrokernelTester() |
| 1028 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1029 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1030 | } |
| 1031 | } |
| 1032 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1033 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X16, batch_gt_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1034 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1035 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 1036 | VUnOpMicrokernelTester() |
| 1037 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1038 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1039 | } |
| 1040 | } |
| 1041 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1042 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X16, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1043 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1044 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1045 | VUnOpMicrokernelTester() |
| 1046 | .batch_size(batch_size) |
| 1047 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1048 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1049 | } |
| 1050 | } |
| 1051 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1052 | |
| 1053 | |
| 1054 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1055 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X20, batch_eq_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1056 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1057 | VUnOpMicrokernelTester() |
| 1058 | .batch_size(20) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1059 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1060 | } |
| 1061 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1062 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X20, batch_div_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1063 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1064 | for (size_t batch_size = 40; batch_size < 200; batch_size += 20) { |
| 1065 | VUnOpMicrokernelTester() |
| 1066 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1067 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1068 | } |
| 1069 | } |
| 1070 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1071 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X20, batch_lt_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1072 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1073 | for (size_t batch_size = 1; batch_size < 20; batch_size++) { |
| 1074 | VUnOpMicrokernelTester() |
| 1075 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1076 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1077 | } |
| 1078 | } |
| 1079 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1080 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X20, batch_gt_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1081 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1082 | for (size_t batch_size = 21; batch_size < 40; batch_size++) { |
| 1083 | VUnOpMicrokernelTester() |
| 1084 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1085 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1086 | } |
| 1087 | } |
| 1088 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1089 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X20, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1090 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1091 | for (size_t batch_size = 1; batch_size <= 100; batch_size += 19) { |
| 1092 | VUnOpMicrokernelTester() |
| 1093 | .batch_size(batch_size) |
| 1094 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1095 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1096 | } |
| 1097 | } |
| 1098 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1099 | |
| 1100 | |
| 1101 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1102 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X24, batch_eq_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1103 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1104 | VUnOpMicrokernelTester() |
| 1105 | .batch_size(24) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1106 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1107 | } |
| 1108 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1109 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X24, batch_div_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1110 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1111 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 1112 | VUnOpMicrokernelTester() |
| 1113 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1114 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1115 | } |
| 1116 | } |
| 1117 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1118 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X24, batch_lt_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1119 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1120 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 1121 | VUnOpMicrokernelTester() |
| 1122 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1123 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1124 | } |
| 1125 | } |
| 1126 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1127 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X24, batch_gt_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1128 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1129 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 1130 | VUnOpMicrokernelTester() |
| 1131 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1132 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1133 | } |
| 1134 | } |
| 1135 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1136 | TEST(F32_SIGMOID__NEONFMA_RR1_P5_NR2RECPS_X24, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1137 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1138 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1139 | VUnOpMicrokernelTester() |
| 1140 | .batch_size(batch_size) |
| 1141 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1142 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_p5_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1143 | } |
| 1144 | } |
| 1145 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1146 | |
| 1147 | |
| 1148 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1149 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X4, batch_eq_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1150 | TEST_REQUIRES_ARM_NEON; |
| 1151 | VUnOpMicrokernelTester() |
| 1152 | .batch_size(4) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1153 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1154 | } |
| 1155 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1156 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X4, batch_div_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1157 | TEST_REQUIRES_ARM_NEON; |
| 1158 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 1159 | VUnOpMicrokernelTester() |
| 1160 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1161 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1162 | } |
| 1163 | } |
| 1164 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1165 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X4, batch_lt_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1166 | TEST_REQUIRES_ARM_NEON; |
| 1167 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 1168 | VUnOpMicrokernelTester() |
| 1169 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1170 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1171 | } |
| 1172 | } |
| 1173 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1174 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X4, batch_gt_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1175 | TEST_REQUIRES_ARM_NEON; |
| 1176 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 1177 | VUnOpMicrokernelTester() |
| 1178 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1179 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1180 | } |
| 1181 | } |
| 1182 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1183 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X4, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1184 | TEST_REQUIRES_ARM_NEON; |
| 1185 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 1186 | VUnOpMicrokernelTester() |
| 1187 | .batch_size(batch_size) |
| 1188 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1189 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1190 | } |
| 1191 | } |
| 1192 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1193 | |
| 1194 | |
| 1195 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1196 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X8, batch_eq_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1197 | TEST_REQUIRES_ARM_NEON; |
| 1198 | VUnOpMicrokernelTester() |
| 1199 | .batch_size(8) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1200 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1201 | } |
| 1202 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1203 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X8, batch_div_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1204 | TEST_REQUIRES_ARM_NEON; |
| 1205 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 1206 | VUnOpMicrokernelTester() |
| 1207 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1208 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1209 | } |
| 1210 | } |
| 1211 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1212 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X8, batch_lt_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1213 | TEST_REQUIRES_ARM_NEON; |
| 1214 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 1215 | VUnOpMicrokernelTester() |
| 1216 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1217 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1218 | } |
| 1219 | } |
| 1220 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1221 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X8, batch_gt_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1222 | TEST_REQUIRES_ARM_NEON; |
| 1223 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 1224 | VUnOpMicrokernelTester() |
| 1225 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1226 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1227 | } |
| 1228 | } |
| 1229 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1230 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X8, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1231 | TEST_REQUIRES_ARM_NEON; |
| 1232 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 1233 | VUnOpMicrokernelTester() |
| 1234 | .batch_size(batch_size) |
| 1235 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1236 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1237 | } |
| 1238 | } |
| 1239 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1240 | |
| 1241 | |
| 1242 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1243 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X12, batch_eq_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1244 | TEST_REQUIRES_ARM_NEON; |
| 1245 | VUnOpMicrokernelTester() |
| 1246 | .batch_size(12) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1247 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1248 | } |
| 1249 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1250 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X12, batch_div_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1251 | TEST_REQUIRES_ARM_NEON; |
| 1252 | for (size_t batch_size = 24; batch_size < 120; batch_size += 12) { |
| 1253 | VUnOpMicrokernelTester() |
| 1254 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1255 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1256 | } |
| 1257 | } |
| 1258 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1259 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X12, batch_lt_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1260 | TEST_REQUIRES_ARM_NEON; |
| 1261 | for (size_t batch_size = 1; batch_size < 12; batch_size++) { |
| 1262 | VUnOpMicrokernelTester() |
| 1263 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1264 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1265 | } |
| 1266 | } |
| 1267 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1268 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X12, batch_gt_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1269 | TEST_REQUIRES_ARM_NEON; |
| 1270 | for (size_t batch_size = 13; batch_size < 24; batch_size++) { |
| 1271 | VUnOpMicrokernelTester() |
| 1272 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1273 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1274 | } |
| 1275 | } |
| 1276 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1277 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X12, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1278 | TEST_REQUIRES_ARM_NEON; |
| 1279 | for (size_t batch_size = 1; batch_size <= 60; batch_size += 11) { |
| 1280 | VUnOpMicrokernelTester() |
| 1281 | .batch_size(batch_size) |
| 1282 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1283 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1284 | } |
| 1285 | } |
| 1286 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1287 | |
| 1288 | |
| 1289 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1290 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X16, batch_eq_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1291 | TEST_REQUIRES_ARM_NEON; |
| 1292 | VUnOpMicrokernelTester() |
| 1293 | .batch_size(16) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1294 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1295 | } |
| 1296 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1297 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X16, batch_div_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1298 | TEST_REQUIRES_ARM_NEON; |
| 1299 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 1300 | VUnOpMicrokernelTester() |
| 1301 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1302 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1303 | } |
| 1304 | } |
| 1305 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1306 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X16, batch_lt_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1307 | TEST_REQUIRES_ARM_NEON; |
| 1308 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 1309 | VUnOpMicrokernelTester() |
| 1310 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1311 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1312 | } |
| 1313 | } |
| 1314 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1315 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X16, batch_gt_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1316 | TEST_REQUIRES_ARM_NEON; |
| 1317 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 1318 | VUnOpMicrokernelTester() |
| 1319 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1320 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1321 | } |
| 1322 | } |
| 1323 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1324 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X16, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1325 | TEST_REQUIRES_ARM_NEON; |
| 1326 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1327 | VUnOpMicrokernelTester() |
| 1328 | .batch_size(batch_size) |
| 1329 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1330 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1331 | } |
| 1332 | } |
| 1333 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1334 | |
| 1335 | |
| 1336 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1337 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X20, batch_eq_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1338 | TEST_REQUIRES_ARM_NEON; |
| 1339 | VUnOpMicrokernelTester() |
| 1340 | .batch_size(20) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1341 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1342 | } |
| 1343 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1344 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X20, batch_div_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1345 | TEST_REQUIRES_ARM_NEON; |
| 1346 | for (size_t batch_size = 40; batch_size < 200; batch_size += 20) { |
| 1347 | VUnOpMicrokernelTester() |
| 1348 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1349 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1350 | } |
| 1351 | } |
| 1352 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1353 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X20, batch_lt_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1354 | TEST_REQUIRES_ARM_NEON; |
| 1355 | for (size_t batch_size = 1; batch_size < 20; batch_size++) { |
| 1356 | VUnOpMicrokernelTester() |
| 1357 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1358 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1359 | } |
| 1360 | } |
| 1361 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1362 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X20, batch_gt_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1363 | TEST_REQUIRES_ARM_NEON; |
| 1364 | for (size_t batch_size = 21; batch_size < 40; batch_size++) { |
| 1365 | VUnOpMicrokernelTester() |
| 1366 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1367 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1368 | } |
| 1369 | } |
| 1370 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1371 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X20, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1372 | TEST_REQUIRES_ARM_NEON; |
| 1373 | for (size_t batch_size = 1; batch_size <= 100; batch_size += 19) { |
| 1374 | VUnOpMicrokernelTester() |
| 1375 | .batch_size(batch_size) |
| 1376 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1377 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1378 | } |
| 1379 | } |
| 1380 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1381 | |
| 1382 | |
| 1383 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1384 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X24, batch_eq_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1385 | TEST_REQUIRES_ARM_NEON; |
| 1386 | VUnOpMicrokernelTester() |
| 1387 | .batch_size(24) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1388 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1389 | } |
| 1390 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1391 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X24, batch_div_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1392 | TEST_REQUIRES_ARM_NEON; |
| 1393 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 1394 | VUnOpMicrokernelTester() |
| 1395 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1396 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1397 | } |
| 1398 | } |
| 1399 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1400 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X24, batch_lt_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1401 | TEST_REQUIRES_ARM_NEON; |
| 1402 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 1403 | VUnOpMicrokernelTester() |
| 1404 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1405 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1406 | } |
| 1407 | } |
| 1408 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1409 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X24, batch_gt_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1410 | TEST_REQUIRES_ARM_NEON; |
| 1411 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 1412 | VUnOpMicrokernelTester() |
| 1413 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1414 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1415 | } |
| 1416 | } |
| 1417 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1418 | TEST(F32_SIGMOID__NEON_RR2_P5_NR2RECPS_X24, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1419 | TEST_REQUIRES_ARM_NEON; |
| 1420 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1421 | VUnOpMicrokernelTester() |
| 1422 | .batch_size(batch_size) |
| 1423 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1424 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_p5_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 1425 | } |
| 1426 | } |
| 1427 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1428 | |
| 1429 | |
| 1430 | #if XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1431 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X4, batch_eq_4) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1432 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1433 | VUnOpMicrokernelTester() |
| 1434 | .batch_size(4) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1435 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1436 | } |
| 1437 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1438 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X4, batch_div_4) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1439 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1440 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 1441 | VUnOpMicrokernelTester() |
| 1442 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1443 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1444 | } |
| 1445 | } |
| 1446 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1447 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X4, batch_lt_4) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1448 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1449 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 1450 | VUnOpMicrokernelTester() |
| 1451 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1452 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1453 | } |
| 1454 | } |
| 1455 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1456 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X4, batch_gt_4) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1457 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1458 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 1459 | VUnOpMicrokernelTester() |
| 1460 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1461 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1462 | } |
| 1463 | } |
| 1464 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1465 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X4, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1466 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1467 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 1468 | VUnOpMicrokernelTester() |
| 1469 | .batch_size(batch_size) |
| 1470 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1471 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1472 | } |
| 1473 | } |
| 1474 | #endif // XNN_ARCH_ARM64 |
| 1475 | |
| 1476 | |
| 1477 | #if XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1478 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X8, batch_eq_8) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1479 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1480 | VUnOpMicrokernelTester() |
| 1481 | .batch_size(8) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1482 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1483 | } |
| 1484 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1485 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X8, batch_div_8) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1486 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1487 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 1488 | VUnOpMicrokernelTester() |
| 1489 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1490 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1491 | } |
| 1492 | } |
| 1493 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1494 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X8, batch_lt_8) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1495 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1496 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 1497 | VUnOpMicrokernelTester() |
| 1498 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1499 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1500 | } |
| 1501 | } |
| 1502 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1503 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X8, batch_gt_8) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1504 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1505 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 1506 | VUnOpMicrokernelTester() |
| 1507 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1508 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1509 | } |
| 1510 | } |
| 1511 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1512 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X8, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1513 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1514 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 1515 | VUnOpMicrokernelTester() |
| 1516 | .batch_size(batch_size) |
| 1517 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1518 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1519 | } |
| 1520 | } |
| 1521 | #endif // XNN_ARCH_ARM64 |
| 1522 | |
| 1523 | |
| 1524 | #if XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1525 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X12, batch_eq_12) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1526 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1527 | VUnOpMicrokernelTester() |
| 1528 | .batch_size(12) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1529 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1530 | } |
| 1531 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1532 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X12, batch_div_12) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1533 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1534 | for (size_t batch_size = 24; batch_size < 120; batch_size += 12) { |
| 1535 | VUnOpMicrokernelTester() |
| 1536 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1537 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1538 | } |
| 1539 | } |
| 1540 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1541 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X12, batch_lt_12) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1542 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1543 | for (size_t batch_size = 1; batch_size < 12; batch_size++) { |
| 1544 | VUnOpMicrokernelTester() |
| 1545 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1546 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1547 | } |
| 1548 | } |
| 1549 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1550 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X12, batch_gt_12) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1551 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1552 | for (size_t batch_size = 13; batch_size < 24; batch_size++) { |
| 1553 | VUnOpMicrokernelTester() |
| 1554 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1555 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1556 | } |
| 1557 | } |
| 1558 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1559 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X12, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1560 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1561 | for (size_t batch_size = 1; batch_size <= 60; batch_size += 11) { |
| 1562 | VUnOpMicrokernelTester() |
| 1563 | .batch_size(batch_size) |
| 1564 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1565 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1566 | } |
| 1567 | } |
| 1568 | #endif // XNN_ARCH_ARM64 |
| 1569 | |
| 1570 | |
| 1571 | #if XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1572 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X16, batch_eq_16) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1573 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1574 | VUnOpMicrokernelTester() |
| 1575 | .batch_size(16) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1576 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1577 | } |
| 1578 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1579 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X16, batch_div_16) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1580 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1581 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 1582 | VUnOpMicrokernelTester() |
| 1583 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1584 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1585 | } |
| 1586 | } |
| 1587 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1588 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X16, batch_lt_16) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1589 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1590 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 1591 | VUnOpMicrokernelTester() |
| 1592 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1593 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1594 | } |
| 1595 | } |
| 1596 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1597 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X16, batch_gt_16) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1598 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1599 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 1600 | VUnOpMicrokernelTester() |
| 1601 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1602 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1603 | } |
| 1604 | } |
| 1605 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1606 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X16, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1607 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1608 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1609 | VUnOpMicrokernelTester() |
| 1610 | .batch_size(batch_size) |
| 1611 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1612 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1613 | } |
| 1614 | } |
| 1615 | #endif // XNN_ARCH_ARM64 |
| 1616 | |
| 1617 | |
| 1618 | #if XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1619 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X20, batch_eq_20) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1620 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1621 | VUnOpMicrokernelTester() |
| 1622 | .batch_size(20) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1623 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1624 | } |
| 1625 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1626 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X20, batch_div_20) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1627 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1628 | for (size_t batch_size = 40; batch_size < 200; batch_size += 20) { |
| 1629 | VUnOpMicrokernelTester() |
| 1630 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1631 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1632 | } |
| 1633 | } |
| 1634 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1635 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X20, batch_lt_20) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1636 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1637 | for (size_t batch_size = 1; batch_size < 20; batch_size++) { |
| 1638 | VUnOpMicrokernelTester() |
| 1639 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1640 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1641 | } |
| 1642 | } |
| 1643 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1644 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X20, batch_gt_20) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1645 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1646 | for (size_t batch_size = 21; batch_size < 40; batch_size++) { |
| 1647 | VUnOpMicrokernelTester() |
| 1648 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1649 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1650 | } |
| 1651 | } |
| 1652 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1653 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X20, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1654 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1655 | for (size_t batch_size = 1; batch_size <= 100; batch_size += 19) { |
| 1656 | VUnOpMicrokernelTester() |
| 1657 | .batch_size(batch_size) |
| 1658 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1659 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1660 | } |
| 1661 | } |
| 1662 | #endif // XNN_ARCH_ARM64 |
| 1663 | |
| 1664 | |
| 1665 | #if XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1666 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X24, batch_eq_24) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1667 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1668 | VUnOpMicrokernelTester() |
| 1669 | .batch_size(24) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1670 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1671 | } |
| 1672 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1673 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X24, batch_div_24) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1674 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1675 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 1676 | VUnOpMicrokernelTester() |
| 1677 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1678 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1679 | } |
| 1680 | } |
| 1681 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1682 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X24, batch_lt_24) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1683 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1684 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 1685 | VUnOpMicrokernelTester() |
| 1686 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1687 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1688 | } |
| 1689 | } |
| 1690 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1691 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X24, batch_gt_24) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1692 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1693 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 1694 | VUnOpMicrokernelTester() |
| 1695 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1696 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1697 | } |
| 1698 | } |
| 1699 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1700 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_DIV_X24, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1701 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1702 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1703 | VUnOpMicrokernelTester() |
| 1704 | .batch_size(batch_size) |
| 1705 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1706 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1707 | } |
| 1708 | } |
| 1709 | #endif // XNN_ARCH_ARM64 |
| 1710 | |
| 1711 | |
| 1712 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1713 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X4, batch_eq_4) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1714 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1715 | VUnOpMicrokernelTester() |
| 1716 | .batch_size(4) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1717 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1718 | } |
| 1719 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1720 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X4, batch_div_4) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1721 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1722 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 1723 | VUnOpMicrokernelTester() |
| 1724 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1725 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1726 | } |
| 1727 | } |
| 1728 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1729 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X4, batch_lt_4) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1730 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1731 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 1732 | VUnOpMicrokernelTester() |
| 1733 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1734 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1735 | } |
| 1736 | } |
| 1737 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1738 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X4, batch_gt_4) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1739 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1740 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 1741 | VUnOpMicrokernelTester() |
| 1742 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1743 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1744 | } |
| 1745 | } |
| 1746 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1747 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X4, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1748 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1749 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 1750 | VUnOpMicrokernelTester() |
| 1751 | .batch_size(batch_size) |
| 1752 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1753 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1754 | } |
| 1755 | } |
| 1756 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1757 | |
| 1758 | |
| 1759 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1760 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X8, batch_eq_8) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1761 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1762 | VUnOpMicrokernelTester() |
| 1763 | .batch_size(8) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1764 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1765 | } |
| 1766 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1767 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X8, batch_div_8) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1768 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1769 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 1770 | VUnOpMicrokernelTester() |
| 1771 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1772 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1773 | } |
| 1774 | } |
| 1775 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1776 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X8, batch_lt_8) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1777 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1778 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 1779 | VUnOpMicrokernelTester() |
| 1780 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1781 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1782 | } |
| 1783 | } |
| 1784 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1785 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X8, batch_gt_8) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1786 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1787 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 1788 | VUnOpMicrokernelTester() |
| 1789 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1790 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1791 | } |
| 1792 | } |
| 1793 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1794 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X8, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1795 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1796 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 1797 | VUnOpMicrokernelTester() |
| 1798 | .batch_size(batch_size) |
| 1799 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1800 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1801 | } |
| 1802 | } |
| 1803 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1804 | |
| 1805 | |
| 1806 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1807 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X12, batch_eq_12) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1808 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1809 | VUnOpMicrokernelTester() |
| 1810 | .batch_size(12) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1811 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1812 | } |
| 1813 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1814 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X12, batch_div_12) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1815 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1816 | for (size_t batch_size = 24; batch_size < 120; batch_size += 12) { |
| 1817 | VUnOpMicrokernelTester() |
| 1818 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1819 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1820 | } |
| 1821 | } |
| 1822 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1823 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X12, batch_lt_12) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1824 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1825 | for (size_t batch_size = 1; batch_size < 12; batch_size++) { |
| 1826 | VUnOpMicrokernelTester() |
| 1827 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1828 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1829 | } |
| 1830 | } |
| 1831 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1832 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X12, batch_gt_12) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1833 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1834 | for (size_t batch_size = 13; batch_size < 24; batch_size++) { |
| 1835 | VUnOpMicrokernelTester() |
| 1836 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1837 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1838 | } |
| 1839 | } |
| 1840 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1841 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X12, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1842 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1843 | for (size_t batch_size = 1; batch_size <= 60; batch_size += 11) { |
| 1844 | VUnOpMicrokernelTester() |
| 1845 | .batch_size(batch_size) |
| 1846 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1847 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1848 | } |
| 1849 | } |
| 1850 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1851 | |
| 1852 | |
| 1853 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1854 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X16, batch_eq_16) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1855 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1856 | VUnOpMicrokernelTester() |
| 1857 | .batch_size(16) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1858 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1859 | } |
| 1860 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1861 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X16, batch_div_16) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1862 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1863 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 1864 | VUnOpMicrokernelTester() |
| 1865 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1866 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1867 | } |
| 1868 | } |
| 1869 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1870 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X16, batch_lt_16) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1871 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1872 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 1873 | VUnOpMicrokernelTester() |
| 1874 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1875 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1876 | } |
| 1877 | } |
| 1878 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1879 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X16, batch_gt_16) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1880 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1881 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 1882 | VUnOpMicrokernelTester() |
| 1883 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1884 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1885 | } |
| 1886 | } |
| 1887 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1888 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X16, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1889 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1890 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1891 | VUnOpMicrokernelTester() |
| 1892 | .batch_size(batch_size) |
| 1893 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1894 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1895 | } |
| 1896 | } |
| 1897 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1898 | |
| 1899 | |
| 1900 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1901 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X20, batch_eq_20) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1902 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1903 | VUnOpMicrokernelTester() |
| 1904 | .batch_size(20) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1905 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1906 | } |
| 1907 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1908 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X20, batch_div_20) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1909 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1910 | for (size_t batch_size = 40; batch_size < 200; batch_size += 20) { |
| 1911 | VUnOpMicrokernelTester() |
| 1912 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1913 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1914 | } |
| 1915 | } |
| 1916 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1917 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X20, batch_lt_20) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1918 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1919 | for (size_t batch_size = 1; batch_size < 20; batch_size++) { |
| 1920 | VUnOpMicrokernelTester() |
| 1921 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1922 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1923 | } |
| 1924 | } |
| 1925 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1926 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X20, batch_gt_20) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1927 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1928 | for (size_t batch_size = 21; batch_size < 40; batch_size++) { |
| 1929 | VUnOpMicrokernelTester() |
| 1930 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1931 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1932 | } |
| 1933 | } |
| 1934 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1935 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X20, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1936 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1937 | for (size_t batch_size = 1; batch_size <= 100; batch_size += 19) { |
| 1938 | VUnOpMicrokernelTester() |
| 1939 | .batch_size(batch_size) |
| 1940 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1941 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1942 | } |
| 1943 | } |
| 1944 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1945 | |
| 1946 | |
| 1947 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1948 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X24, batch_eq_24) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1949 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1950 | VUnOpMicrokernelTester() |
| 1951 | .batch_size(24) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1952 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1953 | } |
| 1954 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1955 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X24, batch_div_24) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1956 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1957 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 1958 | VUnOpMicrokernelTester() |
| 1959 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1960 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1961 | } |
| 1962 | } |
| 1963 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1964 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X24, batch_lt_24) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1965 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1966 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 1967 | VUnOpMicrokernelTester() |
| 1968 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1969 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1970 | } |
| 1971 | } |
| 1972 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1973 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X24, batch_gt_24) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1974 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1975 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 1976 | VUnOpMicrokernelTester() |
| 1977 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1978 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1979 | } |
| 1980 | } |
| 1981 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1982 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2FMA_X24, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1983 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1984 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1985 | VUnOpMicrokernelTester() |
| 1986 | .batch_size(batch_size) |
| 1987 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1988 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1989 | } |
| 1990 | } |
| 1991 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1992 | |
| 1993 | |
| 1994 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1995 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X4, batch_eq_4) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 1996 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1997 | VUnOpMicrokernelTester() |
| 1998 | .batch_size(4) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 1999 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2000 | } |
| 2001 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2002 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X4, batch_div_4) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2003 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2004 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 2005 | VUnOpMicrokernelTester() |
| 2006 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2007 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2008 | } |
| 2009 | } |
| 2010 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2011 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X4, batch_lt_4) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2012 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2013 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 2014 | VUnOpMicrokernelTester() |
| 2015 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2016 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2017 | } |
| 2018 | } |
| 2019 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2020 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X4, batch_gt_4) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2021 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2022 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 2023 | VUnOpMicrokernelTester() |
| 2024 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2025 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2026 | } |
| 2027 | } |
| 2028 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2029 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X4, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2030 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2031 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 2032 | VUnOpMicrokernelTester() |
| 2033 | .batch_size(batch_size) |
| 2034 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2035 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2036 | } |
| 2037 | } |
| 2038 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2039 | |
| 2040 | |
| 2041 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2042 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X8, batch_eq_8) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2043 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2044 | VUnOpMicrokernelTester() |
| 2045 | .batch_size(8) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2046 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2047 | } |
| 2048 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2049 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X8, batch_div_8) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2050 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2051 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 2052 | VUnOpMicrokernelTester() |
| 2053 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2054 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2055 | } |
| 2056 | } |
| 2057 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2058 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X8, batch_lt_8) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2059 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2060 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 2061 | VUnOpMicrokernelTester() |
| 2062 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2063 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2064 | } |
| 2065 | } |
| 2066 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2067 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X8, batch_gt_8) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2068 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2069 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 2070 | VUnOpMicrokernelTester() |
| 2071 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2072 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2073 | } |
| 2074 | } |
| 2075 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2076 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X8, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2077 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2078 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 2079 | VUnOpMicrokernelTester() |
| 2080 | .batch_size(batch_size) |
| 2081 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2082 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2083 | } |
| 2084 | } |
| 2085 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2086 | |
| 2087 | |
| 2088 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2089 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X12, batch_eq_12) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2090 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2091 | VUnOpMicrokernelTester() |
| 2092 | .batch_size(12) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2093 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2094 | } |
| 2095 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2096 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X12, batch_div_12) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2097 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2098 | for (size_t batch_size = 24; batch_size < 120; batch_size += 12) { |
| 2099 | VUnOpMicrokernelTester() |
| 2100 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2101 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2102 | } |
| 2103 | } |
| 2104 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2105 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X12, batch_lt_12) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2106 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2107 | for (size_t batch_size = 1; batch_size < 12; batch_size++) { |
| 2108 | VUnOpMicrokernelTester() |
| 2109 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2110 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2111 | } |
| 2112 | } |
| 2113 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2114 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X12, batch_gt_12) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2115 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2116 | for (size_t batch_size = 13; batch_size < 24; batch_size++) { |
| 2117 | VUnOpMicrokernelTester() |
| 2118 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2119 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2120 | } |
| 2121 | } |
| 2122 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2123 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X12, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2124 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2125 | for (size_t batch_size = 1; batch_size <= 60; batch_size += 11) { |
| 2126 | VUnOpMicrokernelTester() |
| 2127 | .batch_size(batch_size) |
| 2128 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2129 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2130 | } |
| 2131 | } |
| 2132 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2133 | |
| 2134 | |
| 2135 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2136 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X16, batch_eq_16) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2137 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2138 | VUnOpMicrokernelTester() |
| 2139 | .batch_size(16) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2140 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2141 | } |
| 2142 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2143 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X16, batch_div_16) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2144 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2145 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 2146 | VUnOpMicrokernelTester() |
| 2147 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2148 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2149 | } |
| 2150 | } |
| 2151 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2152 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X16, batch_lt_16) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2153 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2154 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 2155 | VUnOpMicrokernelTester() |
| 2156 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2157 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2158 | } |
| 2159 | } |
| 2160 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2161 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X16, batch_gt_16) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2162 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2163 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 2164 | VUnOpMicrokernelTester() |
| 2165 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2166 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2167 | } |
| 2168 | } |
| 2169 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2170 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X16, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2171 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2172 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 2173 | VUnOpMicrokernelTester() |
| 2174 | .batch_size(batch_size) |
| 2175 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2176 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2177 | } |
| 2178 | } |
| 2179 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2180 | |
| 2181 | |
| 2182 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2183 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X20, batch_eq_20) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2184 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2185 | VUnOpMicrokernelTester() |
| 2186 | .batch_size(20) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2187 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2188 | } |
| 2189 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2190 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X20, batch_div_20) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2191 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2192 | for (size_t batch_size = 40; batch_size < 200; batch_size += 20) { |
| 2193 | VUnOpMicrokernelTester() |
| 2194 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2195 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2196 | } |
| 2197 | } |
| 2198 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2199 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X20, batch_lt_20) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2200 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2201 | for (size_t batch_size = 1; batch_size < 20; batch_size++) { |
| 2202 | VUnOpMicrokernelTester() |
| 2203 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2204 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2205 | } |
| 2206 | } |
| 2207 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2208 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X20, batch_gt_20) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2209 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2210 | for (size_t batch_size = 21; batch_size < 40; batch_size++) { |
| 2211 | VUnOpMicrokernelTester() |
| 2212 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2213 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2214 | } |
| 2215 | } |
| 2216 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2217 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X20, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2218 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2219 | for (size_t batch_size = 1; batch_size <= 100; batch_size += 19) { |
| 2220 | VUnOpMicrokernelTester() |
| 2221 | .batch_size(batch_size) |
| 2222 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2223 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2224 | } |
| 2225 | } |
| 2226 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2227 | |
| 2228 | |
| 2229 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2230 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X24, batch_eq_24) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2231 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2232 | VUnOpMicrokernelTester() |
| 2233 | .batch_size(24) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2234 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2235 | } |
| 2236 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2237 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X24, batch_div_24) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2238 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2239 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 2240 | VUnOpMicrokernelTester() |
| 2241 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2242 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2243 | } |
| 2244 | } |
| 2245 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2246 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X24, batch_lt_24) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2247 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2248 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 2249 | VUnOpMicrokernelTester() |
| 2250 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2251 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2252 | } |
| 2253 | } |
| 2254 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2255 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X24, batch_gt_24) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2256 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2257 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 2258 | VUnOpMicrokernelTester() |
| 2259 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2260 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2261 | } |
| 2262 | } |
| 2263 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2264 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR1RECPS1FMA_X24, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2265 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2266 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 2267 | VUnOpMicrokernelTester() |
| 2268 | .batch_size(batch_size) |
| 2269 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2270 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr1recps1fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2271 | } |
| 2272 | } |
| 2273 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2274 | |
| 2275 | |
| 2276 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2277 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X4, batch_eq_4) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2278 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2279 | VUnOpMicrokernelTester() |
| 2280 | .batch_size(4) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2281 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2282 | } |
| 2283 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2284 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X4, batch_div_4) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2285 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2286 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 2287 | VUnOpMicrokernelTester() |
| 2288 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2289 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2290 | } |
| 2291 | } |
| 2292 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2293 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X4, batch_lt_4) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2294 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2295 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 2296 | VUnOpMicrokernelTester() |
| 2297 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2298 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2299 | } |
| 2300 | } |
| 2301 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2302 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X4, batch_gt_4) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2303 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2304 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 2305 | VUnOpMicrokernelTester() |
| 2306 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2307 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2308 | } |
| 2309 | } |
| 2310 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2311 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X4, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2312 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2313 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 2314 | VUnOpMicrokernelTester() |
| 2315 | .batch_size(batch_size) |
| 2316 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2317 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2318 | } |
| 2319 | } |
| 2320 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2321 | |
| 2322 | |
| 2323 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2324 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X8, batch_eq_8) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2325 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2326 | VUnOpMicrokernelTester() |
| 2327 | .batch_size(8) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2328 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2329 | } |
| 2330 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2331 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X8, batch_div_8) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2332 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2333 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 2334 | VUnOpMicrokernelTester() |
| 2335 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2336 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2337 | } |
| 2338 | } |
| 2339 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2340 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X8, batch_lt_8) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2341 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2342 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 2343 | VUnOpMicrokernelTester() |
| 2344 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2345 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2346 | } |
| 2347 | } |
| 2348 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2349 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X8, batch_gt_8) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2350 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2351 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 2352 | VUnOpMicrokernelTester() |
| 2353 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2354 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2355 | } |
| 2356 | } |
| 2357 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2358 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X8, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2359 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2360 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 2361 | VUnOpMicrokernelTester() |
| 2362 | .batch_size(batch_size) |
| 2363 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2364 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2365 | } |
| 2366 | } |
| 2367 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2368 | |
| 2369 | |
| 2370 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2371 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X12, batch_eq_12) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2372 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2373 | VUnOpMicrokernelTester() |
| 2374 | .batch_size(12) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2375 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2376 | } |
| 2377 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2378 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X12, batch_div_12) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2379 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2380 | for (size_t batch_size = 24; batch_size < 120; batch_size += 12) { |
| 2381 | VUnOpMicrokernelTester() |
| 2382 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2383 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2384 | } |
| 2385 | } |
| 2386 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2387 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X12, batch_lt_12) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2388 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2389 | for (size_t batch_size = 1; batch_size < 12; batch_size++) { |
| 2390 | VUnOpMicrokernelTester() |
| 2391 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2392 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2393 | } |
| 2394 | } |
| 2395 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2396 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X12, batch_gt_12) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2397 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2398 | for (size_t batch_size = 13; batch_size < 24; batch_size++) { |
| 2399 | VUnOpMicrokernelTester() |
| 2400 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2401 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2402 | } |
| 2403 | } |
| 2404 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2405 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X12, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2406 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2407 | for (size_t batch_size = 1; batch_size <= 60; batch_size += 11) { |
| 2408 | VUnOpMicrokernelTester() |
| 2409 | .batch_size(batch_size) |
| 2410 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2411 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2412 | } |
| 2413 | } |
| 2414 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2415 | |
| 2416 | |
| 2417 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2418 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X16, batch_eq_16) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2419 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2420 | VUnOpMicrokernelTester() |
| 2421 | .batch_size(16) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2422 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2423 | } |
| 2424 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2425 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X16, batch_div_16) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2426 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2427 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 2428 | VUnOpMicrokernelTester() |
| 2429 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2430 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2431 | } |
| 2432 | } |
| 2433 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2434 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X16, batch_lt_16) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2435 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2436 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 2437 | VUnOpMicrokernelTester() |
| 2438 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2439 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2440 | } |
| 2441 | } |
| 2442 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2443 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X16, batch_gt_16) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2444 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2445 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 2446 | VUnOpMicrokernelTester() |
| 2447 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2448 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2449 | } |
| 2450 | } |
| 2451 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2452 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X16, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2453 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2454 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 2455 | VUnOpMicrokernelTester() |
| 2456 | .batch_size(batch_size) |
| 2457 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2458 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2459 | } |
| 2460 | } |
| 2461 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2462 | |
| 2463 | |
| 2464 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2465 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X20, batch_eq_20) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2466 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2467 | VUnOpMicrokernelTester() |
| 2468 | .batch_size(20) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2469 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2470 | } |
| 2471 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2472 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X20, batch_div_20) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2473 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2474 | for (size_t batch_size = 40; batch_size < 200; batch_size += 20) { |
| 2475 | VUnOpMicrokernelTester() |
| 2476 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2477 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2478 | } |
| 2479 | } |
| 2480 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2481 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X20, batch_lt_20) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2482 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2483 | for (size_t batch_size = 1; batch_size < 20; batch_size++) { |
| 2484 | VUnOpMicrokernelTester() |
| 2485 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2486 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2487 | } |
| 2488 | } |
| 2489 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2490 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X20, batch_gt_20) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2491 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2492 | for (size_t batch_size = 21; batch_size < 40; batch_size++) { |
| 2493 | VUnOpMicrokernelTester() |
| 2494 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2495 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2496 | } |
| 2497 | } |
| 2498 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2499 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X20, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2500 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2501 | for (size_t batch_size = 1; batch_size <= 100; batch_size += 19) { |
| 2502 | VUnOpMicrokernelTester() |
| 2503 | .batch_size(batch_size) |
| 2504 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2505 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2506 | } |
| 2507 | } |
| 2508 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2509 | |
| 2510 | |
| 2511 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2512 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X24, batch_eq_24) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2513 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2514 | VUnOpMicrokernelTester() |
| 2515 | .batch_size(24) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2516 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2517 | } |
| 2518 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2519 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X24, batch_div_24) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2520 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2521 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 2522 | VUnOpMicrokernelTester() |
| 2523 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2524 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2525 | } |
| 2526 | } |
| 2527 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2528 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X24, batch_lt_24) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2529 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2530 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 2531 | VUnOpMicrokernelTester() |
| 2532 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2533 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2534 | } |
| 2535 | } |
| 2536 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2537 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X24, batch_gt_24) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2538 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2539 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 2540 | VUnOpMicrokernelTester() |
| 2541 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2542 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2543 | } |
| 2544 | } |
| 2545 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2546 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT64_P2_NR2RECPS_X24, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2547 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2548 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 2549 | VUnOpMicrokernelTester() |
| 2550 | .batch_size(batch_size) |
| 2551 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2552 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut64_p2_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2553 | } |
| 2554 | } |
| 2555 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2556 | |
| 2557 | |
| 2558 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2559 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X4, batch_eq_4) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2560 | TEST_REQUIRES_ARM_NEON; |
| 2561 | VUnOpMicrokernelTester() |
| 2562 | .batch_size(4) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2563 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2564 | } |
| 2565 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2566 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X4, batch_div_4) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2567 | TEST_REQUIRES_ARM_NEON; |
| 2568 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 2569 | VUnOpMicrokernelTester() |
| 2570 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2571 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2572 | } |
| 2573 | } |
| 2574 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2575 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X4, batch_lt_4) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2576 | TEST_REQUIRES_ARM_NEON; |
| 2577 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 2578 | VUnOpMicrokernelTester() |
| 2579 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2580 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2581 | } |
| 2582 | } |
| 2583 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2584 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X4, batch_gt_4) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2585 | TEST_REQUIRES_ARM_NEON; |
| 2586 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 2587 | VUnOpMicrokernelTester() |
| 2588 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2589 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2590 | } |
| 2591 | } |
| 2592 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2593 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X4, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2594 | TEST_REQUIRES_ARM_NEON; |
| 2595 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 2596 | VUnOpMicrokernelTester() |
| 2597 | .batch_size(batch_size) |
| 2598 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2599 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2600 | } |
| 2601 | } |
| 2602 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2603 | |
| 2604 | |
| 2605 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2606 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X8, batch_eq_8) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2607 | TEST_REQUIRES_ARM_NEON; |
| 2608 | VUnOpMicrokernelTester() |
| 2609 | .batch_size(8) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2610 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2611 | } |
| 2612 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2613 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X8, batch_div_8) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2614 | TEST_REQUIRES_ARM_NEON; |
| 2615 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 2616 | VUnOpMicrokernelTester() |
| 2617 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2618 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2619 | } |
| 2620 | } |
| 2621 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2622 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X8, batch_lt_8) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2623 | TEST_REQUIRES_ARM_NEON; |
| 2624 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 2625 | VUnOpMicrokernelTester() |
| 2626 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2627 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2628 | } |
| 2629 | } |
| 2630 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2631 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X8, batch_gt_8) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2632 | TEST_REQUIRES_ARM_NEON; |
| 2633 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 2634 | VUnOpMicrokernelTester() |
| 2635 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2636 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2637 | } |
| 2638 | } |
| 2639 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2640 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X8, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2641 | TEST_REQUIRES_ARM_NEON; |
| 2642 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 2643 | VUnOpMicrokernelTester() |
| 2644 | .batch_size(batch_size) |
| 2645 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2646 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2647 | } |
| 2648 | } |
| 2649 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2650 | |
| 2651 | |
| 2652 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2653 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X12, batch_eq_12) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2654 | TEST_REQUIRES_ARM_NEON; |
| 2655 | VUnOpMicrokernelTester() |
| 2656 | .batch_size(12) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2657 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2658 | } |
| 2659 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2660 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X12, batch_div_12) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2661 | TEST_REQUIRES_ARM_NEON; |
| 2662 | for (size_t batch_size = 24; batch_size < 120; batch_size += 12) { |
| 2663 | VUnOpMicrokernelTester() |
| 2664 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2665 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2666 | } |
| 2667 | } |
| 2668 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2669 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X12, batch_lt_12) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2670 | TEST_REQUIRES_ARM_NEON; |
| 2671 | for (size_t batch_size = 1; batch_size < 12; batch_size++) { |
| 2672 | VUnOpMicrokernelTester() |
| 2673 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2674 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2675 | } |
| 2676 | } |
| 2677 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2678 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X12, batch_gt_12) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2679 | TEST_REQUIRES_ARM_NEON; |
| 2680 | for (size_t batch_size = 13; batch_size < 24; batch_size++) { |
| 2681 | VUnOpMicrokernelTester() |
| 2682 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2683 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2684 | } |
| 2685 | } |
| 2686 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2687 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X12, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2688 | TEST_REQUIRES_ARM_NEON; |
| 2689 | for (size_t batch_size = 1; batch_size <= 60; batch_size += 11) { |
| 2690 | VUnOpMicrokernelTester() |
| 2691 | .batch_size(batch_size) |
| 2692 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2693 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2694 | } |
| 2695 | } |
| 2696 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2697 | |
| 2698 | |
| 2699 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2700 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X16, batch_eq_16) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2701 | TEST_REQUIRES_ARM_NEON; |
| 2702 | VUnOpMicrokernelTester() |
| 2703 | .batch_size(16) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2704 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2705 | } |
| 2706 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2707 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X16, batch_div_16) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2708 | TEST_REQUIRES_ARM_NEON; |
| 2709 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 2710 | VUnOpMicrokernelTester() |
| 2711 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2712 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2713 | } |
| 2714 | } |
| 2715 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2716 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X16, batch_lt_16) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2717 | TEST_REQUIRES_ARM_NEON; |
| 2718 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 2719 | VUnOpMicrokernelTester() |
| 2720 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2721 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2722 | } |
| 2723 | } |
| 2724 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2725 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X16, batch_gt_16) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2726 | TEST_REQUIRES_ARM_NEON; |
| 2727 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 2728 | VUnOpMicrokernelTester() |
| 2729 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2730 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2731 | } |
| 2732 | } |
| 2733 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2734 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X16, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2735 | TEST_REQUIRES_ARM_NEON; |
| 2736 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 2737 | VUnOpMicrokernelTester() |
| 2738 | .batch_size(batch_size) |
| 2739 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2740 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2741 | } |
| 2742 | } |
| 2743 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2744 | |
| 2745 | |
| 2746 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2747 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X20, batch_eq_20) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2748 | TEST_REQUIRES_ARM_NEON; |
| 2749 | VUnOpMicrokernelTester() |
| 2750 | .batch_size(20) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2751 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2752 | } |
| 2753 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2754 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X20, batch_div_20) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2755 | TEST_REQUIRES_ARM_NEON; |
| 2756 | for (size_t batch_size = 40; batch_size < 200; batch_size += 20) { |
| 2757 | VUnOpMicrokernelTester() |
| 2758 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2759 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2760 | } |
| 2761 | } |
| 2762 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2763 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X20, batch_lt_20) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2764 | TEST_REQUIRES_ARM_NEON; |
| 2765 | for (size_t batch_size = 1; batch_size < 20; batch_size++) { |
| 2766 | VUnOpMicrokernelTester() |
| 2767 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2768 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2769 | } |
| 2770 | } |
| 2771 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2772 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X20, batch_gt_20) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2773 | TEST_REQUIRES_ARM_NEON; |
| 2774 | for (size_t batch_size = 21; batch_size < 40; batch_size++) { |
| 2775 | VUnOpMicrokernelTester() |
| 2776 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2777 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2778 | } |
| 2779 | } |
| 2780 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2781 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X20, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2782 | TEST_REQUIRES_ARM_NEON; |
| 2783 | for (size_t batch_size = 1; batch_size <= 100; batch_size += 19) { |
| 2784 | VUnOpMicrokernelTester() |
| 2785 | .batch_size(batch_size) |
| 2786 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2787 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2788 | } |
| 2789 | } |
| 2790 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2791 | |
| 2792 | |
| 2793 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2794 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X24, batch_eq_24) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2795 | TEST_REQUIRES_ARM_NEON; |
| 2796 | VUnOpMicrokernelTester() |
| 2797 | .batch_size(24) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2798 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2799 | } |
| 2800 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2801 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X24, batch_div_24) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2802 | TEST_REQUIRES_ARM_NEON; |
| 2803 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 2804 | VUnOpMicrokernelTester() |
| 2805 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2806 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2807 | } |
| 2808 | } |
| 2809 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2810 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X24, batch_lt_24) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2811 | TEST_REQUIRES_ARM_NEON; |
| 2812 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 2813 | VUnOpMicrokernelTester() |
| 2814 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2815 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2816 | } |
| 2817 | } |
| 2818 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2819 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X24, batch_gt_24) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2820 | TEST_REQUIRES_ARM_NEON; |
| 2821 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 2822 | VUnOpMicrokernelTester() |
| 2823 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2824 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2825 | } |
| 2826 | } |
| 2827 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2828 | TEST(F32_SIGMOID__NEON_RR2_LUT64_P2_NR2RECPS_X24, inplace) { |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2829 | TEST_REQUIRES_ARM_NEON; |
| 2830 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 2831 | VUnOpMicrokernelTester() |
| 2832 | .batch_size(batch_size) |
| 2833 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2834 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut64_p2_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 68b3b45 | 2020-01-02 10:11:15 -0800 | [diff] [blame] | 2835 | } |
| 2836 | } |
| 2837 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2838 | |
| 2839 | |
| 2840 | #if XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2841 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X4, batch_eq_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2842 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2843 | VUnOpMicrokernelTester() |
| 2844 | .batch_size(4) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2845 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2846 | } |
| 2847 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2848 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X4, batch_div_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2849 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2850 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 2851 | VUnOpMicrokernelTester() |
| 2852 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2853 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2854 | } |
| 2855 | } |
| 2856 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2857 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X4, batch_lt_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2858 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2859 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 2860 | VUnOpMicrokernelTester() |
| 2861 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2862 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2863 | } |
| 2864 | } |
| 2865 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2866 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X4, batch_gt_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2867 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2868 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 2869 | VUnOpMicrokernelTester() |
| 2870 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2871 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2872 | } |
| 2873 | } |
| 2874 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2875 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X4, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2876 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2877 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 2878 | VUnOpMicrokernelTester() |
| 2879 | .batch_size(batch_size) |
| 2880 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2881 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2882 | } |
| 2883 | } |
| 2884 | #endif // XNN_ARCH_ARM64 |
| 2885 | |
| 2886 | |
| 2887 | #if XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2888 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X8, batch_eq_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2889 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2890 | VUnOpMicrokernelTester() |
| 2891 | .batch_size(8) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2892 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2893 | } |
| 2894 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2895 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X8, batch_div_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2896 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2897 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 2898 | VUnOpMicrokernelTester() |
| 2899 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2900 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2901 | } |
| 2902 | } |
| 2903 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2904 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X8, batch_lt_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2905 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2906 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 2907 | VUnOpMicrokernelTester() |
| 2908 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2909 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2910 | } |
| 2911 | } |
| 2912 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2913 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X8, batch_gt_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2914 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2915 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 2916 | VUnOpMicrokernelTester() |
| 2917 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2918 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2919 | } |
| 2920 | } |
| 2921 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2922 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X8, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2923 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2924 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 2925 | VUnOpMicrokernelTester() |
| 2926 | .batch_size(batch_size) |
| 2927 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2928 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2929 | } |
| 2930 | } |
| 2931 | #endif // XNN_ARCH_ARM64 |
| 2932 | |
| 2933 | |
| 2934 | #if XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2935 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X12, batch_eq_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2936 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2937 | VUnOpMicrokernelTester() |
| 2938 | .batch_size(12) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2939 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2940 | } |
| 2941 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2942 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X12, batch_div_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2943 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2944 | for (size_t batch_size = 24; batch_size < 120; batch_size += 12) { |
| 2945 | VUnOpMicrokernelTester() |
| 2946 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2947 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2948 | } |
| 2949 | } |
| 2950 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2951 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X12, batch_lt_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2952 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2953 | for (size_t batch_size = 1; batch_size < 12; batch_size++) { |
| 2954 | VUnOpMicrokernelTester() |
| 2955 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2956 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2957 | } |
| 2958 | } |
| 2959 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2960 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X12, batch_gt_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2961 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2962 | for (size_t batch_size = 13; batch_size < 24; batch_size++) { |
| 2963 | VUnOpMicrokernelTester() |
| 2964 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2965 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2966 | } |
| 2967 | } |
| 2968 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2969 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X12, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2970 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2971 | for (size_t batch_size = 1; batch_size <= 60; batch_size += 11) { |
| 2972 | VUnOpMicrokernelTester() |
| 2973 | .batch_size(batch_size) |
| 2974 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2975 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2976 | } |
| 2977 | } |
| 2978 | #endif // XNN_ARCH_ARM64 |
| 2979 | |
| 2980 | |
| 2981 | #if XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2982 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X16, batch_eq_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2983 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2984 | VUnOpMicrokernelTester() |
| 2985 | .batch_size(16) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2986 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2987 | } |
| 2988 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2989 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X16, batch_div_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2990 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2991 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 2992 | VUnOpMicrokernelTester() |
| 2993 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2994 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2995 | } |
| 2996 | } |
| 2997 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 2998 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X16, batch_lt_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 2999 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3000 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 3001 | VUnOpMicrokernelTester() |
| 3002 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3003 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3004 | } |
| 3005 | } |
| 3006 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3007 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X16, batch_gt_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3008 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3009 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 3010 | VUnOpMicrokernelTester() |
| 3011 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3012 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3013 | } |
| 3014 | } |
| 3015 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3016 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X16, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3017 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3018 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 3019 | VUnOpMicrokernelTester() |
| 3020 | .batch_size(batch_size) |
| 3021 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3022 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3023 | } |
| 3024 | } |
| 3025 | #endif // XNN_ARCH_ARM64 |
| 3026 | |
| 3027 | |
| 3028 | #if XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3029 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X20, batch_eq_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3030 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3031 | VUnOpMicrokernelTester() |
| 3032 | .batch_size(20) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3033 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3034 | } |
| 3035 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3036 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X20, batch_div_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3037 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3038 | for (size_t batch_size = 40; batch_size < 200; batch_size += 20) { |
| 3039 | VUnOpMicrokernelTester() |
| 3040 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3041 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3042 | } |
| 3043 | } |
| 3044 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3045 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X20, batch_lt_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3046 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3047 | for (size_t batch_size = 1; batch_size < 20; batch_size++) { |
| 3048 | VUnOpMicrokernelTester() |
| 3049 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3050 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3051 | } |
| 3052 | } |
| 3053 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3054 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X20, batch_gt_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3055 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3056 | for (size_t batch_size = 21; batch_size < 40; batch_size++) { |
| 3057 | VUnOpMicrokernelTester() |
| 3058 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3059 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3060 | } |
| 3061 | } |
| 3062 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3063 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X20, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3064 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3065 | for (size_t batch_size = 1; batch_size <= 100; batch_size += 19) { |
| 3066 | VUnOpMicrokernelTester() |
| 3067 | .batch_size(batch_size) |
| 3068 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3069 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3070 | } |
| 3071 | } |
| 3072 | #endif // XNN_ARCH_ARM64 |
| 3073 | |
| 3074 | |
| 3075 | #if XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3076 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X24, batch_eq_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3077 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3078 | VUnOpMicrokernelTester() |
| 3079 | .batch_size(24) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3080 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3081 | } |
| 3082 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3083 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X24, batch_div_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3084 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3085 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 3086 | VUnOpMicrokernelTester() |
| 3087 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3088 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3089 | } |
| 3090 | } |
| 3091 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3092 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X24, batch_lt_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3093 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3094 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 3095 | VUnOpMicrokernelTester() |
| 3096 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3097 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3098 | } |
| 3099 | } |
| 3100 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3101 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X24, batch_gt_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3102 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3103 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 3104 | VUnOpMicrokernelTester() |
| 3105 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3106 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3107 | } |
| 3108 | } |
| 3109 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3110 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_DIV_X24, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3111 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3112 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 3113 | VUnOpMicrokernelTester() |
| 3114 | .batch_size(batch_size) |
| 3115 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3116 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3117 | } |
| 3118 | } |
| 3119 | #endif // XNN_ARCH_ARM64 |
| 3120 | |
| 3121 | |
| 3122 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3123 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X4, batch_eq_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3124 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3125 | VUnOpMicrokernelTester() |
| 3126 | .batch_size(4) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3127 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3128 | } |
| 3129 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3130 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X4, batch_div_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3131 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3132 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 3133 | VUnOpMicrokernelTester() |
| 3134 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3135 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3136 | } |
| 3137 | } |
| 3138 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3139 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X4, batch_lt_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3140 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3141 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 3142 | VUnOpMicrokernelTester() |
| 3143 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3144 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3145 | } |
| 3146 | } |
| 3147 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3148 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X4, batch_gt_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3149 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3150 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 3151 | VUnOpMicrokernelTester() |
| 3152 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3153 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3154 | } |
| 3155 | } |
| 3156 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3157 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X4, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3158 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3159 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 3160 | VUnOpMicrokernelTester() |
| 3161 | .batch_size(batch_size) |
| 3162 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3163 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3164 | } |
| 3165 | } |
| 3166 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3167 | |
| 3168 | |
| 3169 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3170 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X8, batch_eq_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3171 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3172 | VUnOpMicrokernelTester() |
| 3173 | .batch_size(8) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3174 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3175 | } |
| 3176 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3177 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X8, batch_div_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3178 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3179 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 3180 | VUnOpMicrokernelTester() |
| 3181 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3182 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3183 | } |
| 3184 | } |
| 3185 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3186 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X8, batch_lt_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3187 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3188 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 3189 | VUnOpMicrokernelTester() |
| 3190 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3191 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3192 | } |
| 3193 | } |
| 3194 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3195 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X8, batch_gt_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3196 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3197 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 3198 | VUnOpMicrokernelTester() |
| 3199 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3200 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3201 | } |
| 3202 | } |
| 3203 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3204 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X8, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3205 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3206 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 3207 | VUnOpMicrokernelTester() |
| 3208 | .batch_size(batch_size) |
| 3209 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3210 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3211 | } |
| 3212 | } |
| 3213 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3214 | |
| 3215 | |
| 3216 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3217 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X12, batch_eq_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3218 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3219 | VUnOpMicrokernelTester() |
| 3220 | .batch_size(12) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3221 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3222 | } |
| 3223 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3224 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X12, batch_div_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3225 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3226 | for (size_t batch_size = 24; batch_size < 120; batch_size += 12) { |
| 3227 | VUnOpMicrokernelTester() |
| 3228 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3229 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3230 | } |
| 3231 | } |
| 3232 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3233 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X12, batch_lt_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3234 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3235 | for (size_t batch_size = 1; batch_size < 12; batch_size++) { |
| 3236 | VUnOpMicrokernelTester() |
| 3237 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3238 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3239 | } |
| 3240 | } |
| 3241 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3242 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X12, batch_gt_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3243 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3244 | for (size_t batch_size = 13; batch_size < 24; batch_size++) { |
| 3245 | VUnOpMicrokernelTester() |
| 3246 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3247 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3248 | } |
| 3249 | } |
| 3250 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3251 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X12, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3252 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3253 | for (size_t batch_size = 1; batch_size <= 60; batch_size += 11) { |
| 3254 | VUnOpMicrokernelTester() |
| 3255 | .batch_size(batch_size) |
| 3256 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3257 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3258 | } |
| 3259 | } |
| 3260 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3261 | |
| 3262 | |
| 3263 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3264 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X16, batch_eq_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3265 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3266 | VUnOpMicrokernelTester() |
| 3267 | .batch_size(16) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3268 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3269 | } |
| 3270 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3271 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X16, batch_div_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3272 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3273 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 3274 | VUnOpMicrokernelTester() |
| 3275 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3276 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3277 | } |
| 3278 | } |
| 3279 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3280 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X16, batch_lt_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3281 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3282 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 3283 | VUnOpMicrokernelTester() |
| 3284 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3285 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3286 | } |
| 3287 | } |
| 3288 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3289 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X16, batch_gt_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3290 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3291 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 3292 | VUnOpMicrokernelTester() |
| 3293 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3294 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3295 | } |
| 3296 | } |
| 3297 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3298 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X16, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3299 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3300 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 3301 | VUnOpMicrokernelTester() |
| 3302 | .batch_size(batch_size) |
| 3303 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3304 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3305 | } |
| 3306 | } |
| 3307 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3308 | |
| 3309 | |
| 3310 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3311 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X20, batch_eq_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3312 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3313 | VUnOpMicrokernelTester() |
| 3314 | .batch_size(20) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3315 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3316 | } |
| 3317 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3318 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X20, batch_div_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3319 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3320 | for (size_t batch_size = 40; batch_size < 200; batch_size += 20) { |
| 3321 | VUnOpMicrokernelTester() |
| 3322 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3323 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3324 | } |
| 3325 | } |
| 3326 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3327 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X20, batch_lt_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3328 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3329 | for (size_t batch_size = 1; batch_size < 20; batch_size++) { |
| 3330 | VUnOpMicrokernelTester() |
| 3331 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3332 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3333 | } |
| 3334 | } |
| 3335 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3336 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X20, batch_gt_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3337 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3338 | for (size_t batch_size = 21; batch_size < 40; batch_size++) { |
| 3339 | VUnOpMicrokernelTester() |
| 3340 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3341 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3342 | } |
| 3343 | } |
| 3344 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3345 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X20, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3346 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3347 | for (size_t batch_size = 1; batch_size <= 100; batch_size += 19) { |
| 3348 | VUnOpMicrokernelTester() |
| 3349 | .batch_size(batch_size) |
| 3350 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3351 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3352 | } |
| 3353 | } |
| 3354 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3355 | |
| 3356 | |
| 3357 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3358 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X24, batch_eq_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3359 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3360 | VUnOpMicrokernelTester() |
| 3361 | .batch_size(24) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3362 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3363 | } |
| 3364 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3365 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X24, batch_div_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3366 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3367 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 3368 | VUnOpMicrokernelTester() |
| 3369 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3370 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3371 | } |
| 3372 | } |
| 3373 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3374 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X24, batch_lt_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3375 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3376 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 3377 | VUnOpMicrokernelTester() |
| 3378 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3379 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3380 | } |
| 3381 | } |
| 3382 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3383 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X24, batch_gt_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3384 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3385 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 3386 | VUnOpMicrokernelTester() |
| 3387 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3388 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3389 | } |
| 3390 | } |
| 3391 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3392 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2FMA_X24, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3393 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3394 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 3395 | VUnOpMicrokernelTester() |
| 3396 | .batch_size(batch_size) |
| 3397 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3398 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3399 | } |
| 3400 | } |
| 3401 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3402 | |
| 3403 | |
| 3404 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3405 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X4, batch_eq_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3406 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3407 | VUnOpMicrokernelTester() |
| 3408 | .batch_size(4) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3409 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3410 | } |
| 3411 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3412 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X4, batch_div_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3413 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3414 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 3415 | VUnOpMicrokernelTester() |
| 3416 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3417 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3418 | } |
| 3419 | } |
| 3420 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3421 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X4, batch_lt_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3422 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3423 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 3424 | VUnOpMicrokernelTester() |
| 3425 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3426 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3427 | } |
| 3428 | } |
| 3429 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3430 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X4, batch_gt_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3431 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3432 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 3433 | VUnOpMicrokernelTester() |
| 3434 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3435 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3436 | } |
| 3437 | } |
| 3438 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3439 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X4, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3440 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3441 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 3442 | VUnOpMicrokernelTester() |
| 3443 | .batch_size(batch_size) |
| 3444 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3445 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3446 | } |
| 3447 | } |
| 3448 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3449 | |
| 3450 | |
| 3451 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3452 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X8, batch_eq_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3453 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3454 | VUnOpMicrokernelTester() |
| 3455 | .batch_size(8) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3456 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3457 | } |
| 3458 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3459 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X8, batch_div_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3460 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3461 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 3462 | VUnOpMicrokernelTester() |
| 3463 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3464 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3465 | } |
| 3466 | } |
| 3467 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3468 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X8, batch_lt_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3469 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3470 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 3471 | VUnOpMicrokernelTester() |
| 3472 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3473 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3474 | } |
| 3475 | } |
| 3476 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3477 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X8, batch_gt_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3478 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3479 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 3480 | VUnOpMicrokernelTester() |
| 3481 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3482 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3483 | } |
| 3484 | } |
| 3485 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3486 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X8, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3487 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3488 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 3489 | VUnOpMicrokernelTester() |
| 3490 | .batch_size(batch_size) |
| 3491 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3492 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3493 | } |
| 3494 | } |
| 3495 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3496 | |
| 3497 | |
| 3498 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3499 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X12, batch_eq_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3500 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3501 | VUnOpMicrokernelTester() |
| 3502 | .batch_size(12) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3503 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3504 | } |
| 3505 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3506 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X12, batch_div_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3507 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3508 | for (size_t batch_size = 24; batch_size < 120; batch_size += 12) { |
| 3509 | VUnOpMicrokernelTester() |
| 3510 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3511 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3512 | } |
| 3513 | } |
| 3514 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3515 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X12, batch_lt_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3516 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3517 | for (size_t batch_size = 1; batch_size < 12; batch_size++) { |
| 3518 | VUnOpMicrokernelTester() |
| 3519 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3520 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3521 | } |
| 3522 | } |
| 3523 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3524 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X12, batch_gt_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3525 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3526 | for (size_t batch_size = 13; batch_size < 24; batch_size++) { |
| 3527 | VUnOpMicrokernelTester() |
| 3528 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3529 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3530 | } |
| 3531 | } |
| 3532 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3533 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X12, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3534 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3535 | for (size_t batch_size = 1; batch_size <= 60; batch_size += 11) { |
| 3536 | VUnOpMicrokernelTester() |
| 3537 | .batch_size(batch_size) |
| 3538 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3539 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3540 | } |
| 3541 | } |
| 3542 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3543 | |
| 3544 | |
| 3545 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3546 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X16, batch_eq_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3547 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3548 | VUnOpMicrokernelTester() |
| 3549 | .batch_size(16) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3550 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3551 | } |
| 3552 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3553 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X16, batch_div_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3554 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3555 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 3556 | VUnOpMicrokernelTester() |
| 3557 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3558 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3559 | } |
| 3560 | } |
| 3561 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3562 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X16, batch_lt_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3563 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3564 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 3565 | VUnOpMicrokernelTester() |
| 3566 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3567 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3568 | } |
| 3569 | } |
| 3570 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3571 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X16, batch_gt_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3572 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3573 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 3574 | VUnOpMicrokernelTester() |
| 3575 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3576 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3577 | } |
| 3578 | } |
| 3579 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3580 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X16, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3581 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3582 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 3583 | VUnOpMicrokernelTester() |
| 3584 | .batch_size(batch_size) |
| 3585 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3586 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3587 | } |
| 3588 | } |
| 3589 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3590 | |
| 3591 | |
| 3592 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3593 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X20, batch_eq_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3594 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3595 | VUnOpMicrokernelTester() |
| 3596 | .batch_size(20) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3597 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3598 | } |
| 3599 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3600 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X20, batch_div_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3601 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3602 | for (size_t batch_size = 40; batch_size < 200; batch_size += 20) { |
| 3603 | VUnOpMicrokernelTester() |
| 3604 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3605 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3606 | } |
| 3607 | } |
| 3608 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3609 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X20, batch_lt_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3610 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3611 | for (size_t batch_size = 1; batch_size < 20; batch_size++) { |
| 3612 | VUnOpMicrokernelTester() |
| 3613 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3614 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3615 | } |
| 3616 | } |
| 3617 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3618 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X20, batch_gt_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3619 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3620 | for (size_t batch_size = 21; batch_size < 40; batch_size++) { |
| 3621 | VUnOpMicrokernelTester() |
| 3622 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3623 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3624 | } |
| 3625 | } |
| 3626 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3627 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X20, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3628 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3629 | for (size_t batch_size = 1; batch_size <= 100; batch_size += 19) { |
| 3630 | VUnOpMicrokernelTester() |
| 3631 | .batch_size(batch_size) |
| 3632 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3633 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3634 | } |
| 3635 | } |
| 3636 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3637 | |
| 3638 | |
| 3639 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3640 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X24, batch_eq_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3641 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3642 | VUnOpMicrokernelTester() |
| 3643 | .batch_size(24) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3644 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3645 | } |
| 3646 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3647 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X24, batch_div_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3648 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3649 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 3650 | VUnOpMicrokernelTester() |
| 3651 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3652 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3653 | } |
| 3654 | } |
| 3655 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3656 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X24, batch_lt_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3657 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3658 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 3659 | VUnOpMicrokernelTester() |
| 3660 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3661 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3662 | } |
| 3663 | } |
| 3664 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3665 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X24, batch_gt_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3666 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3667 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 3668 | VUnOpMicrokernelTester() |
| 3669 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3670 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3671 | } |
| 3672 | } |
| 3673 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3674 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR1RECPS1FMA_X24, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3675 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3676 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 3677 | VUnOpMicrokernelTester() |
| 3678 | .batch_size(batch_size) |
| 3679 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3680 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr1recps1fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3681 | } |
| 3682 | } |
| 3683 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3684 | |
| 3685 | |
| 3686 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3687 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X4, batch_eq_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3688 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3689 | VUnOpMicrokernelTester() |
| 3690 | .batch_size(4) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3691 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3692 | } |
| 3693 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3694 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X4, batch_div_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3695 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3696 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 3697 | VUnOpMicrokernelTester() |
| 3698 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3699 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3700 | } |
| 3701 | } |
| 3702 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3703 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X4, batch_lt_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3704 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3705 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 3706 | VUnOpMicrokernelTester() |
| 3707 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3708 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3709 | } |
| 3710 | } |
| 3711 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3712 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X4, batch_gt_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3713 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3714 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 3715 | VUnOpMicrokernelTester() |
| 3716 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3717 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3718 | } |
| 3719 | } |
| 3720 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3721 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X4, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3722 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3723 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 3724 | VUnOpMicrokernelTester() |
| 3725 | .batch_size(batch_size) |
| 3726 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3727 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3728 | } |
| 3729 | } |
| 3730 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3731 | |
| 3732 | |
| 3733 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3734 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X8, batch_eq_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3735 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3736 | VUnOpMicrokernelTester() |
| 3737 | .batch_size(8) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3738 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3739 | } |
| 3740 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3741 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X8, batch_div_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3742 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3743 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 3744 | VUnOpMicrokernelTester() |
| 3745 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3746 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3747 | } |
| 3748 | } |
| 3749 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3750 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X8, batch_lt_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3751 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3752 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 3753 | VUnOpMicrokernelTester() |
| 3754 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3755 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3756 | } |
| 3757 | } |
| 3758 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3759 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X8, batch_gt_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3760 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3761 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 3762 | VUnOpMicrokernelTester() |
| 3763 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3764 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3765 | } |
| 3766 | } |
| 3767 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3768 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X8, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3769 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3770 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 3771 | VUnOpMicrokernelTester() |
| 3772 | .batch_size(batch_size) |
| 3773 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3774 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3775 | } |
| 3776 | } |
| 3777 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3778 | |
| 3779 | |
| 3780 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3781 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X12, batch_eq_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3782 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3783 | VUnOpMicrokernelTester() |
| 3784 | .batch_size(12) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3785 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3786 | } |
| 3787 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3788 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X12, batch_div_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3789 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3790 | for (size_t batch_size = 24; batch_size < 120; batch_size += 12) { |
| 3791 | VUnOpMicrokernelTester() |
| 3792 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3793 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3794 | } |
| 3795 | } |
| 3796 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3797 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X12, batch_lt_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3798 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3799 | for (size_t batch_size = 1; batch_size < 12; batch_size++) { |
| 3800 | VUnOpMicrokernelTester() |
| 3801 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3802 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3803 | } |
| 3804 | } |
| 3805 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3806 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X12, batch_gt_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3807 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3808 | for (size_t batch_size = 13; batch_size < 24; batch_size++) { |
| 3809 | VUnOpMicrokernelTester() |
| 3810 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3811 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3812 | } |
| 3813 | } |
| 3814 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3815 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X12, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3816 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3817 | for (size_t batch_size = 1; batch_size <= 60; batch_size += 11) { |
| 3818 | VUnOpMicrokernelTester() |
| 3819 | .batch_size(batch_size) |
| 3820 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3821 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3822 | } |
| 3823 | } |
| 3824 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3825 | |
| 3826 | |
| 3827 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3828 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X16, batch_eq_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3829 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3830 | VUnOpMicrokernelTester() |
| 3831 | .batch_size(16) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3832 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3833 | } |
| 3834 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3835 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X16, batch_div_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3836 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3837 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 3838 | VUnOpMicrokernelTester() |
| 3839 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3840 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3841 | } |
| 3842 | } |
| 3843 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3844 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X16, batch_lt_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3845 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3846 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 3847 | VUnOpMicrokernelTester() |
| 3848 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3849 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3850 | } |
| 3851 | } |
| 3852 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3853 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X16, batch_gt_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3854 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3855 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 3856 | VUnOpMicrokernelTester() |
| 3857 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3858 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3859 | } |
| 3860 | } |
| 3861 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3862 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X16, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3863 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3864 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 3865 | VUnOpMicrokernelTester() |
| 3866 | .batch_size(batch_size) |
| 3867 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3868 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3869 | } |
| 3870 | } |
| 3871 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3872 | |
| 3873 | |
| 3874 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3875 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X20, batch_eq_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3876 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3877 | VUnOpMicrokernelTester() |
| 3878 | .batch_size(20) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3879 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3880 | } |
| 3881 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3882 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X20, batch_div_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3883 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3884 | for (size_t batch_size = 40; batch_size < 200; batch_size += 20) { |
| 3885 | VUnOpMicrokernelTester() |
| 3886 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3887 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3888 | } |
| 3889 | } |
| 3890 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3891 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X20, batch_lt_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3892 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3893 | for (size_t batch_size = 1; batch_size < 20; batch_size++) { |
| 3894 | VUnOpMicrokernelTester() |
| 3895 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3896 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3897 | } |
| 3898 | } |
| 3899 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3900 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X20, batch_gt_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3901 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3902 | for (size_t batch_size = 21; batch_size < 40; batch_size++) { |
| 3903 | VUnOpMicrokernelTester() |
| 3904 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3905 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3906 | } |
| 3907 | } |
| 3908 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3909 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X20, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3910 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3911 | for (size_t batch_size = 1; batch_size <= 100; batch_size += 19) { |
| 3912 | VUnOpMicrokernelTester() |
| 3913 | .batch_size(batch_size) |
| 3914 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3915 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3916 | } |
| 3917 | } |
| 3918 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3919 | |
| 3920 | |
| 3921 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3922 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X24, batch_eq_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3923 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3924 | VUnOpMicrokernelTester() |
| 3925 | .batch_size(24) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3926 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3927 | } |
| 3928 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3929 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X24, batch_div_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3930 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3931 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 3932 | VUnOpMicrokernelTester() |
| 3933 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3934 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3935 | } |
| 3936 | } |
| 3937 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3938 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X24, batch_lt_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3939 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3940 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 3941 | VUnOpMicrokernelTester() |
| 3942 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3943 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3944 | } |
| 3945 | } |
| 3946 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3947 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X24, batch_gt_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3948 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3949 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 3950 | VUnOpMicrokernelTester() |
| 3951 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3952 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3953 | } |
| 3954 | } |
| 3955 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3956 | TEST(F32_SIGMOID__NEONFMA_RR1_LUT2048_P1_NR2RECPS_X24, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3957 | TEST_REQUIRES_ARM_NEON_FMA; |
| 3958 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 3959 | VUnOpMicrokernelTester() |
| 3960 | .batch_size(batch_size) |
| 3961 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3962 | .Test(xnn_f32_sigmoid_ukernel__neonfma_rr1_lut2048_p1_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3963 | } |
| 3964 | } |
| 3965 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3966 | |
| 3967 | |
| 3968 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3969 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X4, batch_eq_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3970 | TEST_REQUIRES_ARM_NEON; |
| 3971 | VUnOpMicrokernelTester() |
| 3972 | .batch_size(4) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3973 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3974 | } |
| 3975 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3976 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X4, batch_div_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3977 | TEST_REQUIRES_ARM_NEON; |
| 3978 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 3979 | VUnOpMicrokernelTester() |
| 3980 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3981 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3982 | } |
| 3983 | } |
| 3984 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3985 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X4, batch_lt_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3986 | TEST_REQUIRES_ARM_NEON; |
| 3987 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 3988 | VUnOpMicrokernelTester() |
| 3989 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3990 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3991 | } |
| 3992 | } |
| 3993 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3994 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X4, batch_gt_4) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 3995 | TEST_REQUIRES_ARM_NEON; |
| 3996 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 3997 | VUnOpMicrokernelTester() |
| 3998 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 3999 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4000 | } |
| 4001 | } |
| 4002 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4003 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X4, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4004 | TEST_REQUIRES_ARM_NEON; |
| 4005 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 4006 | VUnOpMicrokernelTester() |
| 4007 | .batch_size(batch_size) |
| 4008 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4009 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4010 | } |
| 4011 | } |
| 4012 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 4013 | |
| 4014 | |
| 4015 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4016 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X8, batch_eq_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4017 | TEST_REQUIRES_ARM_NEON; |
| 4018 | VUnOpMicrokernelTester() |
| 4019 | .batch_size(8) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4020 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4021 | } |
| 4022 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4023 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X8, batch_div_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4024 | TEST_REQUIRES_ARM_NEON; |
| 4025 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 4026 | VUnOpMicrokernelTester() |
| 4027 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4028 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4029 | } |
| 4030 | } |
| 4031 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4032 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X8, batch_lt_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4033 | TEST_REQUIRES_ARM_NEON; |
| 4034 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 4035 | VUnOpMicrokernelTester() |
| 4036 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4037 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4038 | } |
| 4039 | } |
| 4040 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4041 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X8, batch_gt_8) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4042 | TEST_REQUIRES_ARM_NEON; |
| 4043 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 4044 | VUnOpMicrokernelTester() |
| 4045 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4046 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4047 | } |
| 4048 | } |
| 4049 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4050 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X8, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4051 | TEST_REQUIRES_ARM_NEON; |
| 4052 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 4053 | VUnOpMicrokernelTester() |
| 4054 | .batch_size(batch_size) |
| 4055 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4056 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4057 | } |
| 4058 | } |
| 4059 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 4060 | |
| 4061 | |
| 4062 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4063 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X12, batch_eq_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4064 | TEST_REQUIRES_ARM_NEON; |
| 4065 | VUnOpMicrokernelTester() |
| 4066 | .batch_size(12) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4067 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4068 | } |
| 4069 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4070 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X12, batch_div_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4071 | TEST_REQUIRES_ARM_NEON; |
| 4072 | for (size_t batch_size = 24; batch_size < 120; batch_size += 12) { |
| 4073 | VUnOpMicrokernelTester() |
| 4074 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4075 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4076 | } |
| 4077 | } |
| 4078 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4079 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X12, batch_lt_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4080 | TEST_REQUIRES_ARM_NEON; |
| 4081 | for (size_t batch_size = 1; batch_size < 12; batch_size++) { |
| 4082 | VUnOpMicrokernelTester() |
| 4083 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4084 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4085 | } |
| 4086 | } |
| 4087 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4088 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X12, batch_gt_12) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4089 | TEST_REQUIRES_ARM_NEON; |
| 4090 | for (size_t batch_size = 13; batch_size < 24; batch_size++) { |
| 4091 | VUnOpMicrokernelTester() |
| 4092 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4093 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4094 | } |
| 4095 | } |
| 4096 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4097 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X12, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4098 | TEST_REQUIRES_ARM_NEON; |
| 4099 | for (size_t batch_size = 1; batch_size <= 60; batch_size += 11) { |
| 4100 | VUnOpMicrokernelTester() |
| 4101 | .batch_size(batch_size) |
| 4102 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4103 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4104 | } |
| 4105 | } |
| 4106 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 4107 | |
| 4108 | |
| 4109 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4110 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X16, batch_eq_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4111 | TEST_REQUIRES_ARM_NEON; |
| 4112 | VUnOpMicrokernelTester() |
| 4113 | .batch_size(16) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4114 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4115 | } |
| 4116 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4117 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X16, batch_div_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4118 | TEST_REQUIRES_ARM_NEON; |
| 4119 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 4120 | VUnOpMicrokernelTester() |
| 4121 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4122 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4123 | } |
| 4124 | } |
| 4125 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4126 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X16, batch_lt_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4127 | TEST_REQUIRES_ARM_NEON; |
| 4128 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 4129 | VUnOpMicrokernelTester() |
| 4130 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4131 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4132 | } |
| 4133 | } |
| 4134 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4135 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X16, batch_gt_16) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4136 | TEST_REQUIRES_ARM_NEON; |
| 4137 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 4138 | VUnOpMicrokernelTester() |
| 4139 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4140 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4141 | } |
| 4142 | } |
| 4143 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4144 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X16, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4145 | TEST_REQUIRES_ARM_NEON; |
| 4146 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 4147 | VUnOpMicrokernelTester() |
| 4148 | .batch_size(batch_size) |
| 4149 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4150 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4151 | } |
| 4152 | } |
| 4153 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 4154 | |
| 4155 | |
| 4156 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4157 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X20, batch_eq_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4158 | TEST_REQUIRES_ARM_NEON; |
| 4159 | VUnOpMicrokernelTester() |
| 4160 | .batch_size(20) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4161 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4162 | } |
| 4163 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4164 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X20, batch_div_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4165 | TEST_REQUIRES_ARM_NEON; |
| 4166 | for (size_t batch_size = 40; batch_size < 200; batch_size += 20) { |
| 4167 | VUnOpMicrokernelTester() |
| 4168 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4169 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4170 | } |
| 4171 | } |
| 4172 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4173 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X20, batch_lt_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4174 | TEST_REQUIRES_ARM_NEON; |
| 4175 | for (size_t batch_size = 1; batch_size < 20; batch_size++) { |
| 4176 | VUnOpMicrokernelTester() |
| 4177 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4178 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4179 | } |
| 4180 | } |
| 4181 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4182 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X20, batch_gt_20) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4183 | TEST_REQUIRES_ARM_NEON; |
| 4184 | for (size_t batch_size = 21; batch_size < 40; batch_size++) { |
| 4185 | VUnOpMicrokernelTester() |
| 4186 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4187 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4188 | } |
| 4189 | } |
| 4190 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4191 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X20, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4192 | TEST_REQUIRES_ARM_NEON; |
| 4193 | for (size_t batch_size = 1; batch_size <= 100; batch_size += 19) { |
| 4194 | VUnOpMicrokernelTester() |
| 4195 | .batch_size(batch_size) |
| 4196 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4197 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4198 | } |
| 4199 | } |
| 4200 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 4201 | |
| 4202 | |
| 4203 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4204 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X24, batch_eq_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4205 | TEST_REQUIRES_ARM_NEON; |
| 4206 | VUnOpMicrokernelTester() |
| 4207 | .batch_size(24) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4208 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4209 | } |
| 4210 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4211 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X24, batch_div_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4212 | TEST_REQUIRES_ARM_NEON; |
| 4213 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 4214 | VUnOpMicrokernelTester() |
| 4215 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4216 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4217 | } |
| 4218 | } |
| 4219 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4220 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X24, batch_lt_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4221 | TEST_REQUIRES_ARM_NEON; |
| 4222 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 4223 | VUnOpMicrokernelTester() |
| 4224 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4225 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4226 | } |
| 4227 | } |
| 4228 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4229 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X24, batch_gt_24) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4230 | TEST_REQUIRES_ARM_NEON; |
| 4231 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 4232 | VUnOpMicrokernelTester() |
| 4233 | .batch_size(batch_size) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4234 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4235 | } |
| 4236 | } |
| 4237 | |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4238 | TEST(F32_SIGMOID__NEON_RR2_LUT2048_P1_NR2RECPS_X24, inplace) { |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4239 | TEST_REQUIRES_ARM_NEON; |
| 4240 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 4241 | VUnOpMicrokernelTester() |
| 4242 | .batch_size(batch_size) |
| 4243 | .inplace(true) |
Marat Dukhan | 4a24a58 | 2020-01-06 13:30:00 -0800 | [diff] [blame] | 4244 | .Test(xnn_f32_sigmoid_ukernel__neon_rr2_lut2048_p1_nr2recps_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4245 | } |
| 4246 | } |
| 4247 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 4248 | |
| 4249 | |
| 4250 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 14bec50 | 2019-11-18 11:35:31 -0800 | [diff] [blame] | 4251 | TEST(F32_SIGMOID__NEON_FRAC_P9_P10_NR1RECPS_X16, batch_eq_16) { |
| 4252 | TEST_REQUIRES_ARM_NEON; |
Erich Elsen | 8fd7b5f | 2019-11-18 10:50:41 -0800 | [diff] [blame] | 4253 | VUnOpMicrokernelTester() |
| 4254 | .batch_size(16) |
Marat Dukhan | 14bec50 | 2019-11-18 11:35:31 -0800 | [diff] [blame] | 4255 | .Test(xnn_f32_sigmoid_ukernel__neon_frac_p9_p10_nr1recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Erich Elsen | 8fd7b5f | 2019-11-18 10:50:41 -0800 | [diff] [blame] | 4256 | } |
| 4257 | |
Marat Dukhan | 14bec50 | 2019-11-18 11:35:31 -0800 | [diff] [blame] | 4258 | TEST(F32_SIGMOID__NEON_FRAC_P9_P10_NR1RECPS_X16, batch_div_16) { |
| 4259 | TEST_REQUIRES_ARM_NEON; |
Erich Elsen | 8fd7b5f | 2019-11-18 10:50:41 -0800 | [diff] [blame] | 4260 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 4261 | VUnOpMicrokernelTester() |
| 4262 | .batch_size(batch_size) |
Marat Dukhan | 14bec50 | 2019-11-18 11:35:31 -0800 | [diff] [blame] | 4263 | .Test(xnn_f32_sigmoid_ukernel__neon_frac_p9_p10_nr1recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Erich Elsen | 8fd7b5f | 2019-11-18 10:50:41 -0800 | [diff] [blame] | 4264 | } |
| 4265 | } |
| 4266 | |
Marat Dukhan | 14bec50 | 2019-11-18 11:35:31 -0800 | [diff] [blame] | 4267 | TEST(F32_SIGMOID__NEON_FRAC_P9_P10_NR1RECPS_X16, batch_lt_16) { |
| 4268 | TEST_REQUIRES_ARM_NEON; |
Erich Elsen | 8fd7b5f | 2019-11-18 10:50:41 -0800 | [diff] [blame] | 4269 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 4270 | VUnOpMicrokernelTester() |
| 4271 | .batch_size(batch_size) |
Marat Dukhan | 14bec50 | 2019-11-18 11:35:31 -0800 | [diff] [blame] | 4272 | .Test(xnn_f32_sigmoid_ukernel__neon_frac_p9_p10_nr1recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Erich Elsen | 8fd7b5f | 2019-11-18 10:50:41 -0800 | [diff] [blame] | 4273 | } |
| 4274 | } |
| 4275 | |
Marat Dukhan | 14bec50 | 2019-11-18 11:35:31 -0800 | [diff] [blame] | 4276 | TEST(F32_SIGMOID__NEON_FRAC_P9_P10_NR1RECPS_X16, batch_gt_16) { |
| 4277 | TEST_REQUIRES_ARM_NEON; |
Erich Elsen | 8fd7b5f | 2019-11-18 10:50:41 -0800 | [diff] [blame] | 4278 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 4279 | VUnOpMicrokernelTester() |
| 4280 | .batch_size(batch_size) |
Marat Dukhan | 14bec50 | 2019-11-18 11:35:31 -0800 | [diff] [blame] | 4281 | .Test(xnn_f32_sigmoid_ukernel__neon_frac_p9_p10_nr1recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Erich Elsen | 8fd7b5f | 2019-11-18 10:50:41 -0800 | [diff] [blame] | 4282 | } |
| 4283 | } |
| 4284 | |
Marat Dukhan | 14bec50 | 2019-11-18 11:35:31 -0800 | [diff] [blame] | 4285 | TEST(F32_SIGMOID__NEON_FRAC_P9_P10_NR1RECPS_X16, inplace) { |
| 4286 | TEST_REQUIRES_ARM_NEON; |
Erich Elsen | 8fd7b5f | 2019-11-18 10:50:41 -0800 | [diff] [blame] | 4287 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 4288 | VUnOpMicrokernelTester() |
| 4289 | .batch_size(batch_size) |
| 4290 | .inplace(true) |
Marat Dukhan | 14bec50 | 2019-11-18 11:35:31 -0800 | [diff] [blame] | 4291 | .Test(xnn_f32_sigmoid_ukernel__neon_frac_p9_p10_nr1recps_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
Erich Elsen | 8fd7b5f | 2019-11-18 10:50:41 -0800 | [diff] [blame] | 4292 | } |
| 4293 | } |
| 4294 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 7bee751 | 2019-11-18 15:15:48 -0800 | [diff] [blame] | 4295 | |
| 4296 | |
| 4297 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4298 | TEST(F32_SIGMOID__SSE2_P5_DIV_X4, batch_eq_4) { |
| 4299 | TEST_REQUIRES_X86_SSE2; |
| 4300 | VUnOpMicrokernelTester() |
| 4301 | .batch_size(4) |
| 4302 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4303 | } |
| 4304 | |
| 4305 | TEST(F32_SIGMOID__SSE2_P5_DIV_X4, batch_div_4) { |
| 4306 | TEST_REQUIRES_X86_SSE2; |
| 4307 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 4308 | VUnOpMicrokernelTester() |
| 4309 | .batch_size(batch_size) |
| 4310 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4311 | } |
| 4312 | } |
| 4313 | |
| 4314 | TEST(F32_SIGMOID__SSE2_P5_DIV_X4, batch_lt_4) { |
| 4315 | TEST_REQUIRES_X86_SSE2; |
| 4316 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 4317 | VUnOpMicrokernelTester() |
| 4318 | .batch_size(batch_size) |
| 4319 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4320 | } |
| 4321 | } |
| 4322 | |
| 4323 | TEST(F32_SIGMOID__SSE2_P5_DIV_X4, batch_gt_4) { |
| 4324 | TEST_REQUIRES_X86_SSE2; |
| 4325 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 4326 | VUnOpMicrokernelTester() |
| 4327 | .batch_size(batch_size) |
| 4328 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4329 | } |
| 4330 | } |
| 4331 | |
| 4332 | TEST(F32_SIGMOID__SSE2_P5_DIV_X4, inplace) { |
| 4333 | TEST_REQUIRES_X86_SSE2; |
| 4334 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 4335 | VUnOpMicrokernelTester() |
| 4336 | .batch_size(batch_size) |
| 4337 | .inplace(true) |
| 4338 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4339 | } |
| 4340 | } |
| 4341 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4342 | |
| 4343 | |
| 4344 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | 7bee751 | 2019-11-18 15:15:48 -0800 | [diff] [blame] | 4345 | TEST(F32_SIGMOID__SSE2_P5_DIV_X8, batch_eq_8) { |
| 4346 | TEST_REQUIRES_X86_SSE2; |
| 4347 | VUnOpMicrokernelTester() |
| 4348 | .batch_size(8) |
| 4349 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4350 | } |
| 4351 | |
| 4352 | TEST(F32_SIGMOID__SSE2_P5_DIV_X8, batch_div_8) { |
| 4353 | TEST_REQUIRES_X86_SSE2; |
| 4354 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 4355 | VUnOpMicrokernelTester() |
| 4356 | .batch_size(batch_size) |
| 4357 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4358 | } |
| 4359 | } |
| 4360 | |
| 4361 | TEST(F32_SIGMOID__SSE2_P5_DIV_X8, batch_lt_8) { |
| 4362 | TEST_REQUIRES_X86_SSE2; |
| 4363 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 4364 | VUnOpMicrokernelTester() |
| 4365 | .batch_size(batch_size) |
| 4366 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4367 | } |
| 4368 | } |
| 4369 | |
| 4370 | TEST(F32_SIGMOID__SSE2_P5_DIV_X8, batch_gt_8) { |
| 4371 | TEST_REQUIRES_X86_SSE2; |
| 4372 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 4373 | VUnOpMicrokernelTester() |
| 4374 | .batch_size(batch_size) |
| 4375 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4376 | } |
| 4377 | } |
| 4378 | |
| 4379 | TEST(F32_SIGMOID__SSE2_P5_DIV_X8, inplace) { |
| 4380 | TEST_REQUIRES_X86_SSE2; |
| 4381 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 4382 | VUnOpMicrokernelTester() |
| 4383 | .batch_size(batch_size) |
| 4384 | .inplace(true) |
| 4385 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4386 | } |
| 4387 | } |
| 4388 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4389 | |
| 4390 | |
| 4391 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4392 | TEST(F32_SIGMOID__SSE2_P5_DIV_X12, batch_eq_12) { |
| 4393 | TEST_REQUIRES_X86_SSE2; |
| 4394 | VUnOpMicrokernelTester() |
| 4395 | .batch_size(12) |
| 4396 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4397 | } |
| 4398 | |
| 4399 | TEST(F32_SIGMOID__SSE2_P5_DIV_X12, batch_div_12) { |
| 4400 | TEST_REQUIRES_X86_SSE2; |
| 4401 | for (size_t batch_size = 24; batch_size < 120; batch_size += 12) { |
| 4402 | VUnOpMicrokernelTester() |
| 4403 | .batch_size(batch_size) |
| 4404 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4405 | } |
| 4406 | } |
| 4407 | |
| 4408 | TEST(F32_SIGMOID__SSE2_P5_DIV_X12, batch_lt_12) { |
| 4409 | TEST_REQUIRES_X86_SSE2; |
| 4410 | for (size_t batch_size = 1; batch_size < 12; batch_size++) { |
| 4411 | VUnOpMicrokernelTester() |
| 4412 | .batch_size(batch_size) |
| 4413 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4414 | } |
| 4415 | } |
| 4416 | |
| 4417 | TEST(F32_SIGMOID__SSE2_P5_DIV_X12, batch_gt_12) { |
| 4418 | TEST_REQUIRES_X86_SSE2; |
| 4419 | for (size_t batch_size = 13; batch_size < 24; batch_size++) { |
| 4420 | VUnOpMicrokernelTester() |
| 4421 | .batch_size(batch_size) |
| 4422 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4423 | } |
| 4424 | } |
| 4425 | |
| 4426 | TEST(F32_SIGMOID__SSE2_P5_DIV_X12, inplace) { |
| 4427 | TEST_REQUIRES_X86_SSE2; |
| 4428 | for (size_t batch_size = 1; batch_size <= 60; batch_size += 11) { |
| 4429 | VUnOpMicrokernelTester() |
| 4430 | .batch_size(batch_size) |
| 4431 | .inplace(true) |
| 4432 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4433 | } |
| 4434 | } |
| 4435 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4436 | |
| 4437 | |
| 4438 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | 7bee751 | 2019-11-18 15:15:48 -0800 | [diff] [blame] | 4439 | TEST(F32_SIGMOID__SSE2_P5_DIV_X16, batch_eq_16) { |
| 4440 | TEST_REQUIRES_X86_SSE2; |
| 4441 | VUnOpMicrokernelTester() |
| 4442 | .batch_size(16) |
| 4443 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4444 | } |
| 4445 | |
| 4446 | TEST(F32_SIGMOID__SSE2_P5_DIV_X16, batch_div_16) { |
| 4447 | TEST_REQUIRES_X86_SSE2; |
| 4448 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 4449 | VUnOpMicrokernelTester() |
| 4450 | .batch_size(batch_size) |
| 4451 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4452 | } |
| 4453 | } |
| 4454 | |
| 4455 | TEST(F32_SIGMOID__SSE2_P5_DIV_X16, batch_lt_16) { |
| 4456 | TEST_REQUIRES_X86_SSE2; |
| 4457 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 4458 | VUnOpMicrokernelTester() |
| 4459 | .batch_size(batch_size) |
| 4460 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4461 | } |
| 4462 | } |
| 4463 | |
| 4464 | TEST(F32_SIGMOID__SSE2_P5_DIV_X16, batch_gt_16) { |
| 4465 | TEST_REQUIRES_X86_SSE2; |
| 4466 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 4467 | VUnOpMicrokernelTester() |
| 4468 | .batch_size(batch_size) |
| 4469 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4470 | } |
| 4471 | } |
| 4472 | |
| 4473 | TEST(F32_SIGMOID__SSE2_P5_DIV_X16, inplace) { |
| 4474 | TEST_REQUIRES_X86_SSE2; |
| 4475 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 4476 | VUnOpMicrokernelTester() |
| 4477 | .batch_size(batch_size) |
| 4478 | .inplace(true) |
| 4479 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4480 | } |
| 4481 | } |
| 4482 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | 3a77ea7 | 2019-12-23 12:10:24 -0800 | [diff] [blame] | 4483 | |
| 4484 | |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 4485 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4486 | TEST(F32_SIGMOID__SSE2_P5_DIV_X20, batch_eq_20) { |
| 4487 | TEST_REQUIRES_X86_SSE2; |
| 4488 | VUnOpMicrokernelTester() |
| 4489 | .batch_size(20) |
| 4490 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4491 | } |
| 4492 | |
| 4493 | TEST(F32_SIGMOID__SSE2_P5_DIV_X20, batch_div_20) { |
| 4494 | TEST_REQUIRES_X86_SSE2; |
| 4495 | for (size_t batch_size = 40; batch_size < 200; batch_size += 20) { |
| 4496 | VUnOpMicrokernelTester() |
| 4497 | .batch_size(batch_size) |
| 4498 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4499 | } |
| 4500 | } |
| 4501 | |
| 4502 | TEST(F32_SIGMOID__SSE2_P5_DIV_X20, batch_lt_20) { |
| 4503 | TEST_REQUIRES_X86_SSE2; |
| 4504 | for (size_t batch_size = 1; batch_size < 20; batch_size++) { |
| 4505 | VUnOpMicrokernelTester() |
| 4506 | .batch_size(batch_size) |
| 4507 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4508 | } |
| 4509 | } |
| 4510 | |
| 4511 | TEST(F32_SIGMOID__SSE2_P5_DIV_X20, batch_gt_20) { |
| 4512 | TEST_REQUIRES_X86_SSE2; |
| 4513 | for (size_t batch_size = 21; batch_size < 40; batch_size++) { |
| 4514 | VUnOpMicrokernelTester() |
| 4515 | .batch_size(batch_size) |
| 4516 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4517 | } |
| 4518 | } |
| 4519 | |
| 4520 | TEST(F32_SIGMOID__SSE2_P5_DIV_X20, inplace) { |
| 4521 | TEST_REQUIRES_X86_SSE2; |
| 4522 | for (size_t batch_size = 1; batch_size <= 100; batch_size += 19) { |
| 4523 | VUnOpMicrokernelTester() |
| 4524 | .batch_size(batch_size) |
| 4525 | .inplace(true) |
| 4526 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4527 | } |
| 4528 | } |
| 4529 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4530 | |
| 4531 | |
| 4532 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4533 | TEST(F32_SIGMOID__SSE2_P5_DIV_X24, batch_eq_24) { |
| 4534 | TEST_REQUIRES_X86_SSE2; |
| 4535 | VUnOpMicrokernelTester() |
| 4536 | .batch_size(24) |
| 4537 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4538 | } |
| 4539 | |
| 4540 | TEST(F32_SIGMOID__SSE2_P5_DIV_X24, batch_div_24) { |
| 4541 | TEST_REQUIRES_X86_SSE2; |
| 4542 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 4543 | VUnOpMicrokernelTester() |
| 4544 | .batch_size(batch_size) |
| 4545 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4546 | } |
| 4547 | } |
| 4548 | |
| 4549 | TEST(F32_SIGMOID__SSE2_P5_DIV_X24, batch_lt_24) { |
| 4550 | TEST_REQUIRES_X86_SSE2; |
| 4551 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 4552 | VUnOpMicrokernelTester() |
| 4553 | .batch_size(batch_size) |
| 4554 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4555 | } |
| 4556 | } |
| 4557 | |
| 4558 | TEST(F32_SIGMOID__SSE2_P5_DIV_X24, batch_gt_24) { |
| 4559 | TEST_REQUIRES_X86_SSE2; |
| 4560 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 4561 | VUnOpMicrokernelTester() |
| 4562 | .batch_size(batch_size) |
| 4563 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4564 | } |
| 4565 | } |
| 4566 | |
| 4567 | TEST(F32_SIGMOID__SSE2_P5_DIV_X24, inplace) { |
| 4568 | TEST_REQUIRES_X86_SSE2; |
| 4569 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 4570 | VUnOpMicrokernelTester() |
| 4571 | .batch_size(batch_size) |
| 4572 | .inplace(true) |
| 4573 | .Test(xnn_f32_sigmoid_ukernel__sse2_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4574 | } |
| 4575 | } |
| 4576 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4577 | |
| 4578 | |
| 4579 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4580 | TEST(F32_SIGMOID__SSE41_P5_DIV_X4, batch_eq_4) { |
| 4581 | TEST_REQUIRES_X86_SSE41; |
| 4582 | VUnOpMicrokernelTester() |
| 4583 | .batch_size(4) |
| 4584 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4585 | } |
| 4586 | |
| 4587 | TEST(F32_SIGMOID__SSE41_P5_DIV_X4, batch_div_4) { |
| 4588 | TEST_REQUIRES_X86_SSE41; |
| 4589 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 4590 | VUnOpMicrokernelTester() |
| 4591 | .batch_size(batch_size) |
| 4592 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4593 | } |
| 4594 | } |
| 4595 | |
| 4596 | TEST(F32_SIGMOID__SSE41_P5_DIV_X4, batch_lt_4) { |
| 4597 | TEST_REQUIRES_X86_SSE41; |
| 4598 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 4599 | VUnOpMicrokernelTester() |
| 4600 | .batch_size(batch_size) |
| 4601 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4602 | } |
| 4603 | } |
| 4604 | |
| 4605 | TEST(F32_SIGMOID__SSE41_P5_DIV_X4, batch_gt_4) { |
| 4606 | TEST_REQUIRES_X86_SSE41; |
| 4607 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 4608 | VUnOpMicrokernelTester() |
| 4609 | .batch_size(batch_size) |
| 4610 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4611 | } |
| 4612 | } |
| 4613 | |
| 4614 | TEST(F32_SIGMOID__SSE41_P5_DIV_X4, inplace) { |
| 4615 | TEST_REQUIRES_X86_SSE41; |
| 4616 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 4617 | VUnOpMicrokernelTester() |
| 4618 | .batch_size(batch_size) |
| 4619 | .inplace(true) |
| 4620 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4621 | } |
| 4622 | } |
| 4623 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4624 | |
| 4625 | |
| 4626 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4627 | TEST(F32_SIGMOID__SSE41_P5_DIV_X8, batch_eq_8) { |
| 4628 | TEST_REQUIRES_X86_SSE41; |
| 4629 | VUnOpMicrokernelTester() |
| 4630 | .batch_size(8) |
| 4631 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4632 | } |
| 4633 | |
| 4634 | TEST(F32_SIGMOID__SSE41_P5_DIV_X8, batch_div_8) { |
| 4635 | TEST_REQUIRES_X86_SSE41; |
| 4636 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 4637 | VUnOpMicrokernelTester() |
| 4638 | .batch_size(batch_size) |
| 4639 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4640 | } |
| 4641 | } |
| 4642 | |
| 4643 | TEST(F32_SIGMOID__SSE41_P5_DIV_X8, batch_lt_8) { |
| 4644 | TEST_REQUIRES_X86_SSE41; |
| 4645 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 4646 | VUnOpMicrokernelTester() |
| 4647 | .batch_size(batch_size) |
| 4648 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4649 | } |
| 4650 | } |
| 4651 | |
| 4652 | TEST(F32_SIGMOID__SSE41_P5_DIV_X8, batch_gt_8) { |
| 4653 | TEST_REQUIRES_X86_SSE41; |
| 4654 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 4655 | VUnOpMicrokernelTester() |
| 4656 | .batch_size(batch_size) |
| 4657 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4658 | } |
| 4659 | } |
| 4660 | |
| 4661 | TEST(F32_SIGMOID__SSE41_P5_DIV_X8, inplace) { |
| 4662 | TEST_REQUIRES_X86_SSE41; |
| 4663 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 4664 | VUnOpMicrokernelTester() |
| 4665 | .batch_size(batch_size) |
| 4666 | .inplace(true) |
| 4667 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4668 | } |
| 4669 | } |
| 4670 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4671 | |
| 4672 | |
| 4673 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4674 | TEST(F32_SIGMOID__SSE41_P5_DIV_X12, batch_eq_12) { |
| 4675 | TEST_REQUIRES_X86_SSE41; |
| 4676 | VUnOpMicrokernelTester() |
| 4677 | .batch_size(12) |
| 4678 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4679 | } |
| 4680 | |
| 4681 | TEST(F32_SIGMOID__SSE41_P5_DIV_X12, batch_div_12) { |
| 4682 | TEST_REQUIRES_X86_SSE41; |
| 4683 | for (size_t batch_size = 24; batch_size < 120; batch_size += 12) { |
| 4684 | VUnOpMicrokernelTester() |
| 4685 | .batch_size(batch_size) |
| 4686 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4687 | } |
| 4688 | } |
| 4689 | |
| 4690 | TEST(F32_SIGMOID__SSE41_P5_DIV_X12, batch_lt_12) { |
| 4691 | TEST_REQUIRES_X86_SSE41; |
| 4692 | for (size_t batch_size = 1; batch_size < 12; batch_size++) { |
| 4693 | VUnOpMicrokernelTester() |
| 4694 | .batch_size(batch_size) |
| 4695 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4696 | } |
| 4697 | } |
| 4698 | |
| 4699 | TEST(F32_SIGMOID__SSE41_P5_DIV_X12, batch_gt_12) { |
| 4700 | TEST_REQUIRES_X86_SSE41; |
| 4701 | for (size_t batch_size = 13; batch_size < 24; batch_size++) { |
| 4702 | VUnOpMicrokernelTester() |
| 4703 | .batch_size(batch_size) |
| 4704 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4705 | } |
| 4706 | } |
| 4707 | |
| 4708 | TEST(F32_SIGMOID__SSE41_P5_DIV_X12, inplace) { |
| 4709 | TEST_REQUIRES_X86_SSE41; |
| 4710 | for (size_t batch_size = 1; batch_size <= 60; batch_size += 11) { |
| 4711 | VUnOpMicrokernelTester() |
| 4712 | .batch_size(batch_size) |
| 4713 | .inplace(true) |
| 4714 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4715 | } |
| 4716 | } |
| 4717 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4718 | |
| 4719 | |
| 4720 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4721 | TEST(F32_SIGMOID__SSE41_P5_DIV_X16, batch_eq_16) { |
| 4722 | TEST_REQUIRES_X86_SSE41; |
| 4723 | VUnOpMicrokernelTester() |
| 4724 | .batch_size(16) |
| 4725 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4726 | } |
| 4727 | |
| 4728 | TEST(F32_SIGMOID__SSE41_P5_DIV_X16, batch_div_16) { |
| 4729 | TEST_REQUIRES_X86_SSE41; |
| 4730 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 4731 | VUnOpMicrokernelTester() |
| 4732 | .batch_size(batch_size) |
| 4733 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4734 | } |
| 4735 | } |
| 4736 | |
| 4737 | TEST(F32_SIGMOID__SSE41_P5_DIV_X16, batch_lt_16) { |
| 4738 | TEST_REQUIRES_X86_SSE41; |
| 4739 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 4740 | VUnOpMicrokernelTester() |
| 4741 | .batch_size(batch_size) |
| 4742 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4743 | } |
| 4744 | } |
| 4745 | |
| 4746 | TEST(F32_SIGMOID__SSE41_P5_DIV_X16, batch_gt_16) { |
| 4747 | TEST_REQUIRES_X86_SSE41; |
| 4748 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 4749 | VUnOpMicrokernelTester() |
| 4750 | .batch_size(batch_size) |
| 4751 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4752 | } |
| 4753 | } |
| 4754 | |
| 4755 | TEST(F32_SIGMOID__SSE41_P5_DIV_X16, inplace) { |
| 4756 | TEST_REQUIRES_X86_SSE41; |
| 4757 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 4758 | VUnOpMicrokernelTester() |
| 4759 | .batch_size(batch_size) |
| 4760 | .inplace(true) |
| 4761 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4762 | } |
| 4763 | } |
| 4764 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4765 | |
| 4766 | |
| 4767 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4768 | TEST(F32_SIGMOID__SSE41_P5_DIV_X20, batch_eq_20) { |
| 4769 | TEST_REQUIRES_X86_SSE41; |
| 4770 | VUnOpMicrokernelTester() |
| 4771 | .batch_size(20) |
| 4772 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4773 | } |
| 4774 | |
| 4775 | TEST(F32_SIGMOID__SSE41_P5_DIV_X20, batch_div_20) { |
| 4776 | TEST_REQUIRES_X86_SSE41; |
| 4777 | for (size_t batch_size = 40; batch_size < 200; batch_size += 20) { |
| 4778 | VUnOpMicrokernelTester() |
| 4779 | .batch_size(batch_size) |
| 4780 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4781 | } |
| 4782 | } |
| 4783 | |
| 4784 | TEST(F32_SIGMOID__SSE41_P5_DIV_X20, batch_lt_20) { |
| 4785 | TEST_REQUIRES_X86_SSE41; |
| 4786 | for (size_t batch_size = 1; batch_size < 20; batch_size++) { |
| 4787 | VUnOpMicrokernelTester() |
| 4788 | .batch_size(batch_size) |
| 4789 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4790 | } |
| 4791 | } |
| 4792 | |
| 4793 | TEST(F32_SIGMOID__SSE41_P5_DIV_X20, batch_gt_20) { |
| 4794 | TEST_REQUIRES_X86_SSE41; |
| 4795 | for (size_t batch_size = 21; batch_size < 40; batch_size++) { |
| 4796 | VUnOpMicrokernelTester() |
| 4797 | .batch_size(batch_size) |
| 4798 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4799 | } |
| 4800 | } |
| 4801 | |
| 4802 | TEST(F32_SIGMOID__SSE41_P5_DIV_X20, inplace) { |
| 4803 | TEST_REQUIRES_X86_SSE41; |
| 4804 | for (size_t batch_size = 1; batch_size <= 100; batch_size += 19) { |
| 4805 | VUnOpMicrokernelTester() |
| 4806 | .batch_size(batch_size) |
| 4807 | .inplace(true) |
| 4808 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4809 | } |
| 4810 | } |
| 4811 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4812 | |
| 4813 | |
| 4814 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4815 | TEST(F32_SIGMOID__SSE41_P5_DIV_X24, batch_eq_24) { |
| 4816 | TEST_REQUIRES_X86_SSE41; |
| 4817 | VUnOpMicrokernelTester() |
| 4818 | .batch_size(24) |
| 4819 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4820 | } |
| 4821 | |
| 4822 | TEST(F32_SIGMOID__SSE41_P5_DIV_X24, batch_div_24) { |
| 4823 | TEST_REQUIRES_X86_SSE41; |
| 4824 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 4825 | VUnOpMicrokernelTester() |
| 4826 | .batch_size(batch_size) |
| 4827 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4828 | } |
| 4829 | } |
| 4830 | |
| 4831 | TEST(F32_SIGMOID__SSE41_P5_DIV_X24, batch_lt_24) { |
| 4832 | TEST_REQUIRES_X86_SSE41; |
| 4833 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 4834 | VUnOpMicrokernelTester() |
| 4835 | .batch_size(batch_size) |
| 4836 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4837 | } |
| 4838 | } |
| 4839 | |
| 4840 | TEST(F32_SIGMOID__SSE41_P5_DIV_X24, batch_gt_24) { |
| 4841 | TEST_REQUIRES_X86_SSE41; |
| 4842 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 4843 | VUnOpMicrokernelTester() |
| 4844 | .batch_size(batch_size) |
| 4845 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4846 | } |
| 4847 | } |
| 4848 | |
| 4849 | TEST(F32_SIGMOID__SSE41_P5_DIV_X24, inplace) { |
| 4850 | TEST_REQUIRES_X86_SSE41; |
| 4851 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 4852 | VUnOpMicrokernelTester() |
| 4853 | .batch_size(batch_size) |
| 4854 | .inplace(true) |
| 4855 | .Test(xnn_f32_sigmoid_ukernel__sse41_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4856 | } |
| 4857 | } |
| 4858 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4859 | |
| 4860 | |
Marat Dukhan | fa0a432 | 2020-01-06 16:14:29 -0800 | [diff] [blame] | 4861 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4862 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X8, batch_eq_8) { |
| 4863 | TEST_REQUIRES_X86_AVX2; |
| 4864 | VUnOpMicrokernelTester() |
| 4865 | .batch_size(8) |
| 4866 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4867 | } |
| 4868 | |
| 4869 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X8, batch_div_8) { |
| 4870 | TEST_REQUIRES_X86_AVX2; |
| 4871 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 4872 | VUnOpMicrokernelTester() |
| 4873 | .batch_size(batch_size) |
| 4874 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4875 | } |
| 4876 | } |
| 4877 | |
| 4878 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X8, batch_lt_8) { |
| 4879 | TEST_REQUIRES_X86_AVX2; |
| 4880 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 4881 | VUnOpMicrokernelTester() |
| 4882 | .batch_size(batch_size) |
| 4883 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4884 | } |
| 4885 | } |
| 4886 | |
| 4887 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X8, batch_gt_8) { |
| 4888 | TEST_REQUIRES_X86_AVX2; |
| 4889 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 4890 | VUnOpMicrokernelTester() |
| 4891 | .batch_size(batch_size) |
| 4892 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4893 | } |
| 4894 | } |
| 4895 | |
| 4896 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X8, inplace) { |
| 4897 | TEST_REQUIRES_X86_AVX2; |
| 4898 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 4899 | VUnOpMicrokernelTester() |
| 4900 | .batch_size(batch_size) |
| 4901 | .inplace(true) |
| 4902 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4903 | } |
| 4904 | } |
| 4905 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4906 | |
| 4907 | |
| 4908 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4909 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X16, batch_eq_16) { |
| 4910 | TEST_REQUIRES_X86_AVX2; |
| 4911 | VUnOpMicrokernelTester() |
| 4912 | .batch_size(16) |
| 4913 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4914 | } |
| 4915 | |
| 4916 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X16, batch_div_16) { |
| 4917 | TEST_REQUIRES_X86_AVX2; |
| 4918 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 4919 | VUnOpMicrokernelTester() |
| 4920 | .batch_size(batch_size) |
| 4921 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4922 | } |
| 4923 | } |
| 4924 | |
| 4925 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X16, batch_lt_16) { |
| 4926 | TEST_REQUIRES_X86_AVX2; |
| 4927 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 4928 | VUnOpMicrokernelTester() |
| 4929 | .batch_size(batch_size) |
| 4930 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4931 | } |
| 4932 | } |
| 4933 | |
| 4934 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X16, batch_gt_16) { |
| 4935 | TEST_REQUIRES_X86_AVX2; |
| 4936 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 4937 | VUnOpMicrokernelTester() |
| 4938 | .batch_size(batch_size) |
| 4939 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4940 | } |
| 4941 | } |
| 4942 | |
| 4943 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X16, inplace) { |
| 4944 | TEST_REQUIRES_X86_AVX2; |
| 4945 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 4946 | VUnOpMicrokernelTester() |
| 4947 | .batch_size(batch_size) |
| 4948 | .inplace(true) |
| 4949 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4950 | } |
| 4951 | } |
| 4952 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4953 | |
| 4954 | |
| 4955 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4956 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X24, batch_eq_24) { |
| 4957 | TEST_REQUIRES_X86_AVX2; |
| 4958 | VUnOpMicrokernelTester() |
| 4959 | .batch_size(24) |
| 4960 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4961 | } |
| 4962 | |
| 4963 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X24, batch_div_24) { |
| 4964 | TEST_REQUIRES_X86_AVX2; |
| 4965 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 4966 | VUnOpMicrokernelTester() |
| 4967 | .batch_size(batch_size) |
| 4968 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4969 | } |
| 4970 | } |
| 4971 | |
| 4972 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X24, batch_lt_24) { |
| 4973 | TEST_REQUIRES_X86_AVX2; |
| 4974 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 4975 | VUnOpMicrokernelTester() |
| 4976 | .batch_size(batch_size) |
| 4977 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4978 | } |
| 4979 | } |
| 4980 | |
| 4981 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X24, batch_gt_24) { |
| 4982 | TEST_REQUIRES_X86_AVX2; |
| 4983 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 4984 | VUnOpMicrokernelTester() |
| 4985 | .batch_size(batch_size) |
| 4986 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4987 | } |
| 4988 | } |
| 4989 | |
| 4990 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X24, inplace) { |
| 4991 | TEST_REQUIRES_X86_AVX2; |
| 4992 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 4993 | VUnOpMicrokernelTester() |
| 4994 | .batch_size(batch_size) |
| 4995 | .inplace(true) |
| 4996 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 4997 | } |
| 4998 | } |
| 4999 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5000 | |
| 5001 | |
| 5002 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5003 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X32, batch_eq_32) { |
| 5004 | TEST_REQUIRES_X86_AVX2; |
| 5005 | VUnOpMicrokernelTester() |
| 5006 | .batch_size(32) |
| 5007 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x32, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5008 | } |
| 5009 | |
| 5010 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X32, batch_div_32) { |
| 5011 | TEST_REQUIRES_X86_AVX2; |
| 5012 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 5013 | VUnOpMicrokernelTester() |
| 5014 | .batch_size(batch_size) |
| 5015 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x32, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5016 | } |
| 5017 | } |
| 5018 | |
| 5019 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X32, batch_lt_32) { |
| 5020 | TEST_REQUIRES_X86_AVX2; |
| 5021 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 5022 | VUnOpMicrokernelTester() |
| 5023 | .batch_size(batch_size) |
| 5024 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x32, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5025 | } |
| 5026 | } |
| 5027 | |
| 5028 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X32, batch_gt_32) { |
| 5029 | TEST_REQUIRES_X86_AVX2; |
| 5030 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 5031 | VUnOpMicrokernelTester() |
| 5032 | .batch_size(batch_size) |
| 5033 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x32, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5034 | } |
| 5035 | } |
| 5036 | |
| 5037 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X32, inplace) { |
| 5038 | TEST_REQUIRES_X86_AVX2; |
| 5039 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 5040 | VUnOpMicrokernelTester() |
| 5041 | .batch_size(batch_size) |
| 5042 | .inplace(true) |
| 5043 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x32, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5044 | } |
| 5045 | } |
| 5046 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5047 | |
| 5048 | |
| 5049 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5050 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X40, batch_eq_40) { |
| 5051 | TEST_REQUIRES_X86_AVX2; |
| 5052 | VUnOpMicrokernelTester() |
| 5053 | .batch_size(40) |
| 5054 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x40, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5055 | } |
| 5056 | |
| 5057 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X40, batch_div_40) { |
| 5058 | TEST_REQUIRES_X86_AVX2; |
| 5059 | for (size_t batch_size = 80; batch_size < 400; batch_size += 40) { |
| 5060 | VUnOpMicrokernelTester() |
| 5061 | .batch_size(batch_size) |
| 5062 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x40, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5063 | } |
| 5064 | } |
| 5065 | |
| 5066 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X40, batch_lt_40) { |
| 5067 | TEST_REQUIRES_X86_AVX2; |
| 5068 | for (size_t batch_size = 1; batch_size < 40; batch_size++) { |
| 5069 | VUnOpMicrokernelTester() |
| 5070 | .batch_size(batch_size) |
| 5071 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x40, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5072 | } |
| 5073 | } |
| 5074 | |
| 5075 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X40, batch_gt_40) { |
| 5076 | TEST_REQUIRES_X86_AVX2; |
| 5077 | for (size_t batch_size = 41; batch_size < 80; batch_size++) { |
| 5078 | VUnOpMicrokernelTester() |
| 5079 | .batch_size(batch_size) |
| 5080 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x40, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5081 | } |
| 5082 | } |
| 5083 | |
| 5084 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X40, inplace) { |
| 5085 | TEST_REQUIRES_X86_AVX2; |
| 5086 | for (size_t batch_size = 1; batch_size <= 200; batch_size += 39) { |
| 5087 | VUnOpMicrokernelTester() |
| 5088 | .batch_size(batch_size) |
| 5089 | .inplace(true) |
| 5090 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x40, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5091 | } |
| 5092 | } |
| 5093 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5094 | |
| 5095 | |
| 5096 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5097 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X48, batch_eq_48) { |
| 5098 | TEST_REQUIRES_X86_AVX2; |
| 5099 | VUnOpMicrokernelTester() |
| 5100 | .batch_size(48) |
| 5101 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x48, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5102 | } |
| 5103 | |
| 5104 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X48, batch_div_48) { |
| 5105 | TEST_REQUIRES_X86_AVX2; |
| 5106 | for (size_t batch_size = 96; batch_size < 480; batch_size += 48) { |
| 5107 | VUnOpMicrokernelTester() |
| 5108 | .batch_size(batch_size) |
| 5109 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x48, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5110 | } |
| 5111 | } |
| 5112 | |
| 5113 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X48, batch_lt_48) { |
| 5114 | TEST_REQUIRES_X86_AVX2; |
| 5115 | for (size_t batch_size = 1; batch_size < 48; batch_size++) { |
| 5116 | VUnOpMicrokernelTester() |
| 5117 | .batch_size(batch_size) |
| 5118 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x48, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5119 | } |
| 5120 | } |
| 5121 | |
| 5122 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X48, batch_gt_48) { |
| 5123 | TEST_REQUIRES_X86_AVX2; |
| 5124 | for (size_t batch_size = 49; batch_size < 96; batch_size++) { |
| 5125 | VUnOpMicrokernelTester() |
| 5126 | .batch_size(batch_size) |
| 5127 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x48, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5128 | } |
| 5129 | } |
| 5130 | |
| 5131 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X48, inplace) { |
| 5132 | TEST_REQUIRES_X86_AVX2; |
| 5133 | for (size_t batch_size = 1; batch_size <= 240; batch_size += 47) { |
| 5134 | VUnOpMicrokernelTester() |
| 5135 | .batch_size(batch_size) |
| 5136 | .inplace(true) |
| 5137 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x48, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5138 | } |
| 5139 | } |
| 5140 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5141 | |
| 5142 | |
| 5143 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5144 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X56, batch_eq_56) { |
| 5145 | TEST_REQUIRES_X86_AVX2; |
| 5146 | VUnOpMicrokernelTester() |
| 5147 | .batch_size(56) |
| 5148 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x56, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5149 | } |
| 5150 | |
| 5151 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X56, batch_div_56) { |
| 5152 | TEST_REQUIRES_X86_AVX2; |
| 5153 | for (size_t batch_size = 112; batch_size < 560; batch_size += 56) { |
| 5154 | VUnOpMicrokernelTester() |
| 5155 | .batch_size(batch_size) |
| 5156 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x56, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5157 | } |
| 5158 | } |
| 5159 | |
| 5160 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X56, batch_lt_56) { |
| 5161 | TEST_REQUIRES_X86_AVX2; |
| 5162 | for (size_t batch_size = 1; batch_size < 56; batch_size++) { |
| 5163 | VUnOpMicrokernelTester() |
| 5164 | .batch_size(batch_size) |
| 5165 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x56, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5166 | } |
| 5167 | } |
| 5168 | |
| 5169 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X56, batch_gt_56) { |
| 5170 | TEST_REQUIRES_X86_AVX2; |
| 5171 | for (size_t batch_size = 57; batch_size < 112; batch_size++) { |
| 5172 | VUnOpMicrokernelTester() |
| 5173 | .batch_size(batch_size) |
| 5174 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x56, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5175 | } |
| 5176 | } |
| 5177 | |
| 5178 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X56, inplace) { |
| 5179 | TEST_REQUIRES_X86_AVX2; |
| 5180 | for (size_t batch_size = 1; batch_size <= 280; batch_size += 55) { |
| 5181 | VUnOpMicrokernelTester() |
| 5182 | .batch_size(batch_size) |
| 5183 | .inplace(true) |
| 5184 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x56, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5185 | } |
| 5186 | } |
| 5187 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5188 | |
| 5189 | |
| 5190 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5191 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X64, batch_eq_64) { |
| 5192 | TEST_REQUIRES_X86_AVX2; |
| 5193 | VUnOpMicrokernelTester() |
| 5194 | .batch_size(64) |
| 5195 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x64, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5196 | } |
| 5197 | |
| 5198 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X64, batch_div_64) { |
| 5199 | TEST_REQUIRES_X86_AVX2; |
| 5200 | for (size_t batch_size = 128; batch_size < 640; batch_size += 64) { |
| 5201 | VUnOpMicrokernelTester() |
| 5202 | .batch_size(batch_size) |
| 5203 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x64, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5204 | } |
| 5205 | } |
| 5206 | |
| 5207 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X64, batch_lt_64) { |
| 5208 | TEST_REQUIRES_X86_AVX2; |
| 5209 | for (size_t batch_size = 1; batch_size < 64; batch_size++) { |
| 5210 | VUnOpMicrokernelTester() |
| 5211 | .batch_size(batch_size) |
| 5212 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x64, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5213 | } |
| 5214 | } |
| 5215 | |
| 5216 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X64, batch_gt_64) { |
| 5217 | TEST_REQUIRES_X86_AVX2; |
| 5218 | for (size_t batch_size = 65; batch_size < 128; batch_size++) { |
| 5219 | VUnOpMicrokernelTester() |
| 5220 | .batch_size(batch_size) |
| 5221 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x64, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5222 | } |
| 5223 | } |
| 5224 | |
| 5225 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X64, inplace) { |
| 5226 | TEST_REQUIRES_X86_AVX2; |
| 5227 | for (size_t batch_size = 1; batch_size <= 320; batch_size += 63) { |
| 5228 | VUnOpMicrokernelTester() |
| 5229 | .batch_size(batch_size) |
| 5230 | .inplace(true) |
| 5231 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x64, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5232 | } |
| 5233 | } |
| 5234 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5235 | |
| 5236 | |
| 5237 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5238 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X72, batch_eq_72) { |
| 5239 | TEST_REQUIRES_X86_AVX2; |
| 5240 | VUnOpMicrokernelTester() |
| 5241 | .batch_size(72) |
| 5242 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x72, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5243 | } |
| 5244 | |
| 5245 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X72, batch_div_72) { |
| 5246 | TEST_REQUIRES_X86_AVX2; |
| 5247 | for (size_t batch_size = 144; batch_size < 720; batch_size += 72) { |
| 5248 | VUnOpMicrokernelTester() |
| 5249 | .batch_size(batch_size) |
| 5250 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x72, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5251 | } |
| 5252 | } |
| 5253 | |
| 5254 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X72, batch_lt_72) { |
| 5255 | TEST_REQUIRES_X86_AVX2; |
| 5256 | for (size_t batch_size = 1; batch_size < 72; batch_size++) { |
| 5257 | VUnOpMicrokernelTester() |
| 5258 | .batch_size(batch_size) |
| 5259 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x72, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5260 | } |
| 5261 | } |
| 5262 | |
| 5263 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X72, batch_gt_72) { |
| 5264 | TEST_REQUIRES_X86_AVX2; |
| 5265 | for (size_t batch_size = 73; batch_size < 144; batch_size++) { |
| 5266 | VUnOpMicrokernelTester() |
| 5267 | .batch_size(batch_size) |
| 5268 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x72, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5269 | } |
| 5270 | } |
| 5271 | |
| 5272 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X72, inplace) { |
| 5273 | TEST_REQUIRES_X86_AVX2; |
| 5274 | for (size_t batch_size = 1; batch_size <= 360; batch_size += 71) { |
| 5275 | VUnOpMicrokernelTester() |
| 5276 | .batch_size(batch_size) |
| 5277 | .inplace(true) |
| 5278 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x72, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5279 | } |
| 5280 | } |
| 5281 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5282 | |
| 5283 | |
| 5284 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5285 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X80, batch_eq_80) { |
| 5286 | TEST_REQUIRES_X86_AVX2; |
| 5287 | VUnOpMicrokernelTester() |
| 5288 | .batch_size(80) |
| 5289 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x80, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5290 | } |
| 5291 | |
| 5292 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X80, batch_div_80) { |
| 5293 | TEST_REQUIRES_X86_AVX2; |
| 5294 | for (size_t batch_size = 160; batch_size < 800; batch_size += 80) { |
| 5295 | VUnOpMicrokernelTester() |
| 5296 | .batch_size(batch_size) |
| 5297 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x80, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5298 | } |
| 5299 | } |
| 5300 | |
| 5301 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X80, batch_lt_80) { |
| 5302 | TEST_REQUIRES_X86_AVX2; |
| 5303 | for (size_t batch_size = 1; batch_size < 80; batch_size++) { |
| 5304 | VUnOpMicrokernelTester() |
| 5305 | .batch_size(batch_size) |
| 5306 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x80, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5307 | } |
| 5308 | } |
| 5309 | |
| 5310 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X80, batch_gt_80) { |
| 5311 | TEST_REQUIRES_X86_AVX2; |
| 5312 | for (size_t batch_size = 81; batch_size < 160; batch_size++) { |
| 5313 | VUnOpMicrokernelTester() |
| 5314 | .batch_size(batch_size) |
| 5315 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x80, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5316 | } |
| 5317 | } |
| 5318 | |
| 5319 | TEST(F32_SIGMOID__AVX2_RR1_P5_DIV_X80, inplace) { |
| 5320 | TEST_REQUIRES_X86_AVX2; |
| 5321 | for (size_t batch_size = 1; batch_size <= 400; batch_size += 79) { |
| 5322 | VUnOpMicrokernelTester() |
| 5323 | .batch_size(batch_size) |
| 5324 | .inplace(true) |
| 5325 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_div_x80, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5326 | } |
| 5327 | } |
| 5328 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5329 | |
| 5330 | |
| 5331 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5332 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X8, batch_eq_8) { |
| 5333 | TEST_REQUIRES_X86_AVX2; |
| 5334 | VUnOpMicrokernelTester() |
| 5335 | .batch_size(8) |
| 5336 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5337 | } |
| 5338 | |
| 5339 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X8, batch_div_8) { |
| 5340 | TEST_REQUIRES_X86_AVX2; |
| 5341 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 5342 | VUnOpMicrokernelTester() |
| 5343 | .batch_size(batch_size) |
| 5344 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5345 | } |
| 5346 | } |
| 5347 | |
| 5348 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X8, batch_lt_8) { |
| 5349 | TEST_REQUIRES_X86_AVX2; |
| 5350 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 5351 | VUnOpMicrokernelTester() |
| 5352 | .batch_size(batch_size) |
| 5353 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5354 | } |
| 5355 | } |
| 5356 | |
| 5357 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X8, batch_gt_8) { |
| 5358 | TEST_REQUIRES_X86_AVX2; |
| 5359 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 5360 | VUnOpMicrokernelTester() |
| 5361 | .batch_size(batch_size) |
| 5362 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5363 | } |
| 5364 | } |
| 5365 | |
| 5366 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X8, inplace) { |
| 5367 | TEST_REQUIRES_X86_AVX2; |
| 5368 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 5369 | VUnOpMicrokernelTester() |
| 5370 | .batch_size(batch_size) |
| 5371 | .inplace(true) |
| 5372 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5373 | } |
| 5374 | } |
| 5375 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5376 | |
| 5377 | |
| 5378 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5379 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X16, batch_eq_16) { |
| 5380 | TEST_REQUIRES_X86_AVX2; |
| 5381 | VUnOpMicrokernelTester() |
| 5382 | .batch_size(16) |
| 5383 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5384 | } |
| 5385 | |
| 5386 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X16, batch_div_16) { |
| 5387 | TEST_REQUIRES_X86_AVX2; |
| 5388 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 5389 | VUnOpMicrokernelTester() |
| 5390 | .batch_size(batch_size) |
| 5391 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5392 | } |
| 5393 | } |
| 5394 | |
| 5395 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X16, batch_lt_16) { |
| 5396 | TEST_REQUIRES_X86_AVX2; |
| 5397 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 5398 | VUnOpMicrokernelTester() |
| 5399 | .batch_size(batch_size) |
| 5400 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5401 | } |
| 5402 | } |
| 5403 | |
| 5404 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X16, batch_gt_16) { |
| 5405 | TEST_REQUIRES_X86_AVX2; |
| 5406 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 5407 | VUnOpMicrokernelTester() |
| 5408 | .batch_size(batch_size) |
| 5409 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5410 | } |
| 5411 | } |
| 5412 | |
| 5413 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X16, inplace) { |
| 5414 | TEST_REQUIRES_X86_AVX2; |
| 5415 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 5416 | VUnOpMicrokernelTester() |
| 5417 | .batch_size(batch_size) |
| 5418 | .inplace(true) |
| 5419 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5420 | } |
| 5421 | } |
| 5422 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5423 | |
| 5424 | |
| 5425 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5426 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X24, batch_eq_24) { |
| 5427 | TEST_REQUIRES_X86_AVX2; |
| 5428 | VUnOpMicrokernelTester() |
| 5429 | .batch_size(24) |
| 5430 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5431 | } |
| 5432 | |
| 5433 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X24, batch_div_24) { |
| 5434 | TEST_REQUIRES_X86_AVX2; |
| 5435 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 5436 | VUnOpMicrokernelTester() |
| 5437 | .batch_size(batch_size) |
| 5438 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5439 | } |
| 5440 | } |
| 5441 | |
| 5442 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X24, batch_lt_24) { |
| 5443 | TEST_REQUIRES_X86_AVX2; |
| 5444 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 5445 | VUnOpMicrokernelTester() |
| 5446 | .batch_size(batch_size) |
| 5447 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5448 | } |
| 5449 | } |
| 5450 | |
| 5451 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X24, batch_gt_24) { |
| 5452 | TEST_REQUIRES_X86_AVX2; |
| 5453 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 5454 | VUnOpMicrokernelTester() |
| 5455 | .batch_size(batch_size) |
| 5456 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5457 | } |
| 5458 | } |
| 5459 | |
| 5460 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X24, inplace) { |
| 5461 | TEST_REQUIRES_X86_AVX2; |
| 5462 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 5463 | VUnOpMicrokernelTester() |
| 5464 | .batch_size(batch_size) |
| 5465 | .inplace(true) |
| 5466 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5467 | } |
| 5468 | } |
| 5469 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5470 | |
| 5471 | |
| 5472 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5473 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X32, batch_eq_32) { |
| 5474 | TEST_REQUIRES_X86_AVX2; |
| 5475 | VUnOpMicrokernelTester() |
| 5476 | .batch_size(32) |
| 5477 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x32, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5478 | } |
| 5479 | |
| 5480 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X32, batch_div_32) { |
| 5481 | TEST_REQUIRES_X86_AVX2; |
| 5482 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 5483 | VUnOpMicrokernelTester() |
| 5484 | .batch_size(batch_size) |
| 5485 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x32, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5486 | } |
| 5487 | } |
| 5488 | |
| 5489 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X32, batch_lt_32) { |
| 5490 | TEST_REQUIRES_X86_AVX2; |
| 5491 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 5492 | VUnOpMicrokernelTester() |
| 5493 | .batch_size(batch_size) |
| 5494 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x32, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5495 | } |
| 5496 | } |
| 5497 | |
| 5498 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X32, batch_gt_32) { |
| 5499 | TEST_REQUIRES_X86_AVX2; |
| 5500 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 5501 | VUnOpMicrokernelTester() |
| 5502 | .batch_size(batch_size) |
| 5503 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x32, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5504 | } |
| 5505 | } |
| 5506 | |
| 5507 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X32, inplace) { |
| 5508 | TEST_REQUIRES_X86_AVX2; |
| 5509 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 5510 | VUnOpMicrokernelTester() |
| 5511 | .batch_size(batch_size) |
| 5512 | .inplace(true) |
| 5513 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x32, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5514 | } |
| 5515 | } |
| 5516 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5517 | |
| 5518 | |
| 5519 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5520 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X40, batch_eq_40) { |
| 5521 | TEST_REQUIRES_X86_AVX2; |
| 5522 | VUnOpMicrokernelTester() |
| 5523 | .batch_size(40) |
| 5524 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x40, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5525 | } |
| 5526 | |
| 5527 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X40, batch_div_40) { |
| 5528 | TEST_REQUIRES_X86_AVX2; |
| 5529 | for (size_t batch_size = 80; batch_size < 400; batch_size += 40) { |
| 5530 | VUnOpMicrokernelTester() |
| 5531 | .batch_size(batch_size) |
| 5532 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x40, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5533 | } |
| 5534 | } |
| 5535 | |
| 5536 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X40, batch_lt_40) { |
| 5537 | TEST_REQUIRES_X86_AVX2; |
| 5538 | for (size_t batch_size = 1; batch_size < 40; batch_size++) { |
| 5539 | VUnOpMicrokernelTester() |
| 5540 | .batch_size(batch_size) |
| 5541 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x40, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5542 | } |
| 5543 | } |
| 5544 | |
| 5545 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X40, batch_gt_40) { |
| 5546 | TEST_REQUIRES_X86_AVX2; |
| 5547 | for (size_t batch_size = 41; batch_size < 80; batch_size++) { |
| 5548 | VUnOpMicrokernelTester() |
| 5549 | .batch_size(batch_size) |
| 5550 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x40, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5551 | } |
| 5552 | } |
| 5553 | |
| 5554 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X40, inplace) { |
| 5555 | TEST_REQUIRES_X86_AVX2; |
| 5556 | for (size_t batch_size = 1; batch_size <= 200; batch_size += 39) { |
| 5557 | VUnOpMicrokernelTester() |
| 5558 | .batch_size(batch_size) |
| 5559 | .inplace(true) |
| 5560 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x40, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5561 | } |
| 5562 | } |
| 5563 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5564 | |
| 5565 | |
| 5566 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5567 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X48, batch_eq_48) { |
| 5568 | TEST_REQUIRES_X86_AVX2; |
| 5569 | VUnOpMicrokernelTester() |
| 5570 | .batch_size(48) |
| 5571 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x48, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5572 | } |
| 5573 | |
| 5574 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X48, batch_div_48) { |
| 5575 | TEST_REQUIRES_X86_AVX2; |
| 5576 | for (size_t batch_size = 96; batch_size < 480; batch_size += 48) { |
| 5577 | VUnOpMicrokernelTester() |
| 5578 | .batch_size(batch_size) |
| 5579 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x48, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5580 | } |
| 5581 | } |
| 5582 | |
| 5583 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X48, batch_lt_48) { |
| 5584 | TEST_REQUIRES_X86_AVX2; |
| 5585 | for (size_t batch_size = 1; batch_size < 48; batch_size++) { |
| 5586 | VUnOpMicrokernelTester() |
| 5587 | .batch_size(batch_size) |
| 5588 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x48, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5589 | } |
| 5590 | } |
| 5591 | |
| 5592 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X48, batch_gt_48) { |
| 5593 | TEST_REQUIRES_X86_AVX2; |
| 5594 | for (size_t batch_size = 49; batch_size < 96; batch_size++) { |
| 5595 | VUnOpMicrokernelTester() |
| 5596 | .batch_size(batch_size) |
| 5597 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x48, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5598 | } |
| 5599 | } |
| 5600 | |
| 5601 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X48, inplace) { |
| 5602 | TEST_REQUIRES_X86_AVX2; |
| 5603 | for (size_t batch_size = 1; batch_size <= 240; batch_size += 47) { |
| 5604 | VUnOpMicrokernelTester() |
| 5605 | .batch_size(batch_size) |
| 5606 | .inplace(true) |
| 5607 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x48, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5608 | } |
| 5609 | } |
| 5610 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5611 | |
| 5612 | |
| 5613 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5614 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X56, batch_eq_56) { |
| 5615 | TEST_REQUIRES_X86_AVX2; |
| 5616 | VUnOpMicrokernelTester() |
| 5617 | .batch_size(56) |
| 5618 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x56, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5619 | } |
| 5620 | |
| 5621 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X56, batch_div_56) { |
| 5622 | TEST_REQUIRES_X86_AVX2; |
| 5623 | for (size_t batch_size = 112; batch_size < 560; batch_size += 56) { |
| 5624 | VUnOpMicrokernelTester() |
| 5625 | .batch_size(batch_size) |
| 5626 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x56, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5627 | } |
| 5628 | } |
| 5629 | |
| 5630 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X56, batch_lt_56) { |
| 5631 | TEST_REQUIRES_X86_AVX2; |
| 5632 | for (size_t batch_size = 1; batch_size < 56; batch_size++) { |
| 5633 | VUnOpMicrokernelTester() |
| 5634 | .batch_size(batch_size) |
| 5635 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x56, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5636 | } |
| 5637 | } |
| 5638 | |
| 5639 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X56, batch_gt_56) { |
| 5640 | TEST_REQUIRES_X86_AVX2; |
| 5641 | for (size_t batch_size = 57; batch_size < 112; batch_size++) { |
| 5642 | VUnOpMicrokernelTester() |
| 5643 | .batch_size(batch_size) |
| 5644 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x56, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5645 | } |
| 5646 | } |
| 5647 | |
| 5648 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X56, inplace) { |
| 5649 | TEST_REQUIRES_X86_AVX2; |
| 5650 | for (size_t batch_size = 1; batch_size <= 280; batch_size += 55) { |
| 5651 | VUnOpMicrokernelTester() |
| 5652 | .batch_size(batch_size) |
| 5653 | .inplace(true) |
| 5654 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x56, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5655 | } |
| 5656 | } |
| 5657 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5658 | |
| 5659 | |
| 5660 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5661 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X64, batch_eq_64) { |
| 5662 | TEST_REQUIRES_X86_AVX2; |
| 5663 | VUnOpMicrokernelTester() |
| 5664 | .batch_size(64) |
| 5665 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x64, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5666 | } |
| 5667 | |
| 5668 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X64, batch_div_64) { |
| 5669 | TEST_REQUIRES_X86_AVX2; |
| 5670 | for (size_t batch_size = 128; batch_size < 640; batch_size += 64) { |
| 5671 | VUnOpMicrokernelTester() |
| 5672 | .batch_size(batch_size) |
| 5673 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x64, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5674 | } |
| 5675 | } |
| 5676 | |
| 5677 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X64, batch_lt_64) { |
| 5678 | TEST_REQUIRES_X86_AVX2; |
| 5679 | for (size_t batch_size = 1; batch_size < 64; batch_size++) { |
| 5680 | VUnOpMicrokernelTester() |
| 5681 | .batch_size(batch_size) |
| 5682 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x64, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5683 | } |
| 5684 | } |
| 5685 | |
| 5686 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X64, batch_gt_64) { |
| 5687 | TEST_REQUIRES_X86_AVX2; |
| 5688 | for (size_t batch_size = 65; batch_size < 128; batch_size++) { |
| 5689 | VUnOpMicrokernelTester() |
| 5690 | .batch_size(batch_size) |
| 5691 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x64, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5692 | } |
| 5693 | } |
| 5694 | |
| 5695 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X64, inplace) { |
| 5696 | TEST_REQUIRES_X86_AVX2; |
| 5697 | for (size_t batch_size = 1; batch_size <= 320; batch_size += 63) { |
| 5698 | VUnOpMicrokernelTester() |
| 5699 | .batch_size(batch_size) |
| 5700 | .inplace(true) |
| 5701 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x64, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5702 | } |
| 5703 | } |
| 5704 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5705 | |
| 5706 | |
| 5707 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5708 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X72, batch_eq_72) { |
| 5709 | TEST_REQUIRES_X86_AVX2; |
| 5710 | VUnOpMicrokernelTester() |
| 5711 | .batch_size(72) |
| 5712 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x72, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5713 | } |
| 5714 | |
| 5715 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X72, batch_div_72) { |
| 5716 | TEST_REQUIRES_X86_AVX2; |
| 5717 | for (size_t batch_size = 144; batch_size < 720; batch_size += 72) { |
| 5718 | VUnOpMicrokernelTester() |
| 5719 | .batch_size(batch_size) |
| 5720 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x72, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5721 | } |
| 5722 | } |
| 5723 | |
| 5724 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X72, batch_lt_72) { |
| 5725 | TEST_REQUIRES_X86_AVX2; |
| 5726 | for (size_t batch_size = 1; batch_size < 72; batch_size++) { |
| 5727 | VUnOpMicrokernelTester() |
| 5728 | .batch_size(batch_size) |
| 5729 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x72, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5730 | } |
| 5731 | } |
| 5732 | |
| 5733 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X72, batch_gt_72) { |
| 5734 | TEST_REQUIRES_X86_AVX2; |
| 5735 | for (size_t batch_size = 73; batch_size < 144; batch_size++) { |
| 5736 | VUnOpMicrokernelTester() |
| 5737 | .batch_size(batch_size) |
| 5738 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x72, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5739 | } |
| 5740 | } |
| 5741 | |
| 5742 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X72, inplace) { |
| 5743 | TEST_REQUIRES_X86_AVX2; |
| 5744 | for (size_t batch_size = 1; batch_size <= 360; batch_size += 71) { |
| 5745 | VUnOpMicrokernelTester() |
| 5746 | .batch_size(batch_size) |
| 5747 | .inplace(true) |
| 5748 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x72, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5749 | } |
| 5750 | } |
| 5751 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5752 | |
| 5753 | |
| 5754 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5755 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X80, batch_eq_80) { |
| 5756 | TEST_REQUIRES_X86_AVX2; |
| 5757 | VUnOpMicrokernelTester() |
| 5758 | .batch_size(80) |
| 5759 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x80, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5760 | } |
| 5761 | |
| 5762 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X80, batch_div_80) { |
| 5763 | TEST_REQUIRES_X86_AVX2; |
| 5764 | for (size_t batch_size = 160; batch_size < 800; batch_size += 80) { |
| 5765 | VUnOpMicrokernelTester() |
| 5766 | .batch_size(batch_size) |
| 5767 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x80, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5768 | } |
| 5769 | } |
| 5770 | |
| 5771 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X80, batch_lt_80) { |
| 5772 | TEST_REQUIRES_X86_AVX2; |
| 5773 | for (size_t batch_size = 1; batch_size < 80; batch_size++) { |
| 5774 | VUnOpMicrokernelTester() |
| 5775 | .batch_size(batch_size) |
| 5776 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x80, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5777 | } |
| 5778 | } |
| 5779 | |
| 5780 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X80, batch_gt_80) { |
| 5781 | TEST_REQUIRES_X86_AVX2; |
| 5782 | for (size_t batch_size = 81; batch_size < 160; batch_size++) { |
| 5783 | VUnOpMicrokernelTester() |
| 5784 | .batch_size(batch_size) |
| 5785 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x80, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5786 | } |
| 5787 | } |
| 5788 | |
| 5789 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR1FMA_X80, inplace) { |
| 5790 | TEST_REQUIRES_X86_AVX2; |
| 5791 | for (size_t batch_size = 1; batch_size <= 400; batch_size += 79) { |
| 5792 | VUnOpMicrokernelTester() |
| 5793 | .batch_size(batch_size) |
| 5794 | .inplace(true) |
| 5795 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr1fma_x80, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5796 | } |
| 5797 | } |
| 5798 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5799 | |
| 5800 | |
| 5801 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5802 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X8, batch_eq_8) { |
| 5803 | TEST_REQUIRES_X86_AVX2; |
| 5804 | VUnOpMicrokernelTester() |
| 5805 | .batch_size(8) |
| 5806 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5807 | } |
| 5808 | |
| 5809 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X8, batch_div_8) { |
| 5810 | TEST_REQUIRES_X86_AVX2; |
| 5811 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 5812 | VUnOpMicrokernelTester() |
| 5813 | .batch_size(batch_size) |
| 5814 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5815 | } |
| 5816 | } |
| 5817 | |
| 5818 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X8, batch_lt_8) { |
| 5819 | TEST_REQUIRES_X86_AVX2; |
| 5820 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 5821 | VUnOpMicrokernelTester() |
| 5822 | .batch_size(batch_size) |
| 5823 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5824 | } |
| 5825 | } |
| 5826 | |
| 5827 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X8, batch_gt_8) { |
| 5828 | TEST_REQUIRES_X86_AVX2; |
| 5829 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 5830 | VUnOpMicrokernelTester() |
| 5831 | .batch_size(batch_size) |
| 5832 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5833 | } |
| 5834 | } |
| 5835 | |
| 5836 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X8, inplace) { |
| 5837 | TEST_REQUIRES_X86_AVX2; |
| 5838 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 5839 | VUnOpMicrokernelTester() |
| 5840 | .batch_size(batch_size) |
| 5841 | .inplace(true) |
| 5842 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x8, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5843 | } |
| 5844 | } |
| 5845 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5846 | |
| 5847 | |
| 5848 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5849 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X16, batch_eq_16) { |
| 5850 | TEST_REQUIRES_X86_AVX2; |
| 5851 | VUnOpMicrokernelTester() |
| 5852 | .batch_size(16) |
| 5853 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5854 | } |
| 5855 | |
| 5856 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X16, batch_div_16) { |
| 5857 | TEST_REQUIRES_X86_AVX2; |
| 5858 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 5859 | VUnOpMicrokernelTester() |
| 5860 | .batch_size(batch_size) |
| 5861 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5862 | } |
| 5863 | } |
| 5864 | |
| 5865 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X16, batch_lt_16) { |
| 5866 | TEST_REQUIRES_X86_AVX2; |
| 5867 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 5868 | VUnOpMicrokernelTester() |
| 5869 | .batch_size(batch_size) |
| 5870 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5871 | } |
| 5872 | } |
| 5873 | |
| 5874 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X16, batch_gt_16) { |
| 5875 | TEST_REQUIRES_X86_AVX2; |
| 5876 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 5877 | VUnOpMicrokernelTester() |
| 5878 | .batch_size(batch_size) |
| 5879 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5880 | } |
| 5881 | } |
| 5882 | |
| 5883 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X16, inplace) { |
| 5884 | TEST_REQUIRES_X86_AVX2; |
| 5885 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 5886 | VUnOpMicrokernelTester() |
| 5887 | .batch_size(batch_size) |
| 5888 | .inplace(true) |
| 5889 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x16, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5890 | } |
| 5891 | } |
| 5892 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5893 | |
| 5894 | |
| 5895 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5896 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X24, batch_eq_24) { |
| 5897 | TEST_REQUIRES_X86_AVX2; |
| 5898 | VUnOpMicrokernelTester() |
| 5899 | .batch_size(24) |
| 5900 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5901 | } |
| 5902 | |
| 5903 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X24, batch_div_24) { |
| 5904 | TEST_REQUIRES_X86_AVX2; |
| 5905 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 5906 | VUnOpMicrokernelTester() |
| 5907 | .batch_size(batch_size) |
| 5908 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5909 | } |
| 5910 | } |
| 5911 | |
| 5912 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X24, batch_lt_24) { |
| 5913 | TEST_REQUIRES_X86_AVX2; |
| 5914 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 5915 | VUnOpMicrokernelTester() |
| 5916 | .batch_size(batch_size) |
| 5917 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5918 | } |
| 5919 | } |
| 5920 | |
| 5921 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X24, batch_gt_24) { |
| 5922 | TEST_REQUIRES_X86_AVX2; |
| 5923 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 5924 | VUnOpMicrokernelTester() |
| 5925 | .batch_size(batch_size) |
| 5926 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5927 | } |
| 5928 | } |
| 5929 | |
| 5930 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X24, inplace) { |
| 5931 | TEST_REQUIRES_X86_AVX2; |
| 5932 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 5933 | VUnOpMicrokernelTester() |
| 5934 | .batch_size(batch_size) |
| 5935 | .inplace(true) |
| 5936 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x24, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5937 | } |
| 5938 | } |
| 5939 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5940 | |
| 5941 | |
| 5942 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5943 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X32, batch_eq_32) { |
| 5944 | TEST_REQUIRES_X86_AVX2; |
| 5945 | VUnOpMicrokernelTester() |
| 5946 | .batch_size(32) |
| 5947 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x32, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5948 | } |
| 5949 | |
| 5950 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X32, batch_div_32) { |
| 5951 | TEST_REQUIRES_X86_AVX2; |
| 5952 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 5953 | VUnOpMicrokernelTester() |
| 5954 | .batch_size(batch_size) |
| 5955 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x32, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5956 | } |
| 5957 | } |
| 5958 | |
| 5959 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X32, batch_lt_32) { |
| 5960 | TEST_REQUIRES_X86_AVX2; |
| 5961 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 5962 | VUnOpMicrokernelTester() |
| 5963 | .batch_size(batch_size) |
| 5964 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x32, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5965 | } |
| 5966 | } |
| 5967 | |
| 5968 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X32, batch_gt_32) { |
| 5969 | TEST_REQUIRES_X86_AVX2; |
| 5970 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 5971 | VUnOpMicrokernelTester() |
| 5972 | .batch_size(batch_size) |
| 5973 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x32, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5974 | } |
| 5975 | } |
| 5976 | |
| 5977 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X32, inplace) { |
| 5978 | TEST_REQUIRES_X86_AVX2; |
| 5979 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 5980 | VUnOpMicrokernelTester() |
| 5981 | .batch_size(batch_size) |
| 5982 | .inplace(true) |
| 5983 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x32, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5984 | } |
| 5985 | } |
| 5986 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5987 | |
| 5988 | |
| 5989 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5990 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X40, batch_eq_40) { |
| 5991 | TEST_REQUIRES_X86_AVX2; |
| 5992 | VUnOpMicrokernelTester() |
| 5993 | .batch_size(40) |
| 5994 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x40, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 5995 | } |
| 5996 | |
| 5997 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X40, batch_div_40) { |
| 5998 | TEST_REQUIRES_X86_AVX2; |
| 5999 | for (size_t batch_size = 80; batch_size < 400; batch_size += 40) { |
| 6000 | VUnOpMicrokernelTester() |
| 6001 | .batch_size(batch_size) |
| 6002 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x40, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6003 | } |
| 6004 | } |
| 6005 | |
| 6006 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X40, batch_lt_40) { |
| 6007 | TEST_REQUIRES_X86_AVX2; |
| 6008 | for (size_t batch_size = 1; batch_size < 40; batch_size++) { |
| 6009 | VUnOpMicrokernelTester() |
| 6010 | .batch_size(batch_size) |
| 6011 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x40, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6012 | } |
| 6013 | } |
| 6014 | |
| 6015 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X40, batch_gt_40) { |
| 6016 | TEST_REQUIRES_X86_AVX2; |
| 6017 | for (size_t batch_size = 41; batch_size < 80; batch_size++) { |
| 6018 | VUnOpMicrokernelTester() |
| 6019 | .batch_size(batch_size) |
| 6020 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x40, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6021 | } |
| 6022 | } |
| 6023 | |
| 6024 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X40, inplace) { |
| 6025 | TEST_REQUIRES_X86_AVX2; |
| 6026 | for (size_t batch_size = 1; batch_size <= 200; batch_size += 39) { |
| 6027 | VUnOpMicrokernelTester() |
| 6028 | .batch_size(batch_size) |
| 6029 | .inplace(true) |
| 6030 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x40, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6031 | } |
| 6032 | } |
| 6033 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 6034 | |
| 6035 | |
| 6036 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 6037 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X48, batch_eq_48) { |
| 6038 | TEST_REQUIRES_X86_AVX2; |
| 6039 | VUnOpMicrokernelTester() |
| 6040 | .batch_size(48) |
| 6041 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x48, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6042 | } |
| 6043 | |
| 6044 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X48, batch_div_48) { |
| 6045 | TEST_REQUIRES_X86_AVX2; |
| 6046 | for (size_t batch_size = 96; batch_size < 480; batch_size += 48) { |
| 6047 | VUnOpMicrokernelTester() |
| 6048 | .batch_size(batch_size) |
| 6049 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x48, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6050 | } |
| 6051 | } |
| 6052 | |
| 6053 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X48, batch_lt_48) { |
| 6054 | TEST_REQUIRES_X86_AVX2; |
| 6055 | for (size_t batch_size = 1; batch_size < 48; batch_size++) { |
| 6056 | VUnOpMicrokernelTester() |
| 6057 | .batch_size(batch_size) |
| 6058 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x48, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6059 | } |
| 6060 | } |
| 6061 | |
| 6062 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X48, batch_gt_48) { |
| 6063 | TEST_REQUIRES_X86_AVX2; |
| 6064 | for (size_t batch_size = 49; batch_size < 96; batch_size++) { |
| 6065 | VUnOpMicrokernelTester() |
| 6066 | .batch_size(batch_size) |
| 6067 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x48, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6068 | } |
| 6069 | } |
| 6070 | |
| 6071 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X48, inplace) { |
| 6072 | TEST_REQUIRES_X86_AVX2; |
| 6073 | for (size_t batch_size = 1; batch_size <= 240; batch_size += 47) { |
| 6074 | VUnOpMicrokernelTester() |
| 6075 | .batch_size(batch_size) |
| 6076 | .inplace(true) |
| 6077 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x48, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6078 | } |
| 6079 | } |
| 6080 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 6081 | |
| 6082 | |
| 6083 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 6084 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X56, batch_eq_56) { |
| 6085 | TEST_REQUIRES_X86_AVX2; |
| 6086 | VUnOpMicrokernelTester() |
| 6087 | .batch_size(56) |
| 6088 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x56, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6089 | } |
| 6090 | |
| 6091 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X56, batch_div_56) { |
| 6092 | TEST_REQUIRES_X86_AVX2; |
| 6093 | for (size_t batch_size = 112; batch_size < 560; batch_size += 56) { |
| 6094 | VUnOpMicrokernelTester() |
| 6095 | .batch_size(batch_size) |
| 6096 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x56, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6097 | } |
| 6098 | } |
| 6099 | |
| 6100 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X56, batch_lt_56) { |
| 6101 | TEST_REQUIRES_X86_AVX2; |
| 6102 | for (size_t batch_size = 1; batch_size < 56; batch_size++) { |
| 6103 | VUnOpMicrokernelTester() |
| 6104 | .batch_size(batch_size) |
| 6105 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x56, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6106 | } |
| 6107 | } |
| 6108 | |
| 6109 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X56, batch_gt_56) { |
| 6110 | TEST_REQUIRES_X86_AVX2; |
| 6111 | for (size_t batch_size = 57; batch_size < 112; batch_size++) { |
| 6112 | VUnOpMicrokernelTester() |
| 6113 | .batch_size(batch_size) |
| 6114 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x56, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6115 | } |
| 6116 | } |
| 6117 | |
| 6118 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X56, inplace) { |
| 6119 | TEST_REQUIRES_X86_AVX2; |
| 6120 | for (size_t batch_size = 1; batch_size <= 280; batch_size += 55) { |
| 6121 | VUnOpMicrokernelTester() |
| 6122 | .batch_size(batch_size) |
| 6123 | .inplace(true) |
| 6124 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x56, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6125 | } |
| 6126 | } |
| 6127 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 6128 | |
| 6129 | |
| 6130 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 6131 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X64, batch_eq_64) { |
| 6132 | TEST_REQUIRES_X86_AVX2; |
| 6133 | VUnOpMicrokernelTester() |
| 6134 | .batch_size(64) |
| 6135 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x64, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6136 | } |
| 6137 | |
| 6138 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X64, batch_div_64) { |
| 6139 | TEST_REQUIRES_X86_AVX2; |
| 6140 | for (size_t batch_size = 128; batch_size < 640; batch_size += 64) { |
| 6141 | VUnOpMicrokernelTester() |
| 6142 | .batch_size(batch_size) |
| 6143 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x64, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6144 | } |
| 6145 | } |
| 6146 | |
| 6147 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X64, batch_lt_64) { |
| 6148 | TEST_REQUIRES_X86_AVX2; |
| 6149 | for (size_t batch_size = 1; batch_size < 64; batch_size++) { |
| 6150 | VUnOpMicrokernelTester() |
| 6151 | .batch_size(batch_size) |
| 6152 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x64, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6153 | } |
| 6154 | } |
| 6155 | |
| 6156 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X64, batch_gt_64) { |
| 6157 | TEST_REQUIRES_X86_AVX2; |
| 6158 | for (size_t batch_size = 65; batch_size < 128; batch_size++) { |
| 6159 | VUnOpMicrokernelTester() |
| 6160 | .batch_size(batch_size) |
| 6161 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x64, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6162 | } |
| 6163 | } |
| 6164 | |
| 6165 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X64, inplace) { |
| 6166 | TEST_REQUIRES_X86_AVX2; |
| 6167 | for (size_t batch_size = 1; batch_size <= 320; batch_size += 63) { |
| 6168 | VUnOpMicrokernelTester() |
| 6169 | .batch_size(batch_size) |
| 6170 | .inplace(true) |
| 6171 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x64, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6172 | } |
| 6173 | } |
| 6174 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 6175 | |
| 6176 | |
| 6177 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 6178 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X72, batch_eq_72) { |
| 6179 | TEST_REQUIRES_X86_AVX2; |
| 6180 | VUnOpMicrokernelTester() |
| 6181 | .batch_size(72) |
| 6182 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x72, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6183 | } |
| 6184 | |
| 6185 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X72, batch_div_72) { |
| 6186 | TEST_REQUIRES_X86_AVX2; |
| 6187 | for (size_t batch_size = 144; batch_size < 720; batch_size += 72) { |
| 6188 | VUnOpMicrokernelTester() |
| 6189 | .batch_size(batch_size) |
| 6190 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x72, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6191 | } |
| 6192 | } |
| 6193 | |
| 6194 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X72, batch_lt_72) { |
| 6195 | TEST_REQUIRES_X86_AVX2; |
| 6196 | for (size_t batch_size = 1; batch_size < 72; batch_size++) { |
| 6197 | VUnOpMicrokernelTester() |
| 6198 | .batch_size(batch_size) |
| 6199 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x72, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6200 | } |
| 6201 | } |
| 6202 | |
| 6203 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X72, batch_gt_72) { |
| 6204 | TEST_REQUIRES_X86_AVX2; |
| 6205 | for (size_t batch_size = 73; batch_size < 144; batch_size++) { |
| 6206 | VUnOpMicrokernelTester() |
| 6207 | .batch_size(batch_size) |
| 6208 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x72, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6209 | } |
| 6210 | } |
| 6211 | |
| 6212 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X72, inplace) { |
| 6213 | TEST_REQUIRES_X86_AVX2; |
| 6214 | for (size_t batch_size = 1; batch_size <= 360; batch_size += 71) { |
| 6215 | VUnOpMicrokernelTester() |
| 6216 | .batch_size(batch_size) |
| 6217 | .inplace(true) |
| 6218 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x72, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6219 | } |
| 6220 | } |
| 6221 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 6222 | |
| 6223 | |
| 6224 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 6225 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X80, batch_eq_80) { |
| 6226 | TEST_REQUIRES_X86_AVX2; |
| 6227 | VUnOpMicrokernelTester() |
| 6228 | .batch_size(80) |
| 6229 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x80, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6230 | } |
| 6231 | |
| 6232 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X80, batch_div_80) { |
| 6233 | TEST_REQUIRES_X86_AVX2; |
| 6234 | for (size_t batch_size = 160; batch_size < 800; batch_size += 80) { |
| 6235 | VUnOpMicrokernelTester() |
| 6236 | .batch_size(batch_size) |
| 6237 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x80, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6238 | } |
| 6239 | } |
| 6240 | |
| 6241 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X80, batch_lt_80) { |
| 6242 | TEST_REQUIRES_X86_AVX2; |
| 6243 | for (size_t batch_size = 1; batch_size < 80; batch_size++) { |
| 6244 | VUnOpMicrokernelTester() |
| 6245 | .batch_size(batch_size) |
| 6246 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x80, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6247 | } |
| 6248 | } |
| 6249 | |
| 6250 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X80, batch_gt_80) { |
| 6251 | TEST_REQUIRES_X86_AVX2; |
| 6252 | for (size_t batch_size = 81; batch_size < 160; batch_size++) { |
| 6253 | VUnOpMicrokernelTester() |
| 6254 | .batch_size(batch_size) |
| 6255 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x80, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6256 | } |
| 6257 | } |
| 6258 | |
| 6259 | TEST(F32_SIGMOID__AVX2_RR1_P5_NR2FMA_X80, inplace) { |
| 6260 | TEST_REQUIRES_X86_AVX2; |
| 6261 | for (size_t batch_size = 1; batch_size <= 400; batch_size += 79) { |
| 6262 | VUnOpMicrokernelTester() |
| 6263 | .batch_size(batch_size) |
| 6264 | .inplace(true) |
| 6265 | .Test(xnn_f32_sigmoid_ukernel__avx2_rr1_p5_nr2fma_x80, VUnOpMicrokernelTester::OpType::Sigmoid); |
| 6266 | } |
| 6267 | } |
| 6268 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 6269 | |
| 6270 | |
Marat Dukhan | 8d3c07e | 2020-01-02 01:20:59 -0800 | [diff] [blame] | 6271 | #if !XNN_ARCH_ASMJS && !XNN_ARCH_WASM |
| 6272 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X4, batch_eq_4) { |
| 6273 | TEST_REQUIRES_PSIMD; |
| 6274 | VUnOpMicrokernelTester() |
| 6275 | .batch_size(4) |
| 6276 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6277 | } |
| 6278 | |
| 6279 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X4, batch_div_4) { |
| 6280 | TEST_REQUIRES_PSIMD; |
| 6281 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 6282 | VUnOpMicrokernelTester() |
| 6283 | .batch_size(batch_size) |
| 6284 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6285 | } |
| 6286 | } |
| 6287 | |
| 6288 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X4, batch_lt_4) { |
| 6289 | TEST_REQUIRES_PSIMD; |
| 6290 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 6291 | VUnOpMicrokernelTester() |
| 6292 | .batch_size(batch_size) |
| 6293 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6294 | } |
| 6295 | } |
| 6296 | |
| 6297 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X4, batch_gt_4) { |
| 6298 | TEST_REQUIRES_PSIMD; |
| 6299 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 6300 | VUnOpMicrokernelTester() |
| 6301 | .batch_size(batch_size) |
| 6302 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6303 | } |
| 6304 | } |
| 6305 | |
| 6306 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X4, inplace) { |
| 6307 | TEST_REQUIRES_PSIMD; |
| 6308 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 6309 | VUnOpMicrokernelTester() |
| 6310 | .batch_size(batch_size) |
| 6311 | .inplace(true) |
| 6312 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6313 | } |
| 6314 | } |
| 6315 | #endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM |
| 6316 | |
| 6317 | |
| 6318 | #if !XNN_ARCH_ASMJS && !XNN_ARCH_WASM |
| 6319 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X8, batch_eq_8) { |
| 6320 | TEST_REQUIRES_PSIMD; |
| 6321 | VUnOpMicrokernelTester() |
| 6322 | .batch_size(8) |
| 6323 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6324 | } |
| 6325 | |
| 6326 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X8, batch_div_8) { |
| 6327 | TEST_REQUIRES_PSIMD; |
| 6328 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 6329 | VUnOpMicrokernelTester() |
| 6330 | .batch_size(batch_size) |
| 6331 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6332 | } |
| 6333 | } |
| 6334 | |
| 6335 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X8, batch_lt_8) { |
| 6336 | TEST_REQUIRES_PSIMD; |
| 6337 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 6338 | VUnOpMicrokernelTester() |
| 6339 | .batch_size(batch_size) |
| 6340 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6341 | } |
| 6342 | } |
| 6343 | |
| 6344 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X8, batch_gt_8) { |
| 6345 | TEST_REQUIRES_PSIMD; |
| 6346 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 6347 | VUnOpMicrokernelTester() |
| 6348 | .batch_size(batch_size) |
| 6349 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6350 | } |
| 6351 | } |
| 6352 | |
| 6353 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X8, inplace) { |
| 6354 | TEST_REQUIRES_PSIMD; |
| 6355 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 6356 | VUnOpMicrokernelTester() |
| 6357 | .batch_size(batch_size) |
| 6358 | .inplace(true) |
| 6359 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x8, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6360 | } |
| 6361 | } |
| 6362 | #endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM |
| 6363 | |
| 6364 | |
| 6365 | #if !XNN_ARCH_ASMJS && !XNN_ARCH_WASM |
| 6366 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X12, batch_eq_12) { |
| 6367 | TEST_REQUIRES_PSIMD; |
| 6368 | VUnOpMicrokernelTester() |
| 6369 | .batch_size(12) |
| 6370 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6371 | } |
| 6372 | |
| 6373 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X12, batch_div_12) { |
| 6374 | TEST_REQUIRES_PSIMD; |
| 6375 | for (size_t batch_size = 24; batch_size < 120; batch_size += 12) { |
| 6376 | VUnOpMicrokernelTester() |
| 6377 | .batch_size(batch_size) |
| 6378 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6379 | } |
| 6380 | } |
| 6381 | |
| 6382 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X12, batch_lt_12) { |
| 6383 | TEST_REQUIRES_PSIMD; |
| 6384 | for (size_t batch_size = 1; batch_size < 12; batch_size++) { |
| 6385 | VUnOpMicrokernelTester() |
| 6386 | .batch_size(batch_size) |
| 6387 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6388 | } |
| 6389 | } |
| 6390 | |
| 6391 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X12, batch_gt_12) { |
| 6392 | TEST_REQUIRES_PSIMD; |
| 6393 | for (size_t batch_size = 13; batch_size < 24; batch_size++) { |
| 6394 | VUnOpMicrokernelTester() |
| 6395 | .batch_size(batch_size) |
| 6396 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6397 | } |
| 6398 | } |
| 6399 | |
| 6400 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X12, inplace) { |
| 6401 | TEST_REQUIRES_PSIMD; |
| 6402 | for (size_t batch_size = 1; batch_size <= 60; batch_size += 11) { |
| 6403 | VUnOpMicrokernelTester() |
| 6404 | .batch_size(batch_size) |
| 6405 | .inplace(true) |
| 6406 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x12, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6407 | } |
| 6408 | } |
| 6409 | #endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM |
| 6410 | |
| 6411 | |
| 6412 | #if !XNN_ARCH_ASMJS && !XNN_ARCH_WASM |
| 6413 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X16, batch_eq_16) { |
| 6414 | TEST_REQUIRES_PSIMD; |
| 6415 | VUnOpMicrokernelTester() |
| 6416 | .batch_size(16) |
| 6417 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6418 | } |
| 6419 | |
| 6420 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X16, batch_div_16) { |
| 6421 | TEST_REQUIRES_PSIMD; |
| 6422 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 6423 | VUnOpMicrokernelTester() |
| 6424 | .batch_size(batch_size) |
| 6425 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6426 | } |
| 6427 | } |
| 6428 | |
| 6429 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X16, batch_lt_16) { |
| 6430 | TEST_REQUIRES_PSIMD; |
| 6431 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 6432 | VUnOpMicrokernelTester() |
| 6433 | .batch_size(batch_size) |
| 6434 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6435 | } |
| 6436 | } |
| 6437 | |
| 6438 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X16, batch_gt_16) { |
| 6439 | TEST_REQUIRES_PSIMD; |
| 6440 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 6441 | VUnOpMicrokernelTester() |
| 6442 | .batch_size(batch_size) |
| 6443 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6444 | } |
| 6445 | } |
| 6446 | |
| 6447 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X16, inplace) { |
| 6448 | TEST_REQUIRES_PSIMD; |
| 6449 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 6450 | VUnOpMicrokernelTester() |
| 6451 | .batch_size(batch_size) |
| 6452 | .inplace(true) |
| 6453 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x16, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6454 | } |
| 6455 | } |
| 6456 | #endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM |
| 6457 | |
| 6458 | |
| 6459 | #if !XNN_ARCH_ASMJS && !XNN_ARCH_WASM |
| 6460 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X20, batch_eq_20) { |
| 6461 | TEST_REQUIRES_PSIMD; |
| 6462 | VUnOpMicrokernelTester() |
| 6463 | .batch_size(20) |
| 6464 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6465 | } |
| 6466 | |
| 6467 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X20, batch_div_20) { |
| 6468 | TEST_REQUIRES_PSIMD; |
| 6469 | for (size_t batch_size = 40; batch_size < 200; batch_size += 20) { |
| 6470 | VUnOpMicrokernelTester() |
| 6471 | .batch_size(batch_size) |
| 6472 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6473 | } |
| 6474 | } |
| 6475 | |
| 6476 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X20, batch_lt_20) { |
| 6477 | TEST_REQUIRES_PSIMD; |
| 6478 | for (size_t batch_size = 1; batch_size < 20; batch_size++) { |
| 6479 | VUnOpMicrokernelTester() |
| 6480 | .batch_size(batch_size) |
| 6481 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6482 | } |
| 6483 | } |
| 6484 | |
| 6485 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X20, batch_gt_20) { |
| 6486 | TEST_REQUIRES_PSIMD; |
| 6487 | for (size_t batch_size = 21; batch_size < 40; batch_size++) { |
| 6488 | VUnOpMicrokernelTester() |
| 6489 | .batch_size(batch_size) |
| 6490 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6491 | } |
| 6492 | } |
| 6493 | |
| 6494 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X20, inplace) { |
| 6495 | TEST_REQUIRES_PSIMD; |
| 6496 | for (size_t batch_size = 1; batch_size <= 100; batch_size += 19) { |
| 6497 | VUnOpMicrokernelTester() |
| 6498 | .batch_size(batch_size) |
| 6499 | .inplace(true) |
| 6500 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x20, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6501 | } |
| 6502 | } |
| 6503 | #endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM |
| 6504 | |
| 6505 | |
| 6506 | #if !XNN_ARCH_ASMJS && !XNN_ARCH_WASM |
| 6507 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X24, batch_eq_24) { |
| 6508 | TEST_REQUIRES_PSIMD; |
| 6509 | VUnOpMicrokernelTester() |
| 6510 | .batch_size(24) |
| 6511 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6512 | } |
| 6513 | |
| 6514 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X24, batch_div_24) { |
| 6515 | TEST_REQUIRES_PSIMD; |
| 6516 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 6517 | VUnOpMicrokernelTester() |
| 6518 | .batch_size(batch_size) |
| 6519 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6520 | } |
| 6521 | } |
| 6522 | |
| 6523 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X24, batch_lt_24) { |
| 6524 | TEST_REQUIRES_PSIMD; |
| 6525 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 6526 | VUnOpMicrokernelTester() |
| 6527 | .batch_size(batch_size) |
| 6528 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6529 | } |
| 6530 | } |
| 6531 | |
| 6532 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X24, batch_gt_24) { |
| 6533 | TEST_REQUIRES_PSIMD; |
| 6534 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 6535 | VUnOpMicrokernelTester() |
| 6536 | .batch_size(batch_size) |
| 6537 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6538 | } |
| 6539 | } |
| 6540 | |
| 6541 | TEST(F32_SIGMOID__PSIMD_P5_DIV_X24, inplace) { |
| 6542 | TEST_REQUIRES_PSIMD; |
| 6543 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 6544 | VUnOpMicrokernelTester() |
| 6545 | .batch_size(batch_size) |
| 6546 | .inplace(true) |
| 6547 | .Test(xnn_f32_sigmoid_ukernel__psimd_p5_div_x24, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6548 | } |
| 6549 | } |
| 6550 | #endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM |
| 6551 | |
| 6552 | |
Marat Dukhan | 3a77ea7 | 2019-12-23 12:10:24 -0800 | [diff] [blame] | 6553 | TEST(F32_SIGMOID__SCALAR_LUT2048_P1_DIV_X1, batch_eq_1) { |
| 6554 | VUnOpMicrokernelTester() |
| 6555 | .batch_size(1) |
| 6556 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut2048_p1_div_x1, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6557 | } |
| 6558 | |
| 6559 | TEST(F32_SIGMOID__SCALAR_LUT2048_P1_DIV_X1, batch_gt_1) { |
| 6560 | for (size_t batch_size = 2; batch_size < 10; batch_size++) { |
| 6561 | VUnOpMicrokernelTester() |
| 6562 | .batch_size(batch_size) |
| 6563 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut2048_p1_div_x1, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6564 | } |
| 6565 | } |
| 6566 | |
| 6567 | TEST(F32_SIGMOID__SCALAR_LUT2048_P1_DIV_X1, inplace) { |
| 6568 | for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) { |
| 6569 | VUnOpMicrokernelTester() |
| 6570 | .batch_size(batch_size) |
| 6571 | .inplace(true) |
| 6572 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut2048_p1_div_x1, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6573 | } |
| 6574 | } |
| 6575 | |
| 6576 | TEST(F32_SIGMOID__SCALAR_LUT2048_P1_DIV_X2, batch_eq_2) { |
| 6577 | VUnOpMicrokernelTester() |
| 6578 | .batch_size(2) |
| 6579 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut2048_p1_div_x2, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6580 | } |
| 6581 | |
| 6582 | TEST(F32_SIGMOID__SCALAR_LUT2048_P1_DIV_X2, batch_div_2) { |
| 6583 | for (size_t batch_size = 4; batch_size < 20; batch_size += 2) { |
| 6584 | VUnOpMicrokernelTester() |
| 6585 | .batch_size(batch_size) |
| 6586 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut2048_p1_div_x2, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6587 | } |
| 6588 | } |
| 6589 | |
| 6590 | TEST(F32_SIGMOID__SCALAR_LUT2048_P1_DIV_X2, batch_lt_2) { |
| 6591 | for (size_t batch_size = 1; batch_size < 2; batch_size++) { |
| 6592 | VUnOpMicrokernelTester() |
| 6593 | .batch_size(batch_size) |
| 6594 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut2048_p1_div_x2, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6595 | } |
| 6596 | } |
| 6597 | |
| 6598 | TEST(F32_SIGMOID__SCALAR_LUT2048_P1_DIV_X2, batch_gt_2) { |
| 6599 | for (size_t batch_size = 3; batch_size < 4; batch_size++) { |
| 6600 | VUnOpMicrokernelTester() |
| 6601 | .batch_size(batch_size) |
| 6602 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut2048_p1_div_x2, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6603 | } |
| 6604 | } |
| 6605 | |
| 6606 | TEST(F32_SIGMOID__SCALAR_LUT2048_P1_DIV_X2, inplace) { |
| 6607 | for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) { |
| 6608 | VUnOpMicrokernelTester() |
| 6609 | .batch_size(batch_size) |
| 6610 | .inplace(true) |
| 6611 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut2048_p1_div_x2, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6612 | } |
| 6613 | } |
| 6614 | |
| 6615 | TEST(F32_SIGMOID__SCALAR_LUT2048_P1_DIV_X4, batch_eq_4) { |
| 6616 | VUnOpMicrokernelTester() |
| 6617 | .batch_size(4) |
| 6618 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut2048_p1_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6619 | } |
| 6620 | |
| 6621 | TEST(F32_SIGMOID__SCALAR_LUT2048_P1_DIV_X4, batch_div_4) { |
| 6622 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 6623 | VUnOpMicrokernelTester() |
| 6624 | .batch_size(batch_size) |
| 6625 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut2048_p1_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6626 | } |
| 6627 | } |
| 6628 | |
| 6629 | TEST(F32_SIGMOID__SCALAR_LUT2048_P1_DIV_X4, batch_lt_4) { |
| 6630 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 6631 | VUnOpMicrokernelTester() |
| 6632 | .batch_size(batch_size) |
| 6633 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut2048_p1_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6634 | } |
| 6635 | } |
| 6636 | |
| 6637 | TEST(F32_SIGMOID__SCALAR_LUT2048_P1_DIV_X4, batch_gt_4) { |
| 6638 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 6639 | VUnOpMicrokernelTester() |
| 6640 | .batch_size(batch_size) |
| 6641 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut2048_p1_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6642 | } |
| 6643 | } |
| 6644 | |
| 6645 | TEST(F32_SIGMOID__SCALAR_LUT2048_P1_DIV_X4, inplace) { |
| 6646 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 6647 | VUnOpMicrokernelTester() |
| 6648 | .batch_size(batch_size) |
| 6649 | .inplace(true) |
| 6650 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut2048_p1_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6651 | } |
| 6652 | } |
| 6653 | |
| 6654 | TEST(F32_SIGMOID__SCALAR_LUT64_P2_DIV_X1, batch_eq_1) { |
| 6655 | VUnOpMicrokernelTester() |
| 6656 | .batch_size(1) |
| 6657 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut64_p2_div_x1, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6658 | } |
| 6659 | |
| 6660 | TEST(F32_SIGMOID__SCALAR_LUT64_P2_DIV_X1, batch_gt_1) { |
| 6661 | for (size_t batch_size = 2; batch_size < 10; batch_size++) { |
| 6662 | VUnOpMicrokernelTester() |
| 6663 | .batch_size(batch_size) |
| 6664 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut64_p2_div_x1, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6665 | } |
| 6666 | } |
| 6667 | |
| 6668 | TEST(F32_SIGMOID__SCALAR_LUT64_P2_DIV_X1, inplace) { |
| 6669 | for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) { |
| 6670 | VUnOpMicrokernelTester() |
| 6671 | .batch_size(batch_size) |
| 6672 | .inplace(true) |
| 6673 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut64_p2_div_x1, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6674 | } |
| 6675 | } |
| 6676 | |
| 6677 | TEST(F32_SIGMOID__SCALAR_LUT64_P2_DIV_X2, batch_eq_2) { |
| 6678 | VUnOpMicrokernelTester() |
| 6679 | .batch_size(2) |
| 6680 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut64_p2_div_x2, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6681 | } |
| 6682 | |
| 6683 | TEST(F32_SIGMOID__SCALAR_LUT64_P2_DIV_X2, batch_div_2) { |
| 6684 | for (size_t batch_size = 4; batch_size < 20; batch_size += 2) { |
| 6685 | VUnOpMicrokernelTester() |
| 6686 | .batch_size(batch_size) |
| 6687 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut64_p2_div_x2, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6688 | } |
| 6689 | } |
| 6690 | |
| 6691 | TEST(F32_SIGMOID__SCALAR_LUT64_P2_DIV_X2, batch_lt_2) { |
| 6692 | for (size_t batch_size = 1; batch_size < 2; batch_size++) { |
| 6693 | VUnOpMicrokernelTester() |
| 6694 | .batch_size(batch_size) |
| 6695 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut64_p2_div_x2, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6696 | } |
| 6697 | } |
| 6698 | |
| 6699 | TEST(F32_SIGMOID__SCALAR_LUT64_P2_DIV_X2, batch_gt_2) { |
| 6700 | for (size_t batch_size = 3; batch_size < 4; batch_size++) { |
| 6701 | VUnOpMicrokernelTester() |
| 6702 | .batch_size(batch_size) |
| 6703 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut64_p2_div_x2, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6704 | } |
| 6705 | } |
| 6706 | |
| 6707 | TEST(F32_SIGMOID__SCALAR_LUT64_P2_DIV_X2, inplace) { |
| 6708 | for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) { |
| 6709 | VUnOpMicrokernelTester() |
| 6710 | .batch_size(batch_size) |
| 6711 | .inplace(true) |
| 6712 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut64_p2_div_x2, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6713 | } |
| 6714 | } |
| 6715 | |
| 6716 | TEST(F32_SIGMOID__SCALAR_LUT64_P2_DIV_X4, batch_eq_4) { |
| 6717 | VUnOpMicrokernelTester() |
| 6718 | .batch_size(4) |
| 6719 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut64_p2_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6720 | } |
| 6721 | |
| 6722 | TEST(F32_SIGMOID__SCALAR_LUT64_P2_DIV_X4, batch_div_4) { |
| 6723 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 6724 | VUnOpMicrokernelTester() |
| 6725 | .batch_size(batch_size) |
| 6726 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut64_p2_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6727 | } |
| 6728 | } |
| 6729 | |
| 6730 | TEST(F32_SIGMOID__SCALAR_LUT64_P2_DIV_X4, batch_lt_4) { |
| 6731 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 6732 | VUnOpMicrokernelTester() |
| 6733 | .batch_size(batch_size) |
| 6734 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut64_p2_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6735 | } |
| 6736 | } |
| 6737 | |
| 6738 | TEST(F32_SIGMOID__SCALAR_LUT64_P2_DIV_X4, batch_gt_4) { |
| 6739 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 6740 | VUnOpMicrokernelTester() |
| 6741 | .batch_size(batch_size) |
| 6742 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut64_p2_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6743 | } |
| 6744 | } |
| 6745 | |
| 6746 | TEST(F32_SIGMOID__SCALAR_LUT64_P2_DIV_X4, inplace) { |
| 6747 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 6748 | VUnOpMicrokernelTester() |
| 6749 | .batch_size(batch_size) |
| 6750 | .inplace(true) |
| 6751 | .Test(xnn_f32_sigmoid_ukernel__scalar_lut64_p2_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6752 | } |
| 6753 | } |
| 6754 | |
| 6755 | TEST(F32_SIGMOID__SCALAR_P5_DIV_X1, batch_eq_1) { |
| 6756 | VUnOpMicrokernelTester() |
| 6757 | .batch_size(1) |
| 6758 | .Test(xnn_f32_sigmoid_ukernel__scalar_p5_div_x1, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6759 | } |
| 6760 | |
| 6761 | TEST(F32_SIGMOID__SCALAR_P5_DIV_X1, batch_gt_1) { |
| 6762 | for (size_t batch_size = 2; batch_size < 10; batch_size++) { |
| 6763 | VUnOpMicrokernelTester() |
| 6764 | .batch_size(batch_size) |
| 6765 | .Test(xnn_f32_sigmoid_ukernel__scalar_p5_div_x1, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6766 | } |
| 6767 | } |
| 6768 | |
| 6769 | TEST(F32_SIGMOID__SCALAR_P5_DIV_X1, inplace) { |
| 6770 | for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) { |
| 6771 | VUnOpMicrokernelTester() |
| 6772 | .batch_size(batch_size) |
| 6773 | .inplace(true) |
| 6774 | .Test(xnn_f32_sigmoid_ukernel__scalar_p5_div_x1, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6775 | } |
| 6776 | } |
| 6777 | |
| 6778 | TEST(F32_SIGMOID__SCALAR_P5_DIV_X2, batch_eq_2) { |
| 6779 | VUnOpMicrokernelTester() |
| 6780 | .batch_size(2) |
| 6781 | .Test(xnn_f32_sigmoid_ukernel__scalar_p5_div_x2, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6782 | } |
| 6783 | |
| 6784 | TEST(F32_SIGMOID__SCALAR_P5_DIV_X2, batch_div_2) { |
| 6785 | for (size_t batch_size = 4; batch_size < 20; batch_size += 2) { |
| 6786 | VUnOpMicrokernelTester() |
| 6787 | .batch_size(batch_size) |
| 6788 | .Test(xnn_f32_sigmoid_ukernel__scalar_p5_div_x2, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6789 | } |
| 6790 | } |
| 6791 | |
| 6792 | TEST(F32_SIGMOID__SCALAR_P5_DIV_X2, batch_lt_2) { |
| 6793 | for (size_t batch_size = 1; batch_size < 2; batch_size++) { |
| 6794 | VUnOpMicrokernelTester() |
| 6795 | .batch_size(batch_size) |
| 6796 | .Test(xnn_f32_sigmoid_ukernel__scalar_p5_div_x2, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6797 | } |
| 6798 | } |
| 6799 | |
| 6800 | TEST(F32_SIGMOID__SCALAR_P5_DIV_X2, batch_gt_2) { |
| 6801 | for (size_t batch_size = 3; batch_size < 4; batch_size++) { |
| 6802 | VUnOpMicrokernelTester() |
| 6803 | .batch_size(batch_size) |
| 6804 | .Test(xnn_f32_sigmoid_ukernel__scalar_p5_div_x2, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6805 | } |
| 6806 | } |
| 6807 | |
| 6808 | TEST(F32_SIGMOID__SCALAR_P5_DIV_X2, inplace) { |
| 6809 | for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) { |
| 6810 | VUnOpMicrokernelTester() |
| 6811 | .batch_size(batch_size) |
| 6812 | .inplace(true) |
| 6813 | .Test(xnn_f32_sigmoid_ukernel__scalar_p5_div_x2, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6814 | } |
| 6815 | } |
| 6816 | |
| 6817 | TEST(F32_SIGMOID__SCALAR_P5_DIV_X4, batch_eq_4) { |
| 6818 | VUnOpMicrokernelTester() |
| 6819 | .batch_size(4) |
| 6820 | .Test(xnn_f32_sigmoid_ukernel__scalar_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6821 | } |
| 6822 | |
| 6823 | TEST(F32_SIGMOID__SCALAR_P5_DIV_X4, batch_div_4) { |
| 6824 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 6825 | VUnOpMicrokernelTester() |
| 6826 | .batch_size(batch_size) |
| 6827 | .Test(xnn_f32_sigmoid_ukernel__scalar_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6828 | } |
| 6829 | } |
| 6830 | |
| 6831 | TEST(F32_SIGMOID__SCALAR_P5_DIV_X4, batch_lt_4) { |
| 6832 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 6833 | VUnOpMicrokernelTester() |
| 6834 | .batch_size(batch_size) |
| 6835 | .Test(xnn_f32_sigmoid_ukernel__scalar_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6836 | } |
| 6837 | } |
| 6838 | |
| 6839 | TEST(F32_SIGMOID__SCALAR_P5_DIV_X4, batch_gt_4) { |
| 6840 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 6841 | VUnOpMicrokernelTester() |
| 6842 | .batch_size(batch_size) |
| 6843 | .Test(xnn_f32_sigmoid_ukernel__scalar_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6844 | } |
| 6845 | } |
| 6846 | |
| 6847 | TEST(F32_SIGMOID__SCALAR_P5_DIV_X4, inplace) { |
| 6848 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 6849 | VUnOpMicrokernelTester() |
| 6850 | .batch_size(batch_size) |
| 6851 | .inplace(true) |
| 6852 | .Test(xnn_f32_sigmoid_ukernel__scalar_p5_div_x4, VUnOpMicrokernelTester::OpType::Sigmoid, VUnOpMicrokernelTester::Variant::Scalar); |
| 6853 | } |
| 6854 | } |