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XNNPACK Teamb455b122019-09-27 18:10:33 -07001// Copyright 2019 Google LLC
2//
3// This source code is licensed under the BSD-style license found in the
4// LICENSE file in the root directory of this source tree.
5
XNNPACK Teamb455b122019-09-27 18:10:33 -07006#include <gtest/gtest.h>
7
Marat Dukhan1dadbf72019-10-01 10:46:20 -07008#include <xnnpack/common.h>
XNNPACK Teamb455b122019-09-27 18:10:33 -07009#include <xnnpack/isa-checks.h>
XNNPACK Teamb455b122019-09-27 18:10:33 -070010
Marat Dukhan1dadbf72019-10-01 10:46:20 -070011#include <xnnpack/gavgpool.h>
XNNPACK Teamb455b122019-09-27 18:10:33 -070012#include "gavgpool-spchw-microkernel-tester.h"
13
14
Marat Dukhan1dadbf72019-10-01 10:46:20 -070015#if XNN_ARCH_ARM || XNN_ARCH_ARM64
XNNPACK Teamb455b122019-09-27 18:10:33 -070016 TEST(F32_GAVGPOOL_SPCHW__NEON_X4, elements_eq_4) {
17 TEST_REQUIRES_ARM_NEON;
18 GAvgPoolSpCHWMicrokernelTester()
19 .elements(4)
20 .channels(4)
21 .Test(xnn_f32_gavgpool_spchw_ukernel__neon_x4);
22 }
23
24 TEST(F32_GAVGPOOL_SPCHW__NEON_X4, elements_div_4) {
25 TEST_REQUIRES_ARM_NEON;
26 for (size_t elements = 8; elements < 32; elements += 4) {
27 GAvgPoolSpCHWMicrokernelTester()
28 .elements(elements)
29 .channels(4)
30 .Test(xnn_f32_gavgpool_spchw_ukernel__neon_x4);
31 }
32 }
33
34 TEST(F32_GAVGPOOL_SPCHW__NEON_X4, elements_lt_4) {
35 TEST_REQUIRES_ARM_NEON;
36 for (size_t elements = 1; elements < 4; elements++) {
37 GAvgPoolSpCHWMicrokernelTester()
38 .elements(elements)
39 .channels(4)
40 .Test(xnn_f32_gavgpool_spchw_ukernel__neon_x4);
41 }
42 }
43
44 TEST(F32_GAVGPOOL_SPCHW__NEON_X4, elements_gt_4) {
45 TEST_REQUIRES_ARM_NEON;
46 for (size_t elements = 5; elements < 8; elements++) {
47 GAvgPoolSpCHWMicrokernelTester()
48 .elements(elements)
49 .channels(4)
50 .Test(xnn_f32_gavgpool_spchw_ukernel__neon_x4);
51 }
52 }
53
54 TEST(F32_GAVGPOOL_SPCHW__NEON_X4, channels_lt_4) {
55 TEST_REQUIRES_ARM_NEON;
56 for (size_t channels = 1; channels < 4; channels++) {
57 for (size_t elements = 1; elements < 16; elements += 3) {
58 GAvgPoolSpCHWMicrokernelTester()
59 .elements(elements)
60 .channels(channels)
61 .Test(xnn_f32_gavgpool_spchw_ukernel__neon_x4);
62 }
63 }
64 }
65
66 TEST(F32_GAVGPOOL_SPCHW__NEON_X4, channels_gt_4) {
67 TEST_REQUIRES_ARM_NEON;
68 for (size_t channels = 5; channels < 8; channels++) {
69 for (size_t elements = 1; elements < 16; elements += 3) {
70 GAvgPoolSpCHWMicrokernelTester()
71 .elements(elements)
72 .channels(channels)
73 .Test(xnn_f32_gavgpool_spchw_ukernel__neon_x4);
74 }
75 }
76 }
77
78 TEST(F32_GAVGPOOL_SPCHW__NEON_X4, channels_div_4) {
79 TEST_REQUIRES_ARM_NEON;
80 for (size_t channels = 8; channels <= 16; channels += 4) {
81 for (size_t elements = 1; elements < 16; elements += 3) {
82 GAvgPoolSpCHWMicrokernelTester()
83 .elements(elements)
84 .channels(channels)
85 .Test(xnn_f32_gavgpool_spchw_ukernel__neon_x4);
86 }
87 }
88 }
89
90 TEST(F32_GAVGPOOL_SPCHW__NEON_X4, qmin) {
91 TEST_REQUIRES_ARM_NEON;
92 for (size_t elements = 1; elements < 16; elements += 3) {
93 GAvgPoolSpCHWMicrokernelTester()
94 .elements(elements)
95 .channels(4)
96 .qmin(128)
97 .Test(xnn_f32_gavgpool_spchw_ukernel__neon_x4);
98 }
99 }
100
101 TEST(F32_GAVGPOOL_SPCHW__NEON_X4, qmax) {
102 TEST_REQUIRES_ARM_NEON;
103 for (size_t elements = 1; elements < 16; elements += 3) {
104 GAvgPoolSpCHWMicrokernelTester()
105 .elements(elements)
106 .channels(4)
107 .qmax(128)
108 .Test(xnn_f32_gavgpool_spchw_ukernel__neon_x4);
109 }
110 }
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700111#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
XNNPACK Teamb455b122019-09-27 18:10:33 -0700112
113
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700114#if XNN_ARCH_X86 || XNN_ARCH_X86_64
XNNPACK Teamb455b122019-09-27 18:10:33 -0700115 TEST(F32_GAVGPOOL_SPCHW__SSE_X4, elements_eq_4) {
116 TEST_REQUIRES_X86_SSE;
117 GAvgPoolSpCHWMicrokernelTester()
118 .elements(4)
119 .channels(4)
120 .Test(xnn_f32_gavgpool_spchw_ukernel__sse_x4);
121 }
122
123 TEST(F32_GAVGPOOL_SPCHW__SSE_X4, elements_div_4) {
124 TEST_REQUIRES_X86_SSE;
125 for (size_t elements = 8; elements < 32; elements += 4) {
126 GAvgPoolSpCHWMicrokernelTester()
127 .elements(elements)
128 .channels(4)
129 .Test(xnn_f32_gavgpool_spchw_ukernel__sse_x4);
130 }
131 }
132
133 TEST(F32_GAVGPOOL_SPCHW__SSE_X4, elements_lt_4) {
134 TEST_REQUIRES_X86_SSE;
135 for (size_t elements = 1; elements < 4; elements++) {
136 GAvgPoolSpCHWMicrokernelTester()
137 .elements(elements)
138 .channels(4)
139 .Test(xnn_f32_gavgpool_spchw_ukernel__sse_x4);
140 }
141 }
142
143 TEST(F32_GAVGPOOL_SPCHW__SSE_X4, elements_gt_4) {
144 TEST_REQUIRES_X86_SSE;
145 for (size_t elements = 5; elements < 8; elements++) {
146 GAvgPoolSpCHWMicrokernelTester()
147 .elements(elements)
148 .channels(4)
149 .Test(xnn_f32_gavgpool_spchw_ukernel__sse_x4);
150 }
151 }
152
153 TEST(F32_GAVGPOOL_SPCHW__SSE_X4, channels_lt_4) {
154 TEST_REQUIRES_X86_SSE;
155 for (size_t channels = 1; channels < 4; channels++) {
156 for (size_t elements = 1; elements < 16; elements += 3) {
157 GAvgPoolSpCHWMicrokernelTester()
158 .elements(elements)
159 .channels(channels)
160 .Test(xnn_f32_gavgpool_spchw_ukernel__sse_x4);
161 }
162 }
163 }
164
165 TEST(F32_GAVGPOOL_SPCHW__SSE_X4, channels_gt_4) {
166 TEST_REQUIRES_X86_SSE;
167 for (size_t channels = 5; channels < 8; channels++) {
168 for (size_t elements = 1; elements < 16; elements += 3) {
169 GAvgPoolSpCHWMicrokernelTester()
170 .elements(elements)
171 .channels(channels)
172 .Test(xnn_f32_gavgpool_spchw_ukernel__sse_x4);
173 }
174 }
175 }
176
177 TEST(F32_GAVGPOOL_SPCHW__SSE_X4, channels_div_4) {
178 TEST_REQUIRES_X86_SSE;
179 for (size_t channels = 8; channels <= 16; channels += 4) {
180 for (size_t elements = 1; elements < 16; elements += 3) {
181 GAvgPoolSpCHWMicrokernelTester()
182 .elements(elements)
183 .channels(channels)
184 .Test(xnn_f32_gavgpool_spchw_ukernel__sse_x4);
185 }
186 }
187 }
188
189 TEST(F32_GAVGPOOL_SPCHW__SSE_X4, qmin) {
190 TEST_REQUIRES_X86_SSE;
191 for (size_t elements = 1; elements < 16; elements += 3) {
192 GAvgPoolSpCHWMicrokernelTester()
193 .elements(elements)
194 .channels(4)
195 .qmin(128)
196 .Test(xnn_f32_gavgpool_spchw_ukernel__sse_x4);
197 }
198 }
199
200 TEST(F32_GAVGPOOL_SPCHW__SSE_X4, qmax) {
201 TEST_REQUIRES_X86_SSE;
202 for (size_t elements = 1; elements < 16; elements += 3) {
203 GAvgPoolSpCHWMicrokernelTester()
204 .elements(elements)
205 .channels(4)
206 .qmax(128)
207 .Test(xnn_f32_gavgpool_spchw_ukernel__sse_x4);
208 }
209 }
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700210#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
Erich Elsen34dc2c02019-10-16 05:11:41 -0700211
Marat Dukhan32c74f72019-10-23 22:07:13 -0700212
213TEST(F32_GAVGPOOL_SPCHW__SCALAR_X1, elements_eq_4) {
Erich Elsen34dc2c02019-10-16 05:11:41 -0700214 GAvgPoolSpCHWMicrokernelTester()
Marat Dukhan32c74f72019-10-23 22:07:13 -0700215 .elements(4)
Erich Elsen34dc2c02019-10-16 05:11:41 -0700216 .channels(1)
217 .Test(xnn_f32_gavgpool_spchw_ukernel__scalar_x1, GAvgPoolSpCHWMicrokernelTester::Variant::Scalar);
218}
219
Marat Dukhan32c74f72019-10-23 22:07:13 -0700220TEST(F32_GAVGPOOL_SPCHW__SCALAR_X1, elements_div_4) {
221 for (size_t elements = 8; elements < 32; elements += 4) {
Erich Elsen34dc2c02019-10-16 05:11:41 -0700222 GAvgPoolSpCHWMicrokernelTester()
223 .elements(elements)
224 .channels(1)
225 .Test(xnn_f32_gavgpool_spchw_ukernel__scalar_x1, GAvgPoolSpCHWMicrokernelTester::Variant::Scalar);
226 }
227}
228
Marat Dukhan32c74f72019-10-23 22:07:13 -0700229TEST(F32_GAVGPOOL_SPCHW__SCALAR_X1, elements_lt_4) {
230 for (size_t elements = 1; elements < 4; elements++) {
231 GAvgPoolSpCHWMicrokernelTester()
232 .elements(elements)
233 .channels(1)
234 .Test(xnn_f32_gavgpool_spchw_ukernel__scalar_x1, GAvgPoolSpCHWMicrokernelTester::Variant::Scalar);
Erich Elsen34dc2c02019-10-16 05:11:41 -0700235 }
236}
237
Marat Dukhan32c74f72019-10-23 22:07:13 -0700238TEST(F32_GAVGPOOL_SPCHW__SCALAR_X1, elements_gt_4) {
239 for (size_t elements = 5; elements < 8; elements++) {
240 GAvgPoolSpCHWMicrokernelTester()
241 .elements(elements)
242 .channels(1)
243 .Test(xnn_f32_gavgpool_spchw_ukernel__scalar_x1, GAvgPoolSpCHWMicrokernelTester::Variant::Scalar);
Erich Elsen34dc2c02019-10-16 05:11:41 -0700244 }
245}
246
Marat Dukhan32c74f72019-10-23 22:07:13 -0700247TEST(F32_GAVGPOOL_SPCHW__SCALAR_X1, channels_gt_1) {
248 for (size_t channels = 2; channels < 5; channels++) {
Erich Elsen34dc2c02019-10-16 05:11:41 -0700249 for (size_t elements = 1; elements < 16; elements += 3) {
250 GAvgPoolSpCHWMicrokernelTester()
251 .elements(elements)
252 .channels(channels)
253 .Test(xnn_f32_gavgpool_spchw_ukernel__scalar_x1, GAvgPoolSpCHWMicrokernelTester::Variant::Scalar);
254 }
255 }
256}
257
258TEST(F32_GAVGPOOL_SPCHW__SCALAR_X1, qmin) {
259 for (size_t elements = 1; elements < 16; elements += 3) {
260 GAvgPoolSpCHWMicrokernelTester()
261 .elements(elements)
262 .channels(4)
263 .qmin(128)
264 .Test(xnn_f32_gavgpool_spchw_ukernel__scalar_x1, GAvgPoolSpCHWMicrokernelTester::Variant::Scalar);
265 }
266}
267
268TEST(F32_GAVGPOOL_SPCHW__SCALAR_X1, qmax) {
269 for (size_t elements = 1; elements < 16; elements += 3) {
270 GAvgPoolSpCHWMicrokernelTester()
271 .elements(elements)
272 .channels(4)
273 .qmax(128)
274 .Test(xnn_f32_gavgpool_spchw_ukernel__scalar_x1, GAvgPoolSpCHWMicrokernelTester::Variant::Scalar);
275 }
276}