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Marat Dukhan4a7b70f2021-08-02 18:18:10 -07001// Auto-generated file. Do not edit!
2// Template: src/qs8-vmulc/neon.c.in
3// Generator: tools/xngen
4//
5// Copyright 2021 Google LLC
6//
7// This source code is licensed under the BSD-style license found in the
8// LICENSE file in the root directory of this source tree.
9
10#include <assert.h>
11
12#include <arm_neon.h>
13
Marat Dukhan64287252021-09-07 16:20:03 -070014#include <xnnpack/vmul.h>
Marat Dukhan4a7b70f2021-08-02 18:18:10 -070015
16
17void xnn_qu8_vmulc_minmax_fp32_ukernel__neon_ld64_x16(
18 size_t n,
19 const uint8_t* input_a,
20 const uint8_t* input_b,
21 uint8_t* output,
Marat Dukhan7be427a2021-12-13 23:38:20 -080022 const union xnn_qu8_mul_minmax_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS
Marat Dukhan4a7b70f2021-08-02 18:18:10 -070023{
Marat Dukhan1d901012021-08-04 17:01:12 -070024 const uint8x8_t va_zero_point = vld1_dup_u8(params->fp32_neon.a_zero_point);
Marat Dukhan4a7b70f2021-08-02 18:18:10 -070025 const float32x4_t vscale = vld1q_dup_f32(&params->fp32_neon.scale);
Marat Dukhan4a7b70f2021-08-02 18:18:10 -070026 const float32x4_t vmagic_bias = vld1q_dup_f32(&params->fp32_neon.magic_bias);
Marat Dukhan482508b2021-12-05 10:05:51 -080027 const int32x4_t vmagic_bias_less_output_zero_point = vld1q_dup_s32(&params->fp32_neon.magic_bias_less_output_zero_point);
Marat Dukhanc7d07282021-12-07 11:42:14 -080028 const uint8x16_t voutput_min = vld1q_dup_u8(&params->fp32_neon.output_min);
Marat Dukhan482508b2021-12-05 10:05:51 -080029 const uint8x16_t voutput_max = vld1q_dup_u8(&params->fp32_neon.output_max);
Marat Dukhan4a7b70f2021-08-02 18:18:10 -070030
31 const uint8x8_t vb = vld1_dup_u8(input_b);
Marat Dukhan1d901012021-08-04 17:01:12 -070032 const uint8x8_t vb_zero_point = vld1_dup_u8(params->fp32_neon.b_zero_point);
Marat Dukhan4a7b70f2021-08-02 18:18:10 -070033 const int16x8_t vxb = vreinterpretq_s16_u16(vsubl_u8(vb, vb_zero_point));
34 for (; n >= 16 * sizeof(uint8_t); n -= 16 * sizeof(uint8_t)) {
35 const uint8x8_t va01234567 = vld1_u8(input_a); input_a += 8;
36 const uint8x8_t va89ABCDEF = vld1_u8(input_a); input_a += 8;
37
38 const int16x8_t vxa01234567 = vreinterpretq_s16_u16(vsubl_u8(va01234567, va_zero_point));
39 const int16x8_t vxa89ABCDEF = vreinterpretq_s16_u16(vsubl_u8(va89ABCDEF, va_zero_point));
40
41 int32x4_t vacc0123 = vmull_s16(vget_low_s16(vxa01234567), vget_low_s16(vxb));
42 int32x4_t vacc4567 = vmull_s16(vget_high_s16(vxa01234567), vget_high_s16(vxb));
43 int32x4_t vacc89AB = vmull_s16(vget_low_s16(vxa89ABCDEF), vget_low_s16(vxb));
44 int32x4_t vaccCDEF = vmull_s16(vget_high_s16(vxa89ABCDEF), vget_high_s16(vxb));
45
46 float32x4_t vfpacc0123 = vcvtq_f32_s32(vacc0123);
47 float32x4_t vfpacc4567 = vcvtq_f32_s32(vacc4567);
48 float32x4_t vfpacc89AB = vcvtq_f32_s32(vacc89AB);
49 float32x4_t vfpaccCDEF = vcvtq_f32_s32(vaccCDEF);
50
51 vfpacc0123 = vmulq_f32(vfpacc0123, vscale);
52 vfpacc4567 = vmulq_f32(vfpacc4567, vscale);
53 vfpacc89AB = vmulq_f32(vfpacc89AB, vscale);
54 vfpaccCDEF = vmulq_f32(vfpaccCDEF, vscale);
55
Marat Dukhan4a7b70f2021-08-02 18:18:10 -070056 vacc0123 = vreinterpretq_s32_f32(vaddq_f32(vfpacc0123, vmagic_bias));
57 vacc4567 = vreinterpretq_s32_f32(vaddq_f32(vfpacc4567, vmagic_bias));
58 vacc89AB = vreinterpretq_s32_f32(vaddq_f32(vfpacc89AB, vmagic_bias));
59 vaccCDEF = vreinterpretq_s32_f32(vaddq_f32(vfpaccCDEF, vmagic_bias));
60
Marat Dukhanc7d07282021-12-07 11:42:14 -080061 vacc0123 = vqsubq_s32(vacc0123, vmagic_bias_less_output_zero_point);
62 vacc4567 = vqsubq_s32(vacc4567, vmagic_bias_less_output_zero_point);
63 vacc89AB = vqsubq_s32(vacc89AB, vmagic_bias_less_output_zero_point);
64 vaccCDEF = vqsubq_s32(vaccCDEF, vmagic_bias_less_output_zero_point);
Marat Dukhan4a7b70f2021-08-02 18:18:10 -070065
Marat Dukhan33a98fa2022-01-13 00:08:57 -080066 #if XNN_ARCH_ARM64
67 int16x8_t vacc01234567 = vqmovn_high_s32(vqmovn_s32(vacc0123), vacc4567);
68 int16x8_t vacc89ABCDEF = vqmovn_high_s32(vqmovn_s32(vacc89AB), vaccCDEF);
69 #else
70 int16x8_t vacc01234567 = vcombine_s16(vqmovn_s32(vacc0123), vqmovn_s32(vacc4567));
71 int16x8_t vacc89ABCDEF = vcombine_s16(vqmovn_s32(vacc89AB), vqmovn_s32(vaccCDEF));
72 #endif
Marat Dukhan4a7b70f2021-08-02 18:18:10 -070073
Marat Dukhan482508b2021-12-05 10:05:51 -080074
Marat Dukhan33a98fa2022-01-13 00:08:57 -080075 #if XNN_ARCH_ARM64
76 uint8x16_t vout0123456789ABCDEF = vqmovun_high_s16(vqmovun_s16(vacc01234567), vacc89ABCDEF);
77 #else
78 uint8x16_t vout0123456789ABCDEF = vcombine_u8(vqmovun_s16(vacc01234567), vqmovun_s16(vacc89ABCDEF));
79 #endif
Marat Dukhan4a7b70f2021-08-02 18:18:10 -070080
Marat Dukhanc7d07282021-12-07 11:42:14 -080081 vout0123456789ABCDEF = vmaxq_u8(vout0123456789ABCDEF, voutput_min);
82
Marat Dukhan482508b2021-12-05 10:05:51 -080083 vout0123456789ABCDEF = vminq_u8(vout0123456789ABCDEF, voutput_max);
84
Marat Dukhan4a7b70f2021-08-02 18:18:10 -070085 vst1q_u8(output, vout0123456789ABCDEF); output += 16;
86 }
87 if XNN_UNLIKELY(n != 0) {
88 do {
89 const uint8x8_t va01234567 = vld1_u8(input_a); input_a += 8;
90
91 const int16x8_t vxa01234567 = vreinterpretq_s16_u16(vsubl_u8(va01234567, va_zero_point));
92
93 int32x4_t vacc0123 = vmull_s16(vget_low_s16(vxa01234567), vget_low_s16(vxb));
94 int32x4_t vacc4567 = vmull_s16(vget_high_s16(vxa01234567), vget_high_s16(vxb));
95
96 float32x4_t vfpacc0123 = vcvtq_f32_s32(vacc0123);
97 float32x4_t vfpacc4567 = vcvtq_f32_s32(vacc4567);
98
99 vfpacc0123 = vmulq_f32(vfpacc0123, vscale);
100 vfpacc4567 = vmulq_f32(vfpacc4567, vscale);
101
Marat Dukhan4a7b70f2021-08-02 18:18:10 -0700102 vacc0123 = vreinterpretq_s32_f32(vaddq_f32(vfpacc0123, vmagic_bias));
103 vacc4567 = vreinterpretq_s32_f32(vaddq_f32(vfpacc4567, vmagic_bias));
104
Marat Dukhanc7d07282021-12-07 11:42:14 -0800105 vacc0123 = vqsubq_s32(vacc0123, vmagic_bias_less_output_zero_point);
106 vacc4567 = vqsubq_s32(vacc4567, vmagic_bias_less_output_zero_point);
Marat Dukhan4a7b70f2021-08-02 18:18:10 -0700107
Marat Dukhan33a98fa2022-01-13 00:08:57 -0800108 #if XNN_ARCH_ARM64
109 int16x8_t vacc01234567 = vqmovn_high_s32(vqmovn_s32(vacc0123), vacc4567);
110 #else
111 int16x8_t vacc01234567 = vcombine_s16(vqmovn_s32(vacc0123), vqmovn_s32(vacc4567));
112 #endif
113
114
Marat Dukhan482508b2021-12-05 10:05:51 -0800115 uint8x8_t vout01234567 = vqmovun_s16(vacc01234567);
Marat Dukhan4a7b70f2021-08-02 18:18:10 -0700116
Marat Dukhanc7d07282021-12-07 11:42:14 -0800117 vout01234567 = vmax_u8(vout01234567, vget_low_u8(voutput_min));
Marat Dukhan482508b2021-12-05 10:05:51 -0800118 vout01234567 = vmin_u8(vout01234567, vget_low_u8(voutput_max));
Marat Dukhan4a7b70f2021-08-02 18:18:10 -0700119 if XNN_LIKELY(n >= (8 * sizeof(uint8_t))) {
120 vst1_u8(output, vout01234567); output += 8;
121 n -= 8 * sizeof(uint8_t);
122 } else {
123 if (n & (4 * sizeof(uint8_t))) {
Marat Dukhan5f7cf552021-11-25 17:37:03 -0800124 vst1_lane_u32((void*) output, vreinterpret_u32_u8(vout01234567), 0); output += 4;
Marat Dukhan4a7b70f2021-08-02 18:18:10 -0700125 vout01234567 = vext_u8(vout01234567, vout01234567, 4);
126 }
127 if (n & (2 * sizeof(uint8_t))) {
Marat Dukhan5f7cf552021-11-25 17:37:03 -0800128 vst1_lane_u16((void*) output, vreinterpret_u16_u8(vout01234567), 0); output += 2;
Marat Dukhan4a7b70f2021-08-02 18:18:10 -0700129 vout01234567 = vext_u8(vout01234567, vout01234567, 2);
130 }
131 if (n & (1 * sizeof(uint8_t))) {
132 vst1_lane_u8(output, vout01234567, 0);
133 }
134 n = 0;
135 }
136 } while (n != 0);
137 }
138}