Marat Dukhan | fee66be | 2021-12-09 17:51:15 -0800 | [diff] [blame] | 1 | // Copyright 2021 Google LLC |
| 2 | // |
| 3 | // This source code is licensed under the BSD-style license found in the |
| 4 | // LICENSE file in the root directory of this source tree. |
| 5 | // |
| 6 | // Auto-generated file. Do not edit! |
| 7 | // Specification: test/qu8-f32-vcvt.yaml |
| 8 | // Generator: tools/generate-vcvt-test.py |
| 9 | |
| 10 | |
| 11 | #include <gtest/gtest.h> |
| 12 | |
| 13 | #include <xnnpack/common.h> |
| 14 | #include <xnnpack/isa-checks.h> |
| 15 | |
| 16 | #include <xnnpack/vcvt.h> |
| 17 | #include "vcvt-microkernel-tester.h" |
| 18 | |
| 19 | |
| 20 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 21 | TEST(QU8_F32_VCVT__NEON_X8, batch_eq_8) { |
| 22 | TEST_REQUIRES_ARM_NEON; |
| 23 | VCvtMicrokernelTester() |
| 24 | .batch_size(8) |
| 25 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x8, xnn_init_qu8_f32_cvt_neon_params); |
| 26 | } |
| 27 | |
| 28 | TEST(QU8_F32_VCVT__NEON_X8, batch_div_8) { |
| 29 | TEST_REQUIRES_ARM_NEON; |
| 30 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 31 | VCvtMicrokernelTester() |
| 32 | .batch_size(batch_size) |
| 33 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x8, xnn_init_qu8_f32_cvt_neon_params); |
| 34 | } |
| 35 | } |
| 36 | |
| 37 | TEST(QU8_F32_VCVT__NEON_X8, batch_lt_8) { |
| 38 | TEST_REQUIRES_ARM_NEON; |
| 39 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 40 | VCvtMicrokernelTester() |
| 41 | .batch_size(batch_size) |
| 42 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x8, xnn_init_qu8_f32_cvt_neon_params); |
| 43 | } |
| 44 | } |
| 45 | |
| 46 | TEST(QU8_F32_VCVT__NEON_X8, batch_gt_8) { |
| 47 | TEST_REQUIRES_ARM_NEON; |
| 48 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 49 | VCvtMicrokernelTester() |
| 50 | .batch_size(batch_size) |
| 51 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x8, xnn_init_qu8_f32_cvt_neon_params); |
| 52 | } |
| 53 | } |
| 54 | |
| 55 | TEST(QU8_F32_VCVT__NEON_X8, scale) { |
| 56 | TEST_REQUIRES_ARM_NEON; |
| 57 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 58 | VCvtMicrokernelTester() |
| 59 | .batch_size(batch_size) |
| 60 | .scale(50) |
| 61 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x8, xnn_init_qu8_f32_cvt_neon_params); |
| 62 | } |
| 63 | } |
| 64 | |
| 65 | TEST(QU8_F32_VCVT__NEON_X8, zero_point) { |
| 66 | TEST_REQUIRES_ARM_NEON; |
| 67 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 68 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 69 | VCvtMicrokernelTester() |
| 70 | .batch_size(batch_size) |
| 71 | .zero_point(zero_point) |
| 72 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x8, xnn_init_qu8_f32_cvt_neon_params); |
| 73 | } |
| 74 | } |
| 75 | } |
| 76 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 77 | |
| 78 | |
| 79 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 80 | TEST(QU8_F32_VCVT__NEON_X16, batch_eq_16) { |
| 81 | TEST_REQUIRES_ARM_NEON; |
| 82 | VCvtMicrokernelTester() |
| 83 | .batch_size(16) |
| 84 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x16, xnn_init_qu8_f32_cvt_neon_params); |
| 85 | } |
| 86 | |
| 87 | TEST(QU8_F32_VCVT__NEON_X16, batch_div_16) { |
| 88 | TEST_REQUIRES_ARM_NEON; |
| 89 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 90 | VCvtMicrokernelTester() |
| 91 | .batch_size(batch_size) |
| 92 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x16, xnn_init_qu8_f32_cvt_neon_params); |
| 93 | } |
| 94 | } |
| 95 | |
| 96 | TEST(QU8_F32_VCVT__NEON_X16, batch_lt_16) { |
| 97 | TEST_REQUIRES_ARM_NEON; |
| 98 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 99 | VCvtMicrokernelTester() |
| 100 | .batch_size(batch_size) |
| 101 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x16, xnn_init_qu8_f32_cvt_neon_params); |
| 102 | } |
| 103 | } |
| 104 | |
| 105 | TEST(QU8_F32_VCVT__NEON_X16, batch_gt_16) { |
| 106 | TEST_REQUIRES_ARM_NEON; |
| 107 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 108 | VCvtMicrokernelTester() |
| 109 | .batch_size(batch_size) |
| 110 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x16, xnn_init_qu8_f32_cvt_neon_params); |
| 111 | } |
| 112 | } |
| 113 | |
| 114 | TEST(QU8_F32_VCVT__NEON_X16, scale) { |
| 115 | TEST_REQUIRES_ARM_NEON; |
| 116 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 117 | VCvtMicrokernelTester() |
| 118 | .batch_size(batch_size) |
| 119 | .scale(50) |
| 120 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x16, xnn_init_qu8_f32_cvt_neon_params); |
| 121 | } |
| 122 | } |
| 123 | |
| 124 | TEST(QU8_F32_VCVT__NEON_X16, zero_point) { |
| 125 | TEST_REQUIRES_ARM_NEON; |
| 126 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 127 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 128 | VCvtMicrokernelTester() |
| 129 | .batch_size(batch_size) |
| 130 | .zero_point(zero_point) |
| 131 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x16, xnn_init_qu8_f32_cvt_neon_params); |
| 132 | } |
| 133 | } |
| 134 | } |
| 135 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 136 | |
| 137 | |
| 138 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 139 | TEST(QU8_F32_VCVT__NEON_X24, batch_eq_24) { |
| 140 | TEST_REQUIRES_ARM_NEON; |
| 141 | VCvtMicrokernelTester() |
| 142 | .batch_size(24) |
| 143 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x24, xnn_init_qu8_f32_cvt_neon_params); |
| 144 | } |
| 145 | |
| 146 | TEST(QU8_F32_VCVT__NEON_X24, batch_div_24) { |
| 147 | TEST_REQUIRES_ARM_NEON; |
| 148 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 149 | VCvtMicrokernelTester() |
| 150 | .batch_size(batch_size) |
| 151 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x24, xnn_init_qu8_f32_cvt_neon_params); |
| 152 | } |
| 153 | } |
| 154 | |
| 155 | TEST(QU8_F32_VCVT__NEON_X24, batch_lt_24) { |
| 156 | TEST_REQUIRES_ARM_NEON; |
| 157 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 158 | VCvtMicrokernelTester() |
| 159 | .batch_size(batch_size) |
| 160 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x24, xnn_init_qu8_f32_cvt_neon_params); |
| 161 | } |
| 162 | } |
| 163 | |
| 164 | TEST(QU8_F32_VCVT__NEON_X24, batch_gt_24) { |
| 165 | TEST_REQUIRES_ARM_NEON; |
| 166 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 167 | VCvtMicrokernelTester() |
| 168 | .batch_size(batch_size) |
| 169 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x24, xnn_init_qu8_f32_cvt_neon_params); |
| 170 | } |
| 171 | } |
| 172 | |
| 173 | TEST(QU8_F32_VCVT__NEON_X24, scale) { |
| 174 | TEST_REQUIRES_ARM_NEON; |
| 175 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 176 | VCvtMicrokernelTester() |
| 177 | .batch_size(batch_size) |
| 178 | .scale(50) |
| 179 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x24, xnn_init_qu8_f32_cvt_neon_params); |
| 180 | } |
| 181 | } |
| 182 | |
| 183 | TEST(QU8_F32_VCVT__NEON_X24, zero_point) { |
| 184 | TEST_REQUIRES_ARM_NEON; |
| 185 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 186 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 187 | VCvtMicrokernelTester() |
| 188 | .batch_size(batch_size) |
| 189 | .zero_point(zero_point) |
| 190 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x24, xnn_init_qu8_f32_cvt_neon_params); |
| 191 | } |
| 192 | } |
| 193 | } |
| 194 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 195 | |
| 196 | |
| 197 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 198 | TEST(QU8_F32_VCVT__NEON_X32, batch_eq_32) { |
| 199 | TEST_REQUIRES_ARM_NEON; |
| 200 | VCvtMicrokernelTester() |
| 201 | .batch_size(32) |
| 202 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x32, xnn_init_qu8_f32_cvt_neon_params); |
| 203 | } |
| 204 | |
| 205 | TEST(QU8_F32_VCVT__NEON_X32, batch_div_32) { |
| 206 | TEST_REQUIRES_ARM_NEON; |
| 207 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 208 | VCvtMicrokernelTester() |
| 209 | .batch_size(batch_size) |
| 210 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x32, xnn_init_qu8_f32_cvt_neon_params); |
| 211 | } |
| 212 | } |
| 213 | |
| 214 | TEST(QU8_F32_VCVT__NEON_X32, batch_lt_32) { |
| 215 | TEST_REQUIRES_ARM_NEON; |
| 216 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 217 | VCvtMicrokernelTester() |
| 218 | .batch_size(batch_size) |
| 219 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x32, xnn_init_qu8_f32_cvt_neon_params); |
| 220 | } |
| 221 | } |
| 222 | |
| 223 | TEST(QU8_F32_VCVT__NEON_X32, batch_gt_32) { |
| 224 | TEST_REQUIRES_ARM_NEON; |
| 225 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 226 | VCvtMicrokernelTester() |
| 227 | .batch_size(batch_size) |
| 228 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x32, xnn_init_qu8_f32_cvt_neon_params); |
| 229 | } |
| 230 | } |
| 231 | |
| 232 | TEST(QU8_F32_VCVT__NEON_X32, scale) { |
| 233 | TEST_REQUIRES_ARM_NEON; |
| 234 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 235 | VCvtMicrokernelTester() |
| 236 | .batch_size(batch_size) |
| 237 | .scale(50) |
| 238 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x32, xnn_init_qu8_f32_cvt_neon_params); |
| 239 | } |
| 240 | } |
| 241 | |
| 242 | TEST(QU8_F32_VCVT__NEON_X32, zero_point) { |
| 243 | TEST_REQUIRES_ARM_NEON; |
| 244 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 245 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 246 | VCvtMicrokernelTester() |
| 247 | .batch_size(batch_size) |
| 248 | .zero_point(zero_point) |
| 249 | .Test(xnn_qu8_f32_vcvt_ukernel__neon_x32, xnn_init_qu8_f32_cvt_neon_params); |
| 250 | } |
| 251 | } |
| 252 | } |
| 253 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | f9cf55d | 2021-12-09 18:54:00 -0800 | [diff] [blame] | 254 | |
| 255 | |
| 256 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | d873fa2 | 2021-12-10 01:55:10 -0800 | [diff] [blame] | 257 | TEST(QU8_F32_VCVT__SSE2_X8, batch_eq_8) { |
| 258 | TEST_REQUIRES_X86_SSE2; |
| 259 | VCvtMicrokernelTester() |
| 260 | .batch_size(8) |
| 261 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x8, xnn_init_qu8_f32_cvt_sse2_params); |
| 262 | } |
| 263 | |
| 264 | TEST(QU8_F32_VCVT__SSE2_X8, batch_div_8) { |
| 265 | TEST_REQUIRES_X86_SSE2; |
| 266 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 267 | VCvtMicrokernelTester() |
| 268 | .batch_size(batch_size) |
| 269 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x8, xnn_init_qu8_f32_cvt_sse2_params); |
| 270 | } |
| 271 | } |
| 272 | |
| 273 | TEST(QU8_F32_VCVT__SSE2_X8, batch_lt_8) { |
| 274 | TEST_REQUIRES_X86_SSE2; |
| 275 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 276 | VCvtMicrokernelTester() |
| 277 | .batch_size(batch_size) |
| 278 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x8, xnn_init_qu8_f32_cvt_sse2_params); |
| 279 | } |
| 280 | } |
| 281 | |
| 282 | TEST(QU8_F32_VCVT__SSE2_X8, batch_gt_8) { |
| 283 | TEST_REQUIRES_X86_SSE2; |
| 284 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 285 | VCvtMicrokernelTester() |
| 286 | .batch_size(batch_size) |
| 287 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x8, xnn_init_qu8_f32_cvt_sse2_params); |
| 288 | } |
| 289 | } |
| 290 | |
| 291 | TEST(QU8_F32_VCVT__SSE2_X8, scale) { |
| 292 | TEST_REQUIRES_X86_SSE2; |
| 293 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 294 | VCvtMicrokernelTester() |
| 295 | .batch_size(batch_size) |
| 296 | .scale(50) |
| 297 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x8, xnn_init_qu8_f32_cvt_sse2_params); |
| 298 | } |
| 299 | } |
| 300 | |
| 301 | TEST(QU8_F32_VCVT__SSE2_X8, zero_point) { |
| 302 | TEST_REQUIRES_X86_SSE2; |
| 303 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 304 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 305 | VCvtMicrokernelTester() |
| 306 | .batch_size(batch_size) |
| 307 | .zero_point(zero_point) |
| 308 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x8, xnn_init_qu8_f32_cvt_sse2_params); |
| 309 | } |
| 310 | } |
| 311 | } |
| 312 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 313 | |
| 314 | |
| 315 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 316 | TEST(QU8_F32_VCVT__SSE2_X16, batch_eq_16) { |
| 317 | TEST_REQUIRES_X86_SSE2; |
| 318 | VCvtMicrokernelTester() |
| 319 | .batch_size(16) |
| 320 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x16, xnn_init_qu8_f32_cvt_sse2_params); |
| 321 | } |
| 322 | |
| 323 | TEST(QU8_F32_VCVT__SSE2_X16, batch_div_16) { |
| 324 | TEST_REQUIRES_X86_SSE2; |
| 325 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 326 | VCvtMicrokernelTester() |
| 327 | .batch_size(batch_size) |
| 328 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x16, xnn_init_qu8_f32_cvt_sse2_params); |
| 329 | } |
| 330 | } |
| 331 | |
| 332 | TEST(QU8_F32_VCVT__SSE2_X16, batch_lt_16) { |
| 333 | TEST_REQUIRES_X86_SSE2; |
| 334 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 335 | VCvtMicrokernelTester() |
| 336 | .batch_size(batch_size) |
| 337 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x16, xnn_init_qu8_f32_cvt_sse2_params); |
| 338 | } |
| 339 | } |
| 340 | |
| 341 | TEST(QU8_F32_VCVT__SSE2_X16, batch_gt_16) { |
| 342 | TEST_REQUIRES_X86_SSE2; |
| 343 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 344 | VCvtMicrokernelTester() |
| 345 | .batch_size(batch_size) |
| 346 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x16, xnn_init_qu8_f32_cvt_sse2_params); |
| 347 | } |
| 348 | } |
| 349 | |
| 350 | TEST(QU8_F32_VCVT__SSE2_X16, scale) { |
| 351 | TEST_REQUIRES_X86_SSE2; |
| 352 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 353 | VCvtMicrokernelTester() |
| 354 | .batch_size(batch_size) |
| 355 | .scale(50) |
| 356 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x16, xnn_init_qu8_f32_cvt_sse2_params); |
| 357 | } |
| 358 | } |
| 359 | |
| 360 | TEST(QU8_F32_VCVT__SSE2_X16, zero_point) { |
| 361 | TEST_REQUIRES_X86_SSE2; |
| 362 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 363 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 364 | VCvtMicrokernelTester() |
| 365 | .batch_size(batch_size) |
| 366 | .zero_point(zero_point) |
| 367 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x16, xnn_init_qu8_f32_cvt_sse2_params); |
| 368 | } |
| 369 | } |
| 370 | } |
| 371 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 372 | |
| 373 | |
| 374 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 375 | TEST(QU8_F32_VCVT__SSE2_X24, batch_eq_24) { |
| 376 | TEST_REQUIRES_X86_SSE2; |
| 377 | VCvtMicrokernelTester() |
| 378 | .batch_size(24) |
| 379 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x24, xnn_init_qu8_f32_cvt_sse2_params); |
| 380 | } |
| 381 | |
| 382 | TEST(QU8_F32_VCVT__SSE2_X24, batch_div_24) { |
| 383 | TEST_REQUIRES_X86_SSE2; |
| 384 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 385 | VCvtMicrokernelTester() |
| 386 | .batch_size(batch_size) |
| 387 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x24, xnn_init_qu8_f32_cvt_sse2_params); |
| 388 | } |
| 389 | } |
| 390 | |
| 391 | TEST(QU8_F32_VCVT__SSE2_X24, batch_lt_24) { |
| 392 | TEST_REQUIRES_X86_SSE2; |
| 393 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 394 | VCvtMicrokernelTester() |
| 395 | .batch_size(batch_size) |
| 396 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x24, xnn_init_qu8_f32_cvt_sse2_params); |
| 397 | } |
| 398 | } |
| 399 | |
| 400 | TEST(QU8_F32_VCVT__SSE2_X24, batch_gt_24) { |
| 401 | TEST_REQUIRES_X86_SSE2; |
| 402 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 403 | VCvtMicrokernelTester() |
| 404 | .batch_size(batch_size) |
| 405 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x24, xnn_init_qu8_f32_cvt_sse2_params); |
| 406 | } |
| 407 | } |
| 408 | |
| 409 | TEST(QU8_F32_VCVT__SSE2_X24, scale) { |
| 410 | TEST_REQUIRES_X86_SSE2; |
| 411 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 412 | VCvtMicrokernelTester() |
| 413 | .batch_size(batch_size) |
| 414 | .scale(50) |
| 415 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x24, xnn_init_qu8_f32_cvt_sse2_params); |
| 416 | } |
| 417 | } |
| 418 | |
| 419 | TEST(QU8_F32_VCVT__SSE2_X24, zero_point) { |
| 420 | TEST_REQUIRES_X86_SSE2; |
| 421 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 422 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 423 | VCvtMicrokernelTester() |
| 424 | .batch_size(batch_size) |
| 425 | .zero_point(zero_point) |
| 426 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x24, xnn_init_qu8_f32_cvt_sse2_params); |
| 427 | } |
| 428 | } |
| 429 | } |
| 430 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 431 | |
| 432 | |
| 433 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 434 | TEST(QU8_F32_VCVT__SSE2_X32, batch_eq_32) { |
| 435 | TEST_REQUIRES_X86_SSE2; |
| 436 | VCvtMicrokernelTester() |
| 437 | .batch_size(32) |
| 438 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x32, xnn_init_qu8_f32_cvt_sse2_params); |
| 439 | } |
| 440 | |
| 441 | TEST(QU8_F32_VCVT__SSE2_X32, batch_div_32) { |
| 442 | TEST_REQUIRES_X86_SSE2; |
| 443 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 444 | VCvtMicrokernelTester() |
| 445 | .batch_size(batch_size) |
| 446 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x32, xnn_init_qu8_f32_cvt_sse2_params); |
| 447 | } |
| 448 | } |
| 449 | |
| 450 | TEST(QU8_F32_VCVT__SSE2_X32, batch_lt_32) { |
| 451 | TEST_REQUIRES_X86_SSE2; |
| 452 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 453 | VCvtMicrokernelTester() |
| 454 | .batch_size(batch_size) |
| 455 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x32, xnn_init_qu8_f32_cvt_sse2_params); |
| 456 | } |
| 457 | } |
| 458 | |
| 459 | TEST(QU8_F32_VCVT__SSE2_X32, batch_gt_32) { |
| 460 | TEST_REQUIRES_X86_SSE2; |
| 461 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 462 | VCvtMicrokernelTester() |
| 463 | .batch_size(batch_size) |
| 464 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x32, xnn_init_qu8_f32_cvt_sse2_params); |
| 465 | } |
| 466 | } |
| 467 | |
| 468 | TEST(QU8_F32_VCVT__SSE2_X32, scale) { |
| 469 | TEST_REQUIRES_X86_SSE2; |
| 470 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 471 | VCvtMicrokernelTester() |
| 472 | .batch_size(batch_size) |
| 473 | .scale(50) |
| 474 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x32, xnn_init_qu8_f32_cvt_sse2_params); |
| 475 | } |
| 476 | } |
| 477 | |
| 478 | TEST(QU8_F32_VCVT__SSE2_X32, zero_point) { |
| 479 | TEST_REQUIRES_X86_SSE2; |
| 480 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 481 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 482 | VCvtMicrokernelTester() |
| 483 | .batch_size(batch_size) |
| 484 | .zero_point(zero_point) |
| 485 | .Test(xnn_qu8_f32_vcvt_ukernel__sse2_x32, xnn_init_qu8_f32_cvt_sse2_params); |
| 486 | } |
| 487 | } |
| 488 | } |
| 489 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 490 | |
| 491 | |
| 492 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | f9cf55d | 2021-12-09 18:54:00 -0800 | [diff] [blame] | 493 | TEST(QU8_F32_VCVT__SSE41_X8, batch_eq_8) { |
| 494 | TEST_REQUIRES_X86_SSE41; |
| 495 | VCvtMicrokernelTester() |
| 496 | .batch_size(8) |
| 497 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x8, xnn_init_qu8_f32_cvt_sse4_params); |
| 498 | } |
| 499 | |
| 500 | TEST(QU8_F32_VCVT__SSE41_X8, batch_div_8) { |
| 501 | TEST_REQUIRES_X86_SSE41; |
| 502 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 503 | VCvtMicrokernelTester() |
| 504 | .batch_size(batch_size) |
| 505 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x8, xnn_init_qu8_f32_cvt_sse4_params); |
| 506 | } |
| 507 | } |
| 508 | |
| 509 | TEST(QU8_F32_VCVT__SSE41_X8, batch_lt_8) { |
| 510 | TEST_REQUIRES_X86_SSE41; |
| 511 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 512 | VCvtMicrokernelTester() |
| 513 | .batch_size(batch_size) |
| 514 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x8, xnn_init_qu8_f32_cvt_sse4_params); |
| 515 | } |
| 516 | } |
| 517 | |
| 518 | TEST(QU8_F32_VCVT__SSE41_X8, batch_gt_8) { |
| 519 | TEST_REQUIRES_X86_SSE41; |
| 520 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 521 | VCvtMicrokernelTester() |
| 522 | .batch_size(batch_size) |
| 523 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x8, xnn_init_qu8_f32_cvt_sse4_params); |
| 524 | } |
| 525 | } |
| 526 | |
| 527 | TEST(QU8_F32_VCVT__SSE41_X8, scale) { |
| 528 | TEST_REQUIRES_X86_SSE41; |
| 529 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 530 | VCvtMicrokernelTester() |
| 531 | .batch_size(batch_size) |
| 532 | .scale(50) |
| 533 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x8, xnn_init_qu8_f32_cvt_sse4_params); |
| 534 | } |
| 535 | } |
| 536 | |
| 537 | TEST(QU8_F32_VCVT__SSE41_X8, zero_point) { |
| 538 | TEST_REQUIRES_X86_SSE41; |
| 539 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 540 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 541 | VCvtMicrokernelTester() |
| 542 | .batch_size(batch_size) |
| 543 | .zero_point(zero_point) |
| 544 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x8, xnn_init_qu8_f32_cvt_sse4_params); |
| 545 | } |
| 546 | } |
| 547 | } |
| 548 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 549 | |
| 550 | |
| 551 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 552 | TEST(QU8_F32_VCVT__SSE41_X16, batch_eq_16) { |
| 553 | TEST_REQUIRES_X86_SSE41; |
| 554 | VCvtMicrokernelTester() |
| 555 | .batch_size(16) |
| 556 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x16, xnn_init_qu8_f32_cvt_sse4_params); |
| 557 | } |
| 558 | |
| 559 | TEST(QU8_F32_VCVT__SSE41_X16, batch_div_16) { |
| 560 | TEST_REQUIRES_X86_SSE41; |
| 561 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 562 | VCvtMicrokernelTester() |
| 563 | .batch_size(batch_size) |
| 564 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x16, xnn_init_qu8_f32_cvt_sse4_params); |
| 565 | } |
| 566 | } |
| 567 | |
| 568 | TEST(QU8_F32_VCVT__SSE41_X16, batch_lt_16) { |
| 569 | TEST_REQUIRES_X86_SSE41; |
| 570 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 571 | VCvtMicrokernelTester() |
| 572 | .batch_size(batch_size) |
| 573 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x16, xnn_init_qu8_f32_cvt_sse4_params); |
| 574 | } |
| 575 | } |
| 576 | |
| 577 | TEST(QU8_F32_VCVT__SSE41_X16, batch_gt_16) { |
| 578 | TEST_REQUIRES_X86_SSE41; |
| 579 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 580 | VCvtMicrokernelTester() |
| 581 | .batch_size(batch_size) |
| 582 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x16, xnn_init_qu8_f32_cvt_sse4_params); |
| 583 | } |
| 584 | } |
| 585 | |
| 586 | TEST(QU8_F32_VCVT__SSE41_X16, scale) { |
| 587 | TEST_REQUIRES_X86_SSE41; |
| 588 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 589 | VCvtMicrokernelTester() |
| 590 | .batch_size(batch_size) |
| 591 | .scale(50) |
| 592 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x16, xnn_init_qu8_f32_cvt_sse4_params); |
| 593 | } |
| 594 | } |
| 595 | |
| 596 | TEST(QU8_F32_VCVT__SSE41_X16, zero_point) { |
| 597 | TEST_REQUIRES_X86_SSE41; |
| 598 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 599 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 600 | VCvtMicrokernelTester() |
| 601 | .batch_size(batch_size) |
| 602 | .zero_point(zero_point) |
| 603 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x16, xnn_init_qu8_f32_cvt_sse4_params); |
| 604 | } |
| 605 | } |
| 606 | } |
| 607 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 608 | |
| 609 | |
| 610 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 611 | TEST(QU8_F32_VCVT__SSE41_X24, batch_eq_24) { |
| 612 | TEST_REQUIRES_X86_SSE41; |
| 613 | VCvtMicrokernelTester() |
| 614 | .batch_size(24) |
| 615 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x24, xnn_init_qu8_f32_cvt_sse4_params); |
| 616 | } |
| 617 | |
| 618 | TEST(QU8_F32_VCVT__SSE41_X24, batch_div_24) { |
| 619 | TEST_REQUIRES_X86_SSE41; |
| 620 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 621 | VCvtMicrokernelTester() |
| 622 | .batch_size(batch_size) |
| 623 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x24, xnn_init_qu8_f32_cvt_sse4_params); |
| 624 | } |
| 625 | } |
| 626 | |
| 627 | TEST(QU8_F32_VCVT__SSE41_X24, batch_lt_24) { |
| 628 | TEST_REQUIRES_X86_SSE41; |
| 629 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 630 | VCvtMicrokernelTester() |
| 631 | .batch_size(batch_size) |
| 632 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x24, xnn_init_qu8_f32_cvt_sse4_params); |
| 633 | } |
| 634 | } |
| 635 | |
| 636 | TEST(QU8_F32_VCVT__SSE41_X24, batch_gt_24) { |
| 637 | TEST_REQUIRES_X86_SSE41; |
| 638 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 639 | VCvtMicrokernelTester() |
| 640 | .batch_size(batch_size) |
| 641 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x24, xnn_init_qu8_f32_cvt_sse4_params); |
| 642 | } |
| 643 | } |
| 644 | |
| 645 | TEST(QU8_F32_VCVT__SSE41_X24, scale) { |
| 646 | TEST_REQUIRES_X86_SSE41; |
| 647 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 648 | VCvtMicrokernelTester() |
| 649 | .batch_size(batch_size) |
| 650 | .scale(50) |
| 651 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x24, xnn_init_qu8_f32_cvt_sse4_params); |
| 652 | } |
| 653 | } |
| 654 | |
| 655 | TEST(QU8_F32_VCVT__SSE41_X24, zero_point) { |
| 656 | TEST_REQUIRES_X86_SSE41; |
| 657 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 658 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 659 | VCvtMicrokernelTester() |
| 660 | .batch_size(batch_size) |
| 661 | .zero_point(zero_point) |
| 662 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x24, xnn_init_qu8_f32_cvt_sse4_params); |
| 663 | } |
| 664 | } |
| 665 | } |
| 666 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 667 | |
| 668 | |
| 669 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 670 | TEST(QU8_F32_VCVT__SSE41_X32, batch_eq_32) { |
| 671 | TEST_REQUIRES_X86_SSE41; |
| 672 | VCvtMicrokernelTester() |
| 673 | .batch_size(32) |
| 674 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x32, xnn_init_qu8_f32_cvt_sse4_params); |
| 675 | } |
| 676 | |
| 677 | TEST(QU8_F32_VCVT__SSE41_X32, batch_div_32) { |
| 678 | TEST_REQUIRES_X86_SSE41; |
| 679 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 680 | VCvtMicrokernelTester() |
| 681 | .batch_size(batch_size) |
| 682 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x32, xnn_init_qu8_f32_cvt_sse4_params); |
| 683 | } |
| 684 | } |
| 685 | |
| 686 | TEST(QU8_F32_VCVT__SSE41_X32, batch_lt_32) { |
| 687 | TEST_REQUIRES_X86_SSE41; |
| 688 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 689 | VCvtMicrokernelTester() |
| 690 | .batch_size(batch_size) |
| 691 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x32, xnn_init_qu8_f32_cvt_sse4_params); |
| 692 | } |
| 693 | } |
| 694 | |
| 695 | TEST(QU8_F32_VCVT__SSE41_X32, batch_gt_32) { |
| 696 | TEST_REQUIRES_X86_SSE41; |
| 697 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 698 | VCvtMicrokernelTester() |
| 699 | .batch_size(batch_size) |
| 700 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x32, xnn_init_qu8_f32_cvt_sse4_params); |
| 701 | } |
| 702 | } |
| 703 | |
| 704 | TEST(QU8_F32_VCVT__SSE41_X32, scale) { |
| 705 | TEST_REQUIRES_X86_SSE41; |
| 706 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 707 | VCvtMicrokernelTester() |
| 708 | .batch_size(batch_size) |
| 709 | .scale(50) |
| 710 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x32, xnn_init_qu8_f32_cvt_sse4_params); |
| 711 | } |
| 712 | } |
| 713 | |
| 714 | TEST(QU8_F32_VCVT__SSE41_X32, zero_point) { |
| 715 | TEST_REQUIRES_X86_SSE41; |
| 716 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 717 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 718 | VCvtMicrokernelTester() |
| 719 | .batch_size(batch_size) |
| 720 | .zero_point(zero_point) |
| 721 | .Test(xnn_qu8_f32_vcvt_ukernel__sse41_x32, xnn_init_qu8_f32_cvt_sse4_params); |
| 722 | } |
| 723 | } |
| 724 | } |
| 725 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | fbf12b0 | 2021-12-09 22:39:15 -0800 | [diff] [blame] | 726 | |
| 727 | |
Marat Dukhan | cd4089f | 2021-12-14 23:53:33 -0800 | [diff] [blame] | 728 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 729 | TEST(QU8_F32_VCVT__AVX_X8, batch_eq_8) { |
| 730 | TEST_REQUIRES_X86_AVX; |
| 731 | VCvtMicrokernelTester() |
| 732 | .batch_size(8) |
| 733 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x8, xnn_init_qu8_f32_cvt_avx_params); |
| 734 | } |
| 735 | |
| 736 | TEST(QU8_F32_VCVT__AVX_X8, batch_div_8) { |
| 737 | TEST_REQUIRES_X86_AVX; |
| 738 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 739 | VCvtMicrokernelTester() |
| 740 | .batch_size(batch_size) |
| 741 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x8, xnn_init_qu8_f32_cvt_avx_params); |
| 742 | } |
| 743 | } |
| 744 | |
| 745 | TEST(QU8_F32_VCVT__AVX_X8, batch_lt_8) { |
| 746 | TEST_REQUIRES_X86_AVX; |
| 747 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 748 | VCvtMicrokernelTester() |
| 749 | .batch_size(batch_size) |
| 750 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x8, xnn_init_qu8_f32_cvt_avx_params); |
| 751 | } |
| 752 | } |
| 753 | |
| 754 | TEST(QU8_F32_VCVT__AVX_X8, batch_gt_8) { |
| 755 | TEST_REQUIRES_X86_AVX; |
| 756 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 757 | VCvtMicrokernelTester() |
| 758 | .batch_size(batch_size) |
| 759 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x8, xnn_init_qu8_f32_cvt_avx_params); |
| 760 | } |
| 761 | } |
| 762 | |
| 763 | TEST(QU8_F32_VCVT__AVX_X8, scale) { |
| 764 | TEST_REQUIRES_X86_AVX; |
| 765 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 766 | VCvtMicrokernelTester() |
| 767 | .batch_size(batch_size) |
| 768 | .scale(50) |
| 769 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x8, xnn_init_qu8_f32_cvt_avx_params); |
| 770 | } |
| 771 | } |
| 772 | |
| 773 | TEST(QU8_F32_VCVT__AVX_X8, zero_point) { |
| 774 | TEST_REQUIRES_X86_AVX; |
| 775 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 776 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 777 | VCvtMicrokernelTester() |
| 778 | .batch_size(batch_size) |
| 779 | .zero_point(zero_point) |
| 780 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x8, xnn_init_qu8_f32_cvt_avx_params); |
| 781 | } |
| 782 | } |
| 783 | } |
| 784 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 785 | |
| 786 | |
| 787 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 788 | TEST(QU8_F32_VCVT__AVX_X16, batch_eq_16) { |
| 789 | TEST_REQUIRES_X86_AVX; |
| 790 | VCvtMicrokernelTester() |
| 791 | .batch_size(16) |
| 792 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x16, xnn_init_qu8_f32_cvt_avx_params); |
| 793 | } |
| 794 | |
| 795 | TEST(QU8_F32_VCVT__AVX_X16, batch_div_16) { |
| 796 | TEST_REQUIRES_X86_AVX; |
| 797 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 798 | VCvtMicrokernelTester() |
| 799 | .batch_size(batch_size) |
| 800 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x16, xnn_init_qu8_f32_cvt_avx_params); |
| 801 | } |
| 802 | } |
| 803 | |
| 804 | TEST(QU8_F32_VCVT__AVX_X16, batch_lt_16) { |
| 805 | TEST_REQUIRES_X86_AVX; |
| 806 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 807 | VCvtMicrokernelTester() |
| 808 | .batch_size(batch_size) |
| 809 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x16, xnn_init_qu8_f32_cvt_avx_params); |
| 810 | } |
| 811 | } |
| 812 | |
| 813 | TEST(QU8_F32_VCVT__AVX_X16, batch_gt_16) { |
| 814 | TEST_REQUIRES_X86_AVX; |
| 815 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 816 | VCvtMicrokernelTester() |
| 817 | .batch_size(batch_size) |
| 818 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x16, xnn_init_qu8_f32_cvt_avx_params); |
| 819 | } |
| 820 | } |
| 821 | |
| 822 | TEST(QU8_F32_VCVT__AVX_X16, scale) { |
| 823 | TEST_REQUIRES_X86_AVX; |
| 824 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 825 | VCvtMicrokernelTester() |
| 826 | .batch_size(batch_size) |
| 827 | .scale(50) |
| 828 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x16, xnn_init_qu8_f32_cvt_avx_params); |
| 829 | } |
| 830 | } |
| 831 | |
| 832 | TEST(QU8_F32_VCVT__AVX_X16, zero_point) { |
| 833 | TEST_REQUIRES_X86_AVX; |
| 834 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 835 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 836 | VCvtMicrokernelTester() |
| 837 | .batch_size(batch_size) |
| 838 | .zero_point(zero_point) |
| 839 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x16, xnn_init_qu8_f32_cvt_avx_params); |
| 840 | } |
| 841 | } |
| 842 | } |
| 843 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 844 | |
| 845 | |
| 846 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 847 | TEST(QU8_F32_VCVT__AVX_X24, batch_eq_24) { |
| 848 | TEST_REQUIRES_X86_AVX; |
| 849 | VCvtMicrokernelTester() |
| 850 | .batch_size(24) |
| 851 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x24, xnn_init_qu8_f32_cvt_avx_params); |
| 852 | } |
| 853 | |
| 854 | TEST(QU8_F32_VCVT__AVX_X24, batch_div_24) { |
| 855 | TEST_REQUIRES_X86_AVX; |
| 856 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 857 | VCvtMicrokernelTester() |
| 858 | .batch_size(batch_size) |
| 859 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x24, xnn_init_qu8_f32_cvt_avx_params); |
| 860 | } |
| 861 | } |
| 862 | |
| 863 | TEST(QU8_F32_VCVT__AVX_X24, batch_lt_24) { |
| 864 | TEST_REQUIRES_X86_AVX; |
| 865 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 866 | VCvtMicrokernelTester() |
| 867 | .batch_size(batch_size) |
| 868 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x24, xnn_init_qu8_f32_cvt_avx_params); |
| 869 | } |
| 870 | } |
| 871 | |
| 872 | TEST(QU8_F32_VCVT__AVX_X24, batch_gt_24) { |
| 873 | TEST_REQUIRES_X86_AVX; |
| 874 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 875 | VCvtMicrokernelTester() |
| 876 | .batch_size(batch_size) |
| 877 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x24, xnn_init_qu8_f32_cvt_avx_params); |
| 878 | } |
| 879 | } |
| 880 | |
| 881 | TEST(QU8_F32_VCVT__AVX_X24, scale) { |
| 882 | TEST_REQUIRES_X86_AVX; |
| 883 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 884 | VCvtMicrokernelTester() |
| 885 | .batch_size(batch_size) |
| 886 | .scale(50) |
| 887 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x24, xnn_init_qu8_f32_cvt_avx_params); |
| 888 | } |
| 889 | } |
| 890 | |
| 891 | TEST(QU8_F32_VCVT__AVX_X24, zero_point) { |
| 892 | TEST_REQUIRES_X86_AVX; |
| 893 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 894 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 895 | VCvtMicrokernelTester() |
| 896 | .batch_size(batch_size) |
| 897 | .zero_point(zero_point) |
| 898 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x24, xnn_init_qu8_f32_cvt_avx_params); |
| 899 | } |
| 900 | } |
| 901 | } |
| 902 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 903 | |
| 904 | |
| 905 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 906 | TEST(QU8_F32_VCVT__AVX_X32, batch_eq_32) { |
| 907 | TEST_REQUIRES_X86_AVX; |
| 908 | VCvtMicrokernelTester() |
| 909 | .batch_size(32) |
| 910 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x32, xnn_init_qu8_f32_cvt_avx_params); |
| 911 | } |
| 912 | |
| 913 | TEST(QU8_F32_VCVT__AVX_X32, batch_div_32) { |
| 914 | TEST_REQUIRES_X86_AVX; |
| 915 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 916 | VCvtMicrokernelTester() |
| 917 | .batch_size(batch_size) |
| 918 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x32, xnn_init_qu8_f32_cvt_avx_params); |
| 919 | } |
| 920 | } |
| 921 | |
| 922 | TEST(QU8_F32_VCVT__AVX_X32, batch_lt_32) { |
| 923 | TEST_REQUIRES_X86_AVX; |
| 924 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 925 | VCvtMicrokernelTester() |
| 926 | .batch_size(batch_size) |
| 927 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x32, xnn_init_qu8_f32_cvt_avx_params); |
| 928 | } |
| 929 | } |
| 930 | |
| 931 | TEST(QU8_F32_VCVT__AVX_X32, batch_gt_32) { |
| 932 | TEST_REQUIRES_X86_AVX; |
| 933 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 934 | VCvtMicrokernelTester() |
| 935 | .batch_size(batch_size) |
| 936 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x32, xnn_init_qu8_f32_cvt_avx_params); |
| 937 | } |
| 938 | } |
| 939 | |
| 940 | TEST(QU8_F32_VCVT__AVX_X32, scale) { |
| 941 | TEST_REQUIRES_X86_AVX; |
| 942 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 943 | VCvtMicrokernelTester() |
| 944 | .batch_size(batch_size) |
| 945 | .scale(50) |
| 946 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x32, xnn_init_qu8_f32_cvt_avx_params); |
| 947 | } |
| 948 | } |
| 949 | |
| 950 | TEST(QU8_F32_VCVT__AVX_X32, zero_point) { |
| 951 | TEST_REQUIRES_X86_AVX; |
| 952 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 953 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 954 | VCvtMicrokernelTester() |
| 955 | .batch_size(batch_size) |
| 956 | .zero_point(zero_point) |
| 957 | .Test(xnn_qu8_f32_vcvt_ukernel__avx_x32, xnn_init_qu8_f32_cvt_avx_params); |
| 958 | } |
| 959 | } |
| 960 | } |
| 961 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 962 | |
| 963 | |
Marat Dukhan | 7b5f779 | 2021-12-15 00:29:39 -0800 | [diff] [blame] | 964 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 965 | TEST(QU8_F32_VCVT__AVX2_X8, batch_eq_8) { |
| 966 | TEST_REQUIRES_X86_AVX2; |
| 967 | VCvtMicrokernelTester() |
| 968 | .batch_size(8) |
| 969 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x8, xnn_init_qu8_f32_cvt_avx_params); |
| 970 | } |
| 971 | |
| 972 | TEST(QU8_F32_VCVT__AVX2_X8, batch_div_8) { |
| 973 | TEST_REQUIRES_X86_AVX2; |
| 974 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 975 | VCvtMicrokernelTester() |
| 976 | .batch_size(batch_size) |
| 977 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x8, xnn_init_qu8_f32_cvt_avx_params); |
| 978 | } |
| 979 | } |
| 980 | |
| 981 | TEST(QU8_F32_VCVT__AVX2_X8, batch_lt_8) { |
| 982 | TEST_REQUIRES_X86_AVX2; |
| 983 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 984 | VCvtMicrokernelTester() |
| 985 | .batch_size(batch_size) |
| 986 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x8, xnn_init_qu8_f32_cvt_avx_params); |
| 987 | } |
| 988 | } |
| 989 | |
| 990 | TEST(QU8_F32_VCVT__AVX2_X8, batch_gt_8) { |
| 991 | TEST_REQUIRES_X86_AVX2; |
| 992 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 993 | VCvtMicrokernelTester() |
| 994 | .batch_size(batch_size) |
| 995 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x8, xnn_init_qu8_f32_cvt_avx_params); |
| 996 | } |
| 997 | } |
| 998 | |
| 999 | TEST(QU8_F32_VCVT__AVX2_X8, scale) { |
| 1000 | TEST_REQUIRES_X86_AVX2; |
| 1001 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 1002 | VCvtMicrokernelTester() |
| 1003 | .batch_size(batch_size) |
| 1004 | .scale(50) |
| 1005 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x8, xnn_init_qu8_f32_cvt_avx_params); |
| 1006 | } |
| 1007 | } |
| 1008 | |
| 1009 | TEST(QU8_F32_VCVT__AVX2_X8, zero_point) { |
| 1010 | TEST_REQUIRES_X86_AVX2; |
| 1011 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 1012 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 1013 | VCvtMicrokernelTester() |
| 1014 | .batch_size(batch_size) |
| 1015 | .zero_point(zero_point) |
| 1016 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x8, xnn_init_qu8_f32_cvt_avx_params); |
| 1017 | } |
| 1018 | } |
| 1019 | } |
| 1020 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1021 | |
| 1022 | |
| 1023 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1024 | TEST(QU8_F32_VCVT__AVX2_X16, batch_eq_16) { |
| 1025 | TEST_REQUIRES_X86_AVX2; |
| 1026 | VCvtMicrokernelTester() |
| 1027 | .batch_size(16) |
| 1028 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x16, xnn_init_qu8_f32_cvt_avx_params); |
| 1029 | } |
| 1030 | |
| 1031 | TEST(QU8_F32_VCVT__AVX2_X16, batch_div_16) { |
| 1032 | TEST_REQUIRES_X86_AVX2; |
| 1033 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 1034 | VCvtMicrokernelTester() |
| 1035 | .batch_size(batch_size) |
| 1036 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x16, xnn_init_qu8_f32_cvt_avx_params); |
| 1037 | } |
| 1038 | } |
| 1039 | |
| 1040 | TEST(QU8_F32_VCVT__AVX2_X16, batch_lt_16) { |
| 1041 | TEST_REQUIRES_X86_AVX2; |
| 1042 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 1043 | VCvtMicrokernelTester() |
| 1044 | .batch_size(batch_size) |
| 1045 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x16, xnn_init_qu8_f32_cvt_avx_params); |
| 1046 | } |
| 1047 | } |
| 1048 | |
| 1049 | TEST(QU8_F32_VCVT__AVX2_X16, batch_gt_16) { |
| 1050 | TEST_REQUIRES_X86_AVX2; |
| 1051 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 1052 | VCvtMicrokernelTester() |
| 1053 | .batch_size(batch_size) |
| 1054 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x16, xnn_init_qu8_f32_cvt_avx_params); |
| 1055 | } |
| 1056 | } |
| 1057 | |
| 1058 | TEST(QU8_F32_VCVT__AVX2_X16, scale) { |
| 1059 | TEST_REQUIRES_X86_AVX2; |
| 1060 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1061 | VCvtMicrokernelTester() |
| 1062 | .batch_size(batch_size) |
| 1063 | .scale(50) |
| 1064 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x16, xnn_init_qu8_f32_cvt_avx_params); |
| 1065 | } |
| 1066 | } |
| 1067 | |
| 1068 | TEST(QU8_F32_VCVT__AVX2_X16, zero_point) { |
| 1069 | TEST_REQUIRES_X86_AVX2; |
| 1070 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 1071 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1072 | VCvtMicrokernelTester() |
| 1073 | .batch_size(batch_size) |
| 1074 | .zero_point(zero_point) |
| 1075 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x16, xnn_init_qu8_f32_cvt_avx_params); |
| 1076 | } |
| 1077 | } |
| 1078 | } |
| 1079 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1080 | |
| 1081 | |
| 1082 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1083 | TEST(QU8_F32_VCVT__AVX2_X24, batch_eq_24) { |
| 1084 | TEST_REQUIRES_X86_AVX2; |
| 1085 | VCvtMicrokernelTester() |
| 1086 | .batch_size(24) |
| 1087 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x24, xnn_init_qu8_f32_cvt_avx_params); |
| 1088 | } |
| 1089 | |
| 1090 | TEST(QU8_F32_VCVT__AVX2_X24, batch_div_24) { |
| 1091 | TEST_REQUIRES_X86_AVX2; |
| 1092 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 1093 | VCvtMicrokernelTester() |
| 1094 | .batch_size(batch_size) |
| 1095 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x24, xnn_init_qu8_f32_cvt_avx_params); |
| 1096 | } |
| 1097 | } |
| 1098 | |
| 1099 | TEST(QU8_F32_VCVT__AVX2_X24, batch_lt_24) { |
| 1100 | TEST_REQUIRES_X86_AVX2; |
| 1101 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 1102 | VCvtMicrokernelTester() |
| 1103 | .batch_size(batch_size) |
| 1104 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x24, xnn_init_qu8_f32_cvt_avx_params); |
| 1105 | } |
| 1106 | } |
| 1107 | |
| 1108 | TEST(QU8_F32_VCVT__AVX2_X24, batch_gt_24) { |
| 1109 | TEST_REQUIRES_X86_AVX2; |
| 1110 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 1111 | VCvtMicrokernelTester() |
| 1112 | .batch_size(batch_size) |
| 1113 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x24, xnn_init_qu8_f32_cvt_avx_params); |
| 1114 | } |
| 1115 | } |
| 1116 | |
| 1117 | TEST(QU8_F32_VCVT__AVX2_X24, scale) { |
| 1118 | TEST_REQUIRES_X86_AVX2; |
| 1119 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1120 | VCvtMicrokernelTester() |
| 1121 | .batch_size(batch_size) |
| 1122 | .scale(50) |
| 1123 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x24, xnn_init_qu8_f32_cvt_avx_params); |
| 1124 | } |
| 1125 | } |
| 1126 | |
| 1127 | TEST(QU8_F32_VCVT__AVX2_X24, zero_point) { |
| 1128 | TEST_REQUIRES_X86_AVX2; |
| 1129 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 1130 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1131 | VCvtMicrokernelTester() |
| 1132 | .batch_size(batch_size) |
| 1133 | .zero_point(zero_point) |
| 1134 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x24, xnn_init_qu8_f32_cvt_avx_params); |
| 1135 | } |
| 1136 | } |
| 1137 | } |
| 1138 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1139 | |
| 1140 | |
| 1141 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1142 | TEST(QU8_F32_VCVT__AVX2_X32, batch_eq_32) { |
| 1143 | TEST_REQUIRES_X86_AVX2; |
| 1144 | VCvtMicrokernelTester() |
| 1145 | .batch_size(32) |
| 1146 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x32, xnn_init_qu8_f32_cvt_avx_params); |
| 1147 | } |
| 1148 | |
| 1149 | TEST(QU8_F32_VCVT__AVX2_X32, batch_div_32) { |
| 1150 | TEST_REQUIRES_X86_AVX2; |
| 1151 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 1152 | VCvtMicrokernelTester() |
| 1153 | .batch_size(batch_size) |
| 1154 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x32, xnn_init_qu8_f32_cvt_avx_params); |
| 1155 | } |
| 1156 | } |
| 1157 | |
| 1158 | TEST(QU8_F32_VCVT__AVX2_X32, batch_lt_32) { |
| 1159 | TEST_REQUIRES_X86_AVX2; |
| 1160 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 1161 | VCvtMicrokernelTester() |
| 1162 | .batch_size(batch_size) |
| 1163 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x32, xnn_init_qu8_f32_cvt_avx_params); |
| 1164 | } |
| 1165 | } |
| 1166 | |
| 1167 | TEST(QU8_F32_VCVT__AVX2_X32, batch_gt_32) { |
| 1168 | TEST_REQUIRES_X86_AVX2; |
| 1169 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 1170 | VCvtMicrokernelTester() |
| 1171 | .batch_size(batch_size) |
| 1172 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x32, xnn_init_qu8_f32_cvt_avx_params); |
| 1173 | } |
| 1174 | } |
| 1175 | |
| 1176 | TEST(QU8_F32_VCVT__AVX2_X32, scale) { |
| 1177 | TEST_REQUIRES_X86_AVX2; |
| 1178 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 1179 | VCvtMicrokernelTester() |
| 1180 | .batch_size(batch_size) |
| 1181 | .scale(50) |
| 1182 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x32, xnn_init_qu8_f32_cvt_avx_params); |
| 1183 | } |
| 1184 | } |
| 1185 | |
| 1186 | TEST(QU8_F32_VCVT__AVX2_X32, zero_point) { |
| 1187 | TEST_REQUIRES_X86_AVX2; |
| 1188 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 1189 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 1190 | VCvtMicrokernelTester() |
| 1191 | .batch_size(batch_size) |
| 1192 | .zero_point(zero_point) |
| 1193 | .Test(xnn_qu8_f32_vcvt_ukernel__avx2_x32, xnn_init_qu8_f32_cvt_avx_params); |
| 1194 | } |
| 1195 | } |
| 1196 | } |
| 1197 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1198 | |
| 1199 | |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1200 | #if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | fbf12b0 | 2021-12-09 22:39:15 -0800 | [diff] [blame] | 1201 | TEST(QU8_F32_VCVT__WASMSIMD_X8, batch_eq_8) { |
| 1202 | VCvtMicrokernelTester() |
| 1203 | .batch_size(8) |
| 1204 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x8, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1205 | } |
| 1206 | |
| 1207 | TEST(QU8_F32_VCVT__WASMSIMD_X8, batch_div_8) { |
| 1208 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 1209 | VCvtMicrokernelTester() |
| 1210 | .batch_size(batch_size) |
| 1211 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x8, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1212 | } |
| 1213 | } |
| 1214 | |
| 1215 | TEST(QU8_F32_VCVT__WASMSIMD_X8, batch_lt_8) { |
| 1216 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 1217 | VCvtMicrokernelTester() |
| 1218 | .batch_size(batch_size) |
| 1219 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x8, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1220 | } |
| 1221 | } |
| 1222 | |
| 1223 | TEST(QU8_F32_VCVT__WASMSIMD_X8, batch_gt_8) { |
| 1224 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 1225 | VCvtMicrokernelTester() |
| 1226 | .batch_size(batch_size) |
| 1227 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x8, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1228 | } |
| 1229 | } |
| 1230 | |
| 1231 | TEST(QU8_F32_VCVT__WASMSIMD_X8, scale) { |
| 1232 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 1233 | VCvtMicrokernelTester() |
| 1234 | .batch_size(batch_size) |
| 1235 | .scale(50) |
| 1236 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x8, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1237 | } |
| 1238 | } |
| 1239 | |
| 1240 | TEST(QU8_F32_VCVT__WASMSIMD_X8, zero_point) { |
| 1241 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 1242 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 1243 | VCvtMicrokernelTester() |
| 1244 | .batch_size(batch_size) |
| 1245 | .zero_point(zero_point) |
| 1246 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x8, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1247 | } |
| 1248 | } |
| 1249 | } |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1250 | #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | fbf12b0 | 2021-12-09 22:39:15 -0800 | [diff] [blame] | 1251 | |
| 1252 | |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1253 | #if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | fbf12b0 | 2021-12-09 22:39:15 -0800 | [diff] [blame] | 1254 | TEST(QU8_F32_VCVT__WASMSIMD_X16, batch_eq_16) { |
| 1255 | VCvtMicrokernelTester() |
| 1256 | .batch_size(16) |
| 1257 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x16, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1258 | } |
| 1259 | |
| 1260 | TEST(QU8_F32_VCVT__WASMSIMD_X16, batch_div_16) { |
| 1261 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 1262 | VCvtMicrokernelTester() |
| 1263 | .batch_size(batch_size) |
| 1264 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x16, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1265 | } |
| 1266 | } |
| 1267 | |
| 1268 | TEST(QU8_F32_VCVT__WASMSIMD_X16, batch_lt_16) { |
| 1269 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 1270 | VCvtMicrokernelTester() |
| 1271 | .batch_size(batch_size) |
| 1272 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x16, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1273 | } |
| 1274 | } |
| 1275 | |
| 1276 | TEST(QU8_F32_VCVT__WASMSIMD_X16, batch_gt_16) { |
| 1277 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 1278 | VCvtMicrokernelTester() |
| 1279 | .batch_size(batch_size) |
| 1280 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x16, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1281 | } |
| 1282 | } |
| 1283 | |
| 1284 | TEST(QU8_F32_VCVT__WASMSIMD_X16, scale) { |
| 1285 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1286 | VCvtMicrokernelTester() |
| 1287 | .batch_size(batch_size) |
| 1288 | .scale(50) |
| 1289 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x16, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1290 | } |
| 1291 | } |
| 1292 | |
| 1293 | TEST(QU8_F32_VCVT__WASMSIMD_X16, zero_point) { |
| 1294 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 1295 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1296 | VCvtMicrokernelTester() |
| 1297 | .batch_size(batch_size) |
| 1298 | .zero_point(zero_point) |
| 1299 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x16, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1300 | } |
| 1301 | } |
| 1302 | } |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1303 | #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | fbf12b0 | 2021-12-09 22:39:15 -0800 | [diff] [blame] | 1304 | |
| 1305 | |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1306 | #if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | fbf12b0 | 2021-12-09 22:39:15 -0800 | [diff] [blame] | 1307 | TEST(QU8_F32_VCVT__WASMSIMD_X24, batch_eq_24) { |
| 1308 | VCvtMicrokernelTester() |
| 1309 | .batch_size(24) |
| 1310 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x24, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1311 | } |
| 1312 | |
| 1313 | TEST(QU8_F32_VCVT__WASMSIMD_X24, batch_div_24) { |
| 1314 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 1315 | VCvtMicrokernelTester() |
| 1316 | .batch_size(batch_size) |
| 1317 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x24, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1318 | } |
| 1319 | } |
| 1320 | |
| 1321 | TEST(QU8_F32_VCVT__WASMSIMD_X24, batch_lt_24) { |
| 1322 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 1323 | VCvtMicrokernelTester() |
| 1324 | .batch_size(batch_size) |
| 1325 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x24, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1326 | } |
| 1327 | } |
| 1328 | |
| 1329 | TEST(QU8_F32_VCVT__WASMSIMD_X24, batch_gt_24) { |
| 1330 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 1331 | VCvtMicrokernelTester() |
| 1332 | .batch_size(batch_size) |
| 1333 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x24, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1334 | } |
| 1335 | } |
| 1336 | |
| 1337 | TEST(QU8_F32_VCVT__WASMSIMD_X24, scale) { |
| 1338 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1339 | VCvtMicrokernelTester() |
| 1340 | .batch_size(batch_size) |
| 1341 | .scale(50) |
| 1342 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x24, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1343 | } |
| 1344 | } |
| 1345 | |
| 1346 | TEST(QU8_F32_VCVT__WASMSIMD_X24, zero_point) { |
| 1347 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 1348 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1349 | VCvtMicrokernelTester() |
| 1350 | .batch_size(batch_size) |
| 1351 | .zero_point(zero_point) |
| 1352 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x24, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1353 | } |
| 1354 | } |
| 1355 | } |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1356 | #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | fbf12b0 | 2021-12-09 22:39:15 -0800 | [diff] [blame] | 1357 | |
| 1358 | |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1359 | #if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | fbf12b0 | 2021-12-09 22:39:15 -0800 | [diff] [blame] | 1360 | TEST(QU8_F32_VCVT__WASMSIMD_X32, batch_eq_32) { |
| 1361 | VCvtMicrokernelTester() |
| 1362 | .batch_size(32) |
| 1363 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x32, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1364 | } |
| 1365 | |
| 1366 | TEST(QU8_F32_VCVT__WASMSIMD_X32, batch_div_32) { |
| 1367 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 1368 | VCvtMicrokernelTester() |
| 1369 | .batch_size(batch_size) |
| 1370 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x32, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1371 | } |
| 1372 | } |
| 1373 | |
| 1374 | TEST(QU8_F32_VCVT__WASMSIMD_X32, batch_lt_32) { |
| 1375 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 1376 | VCvtMicrokernelTester() |
| 1377 | .batch_size(batch_size) |
| 1378 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x32, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1379 | } |
| 1380 | } |
| 1381 | |
| 1382 | TEST(QU8_F32_VCVT__WASMSIMD_X32, batch_gt_32) { |
| 1383 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 1384 | VCvtMicrokernelTester() |
| 1385 | .batch_size(batch_size) |
| 1386 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x32, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1387 | } |
| 1388 | } |
| 1389 | |
| 1390 | TEST(QU8_F32_VCVT__WASMSIMD_X32, scale) { |
| 1391 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 1392 | VCvtMicrokernelTester() |
| 1393 | .batch_size(batch_size) |
| 1394 | .scale(50) |
| 1395 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x32, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1396 | } |
| 1397 | } |
| 1398 | |
| 1399 | TEST(QU8_F32_VCVT__WASMSIMD_X32, zero_point) { |
| 1400 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 1401 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 1402 | VCvtMicrokernelTester() |
| 1403 | .batch_size(batch_size) |
| 1404 | .zero_point(zero_point) |
| 1405 | .Test(xnn_qu8_f32_vcvt_ukernel__wasmsimd_x32, xnn_init_qu8_f32_cvt_wasmsimd_params); |
| 1406 | } |
| 1407 | } |
| 1408 | } |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 1409 | #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | 86bd270 | 2021-12-10 02:19:56 -0800 | [diff] [blame] | 1410 | |
| 1411 | |
| 1412 | TEST(QU8_F32_VCVT__SCALAR_X1, batch_eq_1) { |
| 1413 | VCvtMicrokernelTester() |
| 1414 | .batch_size(1) |
| 1415 | .Test(xnn_qu8_f32_vcvt_ukernel__scalar_x1, xnn_init_qu8_f32_cvt_scalar_params); |
| 1416 | } |
| 1417 | |
| 1418 | TEST(QU8_F32_VCVT__SCALAR_X1, batch_gt_1) { |
| 1419 | for (size_t batch_size = 2; batch_size < 10; batch_size++) { |
| 1420 | VCvtMicrokernelTester() |
| 1421 | .batch_size(batch_size) |
| 1422 | .Test(xnn_qu8_f32_vcvt_ukernel__scalar_x1, xnn_init_qu8_f32_cvt_scalar_params); |
| 1423 | } |
| 1424 | } |
| 1425 | |
| 1426 | TEST(QU8_F32_VCVT__SCALAR_X1, scale) { |
| 1427 | for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) { |
| 1428 | VCvtMicrokernelTester() |
| 1429 | .batch_size(batch_size) |
| 1430 | .scale(50) |
| 1431 | .Test(xnn_qu8_f32_vcvt_ukernel__scalar_x1, xnn_init_qu8_f32_cvt_scalar_params); |
| 1432 | } |
| 1433 | } |
| 1434 | |
| 1435 | TEST(QU8_F32_VCVT__SCALAR_X1, zero_point) { |
| 1436 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 1437 | for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) { |
| 1438 | VCvtMicrokernelTester() |
| 1439 | .batch_size(batch_size) |
| 1440 | .zero_point(zero_point) |
| 1441 | .Test(xnn_qu8_f32_vcvt_ukernel__scalar_x1, xnn_init_qu8_f32_cvt_scalar_params); |
| 1442 | } |
| 1443 | } |
| 1444 | } |
| 1445 | |
| 1446 | |
| 1447 | TEST(QU8_F32_VCVT__SCALAR_X2, batch_eq_2) { |
| 1448 | VCvtMicrokernelTester() |
| 1449 | .batch_size(2) |
| 1450 | .Test(xnn_qu8_f32_vcvt_ukernel__scalar_x2, xnn_init_qu8_f32_cvt_scalar_params); |
| 1451 | } |
| 1452 | |
| 1453 | TEST(QU8_F32_VCVT__SCALAR_X2, batch_div_2) { |
| 1454 | for (size_t batch_size = 4; batch_size < 20; batch_size += 2) { |
| 1455 | VCvtMicrokernelTester() |
| 1456 | .batch_size(batch_size) |
| 1457 | .Test(xnn_qu8_f32_vcvt_ukernel__scalar_x2, xnn_init_qu8_f32_cvt_scalar_params); |
| 1458 | } |
| 1459 | } |
| 1460 | |
| 1461 | TEST(QU8_F32_VCVT__SCALAR_X2, batch_lt_2) { |
| 1462 | for (size_t batch_size = 1; batch_size < 2; batch_size++) { |
| 1463 | VCvtMicrokernelTester() |
| 1464 | .batch_size(batch_size) |
| 1465 | .Test(xnn_qu8_f32_vcvt_ukernel__scalar_x2, xnn_init_qu8_f32_cvt_scalar_params); |
| 1466 | } |
| 1467 | } |
| 1468 | |
| 1469 | TEST(QU8_F32_VCVT__SCALAR_X2, batch_gt_2) { |
| 1470 | for (size_t batch_size = 3; batch_size < 4; batch_size++) { |
| 1471 | VCvtMicrokernelTester() |
| 1472 | .batch_size(batch_size) |
| 1473 | .Test(xnn_qu8_f32_vcvt_ukernel__scalar_x2, xnn_init_qu8_f32_cvt_scalar_params); |
| 1474 | } |
| 1475 | } |
| 1476 | |
| 1477 | TEST(QU8_F32_VCVT__SCALAR_X2, scale) { |
| 1478 | for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) { |
| 1479 | VCvtMicrokernelTester() |
| 1480 | .batch_size(batch_size) |
| 1481 | .scale(50) |
| 1482 | .Test(xnn_qu8_f32_vcvt_ukernel__scalar_x2, xnn_init_qu8_f32_cvt_scalar_params); |
| 1483 | } |
| 1484 | } |
| 1485 | |
| 1486 | TEST(QU8_F32_VCVT__SCALAR_X2, zero_point) { |
| 1487 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 1488 | for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) { |
| 1489 | VCvtMicrokernelTester() |
| 1490 | .batch_size(batch_size) |
| 1491 | .zero_point(zero_point) |
| 1492 | .Test(xnn_qu8_f32_vcvt_ukernel__scalar_x2, xnn_init_qu8_f32_cvt_scalar_params); |
| 1493 | } |
| 1494 | } |
| 1495 | } |
| 1496 | |
| 1497 | |
| 1498 | TEST(QU8_F32_VCVT__SCALAR_X3, batch_eq_3) { |
| 1499 | VCvtMicrokernelTester() |
| 1500 | .batch_size(3) |
| 1501 | .Test(xnn_qu8_f32_vcvt_ukernel__scalar_x3, xnn_init_qu8_f32_cvt_scalar_params); |
| 1502 | } |
| 1503 | |
| 1504 | TEST(QU8_F32_VCVT__SCALAR_X3, batch_div_3) { |
| 1505 | for (size_t batch_size = 6; batch_size < 30; batch_size += 3) { |
| 1506 | VCvtMicrokernelTester() |
| 1507 | .batch_size(batch_size) |
| 1508 | .Test(xnn_qu8_f32_vcvt_ukernel__scalar_x3, xnn_init_qu8_f32_cvt_scalar_params); |
| 1509 | } |
| 1510 | } |
| 1511 | |
| 1512 | TEST(QU8_F32_VCVT__SCALAR_X3, batch_lt_3) { |
| 1513 | for (size_t batch_size = 1; batch_size < 3; batch_size++) { |
| 1514 | VCvtMicrokernelTester() |
| 1515 | .batch_size(batch_size) |
| 1516 | .Test(xnn_qu8_f32_vcvt_ukernel__scalar_x3, xnn_init_qu8_f32_cvt_scalar_params); |
| 1517 | } |
| 1518 | } |
| 1519 | |
| 1520 | TEST(QU8_F32_VCVT__SCALAR_X3, batch_gt_3) { |
| 1521 | for (size_t batch_size = 4; batch_size < 6; batch_size++) { |
| 1522 | VCvtMicrokernelTester() |
| 1523 | .batch_size(batch_size) |
| 1524 | .Test(xnn_qu8_f32_vcvt_ukernel__scalar_x3, xnn_init_qu8_f32_cvt_scalar_params); |
| 1525 | } |
| 1526 | } |
| 1527 | |
| 1528 | TEST(QU8_F32_VCVT__SCALAR_X3, scale) { |
| 1529 | for (size_t batch_size = 1; batch_size <= 15; batch_size += 2) { |
| 1530 | VCvtMicrokernelTester() |
| 1531 | .batch_size(batch_size) |
| 1532 | .scale(50) |
| 1533 | .Test(xnn_qu8_f32_vcvt_ukernel__scalar_x3, xnn_init_qu8_f32_cvt_scalar_params); |
| 1534 | } |
| 1535 | } |
| 1536 | |
| 1537 | TEST(QU8_F32_VCVT__SCALAR_X3, zero_point) { |
| 1538 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 1539 | for (size_t batch_size = 1; batch_size <= 15; batch_size += 2) { |
| 1540 | VCvtMicrokernelTester() |
| 1541 | .batch_size(batch_size) |
| 1542 | .zero_point(zero_point) |
| 1543 | .Test(xnn_qu8_f32_vcvt_ukernel__scalar_x3, xnn_init_qu8_f32_cvt_scalar_params); |
| 1544 | } |
| 1545 | } |
| 1546 | } |
| 1547 | |
| 1548 | |
| 1549 | TEST(QU8_F32_VCVT__SCALAR_X4, batch_eq_4) { |
| 1550 | VCvtMicrokernelTester() |
| 1551 | .batch_size(4) |
| 1552 | .Test(xnn_qu8_f32_vcvt_ukernel__scalar_x4, xnn_init_qu8_f32_cvt_scalar_params); |
| 1553 | } |
| 1554 | |
| 1555 | TEST(QU8_F32_VCVT__SCALAR_X4, batch_div_4) { |
| 1556 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 1557 | VCvtMicrokernelTester() |
| 1558 | .batch_size(batch_size) |
| 1559 | .Test(xnn_qu8_f32_vcvt_ukernel__scalar_x4, xnn_init_qu8_f32_cvt_scalar_params); |
| 1560 | } |
| 1561 | } |
| 1562 | |
| 1563 | TEST(QU8_F32_VCVT__SCALAR_X4, batch_lt_4) { |
| 1564 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 1565 | VCvtMicrokernelTester() |
| 1566 | .batch_size(batch_size) |
| 1567 | .Test(xnn_qu8_f32_vcvt_ukernel__scalar_x4, xnn_init_qu8_f32_cvt_scalar_params); |
| 1568 | } |
| 1569 | } |
| 1570 | |
| 1571 | TEST(QU8_F32_VCVT__SCALAR_X4, batch_gt_4) { |
| 1572 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 1573 | VCvtMicrokernelTester() |
| 1574 | .batch_size(batch_size) |
| 1575 | .Test(xnn_qu8_f32_vcvt_ukernel__scalar_x4, xnn_init_qu8_f32_cvt_scalar_params); |
| 1576 | } |
| 1577 | } |
| 1578 | |
| 1579 | TEST(QU8_F32_VCVT__SCALAR_X4, scale) { |
| 1580 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 1581 | VCvtMicrokernelTester() |
| 1582 | .batch_size(batch_size) |
| 1583 | .scale(50) |
| 1584 | .Test(xnn_qu8_f32_vcvt_ukernel__scalar_x4, xnn_init_qu8_f32_cvt_scalar_params); |
| 1585 | } |
| 1586 | } |
| 1587 | |
| 1588 | TEST(QU8_F32_VCVT__SCALAR_X4, zero_point) { |
| 1589 | for (int16_t zero_point = 0; zero_point < 5; zero_point += 2) { |
| 1590 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 1591 | VCvtMicrokernelTester() |
| 1592 | .batch_size(batch_size) |
| 1593 | .zero_point(zero_point) |
| 1594 | .Test(xnn_qu8_f32_vcvt_ukernel__scalar_x4, xnn_init_qu8_f32_cvt_scalar_params); |
| 1595 | } |
| 1596 | } |
| 1597 | } |