blob: 46d6cf259a0bcdd2498a4a2d9b674af63bfaefe9 [file] [log] [blame]
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07001// Copyright (c) Facebook, Inc. and its affiliates.
2// All rights reserved.
3//
4// Copyright 2019 Google LLC
5//
6// This source code is licensed under the BSD-style license found in the
7// LICENSE file in the root directory of this source tree.
8//
9// Auto-generated file. Do not edit!
10// Specification: test/qs8-dwconv-minmax-rndnu.yaml
11// Generator: tools/generate-dwconv-test.py
12
13
14#include <gtest/gtest.h>
15
16#include <xnnpack/common.h>
17#include <xnnpack/isa-checks.h>
18
19#include <xnnpack/dwconv.h>
20#include "dwconv-microkernel-tester.h"
21
22
23#if XNN_ARCH_ARM || XNN_ARCH_ARM64
Marat Dukhan5f2939f2021-07-23 13:38:32 -070024 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL8_LD64, c_eq_8) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -070025 TEST_REQUIRES_ARM_NEON;
26 DWConvMicrokernelTester()
27 .cr(8)
28 .kr(9)
29 .channels(8)
Marat Dukhan50323b82022-01-11 00:12:01 -080030 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -070031 }
32
Marat Dukhan5f2939f2021-07-23 13:38:32 -070033 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL8_LD64, c_div_8) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -070034 TEST_REQUIRES_ARM_NEON;
35 for (uint32_t channels = 16; channels < 128; channels += 24) {
36 DWConvMicrokernelTester()
37 .cr(8)
38 .kr(9)
39 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -080040 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -070041 }
42 }
43
Marat Dukhan5f2939f2021-07-23 13:38:32 -070044 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL8_LD64, c_div_8_with_qmin) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -070045 TEST_REQUIRES_ARM_NEON;
46 for (uint32_t channels = 16; channels < 128; channels += 24) {
47 DWConvMicrokernelTester()
48 .cr(8)
49 .kr(9)
50 .channels(channels)
51 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -080052 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -070053 }
54 }
55
Marat Dukhan5f2939f2021-07-23 13:38:32 -070056 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL8_LD64, c_div_8_with_qmax) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -070057 TEST_REQUIRES_ARM_NEON;
58 for (uint32_t channels = 16; channels < 128; channels += 24) {
59 DWConvMicrokernelTester()
60 .cr(8)
61 .kr(9)
62 .channels(channels)
63 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -080064 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -070065 }
66 }
67
Marat Dukhan5f2939f2021-07-23 13:38:32 -070068 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL8_LD64, c_lt_8) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -070069 TEST_REQUIRES_ARM_NEON;
70 for (uint32_t channels = 1; channels < 8; channels++) {
71 DWConvMicrokernelTester()
72 .cr(8)
73 .kr(9)
74 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -080075 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -070076 }
77 }
78
Marat Dukhan5f2939f2021-07-23 13:38:32 -070079 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL8_LD64, c_gt_8) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -070080 TEST_REQUIRES_ARM_NEON;
81 for (uint32_t channels = 9; channels < 16; channels++) {
82 DWConvMicrokernelTester()
83 .cr(8)
84 .kr(9)
85 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -080086 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -070087 }
88 }
89
Marat Dukhan5f2939f2021-07-23 13:38:32 -070090 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL8_LD64, c_gt_8_with_qmin) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -070091 TEST_REQUIRES_ARM_NEON;
92 for (uint32_t channels = 9; channels < 16; channels++) {
93 DWConvMicrokernelTester()
94 .cr(8)
95 .kr(9)
96 .channels(channels)
97 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -080098 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -070099 }
100 }
101
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700102 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL8_LD64, c_gt_8_with_qmax) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700103 TEST_REQUIRES_ARM_NEON;
104 for (uint32_t channels = 9; channels < 16; channels++) {
105 DWConvMicrokernelTester()
106 .cr(8)
107 .kr(9)
108 .channels(channels)
109 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800110 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700111 }
112 }
113
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700114 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL8_LD64, multipixel) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700115 TEST_REQUIRES_ARM_NEON;
116 for (size_t channels = 1; channels <= 40; channels += 7) {
117 DWConvMicrokernelTester()
118 .cr(8)
119 .kr(9)
120 .channels(channels)
121 .width(3)
Marat Dukhan50323b82022-01-11 00:12:01 -0800122 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700123 }
124 }
125
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700126 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL8_LD64, multipixel_with_step) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700127 TEST_REQUIRES_ARM_NEON;
128 for (size_t channels = 1; channels <= 40; channels += 7) {
129 for (size_t step = 2; step <= 9; step++) {
130 DWConvMicrokernelTester()
131 .cr(8)
132 .kr(9)
133 .channels(channels)
134 .width(3)
135 .step(step)
Marat Dukhan50323b82022-01-11 00:12:01 -0800136 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700137 }
138 }
139 }
140
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700141 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL8_LD64, multipixel_with_output_stride) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700142 TEST_REQUIRES_ARM_NEON;
143 for (size_t channels = 1; channels <= 40; channels += 7) {
144 DWConvMicrokernelTester()
145 .cr(8)
146 .kr(9)
147 .channels(8)
148 .width(5)
149 .output_stride(43)
Marat Dukhan50323b82022-01-11 00:12:01 -0800150 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700151 }
152 }
153
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700154 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL8_LD64, multipixel_with_qmin) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700155 TEST_REQUIRES_ARM_NEON;
156 for (size_t channels = 1; channels <= 40; channels += 7) {
157 DWConvMicrokernelTester()
158 .cr(8)
159 .kr(9)
160 .channels(channels)
161 .width(3)
162 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800163 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700164 }
165 }
166
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700167 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL8_LD64, multipixel_with_qmax) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700168 TEST_REQUIRES_ARM_NEON;
169 for (size_t channels = 1; channels <= 40; channels += 7) {
170 DWConvMicrokernelTester()
171 .cr(8)
172 .kr(9)
173 .channels(channels)
174 .width(3)
175 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800176 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700177 }
178 }
179
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700180 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL8_LD64, input_offset) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700181 TEST_REQUIRES_ARM_NEON;
182 for (uint32_t channels = 16; channels < 128; channels += 24) {
183 DWConvMicrokernelTester()
184 .cr(8)
185 .kr(9)
186 .channels(channels)
187 .input_offset(176)
Marat Dukhan50323b82022-01-11 00:12:01 -0800188 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700189 }
190 }
191
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700192 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL8_LD64, zero) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700193 TEST_REQUIRES_ARM_NEON;
194 for (uint32_t mz = 0; mz < 9; mz++) {
195 for (uint32_t channels = 16; channels < 128; channels += 24) {
196 DWConvMicrokernelTester()
197 .cr(8)
198 .kr(9)
199 .channels(channels)
200 .input_offset(176)
201 .zero_index(mz)
Marat Dukhan50323b82022-01-11 00:12:01 -0800202 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700203 }
204 }
205 }
206#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
207
208
209#if XNN_ARCH_ARM || XNN_ARCH_ARM64
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700210 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD64, c_eq_16) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700211 TEST_REQUIRES_ARM_NEON;
212 DWConvMicrokernelTester()
213 .cr(16)
214 .kr(9)
215 .channels(16)
Marat Dukhan50323b82022-01-11 00:12:01 -0800216 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700217 }
218
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700219 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD64, c_div_16) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700220 TEST_REQUIRES_ARM_NEON;
221 for (uint32_t channels = 32; channels < 256; channels += 48) {
222 DWConvMicrokernelTester()
223 .cr(16)
224 .kr(9)
225 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -0800226 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700227 }
228 }
229
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700230 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD64, c_div_16_with_qmin) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700231 TEST_REQUIRES_ARM_NEON;
232 for (uint32_t channels = 32; channels < 256; channels += 48) {
233 DWConvMicrokernelTester()
234 .cr(16)
235 .kr(9)
236 .channels(channels)
237 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800238 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700239 }
240 }
241
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700242 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD64, c_div_16_with_qmax) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700243 TEST_REQUIRES_ARM_NEON;
244 for (uint32_t channels = 32; channels < 256; channels += 48) {
245 DWConvMicrokernelTester()
246 .cr(16)
247 .kr(9)
248 .channels(channels)
249 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800250 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700251 }
252 }
253
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700254 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD64, c_lt_16) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700255 TEST_REQUIRES_ARM_NEON;
256 for (uint32_t channels = 1; channels < 16; channels++) {
257 DWConvMicrokernelTester()
258 .cr(16)
259 .kr(9)
260 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -0800261 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700262 }
263 }
264
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700265 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD64, c_gt_16) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700266 TEST_REQUIRES_ARM_NEON;
267 for (uint32_t channels = 17; channels < 32; channels++) {
268 DWConvMicrokernelTester()
269 .cr(16)
270 .kr(9)
271 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -0800272 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700273 }
274 }
275
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700276 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD64, c_gt_16_with_qmin) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700277 TEST_REQUIRES_ARM_NEON;
278 for (uint32_t channels = 17; channels < 32; channels++) {
279 DWConvMicrokernelTester()
280 .cr(16)
281 .kr(9)
282 .channels(channels)
283 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800284 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700285 }
286 }
287
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700288 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD64, c_gt_16_with_qmax) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700289 TEST_REQUIRES_ARM_NEON;
290 for (uint32_t channels = 17; channels < 32; channels++) {
291 DWConvMicrokernelTester()
292 .cr(16)
293 .kr(9)
294 .channels(channels)
295 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800296 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700297 }
298 }
299
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700300 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD64, multipixel) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700301 TEST_REQUIRES_ARM_NEON;
302 for (size_t channels = 1; channels <= 80; channels += 15) {
303 DWConvMicrokernelTester()
304 .cr(16)
305 .kr(9)
306 .channels(channels)
307 .width(3)
Marat Dukhan50323b82022-01-11 00:12:01 -0800308 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700309 }
310 }
311
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700312 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD64, multipixel_with_step) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700313 TEST_REQUIRES_ARM_NEON;
314 for (size_t channels = 1; channels <= 80; channels += 15) {
315 for (size_t step = 2; step <= 9; step++) {
316 DWConvMicrokernelTester()
317 .cr(16)
318 .kr(9)
319 .channels(channels)
320 .width(3)
321 .step(step)
Marat Dukhan50323b82022-01-11 00:12:01 -0800322 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700323 }
324 }
325 }
326
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700327 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD64, multipixel_with_output_stride) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700328 TEST_REQUIRES_ARM_NEON;
329 for (size_t channels = 1; channels <= 80; channels += 15) {
330 DWConvMicrokernelTester()
331 .cr(16)
332 .kr(9)
333 .channels(16)
334 .width(5)
335 .output_stride(83)
Marat Dukhan50323b82022-01-11 00:12:01 -0800336 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700337 }
338 }
339
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700340 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD64, multipixel_with_qmin) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700341 TEST_REQUIRES_ARM_NEON;
342 for (size_t channels = 1; channels <= 80; channels += 15) {
343 DWConvMicrokernelTester()
344 .cr(16)
345 .kr(9)
346 .channels(channels)
347 .width(3)
348 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800349 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700350 }
351 }
352
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700353 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD64, multipixel_with_qmax) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700354 TEST_REQUIRES_ARM_NEON;
355 for (size_t channels = 1; channels <= 80; channels += 15) {
356 DWConvMicrokernelTester()
357 .cr(16)
358 .kr(9)
359 .channels(channels)
360 .width(3)
361 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800362 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700363 }
364 }
365
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700366 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD64, input_offset) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700367 TEST_REQUIRES_ARM_NEON;
368 for (uint32_t channels = 32; channels < 256; channels += 48) {
369 DWConvMicrokernelTester()
370 .cr(16)
371 .kr(9)
372 .channels(channels)
373 .input_offset(304)
Marat Dukhan50323b82022-01-11 00:12:01 -0800374 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700375 }
376 }
377
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700378 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD64, zero) {
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700379 TEST_REQUIRES_ARM_NEON;
380 for (uint32_t mz = 0; mz < 9; mz++) {
381 for (uint32_t channels = 32; channels < 256; channels += 48) {
382 DWConvMicrokernelTester()
383 .cr(16)
384 .kr(9)
385 .channels(channels)
386 .input_offset(304)
387 .zero_index(mz)
Marat Dukhan50323b82022-01-11 00:12:01 -0800388 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan4ba70b72021-07-19 11:20:16 -0700389 }
390 }
391 }
392#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
393
394
395#if XNN_ARCH_ARM || XNN_ARCH_ARM64
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700396 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD128, c_eq_16) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700397 TEST_REQUIRES_ARM_NEON;
398 DWConvMicrokernelTester()
399 .cr(16)
400 .kr(9)
401 .channels(16)
Marat Dukhan50323b82022-01-11 00:12:01 -0800402 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700403 }
404
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700405 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD128, c_div_16) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700406 TEST_REQUIRES_ARM_NEON;
407 for (uint32_t channels = 32; channels < 256; channels += 48) {
408 DWConvMicrokernelTester()
409 .cr(16)
410 .kr(9)
411 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -0800412 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700413 }
414 }
415
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700416 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD128, c_div_16_with_qmin) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700417 TEST_REQUIRES_ARM_NEON;
418 for (uint32_t channels = 32; channels < 256; channels += 48) {
419 DWConvMicrokernelTester()
420 .cr(16)
421 .kr(9)
422 .channels(channels)
423 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800424 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700425 }
426 }
427
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700428 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD128, c_div_16_with_qmax) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700429 TEST_REQUIRES_ARM_NEON;
430 for (uint32_t channels = 32; channels < 256; channels += 48) {
431 DWConvMicrokernelTester()
432 .cr(16)
433 .kr(9)
434 .channels(channels)
435 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800436 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700437 }
438 }
439
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700440 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD128, c_lt_16) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700441 TEST_REQUIRES_ARM_NEON;
442 for (uint32_t channels = 1; channels < 16; channels++) {
443 DWConvMicrokernelTester()
444 .cr(16)
445 .kr(9)
446 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -0800447 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700448 }
449 }
450
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700451 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD128, c_gt_16) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700452 TEST_REQUIRES_ARM_NEON;
453 for (uint32_t channels = 17; channels < 32; channels++) {
454 DWConvMicrokernelTester()
455 .cr(16)
456 .kr(9)
457 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -0800458 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700459 }
460 }
461
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700462 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD128, c_gt_16_with_qmin) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700463 TEST_REQUIRES_ARM_NEON;
464 for (uint32_t channels = 17; channels < 32; channels++) {
465 DWConvMicrokernelTester()
466 .cr(16)
467 .kr(9)
468 .channels(channels)
469 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800470 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700471 }
472 }
473
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700474 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD128, c_gt_16_with_qmax) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700475 TEST_REQUIRES_ARM_NEON;
476 for (uint32_t channels = 17; channels < 32; channels++) {
477 DWConvMicrokernelTester()
478 .cr(16)
479 .kr(9)
480 .channels(channels)
481 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800482 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700483 }
484 }
485
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700486 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD128, multipixel) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700487 TEST_REQUIRES_ARM_NEON;
488 for (size_t channels = 1; channels <= 80; channels += 15) {
489 DWConvMicrokernelTester()
490 .cr(16)
491 .kr(9)
492 .channels(channels)
493 .width(3)
Marat Dukhan50323b82022-01-11 00:12:01 -0800494 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700495 }
496 }
497
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700498 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD128, multipixel_with_step) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700499 TEST_REQUIRES_ARM_NEON;
500 for (size_t channels = 1; channels <= 80; channels += 15) {
501 for (size_t step = 2; step <= 9; step++) {
502 DWConvMicrokernelTester()
503 .cr(16)
504 .kr(9)
505 .channels(channels)
506 .width(3)
507 .step(step)
Marat Dukhan50323b82022-01-11 00:12:01 -0800508 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700509 }
510 }
511 }
512
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700513 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD128, multipixel_with_output_stride) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700514 TEST_REQUIRES_ARM_NEON;
515 for (size_t channels = 1; channels <= 80; channels += 15) {
516 DWConvMicrokernelTester()
517 .cr(16)
518 .kr(9)
519 .channels(16)
520 .width(5)
521 .output_stride(83)
Marat Dukhan50323b82022-01-11 00:12:01 -0800522 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700523 }
524 }
525
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700526 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD128, multipixel_with_qmin) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700527 TEST_REQUIRES_ARM_NEON;
528 for (size_t channels = 1; channels <= 80; channels += 15) {
529 DWConvMicrokernelTester()
530 .cr(16)
531 .kr(9)
532 .channels(channels)
533 .width(3)
534 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800535 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700536 }
537 }
538
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700539 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD128, multipixel_with_qmax) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700540 TEST_REQUIRES_ARM_NEON;
541 for (size_t channels = 1; channels <= 80; channels += 15) {
542 DWConvMicrokernelTester()
543 .cr(16)
544 .kr(9)
545 .channels(channels)
546 .width(3)
547 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800548 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700549 }
550 }
551
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700552 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD128, input_offset) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700553 TEST_REQUIRES_ARM_NEON;
554 for (uint32_t channels = 32; channels < 256; channels += 48) {
555 DWConvMicrokernelTester()
556 .cr(16)
557 .kr(9)
558 .channels(channels)
559 .input_offset(304)
Marat Dukhan50323b82022-01-11 00:12:01 -0800560 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700561 }
562 }
563
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700564 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL8_LD128, zero) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700565 TEST_REQUIRES_ARM_NEON;
566 for (uint32_t mz = 0; mz < 9; mz++) {
567 for (uint32_t channels = 32; channels < 256; channels += 48) {
568 DWConvMicrokernelTester()
569 .cr(16)
570 .kr(9)
571 .channels(channels)
572 .input_offset(304)
573 .zero_index(mz)
Marat Dukhan50323b82022-01-11 00:12:01 -0800574 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700575 }
576 }
577 }
578#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
579
580
581#if XNN_ARCH_ARM || XNN_ARCH_ARM64
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700582 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL8_LD64, c_eq_8) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700583 TEST_REQUIRES_ARM_NEON;
584 DWConvMicrokernelTester()
585 .cr(8)
586 .kr(25)
587 .channels(8)
Marat Dukhan50323b82022-01-11 00:12:01 -0800588 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700589 }
590
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700591 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL8_LD64, c_div_8) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700592 TEST_REQUIRES_ARM_NEON;
593 for (uint32_t channels = 16; channels < 128; channels += 24) {
594 DWConvMicrokernelTester()
595 .cr(8)
596 .kr(25)
597 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -0800598 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700599 }
600 }
601
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700602 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL8_LD64, c_div_8_with_qmin) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700603 TEST_REQUIRES_ARM_NEON;
604 for (uint32_t channels = 16; channels < 128; channels += 24) {
605 DWConvMicrokernelTester()
606 .cr(8)
607 .kr(25)
608 .channels(channels)
609 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800610 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700611 }
612 }
613
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700614 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL8_LD64, c_div_8_with_qmax) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700615 TEST_REQUIRES_ARM_NEON;
616 for (uint32_t channels = 16; channels < 128; channels += 24) {
617 DWConvMicrokernelTester()
618 .cr(8)
619 .kr(25)
620 .channels(channels)
621 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800622 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700623 }
624 }
625
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700626 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL8_LD64, c_lt_8) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700627 TEST_REQUIRES_ARM_NEON;
628 for (uint32_t channels = 1; channels < 8; channels++) {
629 DWConvMicrokernelTester()
630 .cr(8)
631 .kr(25)
632 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -0800633 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700634 }
635 }
636
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700637 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL8_LD64, c_gt_8) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700638 TEST_REQUIRES_ARM_NEON;
639 for (uint32_t channels = 9; channels < 16; channels++) {
640 DWConvMicrokernelTester()
641 .cr(8)
642 .kr(25)
643 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -0800644 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700645 }
646 }
647
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700648 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL8_LD64, c_gt_8_with_qmin) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700649 TEST_REQUIRES_ARM_NEON;
650 for (uint32_t channels = 9; channels < 16; channels++) {
651 DWConvMicrokernelTester()
652 .cr(8)
653 .kr(25)
654 .channels(channels)
655 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800656 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700657 }
658 }
659
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700660 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL8_LD64, c_gt_8_with_qmax) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700661 TEST_REQUIRES_ARM_NEON;
662 for (uint32_t channels = 9; channels < 16; channels++) {
663 DWConvMicrokernelTester()
664 .cr(8)
665 .kr(25)
666 .channels(channels)
667 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800668 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700669 }
670 }
671
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700672 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL8_LD64, multipixel) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700673 TEST_REQUIRES_ARM_NEON;
674 for (size_t channels = 1; channels <= 40; channels += 7) {
675 DWConvMicrokernelTester()
676 .cr(8)
677 .kr(25)
678 .channels(channels)
679 .width(3)
Marat Dukhan50323b82022-01-11 00:12:01 -0800680 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700681 }
682 }
683
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700684 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL8_LD64, multipixel_with_step) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700685 TEST_REQUIRES_ARM_NEON;
686 for (size_t channels = 1; channels <= 40; channels += 7) {
687 for (size_t step = 2; step <= 25; step++) {
688 DWConvMicrokernelTester()
689 .cr(8)
690 .kr(25)
691 .channels(channels)
692 .width(3)
693 .step(step)
Marat Dukhan50323b82022-01-11 00:12:01 -0800694 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700695 }
696 }
697 }
698
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700699 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL8_LD64, multipixel_with_output_stride) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700700 TEST_REQUIRES_ARM_NEON;
701 for (size_t channels = 1; channels <= 40; channels += 7) {
702 DWConvMicrokernelTester()
703 .cr(8)
704 .kr(25)
705 .channels(8)
706 .width(5)
707 .output_stride(43)
Marat Dukhan50323b82022-01-11 00:12:01 -0800708 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700709 }
710 }
711
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700712 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL8_LD64, multipixel_with_qmin) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700713 TEST_REQUIRES_ARM_NEON;
714 for (size_t channels = 1; channels <= 40; channels += 7) {
715 DWConvMicrokernelTester()
716 .cr(8)
717 .kr(25)
718 .channels(channels)
719 .width(3)
720 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800721 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700722 }
723 }
724
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700725 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL8_LD64, multipixel_with_qmax) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700726 TEST_REQUIRES_ARM_NEON;
727 for (size_t channels = 1; channels <= 40; channels += 7) {
728 DWConvMicrokernelTester()
729 .cr(8)
730 .kr(25)
731 .channels(channels)
732 .width(3)
733 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800734 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700735 }
736 }
737
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700738 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL8_LD64, input_offset) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700739 TEST_REQUIRES_ARM_NEON;
740 for (uint32_t channels = 16; channels < 128; channels += 24) {
741 DWConvMicrokernelTester()
742 .cr(8)
743 .kr(25)
744 .channels(channels)
745 .input_offset(176)
Marat Dukhan50323b82022-01-11 00:12:01 -0800746 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700747 }
748 }
749
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700750 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL8_LD64, zero) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700751 TEST_REQUIRES_ARM_NEON;
752 for (uint32_t mz = 0; mz < 25; mz++) {
753 for (uint32_t channels = 16; channels < 128; channels += 24) {
754 DWConvMicrokernelTester()
755 .cr(8)
756 .kr(25)
757 .channels(channels)
758 .input_offset(176)
759 .zero_index(mz)
Marat Dukhan50323b82022-01-11 00:12:01 -0800760 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700761 }
762 }
763 }
764#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
765
766
767#if XNN_ARCH_ARM || XNN_ARCH_ARM64
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700768 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD64, c_eq_16) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700769 TEST_REQUIRES_ARM_NEON;
770 DWConvMicrokernelTester()
771 .cr(16)
772 .kr(25)
773 .channels(16)
Marat Dukhan50323b82022-01-11 00:12:01 -0800774 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700775 }
776
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700777 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD64, c_div_16) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700778 TEST_REQUIRES_ARM_NEON;
779 for (uint32_t channels = 32; channels < 256; channels += 48) {
780 DWConvMicrokernelTester()
781 .cr(16)
782 .kr(25)
783 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -0800784 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700785 }
786 }
787
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700788 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD64, c_div_16_with_qmin) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700789 TEST_REQUIRES_ARM_NEON;
790 for (uint32_t channels = 32; channels < 256; channels += 48) {
791 DWConvMicrokernelTester()
792 .cr(16)
793 .kr(25)
794 .channels(channels)
795 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800796 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700797 }
798 }
799
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700800 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD64, c_div_16_with_qmax) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700801 TEST_REQUIRES_ARM_NEON;
802 for (uint32_t channels = 32; channels < 256; channels += 48) {
803 DWConvMicrokernelTester()
804 .cr(16)
805 .kr(25)
806 .channels(channels)
807 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800808 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700809 }
810 }
811
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700812 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD64, c_lt_16) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700813 TEST_REQUIRES_ARM_NEON;
814 for (uint32_t channels = 1; channels < 16; channels++) {
815 DWConvMicrokernelTester()
816 .cr(16)
817 .kr(25)
818 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -0800819 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700820 }
821 }
822
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700823 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD64, c_gt_16) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700824 TEST_REQUIRES_ARM_NEON;
825 for (uint32_t channels = 17; channels < 32; channels++) {
826 DWConvMicrokernelTester()
827 .cr(16)
828 .kr(25)
829 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -0800830 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700831 }
832 }
833
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700834 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD64, c_gt_16_with_qmin) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700835 TEST_REQUIRES_ARM_NEON;
836 for (uint32_t channels = 17; channels < 32; channels++) {
837 DWConvMicrokernelTester()
838 .cr(16)
839 .kr(25)
840 .channels(channels)
841 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800842 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700843 }
844 }
845
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700846 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD64, c_gt_16_with_qmax) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700847 TEST_REQUIRES_ARM_NEON;
848 for (uint32_t channels = 17; channels < 32; channels++) {
849 DWConvMicrokernelTester()
850 .cr(16)
851 .kr(25)
852 .channels(channels)
853 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800854 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700855 }
856 }
857
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700858 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD64, multipixel) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700859 TEST_REQUIRES_ARM_NEON;
860 for (size_t channels = 1; channels <= 80; channels += 15) {
861 DWConvMicrokernelTester()
862 .cr(16)
863 .kr(25)
864 .channels(channels)
865 .width(3)
Marat Dukhan50323b82022-01-11 00:12:01 -0800866 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700867 }
868 }
869
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700870 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD64, multipixel_with_step) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700871 TEST_REQUIRES_ARM_NEON;
872 for (size_t channels = 1; channels <= 80; channels += 15) {
873 for (size_t step = 2; step <= 25; step++) {
874 DWConvMicrokernelTester()
875 .cr(16)
876 .kr(25)
877 .channels(channels)
878 .width(3)
879 .step(step)
Marat Dukhan50323b82022-01-11 00:12:01 -0800880 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700881 }
882 }
883 }
884
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700885 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD64, multipixel_with_output_stride) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700886 TEST_REQUIRES_ARM_NEON;
887 for (size_t channels = 1; channels <= 80; channels += 15) {
888 DWConvMicrokernelTester()
889 .cr(16)
890 .kr(25)
891 .channels(16)
892 .width(5)
893 .output_stride(83)
Marat Dukhan50323b82022-01-11 00:12:01 -0800894 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700895 }
896 }
897
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700898 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD64, multipixel_with_qmin) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700899 TEST_REQUIRES_ARM_NEON;
900 for (size_t channels = 1; channels <= 80; channels += 15) {
901 DWConvMicrokernelTester()
902 .cr(16)
903 .kr(25)
904 .channels(channels)
905 .width(3)
906 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800907 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700908 }
909 }
910
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700911 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD64, multipixel_with_qmax) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700912 TEST_REQUIRES_ARM_NEON;
913 for (size_t channels = 1; channels <= 80; channels += 15) {
914 DWConvMicrokernelTester()
915 .cr(16)
916 .kr(25)
917 .channels(channels)
918 .width(3)
919 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800920 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700921 }
922 }
923
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700924 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD64, input_offset) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700925 TEST_REQUIRES_ARM_NEON;
926 for (uint32_t channels = 32; channels < 256; channels += 48) {
927 DWConvMicrokernelTester()
928 .cr(16)
929 .kr(25)
930 .channels(channels)
931 .input_offset(304)
Marat Dukhan50323b82022-01-11 00:12:01 -0800932 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700933 }
934 }
935
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700936 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD64, zero) {
Marat Dukhancaccd8e2021-07-22 23:09:00 -0700937 TEST_REQUIRES_ARM_NEON;
938 for (uint32_t mz = 0; mz < 25; mz++) {
939 for (uint32_t channels = 32; channels < 256; channels += 48) {
940 DWConvMicrokernelTester()
941 .cr(16)
942 .kr(25)
943 .channels(channels)
944 .input_offset(304)
945 .zero_index(mz)
Marat Dukhan50323b82022-01-11 00:12:01 -0800946 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700947 }
948 }
949 }
950#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
951
952
953#if XNN_ARCH_ARM || XNN_ARCH_ARM64
954 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD128, c_eq_16) {
955 TEST_REQUIRES_ARM_NEON;
956 DWConvMicrokernelTester()
957 .cr(16)
958 .kr(25)
959 .channels(16)
Marat Dukhan50323b82022-01-11 00:12:01 -0800960 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700961 }
962
963 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD128, c_div_16) {
964 TEST_REQUIRES_ARM_NEON;
965 for (uint32_t channels = 32; channels < 256; channels += 48) {
966 DWConvMicrokernelTester()
967 .cr(16)
968 .kr(25)
969 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -0800970 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700971 }
972 }
973
974 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD128, c_div_16_with_qmin) {
975 TEST_REQUIRES_ARM_NEON;
976 for (uint32_t channels = 32; channels < 256; channels += 48) {
977 DWConvMicrokernelTester()
978 .cr(16)
979 .kr(25)
980 .channels(channels)
981 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800982 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700983 }
984 }
985
986 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD128, c_div_16_with_qmax) {
987 TEST_REQUIRES_ARM_NEON;
988 for (uint32_t channels = 32; channels < 256; channels += 48) {
989 DWConvMicrokernelTester()
990 .cr(16)
991 .kr(25)
992 .channels(channels)
993 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -0800994 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -0700995 }
996 }
997
998 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD128, c_lt_16) {
999 TEST_REQUIRES_ARM_NEON;
1000 for (uint32_t channels = 1; channels < 16; channels++) {
1001 DWConvMicrokernelTester()
1002 .cr(16)
1003 .kr(25)
1004 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08001005 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001006 }
1007 }
1008
1009 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD128, c_gt_16) {
1010 TEST_REQUIRES_ARM_NEON;
1011 for (uint32_t channels = 17; channels < 32; channels++) {
1012 DWConvMicrokernelTester()
1013 .cr(16)
1014 .kr(25)
1015 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08001016 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001017 }
1018 }
1019
1020 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD128, c_gt_16_with_qmin) {
1021 TEST_REQUIRES_ARM_NEON;
1022 for (uint32_t channels = 17; channels < 32; channels++) {
1023 DWConvMicrokernelTester()
1024 .cr(16)
1025 .kr(25)
1026 .channels(channels)
1027 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001028 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001029 }
1030 }
1031
1032 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD128, c_gt_16_with_qmax) {
1033 TEST_REQUIRES_ARM_NEON;
1034 for (uint32_t channels = 17; channels < 32; channels++) {
1035 DWConvMicrokernelTester()
1036 .cr(16)
1037 .kr(25)
1038 .channels(channels)
1039 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001040 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001041 }
1042 }
1043
1044 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD128, multipixel) {
1045 TEST_REQUIRES_ARM_NEON;
1046 for (size_t channels = 1; channels <= 80; channels += 15) {
1047 DWConvMicrokernelTester()
1048 .cr(16)
1049 .kr(25)
1050 .channels(channels)
1051 .width(3)
Marat Dukhan50323b82022-01-11 00:12:01 -08001052 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001053 }
1054 }
1055
1056 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD128, multipixel_with_step) {
1057 TEST_REQUIRES_ARM_NEON;
1058 for (size_t channels = 1; channels <= 80; channels += 15) {
1059 for (size_t step = 2; step <= 25; step++) {
1060 DWConvMicrokernelTester()
1061 .cr(16)
1062 .kr(25)
1063 .channels(channels)
1064 .width(3)
1065 .step(step)
Marat Dukhan50323b82022-01-11 00:12:01 -08001066 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001067 }
1068 }
1069 }
1070
1071 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD128, multipixel_with_output_stride) {
1072 TEST_REQUIRES_ARM_NEON;
1073 for (size_t channels = 1; channels <= 80; channels += 15) {
1074 DWConvMicrokernelTester()
1075 .cr(16)
1076 .kr(25)
1077 .channels(16)
1078 .width(5)
1079 .output_stride(83)
Marat Dukhan50323b82022-01-11 00:12:01 -08001080 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001081 }
1082 }
1083
1084 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD128, multipixel_with_qmin) {
1085 TEST_REQUIRES_ARM_NEON;
1086 for (size_t channels = 1; channels <= 80; channels += 15) {
1087 DWConvMicrokernelTester()
1088 .cr(16)
1089 .kr(25)
1090 .channels(channels)
1091 .width(3)
1092 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001093 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001094 }
1095 }
1096
1097 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD128, multipixel_with_qmax) {
1098 TEST_REQUIRES_ARM_NEON;
1099 for (size_t channels = 1; channels <= 80; channels += 15) {
1100 DWConvMicrokernelTester()
1101 .cr(16)
1102 .kr(25)
1103 .channels(channels)
1104 .width(3)
1105 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001106 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001107 }
1108 }
1109
1110 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD128, input_offset) {
1111 TEST_REQUIRES_ARM_NEON;
1112 for (uint32_t channels = 32; channels < 256; channels += 48) {
1113 DWConvMicrokernelTester()
1114 .cr(16)
1115 .kr(25)
1116 .channels(channels)
1117 .input_offset(304)
Marat Dukhan50323b82022-01-11 00:12:01 -08001118 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001119 }
1120 }
1121
1122 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL8_LD128, zero) {
1123 TEST_REQUIRES_ARM_NEON;
1124 for (uint32_t mz = 0; mz < 25; mz++) {
1125 for (uint32_t channels = 32; channels < 256; channels += 48) {
1126 DWConvMicrokernelTester()
1127 .cr(16)
1128 .kr(25)
1129 .channels(channels)
1130 .input_offset(304)
1131 .zero_index(mz)
Marat Dukhan50323b82022-01-11 00:12:01 -08001132 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001133 }
1134 }
1135 }
1136#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
1137
1138
1139#if XNN_ARCH_ARM || XNN_ARCH_ARM64
1140 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MLA8_LD64, c_eq_8) {
1141 TEST_REQUIRES_ARM_NEON;
1142 DWConvMicrokernelTester()
1143 .cr(8)
1144 .kr(9)
1145 .channels(8)
Marat Dukhan50323b82022-01-11 00:12:01 -08001146 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001147 }
1148
1149 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MLA8_LD64, c_div_8) {
1150 TEST_REQUIRES_ARM_NEON;
1151 for (uint32_t channels = 16; channels < 128; channels += 24) {
1152 DWConvMicrokernelTester()
1153 .cr(8)
1154 .kr(9)
1155 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08001156 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001157 }
1158 }
1159
1160 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MLA8_LD64, c_div_8_with_qmin) {
1161 TEST_REQUIRES_ARM_NEON;
1162 for (uint32_t channels = 16; channels < 128; channels += 24) {
1163 DWConvMicrokernelTester()
1164 .cr(8)
1165 .kr(9)
1166 .channels(channels)
1167 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001168 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001169 }
1170 }
1171
1172 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MLA8_LD64, c_div_8_with_qmax) {
1173 TEST_REQUIRES_ARM_NEON;
1174 for (uint32_t channels = 16; channels < 128; channels += 24) {
1175 DWConvMicrokernelTester()
1176 .cr(8)
1177 .kr(9)
1178 .channels(channels)
1179 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001180 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001181 }
1182 }
1183
1184 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MLA8_LD64, c_lt_8) {
1185 TEST_REQUIRES_ARM_NEON;
1186 for (uint32_t channels = 1; channels < 8; channels++) {
1187 DWConvMicrokernelTester()
1188 .cr(8)
1189 .kr(9)
1190 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08001191 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001192 }
1193 }
1194
1195 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MLA8_LD64, c_gt_8) {
1196 TEST_REQUIRES_ARM_NEON;
1197 for (uint32_t channels = 9; channels < 16; channels++) {
1198 DWConvMicrokernelTester()
1199 .cr(8)
1200 .kr(9)
1201 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08001202 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001203 }
1204 }
1205
1206 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MLA8_LD64, c_gt_8_with_qmin) {
1207 TEST_REQUIRES_ARM_NEON;
1208 for (uint32_t channels = 9; channels < 16; channels++) {
1209 DWConvMicrokernelTester()
1210 .cr(8)
1211 .kr(9)
1212 .channels(channels)
1213 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001214 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001215 }
1216 }
1217
1218 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MLA8_LD64, c_gt_8_with_qmax) {
1219 TEST_REQUIRES_ARM_NEON;
1220 for (uint32_t channels = 9; channels < 16; channels++) {
1221 DWConvMicrokernelTester()
1222 .cr(8)
1223 .kr(9)
1224 .channels(channels)
1225 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001226 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001227 }
1228 }
1229
1230 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MLA8_LD64, multipixel) {
1231 TEST_REQUIRES_ARM_NEON;
1232 for (size_t channels = 1; channels <= 40; channels += 7) {
1233 DWConvMicrokernelTester()
1234 .cr(8)
1235 .kr(9)
1236 .channels(channels)
1237 .width(3)
Marat Dukhan50323b82022-01-11 00:12:01 -08001238 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001239 }
1240 }
1241
1242 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MLA8_LD64, multipixel_with_step) {
1243 TEST_REQUIRES_ARM_NEON;
1244 for (size_t channels = 1; channels <= 40; channels += 7) {
1245 for (size_t step = 2; step <= 9; step++) {
1246 DWConvMicrokernelTester()
1247 .cr(8)
1248 .kr(9)
1249 .channels(channels)
1250 .width(3)
1251 .step(step)
Marat Dukhan50323b82022-01-11 00:12:01 -08001252 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001253 }
1254 }
1255 }
1256
1257 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MLA8_LD64, multipixel_with_output_stride) {
1258 TEST_REQUIRES_ARM_NEON;
1259 for (size_t channels = 1; channels <= 40; channels += 7) {
1260 DWConvMicrokernelTester()
1261 .cr(8)
1262 .kr(9)
1263 .channels(8)
1264 .width(5)
1265 .output_stride(43)
Marat Dukhan50323b82022-01-11 00:12:01 -08001266 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001267 }
1268 }
1269
1270 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MLA8_LD64, multipixel_with_qmin) {
1271 TEST_REQUIRES_ARM_NEON;
1272 for (size_t channels = 1; channels <= 40; channels += 7) {
1273 DWConvMicrokernelTester()
1274 .cr(8)
1275 .kr(9)
1276 .channels(channels)
1277 .width(3)
1278 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001279 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001280 }
1281 }
1282
1283 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MLA8_LD64, multipixel_with_qmax) {
1284 TEST_REQUIRES_ARM_NEON;
1285 for (size_t channels = 1; channels <= 40; channels += 7) {
1286 DWConvMicrokernelTester()
1287 .cr(8)
1288 .kr(9)
1289 .channels(channels)
1290 .width(3)
1291 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001292 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001293 }
1294 }
1295
1296 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MLA8_LD64, input_offset) {
1297 TEST_REQUIRES_ARM_NEON;
1298 for (uint32_t channels = 16; channels < 128; channels += 24) {
1299 DWConvMicrokernelTester()
1300 .cr(8)
1301 .kr(9)
1302 .channels(channels)
1303 .input_offset(176)
Marat Dukhan50323b82022-01-11 00:12:01 -08001304 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001305 }
1306 }
1307
1308 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MLA8_LD64, zero) {
1309 TEST_REQUIRES_ARM_NEON;
1310 for (uint32_t mz = 0; mz < 9; mz++) {
1311 for (uint32_t channels = 16; channels < 128; channels += 24) {
1312 DWConvMicrokernelTester()
1313 .cr(8)
1314 .kr(9)
1315 .channels(channels)
1316 .input_offset(176)
1317 .zero_index(mz)
Marat Dukhan50323b82022-01-11 00:12:01 -08001318 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001319 }
1320 }
1321 }
1322#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
1323
1324
1325#if XNN_ARCH_ARM || XNN_ARCH_ARM64
1326 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD64, c_eq_16) {
1327 TEST_REQUIRES_ARM_NEON;
1328 DWConvMicrokernelTester()
1329 .cr(16)
1330 .kr(9)
1331 .channels(16)
Marat Dukhan50323b82022-01-11 00:12:01 -08001332 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001333 }
1334
1335 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD64, c_div_16) {
1336 TEST_REQUIRES_ARM_NEON;
1337 for (uint32_t channels = 32; channels < 256; channels += 48) {
1338 DWConvMicrokernelTester()
1339 .cr(16)
1340 .kr(9)
1341 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08001342 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001343 }
1344 }
1345
1346 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD64, c_div_16_with_qmin) {
1347 TEST_REQUIRES_ARM_NEON;
1348 for (uint32_t channels = 32; channels < 256; channels += 48) {
1349 DWConvMicrokernelTester()
1350 .cr(16)
1351 .kr(9)
1352 .channels(channels)
1353 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001354 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001355 }
1356 }
1357
1358 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD64, c_div_16_with_qmax) {
1359 TEST_REQUIRES_ARM_NEON;
1360 for (uint32_t channels = 32; channels < 256; channels += 48) {
1361 DWConvMicrokernelTester()
1362 .cr(16)
1363 .kr(9)
1364 .channels(channels)
1365 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001366 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001367 }
1368 }
1369
1370 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD64, c_lt_16) {
1371 TEST_REQUIRES_ARM_NEON;
1372 for (uint32_t channels = 1; channels < 16; channels++) {
1373 DWConvMicrokernelTester()
1374 .cr(16)
1375 .kr(9)
1376 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08001377 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001378 }
1379 }
1380
1381 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD64, c_gt_16) {
1382 TEST_REQUIRES_ARM_NEON;
1383 for (uint32_t channels = 17; channels < 32; channels++) {
1384 DWConvMicrokernelTester()
1385 .cr(16)
1386 .kr(9)
1387 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08001388 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001389 }
1390 }
1391
1392 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD64, c_gt_16_with_qmin) {
1393 TEST_REQUIRES_ARM_NEON;
1394 for (uint32_t channels = 17; channels < 32; channels++) {
1395 DWConvMicrokernelTester()
1396 .cr(16)
1397 .kr(9)
1398 .channels(channels)
1399 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001400 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001401 }
1402 }
1403
1404 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD64, c_gt_16_with_qmax) {
1405 TEST_REQUIRES_ARM_NEON;
1406 for (uint32_t channels = 17; channels < 32; channels++) {
1407 DWConvMicrokernelTester()
1408 .cr(16)
1409 .kr(9)
1410 .channels(channels)
1411 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001412 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001413 }
1414 }
1415
1416 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD64, multipixel) {
1417 TEST_REQUIRES_ARM_NEON;
1418 for (size_t channels = 1; channels <= 80; channels += 15) {
1419 DWConvMicrokernelTester()
1420 .cr(16)
1421 .kr(9)
1422 .channels(channels)
1423 .width(3)
Marat Dukhan50323b82022-01-11 00:12:01 -08001424 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001425 }
1426 }
1427
1428 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD64, multipixel_with_step) {
1429 TEST_REQUIRES_ARM_NEON;
1430 for (size_t channels = 1; channels <= 80; channels += 15) {
1431 for (size_t step = 2; step <= 9; step++) {
1432 DWConvMicrokernelTester()
1433 .cr(16)
1434 .kr(9)
1435 .channels(channels)
1436 .width(3)
1437 .step(step)
Marat Dukhan50323b82022-01-11 00:12:01 -08001438 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001439 }
1440 }
1441 }
1442
1443 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD64, multipixel_with_output_stride) {
1444 TEST_REQUIRES_ARM_NEON;
1445 for (size_t channels = 1; channels <= 80; channels += 15) {
1446 DWConvMicrokernelTester()
1447 .cr(16)
1448 .kr(9)
1449 .channels(16)
1450 .width(5)
1451 .output_stride(83)
Marat Dukhan50323b82022-01-11 00:12:01 -08001452 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001453 }
1454 }
1455
1456 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD64, multipixel_with_qmin) {
1457 TEST_REQUIRES_ARM_NEON;
1458 for (size_t channels = 1; channels <= 80; channels += 15) {
1459 DWConvMicrokernelTester()
1460 .cr(16)
1461 .kr(9)
1462 .channels(channels)
1463 .width(3)
1464 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001465 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001466 }
1467 }
1468
1469 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD64, multipixel_with_qmax) {
1470 TEST_REQUIRES_ARM_NEON;
1471 for (size_t channels = 1; channels <= 80; channels += 15) {
1472 DWConvMicrokernelTester()
1473 .cr(16)
1474 .kr(9)
1475 .channels(channels)
1476 .width(3)
1477 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001478 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001479 }
1480 }
1481
1482 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD64, input_offset) {
1483 TEST_REQUIRES_ARM_NEON;
1484 for (uint32_t channels = 32; channels < 256; channels += 48) {
1485 DWConvMicrokernelTester()
1486 .cr(16)
1487 .kr(9)
1488 .channels(channels)
1489 .input_offset(304)
Marat Dukhan50323b82022-01-11 00:12:01 -08001490 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001491 }
1492 }
1493
1494 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD64, zero) {
1495 TEST_REQUIRES_ARM_NEON;
1496 for (uint32_t mz = 0; mz < 9; mz++) {
1497 for (uint32_t channels = 32; channels < 256; channels += 48) {
1498 DWConvMicrokernelTester()
1499 .cr(16)
1500 .kr(9)
1501 .channels(channels)
1502 .input_offset(304)
1503 .zero_index(mz)
Marat Dukhan50323b82022-01-11 00:12:01 -08001504 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001505 }
1506 }
1507 }
1508#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
1509
1510
1511#if XNN_ARCH_ARM || XNN_ARCH_ARM64
1512 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD128, c_eq_16) {
1513 TEST_REQUIRES_ARM_NEON;
1514 DWConvMicrokernelTester()
1515 .cr(16)
1516 .kr(9)
1517 .channels(16)
Marat Dukhan50323b82022-01-11 00:12:01 -08001518 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001519 }
1520
1521 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD128, c_div_16) {
1522 TEST_REQUIRES_ARM_NEON;
1523 for (uint32_t channels = 32; channels < 256; channels += 48) {
1524 DWConvMicrokernelTester()
1525 .cr(16)
1526 .kr(9)
1527 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08001528 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001529 }
1530 }
1531
1532 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD128, c_div_16_with_qmin) {
1533 TEST_REQUIRES_ARM_NEON;
1534 for (uint32_t channels = 32; channels < 256; channels += 48) {
1535 DWConvMicrokernelTester()
1536 .cr(16)
1537 .kr(9)
1538 .channels(channels)
1539 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001540 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001541 }
1542 }
1543
1544 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD128, c_div_16_with_qmax) {
1545 TEST_REQUIRES_ARM_NEON;
1546 for (uint32_t channels = 32; channels < 256; channels += 48) {
1547 DWConvMicrokernelTester()
1548 .cr(16)
1549 .kr(9)
1550 .channels(channels)
1551 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001552 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001553 }
1554 }
1555
1556 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD128, c_lt_16) {
1557 TEST_REQUIRES_ARM_NEON;
1558 for (uint32_t channels = 1; channels < 16; channels++) {
1559 DWConvMicrokernelTester()
1560 .cr(16)
1561 .kr(9)
1562 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08001563 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001564 }
1565 }
1566
1567 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD128, c_gt_16) {
1568 TEST_REQUIRES_ARM_NEON;
1569 for (uint32_t channels = 17; channels < 32; channels++) {
1570 DWConvMicrokernelTester()
1571 .cr(16)
1572 .kr(9)
1573 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08001574 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001575 }
1576 }
1577
1578 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD128, c_gt_16_with_qmin) {
1579 TEST_REQUIRES_ARM_NEON;
1580 for (uint32_t channels = 17; channels < 32; channels++) {
1581 DWConvMicrokernelTester()
1582 .cr(16)
1583 .kr(9)
1584 .channels(channels)
1585 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001586 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001587 }
1588 }
1589
1590 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD128, c_gt_16_with_qmax) {
1591 TEST_REQUIRES_ARM_NEON;
1592 for (uint32_t channels = 17; channels < 32; channels++) {
1593 DWConvMicrokernelTester()
1594 .cr(16)
1595 .kr(9)
1596 .channels(channels)
1597 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001598 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001599 }
1600 }
1601
1602 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD128, multipixel) {
1603 TEST_REQUIRES_ARM_NEON;
1604 for (size_t channels = 1; channels <= 80; channels += 15) {
1605 DWConvMicrokernelTester()
1606 .cr(16)
1607 .kr(9)
1608 .channels(channels)
1609 .width(3)
Marat Dukhan50323b82022-01-11 00:12:01 -08001610 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001611 }
1612 }
1613
1614 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD128, multipixel_with_step) {
1615 TEST_REQUIRES_ARM_NEON;
1616 for (size_t channels = 1; channels <= 80; channels += 15) {
1617 for (size_t step = 2; step <= 9; step++) {
1618 DWConvMicrokernelTester()
1619 .cr(16)
1620 .kr(9)
1621 .channels(channels)
1622 .width(3)
1623 .step(step)
Marat Dukhan50323b82022-01-11 00:12:01 -08001624 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001625 }
1626 }
1627 }
1628
1629 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD128, multipixel_with_output_stride) {
1630 TEST_REQUIRES_ARM_NEON;
1631 for (size_t channels = 1; channels <= 80; channels += 15) {
1632 DWConvMicrokernelTester()
1633 .cr(16)
1634 .kr(9)
1635 .channels(16)
1636 .width(5)
1637 .output_stride(83)
Marat Dukhan50323b82022-01-11 00:12:01 -08001638 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001639 }
1640 }
1641
1642 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD128, multipixel_with_qmin) {
1643 TEST_REQUIRES_ARM_NEON;
1644 for (size_t channels = 1; channels <= 80; channels += 15) {
1645 DWConvMicrokernelTester()
1646 .cr(16)
1647 .kr(9)
1648 .channels(channels)
1649 .width(3)
1650 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001651 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001652 }
1653 }
1654
1655 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD128, multipixel_with_qmax) {
1656 TEST_REQUIRES_ARM_NEON;
1657 for (size_t channels = 1; channels <= 80; channels += 15) {
1658 DWConvMicrokernelTester()
1659 .cr(16)
1660 .kr(9)
1661 .channels(channels)
1662 .width(3)
1663 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001664 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001665 }
1666 }
1667
1668 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD128, input_offset) {
1669 TEST_REQUIRES_ARM_NEON;
1670 for (uint32_t channels = 32; channels < 256; channels += 48) {
1671 DWConvMicrokernelTester()
1672 .cr(16)
1673 .kr(9)
1674 .channels(channels)
1675 .input_offset(304)
Marat Dukhan50323b82022-01-11 00:12:01 -08001676 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001677 }
1678 }
1679
1680 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MLA8_LD128, zero) {
1681 TEST_REQUIRES_ARM_NEON;
1682 for (uint32_t mz = 0; mz < 9; mz++) {
1683 for (uint32_t channels = 32; channels < 256; channels += 48) {
1684 DWConvMicrokernelTester()
1685 .cr(16)
1686 .kr(9)
1687 .channels(channels)
1688 .input_offset(304)
1689 .zero_index(mz)
Marat Dukhan50323b82022-01-11 00:12:01 -08001690 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001691 }
1692 }
1693 }
1694#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
1695
1696
1697#if XNN_ARCH_ARM || XNN_ARCH_ARM64
1698 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MLA8_LD64, c_eq_8) {
1699 TEST_REQUIRES_ARM_NEON;
1700 DWConvMicrokernelTester()
1701 .cr(8)
1702 .kr(25)
1703 .channels(8)
Marat Dukhan50323b82022-01-11 00:12:01 -08001704 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001705 }
1706
1707 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MLA8_LD64, c_div_8) {
1708 TEST_REQUIRES_ARM_NEON;
1709 for (uint32_t channels = 16; channels < 128; channels += 24) {
1710 DWConvMicrokernelTester()
1711 .cr(8)
1712 .kr(25)
1713 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08001714 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001715 }
1716 }
1717
1718 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MLA8_LD64, c_div_8_with_qmin) {
1719 TEST_REQUIRES_ARM_NEON;
1720 for (uint32_t channels = 16; channels < 128; channels += 24) {
1721 DWConvMicrokernelTester()
1722 .cr(8)
1723 .kr(25)
1724 .channels(channels)
1725 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001726 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001727 }
1728 }
1729
1730 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MLA8_LD64, c_div_8_with_qmax) {
1731 TEST_REQUIRES_ARM_NEON;
1732 for (uint32_t channels = 16; channels < 128; channels += 24) {
1733 DWConvMicrokernelTester()
1734 .cr(8)
1735 .kr(25)
1736 .channels(channels)
1737 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001738 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001739 }
1740 }
1741
1742 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MLA8_LD64, c_lt_8) {
1743 TEST_REQUIRES_ARM_NEON;
1744 for (uint32_t channels = 1; channels < 8; channels++) {
1745 DWConvMicrokernelTester()
1746 .cr(8)
1747 .kr(25)
1748 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08001749 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001750 }
1751 }
1752
1753 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MLA8_LD64, c_gt_8) {
1754 TEST_REQUIRES_ARM_NEON;
1755 for (uint32_t channels = 9; channels < 16; channels++) {
1756 DWConvMicrokernelTester()
1757 .cr(8)
1758 .kr(25)
1759 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08001760 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001761 }
1762 }
1763
1764 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MLA8_LD64, c_gt_8_with_qmin) {
1765 TEST_REQUIRES_ARM_NEON;
1766 for (uint32_t channels = 9; channels < 16; channels++) {
1767 DWConvMicrokernelTester()
1768 .cr(8)
1769 .kr(25)
1770 .channels(channels)
1771 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001772 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001773 }
1774 }
1775
1776 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MLA8_LD64, c_gt_8_with_qmax) {
1777 TEST_REQUIRES_ARM_NEON;
1778 for (uint32_t channels = 9; channels < 16; channels++) {
1779 DWConvMicrokernelTester()
1780 .cr(8)
1781 .kr(25)
1782 .channels(channels)
1783 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001784 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001785 }
1786 }
1787
1788 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MLA8_LD64, multipixel) {
1789 TEST_REQUIRES_ARM_NEON;
1790 for (size_t channels = 1; channels <= 40; channels += 7) {
1791 DWConvMicrokernelTester()
1792 .cr(8)
1793 .kr(25)
1794 .channels(channels)
1795 .width(3)
Marat Dukhan50323b82022-01-11 00:12:01 -08001796 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001797 }
1798 }
1799
1800 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MLA8_LD64, multipixel_with_step) {
1801 TEST_REQUIRES_ARM_NEON;
1802 for (size_t channels = 1; channels <= 40; channels += 7) {
1803 for (size_t step = 2; step <= 25; step++) {
1804 DWConvMicrokernelTester()
1805 .cr(8)
1806 .kr(25)
1807 .channels(channels)
1808 .width(3)
1809 .step(step)
Marat Dukhan50323b82022-01-11 00:12:01 -08001810 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001811 }
1812 }
1813 }
1814
1815 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MLA8_LD64, multipixel_with_output_stride) {
1816 TEST_REQUIRES_ARM_NEON;
1817 for (size_t channels = 1; channels <= 40; channels += 7) {
1818 DWConvMicrokernelTester()
1819 .cr(8)
1820 .kr(25)
1821 .channels(8)
1822 .width(5)
1823 .output_stride(43)
Marat Dukhan50323b82022-01-11 00:12:01 -08001824 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001825 }
1826 }
1827
1828 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MLA8_LD64, multipixel_with_qmin) {
1829 TEST_REQUIRES_ARM_NEON;
1830 for (size_t channels = 1; channels <= 40; channels += 7) {
1831 DWConvMicrokernelTester()
1832 .cr(8)
1833 .kr(25)
1834 .channels(channels)
1835 .width(3)
1836 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001837 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001838 }
1839 }
1840
1841 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MLA8_LD64, multipixel_with_qmax) {
1842 TEST_REQUIRES_ARM_NEON;
1843 for (size_t channels = 1; channels <= 40; channels += 7) {
1844 DWConvMicrokernelTester()
1845 .cr(8)
1846 .kr(25)
1847 .channels(channels)
1848 .width(3)
1849 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001850 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001851 }
1852 }
1853
1854 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MLA8_LD64, input_offset) {
1855 TEST_REQUIRES_ARM_NEON;
1856 for (uint32_t channels = 16; channels < 128; channels += 24) {
1857 DWConvMicrokernelTester()
1858 .cr(8)
1859 .kr(25)
1860 .channels(channels)
1861 .input_offset(176)
Marat Dukhan50323b82022-01-11 00:12:01 -08001862 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001863 }
1864 }
1865
1866 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MLA8_LD64, zero) {
1867 TEST_REQUIRES_ARM_NEON;
1868 for (uint32_t mz = 0; mz < 25; mz++) {
1869 for (uint32_t channels = 16; channels < 128; channels += 24) {
1870 DWConvMicrokernelTester()
1871 .cr(8)
1872 .kr(25)
1873 .channels(channels)
1874 .input_offset(176)
1875 .zero_index(mz)
Marat Dukhan50323b82022-01-11 00:12:01 -08001876 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001877 }
1878 }
1879 }
1880#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
1881
1882
1883#if XNN_ARCH_ARM || XNN_ARCH_ARM64
1884 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD64, c_eq_16) {
1885 TEST_REQUIRES_ARM_NEON;
1886 DWConvMicrokernelTester()
1887 .cr(16)
1888 .kr(25)
1889 .channels(16)
Marat Dukhan50323b82022-01-11 00:12:01 -08001890 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001891 }
1892
1893 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD64, c_div_16) {
1894 TEST_REQUIRES_ARM_NEON;
1895 for (uint32_t channels = 32; channels < 256; channels += 48) {
1896 DWConvMicrokernelTester()
1897 .cr(16)
1898 .kr(25)
1899 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08001900 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001901 }
1902 }
1903
1904 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD64, c_div_16_with_qmin) {
1905 TEST_REQUIRES_ARM_NEON;
1906 for (uint32_t channels = 32; channels < 256; channels += 48) {
1907 DWConvMicrokernelTester()
1908 .cr(16)
1909 .kr(25)
1910 .channels(channels)
1911 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001912 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001913 }
1914 }
1915
1916 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD64, c_div_16_with_qmax) {
1917 TEST_REQUIRES_ARM_NEON;
1918 for (uint32_t channels = 32; channels < 256; channels += 48) {
1919 DWConvMicrokernelTester()
1920 .cr(16)
1921 .kr(25)
1922 .channels(channels)
1923 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001924 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001925 }
1926 }
1927
1928 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD64, c_lt_16) {
1929 TEST_REQUIRES_ARM_NEON;
1930 for (uint32_t channels = 1; channels < 16; channels++) {
1931 DWConvMicrokernelTester()
1932 .cr(16)
1933 .kr(25)
1934 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08001935 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001936 }
1937 }
1938
1939 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD64, c_gt_16) {
1940 TEST_REQUIRES_ARM_NEON;
1941 for (uint32_t channels = 17; channels < 32; channels++) {
1942 DWConvMicrokernelTester()
1943 .cr(16)
1944 .kr(25)
1945 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08001946 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001947 }
1948 }
1949
1950 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD64, c_gt_16_with_qmin) {
1951 TEST_REQUIRES_ARM_NEON;
1952 for (uint32_t channels = 17; channels < 32; channels++) {
1953 DWConvMicrokernelTester()
1954 .cr(16)
1955 .kr(25)
1956 .channels(channels)
1957 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001958 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001959 }
1960 }
1961
1962 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD64, c_gt_16_with_qmax) {
1963 TEST_REQUIRES_ARM_NEON;
1964 for (uint32_t channels = 17; channels < 32; channels++) {
1965 DWConvMicrokernelTester()
1966 .cr(16)
1967 .kr(25)
1968 .channels(channels)
1969 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08001970 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001971 }
1972 }
1973
1974 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD64, multipixel) {
1975 TEST_REQUIRES_ARM_NEON;
1976 for (size_t channels = 1; channels <= 80; channels += 15) {
1977 DWConvMicrokernelTester()
1978 .cr(16)
1979 .kr(25)
1980 .channels(channels)
1981 .width(3)
Marat Dukhan50323b82022-01-11 00:12:01 -08001982 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001983 }
1984 }
1985
1986 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD64, multipixel_with_step) {
1987 TEST_REQUIRES_ARM_NEON;
1988 for (size_t channels = 1; channels <= 80; channels += 15) {
1989 for (size_t step = 2; step <= 25; step++) {
1990 DWConvMicrokernelTester()
1991 .cr(16)
1992 .kr(25)
1993 .channels(channels)
1994 .width(3)
1995 .step(step)
Marat Dukhan50323b82022-01-11 00:12:01 -08001996 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07001997 }
1998 }
1999 }
2000
2001 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD64, multipixel_with_output_stride) {
2002 TEST_REQUIRES_ARM_NEON;
2003 for (size_t channels = 1; channels <= 80; channels += 15) {
2004 DWConvMicrokernelTester()
2005 .cr(16)
2006 .kr(25)
2007 .channels(16)
2008 .width(5)
2009 .output_stride(83)
Marat Dukhan50323b82022-01-11 00:12:01 -08002010 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002011 }
2012 }
2013
2014 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD64, multipixel_with_qmin) {
2015 TEST_REQUIRES_ARM_NEON;
2016 for (size_t channels = 1; channels <= 80; channels += 15) {
2017 DWConvMicrokernelTester()
2018 .cr(16)
2019 .kr(25)
2020 .channels(channels)
2021 .width(3)
2022 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002023 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002024 }
2025 }
2026
2027 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD64, multipixel_with_qmax) {
2028 TEST_REQUIRES_ARM_NEON;
2029 for (size_t channels = 1; channels <= 80; channels += 15) {
2030 DWConvMicrokernelTester()
2031 .cr(16)
2032 .kr(25)
2033 .channels(channels)
2034 .width(3)
2035 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002036 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002037 }
2038 }
2039
2040 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD64, input_offset) {
2041 TEST_REQUIRES_ARM_NEON;
2042 for (uint32_t channels = 32; channels < 256; channels += 48) {
2043 DWConvMicrokernelTester()
2044 .cr(16)
2045 .kr(25)
2046 .channels(channels)
2047 .input_offset(304)
Marat Dukhan50323b82022-01-11 00:12:01 -08002048 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002049 }
2050 }
2051
2052 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD64, zero) {
2053 TEST_REQUIRES_ARM_NEON;
2054 for (uint32_t mz = 0; mz < 25; mz++) {
2055 for (uint32_t channels = 32; channels < 256; channels += 48) {
2056 DWConvMicrokernelTester()
2057 .cr(16)
2058 .kr(25)
2059 .channels(channels)
2060 .input_offset(304)
2061 .zero_index(mz)
Marat Dukhan50323b82022-01-11 00:12:01 -08002062 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld64, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002063 }
2064 }
2065 }
2066#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
2067
2068
2069#if XNN_ARCH_ARM || XNN_ARCH_ARM64
2070 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD128, c_eq_16) {
2071 TEST_REQUIRES_ARM_NEON;
2072 DWConvMicrokernelTester()
2073 .cr(16)
2074 .kr(25)
2075 .channels(16)
Marat Dukhan50323b82022-01-11 00:12:01 -08002076 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002077 }
2078
2079 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD128, c_div_16) {
2080 TEST_REQUIRES_ARM_NEON;
2081 for (uint32_t channels = 32; channels < 256; channels += 48) {
2082 DWConvMicrokernelTester()
2083 .cr(16)
2084 .kr(25)
2085 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08002086 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002087 }
2088 }
2089
2090 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD128, c_div_16_with_qmin) {
2091 TEST_REQUIRES_ARM_NEON;
2092 for (uint32_t channels = 32; channels < 256; channels += 48) {
2093 DWConvMicrokernelTester()
2094 .cr(16)
2095 .kr(25)
2096 .channels(channels)
2097 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002098 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002099 }
2100 }
2101
2102 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD128, c_div_16_with_qmax) {
2103 TEST_REQUIRES_ARM_NEON;
2104 for (uint32_t channels = 32; channels < 256; channels += 48) {
2105 DWConvMicrokernelTester()
2106 .cr(16)
2107 .kr(25)
2108 .channels(channels)
2109 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002110 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002111 }
2112 }
2113
2114 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD128, c_lt_16) {
2115 TEST_REQUIRES_ARM_NEON;
2116 for (uint32_t channels = 1; channels < 16; channels++) {
2117 DWConvMicrokernelTester()
2118 .cr(16)
2119 .kr(25)
2120 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08002121 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002122 }
2123 }
2124
2125 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD128, c_gt_16) {
2126 TEST_REQUIRES_ARM_NEON;
2127 for (uint32_t channels = 17; channels < 32; channels++) {
2128 DWConvMicrokernelTester()
2129 .cr(16)
2130 .kr(25)
2131 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08002132 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002133 }
2134 }
2135
2136 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD128, c_gt_16_with_qmin) {
2137 TEST_REQUIRES_ARM_NEON;
2138 for (uint32_t channels = 17; channels < 32; channels++) {
2139 DWConvMicrokernelTester()
2140 .cr(16)
2141 .kr(25)
2142 .channels(channels)
2143 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002144 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002145 }
2146 }
2147
2148 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD128, c_gt_16_with_qmax) {
2149 TEST_REQUIRES_ARM_NEON;
2150 for (uint32_t channels = 17; channels < 32; channels++) {
2151 DWConvMicrokernelTester()
2152 .cr(16)
2153 .kr(25)
2154 .channels(channels)
2155 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002156 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002157 }
2158 }
2159
2160 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD128, multipixel) {
2161 TEST_REQUIRES_ARM_NEON;
2162 for (size_t channels = 1; channels <= 80; channels += 15) {
2163 DWConvMicrokernelTester()
2164 .cr(16)
2165 .kr(25)
2166 .channels(channels)
2167 .width(3)
Marat Dukhan50323b82022-01-11 00:12:01 -08002168 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002169 }
2170 }
2171
2172 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD128, multipixel_with_step) {
2173 TEST_REQUIRES_ARM_NEON;
2174 for (size_t channels = 1; channels <= 80; channels += 15) {
2175 for (size_t step = 2; step <= 25; step++) {
2176 DWConvMicrokernelTester()
2177 .cr(16)
2178 .kr(25)
2179 .channels(channels)
2180 .width(3)
2181 .step(step)
Marat Dukhan50323b82022-01-11 00:12:01 -08002182 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002183 }
2184 }
2185 }
2186
2187 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD128, multipixel_with_output_stride) {
2188 TEST_REQUIRES_ARM_NEON;
2189 for (size_t channels = 1; channels <= 80; channels += 15) {
2190 DWConvMicrokernelTester()
2191 .cr(16)
2192 .kr(25)
2193 .channels(16)
2194 .width(5)
2195 .output_stride(83)
Marat Dukhan50323b82022-01-11 00:12:01 -08002196 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002197 }
2198 }
2199
2200 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD128, multipixel_with_qmin) {
2201 TEST_REQUIRES_ARM_NEON;
2202 for (size_t channels = 1; channels <= 80; channels += 15) {
2203 DWConvMicrokernelTester()
2204 .cr(16)
2205 .kr(25)
2206 .channels(channels)
2207 .width(3)
2208 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002209 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002210 }
2211 }
2212
2213 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD128, multipixel_with_qmax) {
2214 TEST_REQUIRES_ARM_NEON;
2215 for (size_t channels = 1; channels <= 80; channels += 15) {
2216 DWConvMicrokernelTester()
2217 .cr(16)
2218 .kr(25)
2219 .channels(channels)
2220 .width(3)
2221 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002222 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002223 }
2224 }
2225
2226 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD128, input_offset) {
2227 TEST_REQUIRES_ARM_NEON;
2228 for (uint32_t channels = 32; channels < 256; channels += 48) {
2229 DWConvMicrokernelTester()
2230 .cr(16)
2231 .kr(25)
2232 .channels(channels)
2233 .input_offset(304)
Marat Dukhan50323b82022-01-11 00:12:01 -08002234 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002235 }
2236 }
2237
2238 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MLA8_LD128, zero) {
2239 TEST_REQUIRES_ARM_NEON;
2240 for (uint32_t mz = 0; mz < 25; mz++) {
2241 for (uint32_t channels = 32; channels < 256; channels += 48) {
2242 DWConvMicrokernelTester()
2243 .cr(16)
2244 .kr(25)
2245 .channels(channels)
2246 .input_offset(304)
2247 .zero_index(mz)
Marat Dukhan50323b82022-01-11 00:12:01 -08002248 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mla8_ld128, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhancaccd8e2021-07-22 23:09:00 -07002249 }
2250 }
2251 }
2252#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
2253
2254
2255#if XNN_ARCH_ARM || XNN_ARCH_ARM64
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002256 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL16, c_eq_8) {
2257 TEST_REQUIRES_ARM_NEON;
2258 DWConvMicrokernelTester()
2259 .cr(8)
2260 .kr(9)
2261 .channels(8)
Marat Dukhan50323b82022-01-11 00:12:01 -08002262 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002263 }
2264
2265 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL16, c_div_8) {
2266 TEST_REQUIRES_ARM_NEON;
2267 for (uint32_t channels = 16; channels < 128; channels += 24) {
2268 DWConvMicrokernelTester()
2269 .cr(8)
2270 .kr(9)
2271 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08002272 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002273 }
2274 }
2275
2276 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL16, c_div_8_with_qmin) {
2277 TEST_REQUIRES_ARM_NEON;
2278 for (uint32_t channels = 16; channels < 128; channels += 24) {
2279 DWConvMicrokernelTester()
2280 .cr(8)
2281 .kr(9)
2282 .channels(channels)
2283 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002284 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002285 }
2286 }
2287
2288 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL16, c_div_8_with_qmax) {
2289 TEST_REQUIRES_ARM_NEON;
2290 for (uint32_t channels = 16; channels < 128; channels += 24) {
2291 DWConvMicrokernelTester()
2292 .cr(8)
2293 .kr(9)
2294 .channels(channels)
2295 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002296 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002297 }
2298 }
2299
2300 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL16, c_lt_8) {
2301 TEST_REQUIRES_ARM_NEON;
2302 for (uint32_t channels = 1; channels < 8; channels++) {
2303 DWConvMicrokernelTester()
2304 .cr(8)
2305 .kr(9)
2306 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08002307 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002308 }
2309 }
2310
2311 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL16, c_gt_8) {
2312 TEST_REQUIRES_ARM_NEON;
2313 for (uint32_t channels = 9; channels < 16; channels++) {
2314 DWConvMicrokernelTester()
2315 .cr(8)
2316 .kr(9)
2317 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08002318 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002319 }
2320 }
2321
2322 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL16, c_gt_8_with_qmin) {
2323 TEST_REQUIRES_ARM_NEON;
2324 for (uint32_t channels = 9; channels < 16; channels++) {
2325 DWConvMicrokernelTester()
2326 .cr(8)
2327 .kr(9)
2328 .channels(channels)
2329 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002330 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002331 }
2332 }
2333
2334 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL16, c_gt_8_with_qmax) {
2335 TEST_REQUIRES_ARM_NEON;
2336 for (uint32_t channels = 9; channels < 16; channels++) {
2337 DWConvMicrokernelTester()
2338 .cr(8)
2339 .kr(9)
2340 .channels(channels)
2341 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002342 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002343 }
2344 }
2345
2346 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL16, multipixel) {
2347 TEST_REQUIRES_ARM_NEON;
2348 for (size_t channels = 1; channels <= 40; channels += 7) {
2349 DWConvMicrokernelTester()
2350 .cr(8)
2351 .kr(9)
2352 .channels(channels)
2353 .width(3)
Marat Dukhan50323b82022-01-11 00:12:01 -08002354 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002355 }
2356 }
2357
2358 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL16, multipixel_with_step) {
2359 TEST_REQUIRES_ARM_NEON;
2360 for (size_t channels = 1; channels <= 40; channels += 7) {
2361 for (size_t step = 2; step <= 9; step++) {
2362 DWConvMicrokernelTester()
2363 .cr(8)
2364 .kr(9)
2365 .channels(channels)
2366 .width(3)
2367 .step(step)
Marat Dukhan50323b82022-01-11 00:12:01 -08002368 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002369 }
2370 }
2371 }
2372
2373 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL16, multipixel_with_output_stride) {
2374 TEST_REQUIRES_ARM_NEON;
2375 for (size_t channels = 1; channels <= 40; channels += 7) {
2376 DWConvMicrokernelTester()
2377 .cr(8)
2378 .kr(9)
2379 .channels(8)
2380 .width(5)
2381 .output_stride(43)
Marat Dukhan50323b82022-01-11 00:12:01 -08002382 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002383 }
2384 }
2385
2386 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL16, multipixel_with_qmin) {
2387 TEST_REQUIRES_ARM_NEON;
2388 for (size_t channels = 1; channels <= 40; channels += 7) {
2389 DWConvMicrokernelTester()
2390 .cr(8)
2391 .kr(9)
2392 .channels(channels)
2393 .width(3)
2394 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002395 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002396 }
2397 }
2398
2399 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL16, multipixel_with_qmax) {
2400 TEST_REQUIRES_ARM_NEON;
2401 for (size_t channels = 1; channels <= 40; channels += 7) {
2402 DWConvMicrokernelTester()
2403 .cr(8)
2404 .kr(9)
2405 .channels(channels)
2406 .width(3)
2407 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002408 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002409 }
2410 }
2411
2412 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL16, input_offset) {
2413 TEST_REQUIRES_ARM_NEON;
2414 for (uint32_t channels = 16; channels < 128; channels += 24) {
2415 DWConvMicrokernelTester()
2416 .cr(8)
2417 .kr(9)
2418 .channels(channels)
2419 .input_offset(176)
Marat Dukhan50323b82022-01-11 00:12:01 -08002420 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002421 }
2422 }
2423
2424 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X9__NEON_MUL16, zero) {
2425 TEST_REQUIRES_ARM_NEON;
2426 for (uint32_t mz = 0; mz < 9; mz++) {
2427 for (uint32_t channels = 16; channels < 128; channels += 24) {
2428 DWConvMicrokernelTester()
2429 .cr(8)
2430 .kr(9)
2431 .channels(channels)
2432 .input_offset(176)
2433 .zero_index(mz)
Marat Dukhan50323b82022-01-11 00:12:01 -08002434 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002435 }
2436 }
2437 }
2438#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
2439
2440
2441#if XNN_ARCH_ARM || XNN_ARCH_ARM64
2442 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL16, c_eq_16) {
2443 TEST_REQUIRES_ARM_NEON;
2444 DWConvMicrokernelTester()
2445 .cr(16)
2446 .kr(9)
2447 .channels(16)
Marat Dukhan50323b82022-01-11 00:12:01 -08002448 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002449 }
2450
2451 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL16, c_div_16) {
2452 TEST_REQUIRES_ARM_NEON;
2453 for (uint32_t channels = 32; channels < 256; channels += 48) {
2454 DWConvMicrokernelTester()
2455 .cr(16)
2456 .kr(9)
2457 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08002458 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002459 }
2460 }
2461
2462 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL16, c_div_16_with_qmin) {
2463 TEST_REQUIRES_ARM_NEON;
2464 for (uint32_t channels = 32; channels < 256; channels += 48) {
2465 DWConvMicrokernelTester()
2466 .cr(16)
2467 .kr(9)
2468 .channels(channels)
2469 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002470 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002471 }
2472 }
2473
2474 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL16, c_div_16_with_qmax) {
2475 TEST_REQUIRES_ARM_NEON;
2476 for (uint32_t channels = 32; channels < 256; channels += 48) {
2477 DWConvMicrokernelTester()
2478 .cr(16)
2479 .kr(9)
2480 .channels(channels)
2481 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002482 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002483 }
2484 }
2485
2486 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL16, c_lt_16) {
2487 TEST_REQUIRES_ARM_NEON;
2488 for (uint32_t channels = 1; channels < 16; channels++) {
2489 DWConvMicrokernelTester()
2490 .cr(16)
2491 .kr(9)
2492 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08002493 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002494 }
2495 }
2496
2497 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL16, c_gt_16) {
2498 TEST_REQUIRES_ARM_NEON;
2499 for (uint32_t channels = 17; channels < 32; channels++) {
2500 DWConvMicrokernelTester()
2501 .cr(16)
2502 .kr(9)
2503 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08002504 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002505 }
2506 }
2507
2508 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL16, c_gt_16_with_qmin) {
2509 TEST_REQUIRES_ARM_NEON;
2510 for (uint32_t channels = 17; channels < 32; channels++) {
2511 DWConvMicrokernelTester()
2512 .cr(16)
2513 .kr(9)
2514 .channels(channels)
2515 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002516 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002517 }
2518 }
2519
2520 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL16, c_gt_16_with_qmax) {
2521 TEST_REQUIRES_ARM_NEON;
2522 for (uint32_t channels = 17; channels < 32; channels++) {
2523 DWConvMicrokernelTester()
2524 .cr(16)
2525 .kr(9)
2526 .channels(channels)
2527 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002528 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002529 }
2530 }
2531
2532 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL16, multipixel) {
2533 TEST_REQUIRES_ARM_NEON;
2534 for (size_t channels = 1; channels <= 80; channels += 15) {
2535 DWConvMicrokernelTester()
2536 .cr(16)
2537 .kr(9)
2538 .channels(channels)
2539 .width(3)
Marat Dukhan50323b82022-01-11 00:12:01 -08002540 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002541 }
2542 }
2543
2544 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL16, multipixel_with_step) {
2545 TEST_REQUIRES_ARM_NEON;
2546 for (size_t channels = 1; channels <= 80; channels += 15) {
2547 for (size_t step = 2; step <= 9; step++) {
2548 DWConvMicrokernelTester()
2549 .cr(16)
2550 .kr(9)
2551 .channels(channels)
2552 .width(3)
2553 .step(step)
Marat Dukhan50323b82022-01-11 00:12:01 -08002554 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002555 }
2556 }
2557 }
2558
2559 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL16, multipixel_with_output_stride) {
2560 TEST_REQUIRES_ARM_NEON;
2561 for (size_t channels = 1; channels <= 80; channels += 15) {
2562 DWConvMicrokernelTester()
2563 .cr(16)
2564 .kr(9)
2565 .channels(16)
2566 .width(5)
2567 .output_stride(83)
Marat Dukhan50323b82022-01-11 00:12:01 -08002568 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002569 }
2570 }
2571
2572 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL16, multipixel_with_qmin) {
2573 TEST_REQUIRES_ARM_NEON;
2574 for (size_t channels = 1; channels <= 80; channels += 15) {
2575 DWConvMicrokernelTester()
2576 .cr(16)
2577 .kr(9)
2578 .channels(channels)
2579 .width(3)
2580 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002581 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002582 }
2583 }
2584
2585 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL16, multipixel_with_qmax) {
2586 TEST_REQUIRES_ARM_NEON;
2587 for (size_t channels = 1; channels <= 80; channels += 15) {
2588 DWConvMicrokernelTester()
2589 .cr(16)
2590 .kr(9)
2591 .channels(channels)
2592 .width(3)
2593 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002594 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002595 }
2596 }
2597
2598 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL16, input_offset) {
2599 TEST_REQUIRES_ARM_NEON;
2600 for (uint32_t channels = 32; channels < 256; channels += 48) {
2601 DWConvMicrokernelTester()
2602 .cr(16)
2603 .kr(9)
2604 .channels(channels)
2605 .input_offset(304)
Marat Dukhan50323b82022-01-11 00:12:01 -08002606 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002607 }
2608 }
2609
2610 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X9__NEON_MUL16, zero) {
2611 TEST_REQUIRES_ARM_NEON;
2612 for (uint32_t mz = 0; mz < 9; mz++) {
2613 for (uint32_t channels = 32; channels < 256; channels += 48) {
2614 DWConvMicrokernelTester()
2615 .cr(16)
2616 .kr(9)
2617 .channels(channels)
2618 .input_offset(304)
2619 .zero_index(mz)
Marat Dukhan50323b82022-01-11 00:12:01 -08002620 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002621 }
2622 }
2623 }
2624#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
2625
2626
2627#if XNN_ARCH_ARM || XNN_ARCH_ARM64
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002628 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X9__NEON_MUL16, c_eq_24) {
2629 TEST_REQUIRES_ARM_NEON;
2630 DWConvMicrokernelTester()
2631 .cr(24)
2632 .kr(9)
2633 .channels(24)
Marat Dukhan50323b82022-01-11 00:12:01 -08002634 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002635 }
2636
2637 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X9__NEON_MUL16, c_div_24) {
2638 TEST_REQUIRES_ARM_NEON;
2639 for (uint32_t channels = 48; channels < 384; channels += 72) {
2640 DWConvMicrokernelTester()
2641 .cr(24)
2642 .kr(9)
2643 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08002644 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002645 }
2646 }
2647
2648 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X9__NEON_MUL16, c_div_24_with_qmin) {
2649 TEST_REQUIRES_ARM_NEON;
2650 for (uint32_t channels = 48; channels < 384; channels += 72) {
2651 DWConvMicrokernelTester()
2652 .cr(24)
2653 .kr(9)
2654 .channels(channels)
2655 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002656 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002657 }
2658 }
2659
2660 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X9__NEON_MUL16, c_div_24_with_qmax) {
2661 TEST_REQUIRES_ARM_NEON;
2662 for (uint32_t channels = 48; channels < 384; channels += 72) {
2663 DWConvMicrokernelTester()
2664 .cr(24)
2665 .kr(9)
2666 .channels(channels)
2667 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002668 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002669 }
2670 }
2671
2672 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X9__NEON_MUL16, c_lt_24) {
2673 TEST_REQUIRES_ARM_NEON;
2674 for (uint32_t channels = 1; channels < 24; channels++) {
2675 DWConvMicrokernelTester()
2676 .cr(24)
2677 .kr(9)
2678 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08002679 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002680 }
2681 }
2682
2683 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X9__NEON_MUL16, c_gt_24) {
2684 TEST_REQUIRES_ARM_NEON;
2685 for (uint32_t channels = 25; channels < 48; channels++) {
2686 DWConvMicrokernelTester()
2687 .cr(24)
2688 .kr(9)
2689 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08002690 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002691 }
2692 }
2693
2694 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X9__NEON_MUL16, c_gt_24_with_qmin) {
2695 TEST_REQUIRES_ARM_NEON;
2696 for (uint32_t channels = 25; channels < 48; channels++) {
2697 DWConvMicrokernelTester()
2698 .cr(24)
2699 .kr(9)
2700 .channels(channels)
2701 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002702 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002703 }
2704 }
2705
2706 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X9__NEON_MUL16, c_gt_24_with_qmax) {
2707 TEST_REQUIRES_ARM_NEON;
2708 for (uint32_t channels = 25; channels < 48; channels++) {
2709 DWConvMicrokernelTester()
2710 .cr(24)
2711 .kr(9)
2712 .channels(channels)
2713 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002714 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002715 }
2716 }
2717
2718 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X9__NEON_MUL16, multipixel) {
2719 TEST_REQUIRES_ARM_NEON;
2720 for (size_t channels = 1; channels <= 120; channels += 23) {
2721 DWConvMicrokernelTester()
2722 .cr(24)
2723 .kr(9)
2724 .channels(channels)
2725 .width(3)
Marat Dukhan50323b82022-01-11 00:12:01 -08002726 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002727 }
2728 }
2729
2730 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X9__NEON_MUL16, multipixel_with_step) {
2731 TEST_REQUIRES_ARM_NEON;
2732 for (size_t channels = 1; channels <= 120; channels += 23) {
2733 for (size_t step = 2; step <= 9; step++) {
2734 DWConvMicrokernelTester()
2735 .cr(24)
2736 .kr(9)
2737 .channels(channels)
2738 .width(3)
2739 .step(step)
Marat Dukhan50323b82022-01-11 00:12:01 -08002740 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002741 }
2742 }
2743 }
2744
2745 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X9__NEON_MUL16, multipixel_with_output_stride) {
2746 TEST_REQUIRES_ARM_NEON;
2747 for (size_t channels = 1; channels <= 120; channels += 23) {
2748 DWConvMicrokernelTester()
2749 .cr(24)
2750 .kr(9)
2751 .channels(24)
2752 .width(5)
2753 .output_stride(127)
Marat Dukhan50323b82022-01-11 00:12:01 -08002754 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002755 }
2756 }
2757
2758 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X9__NEON_MUL16, multipixel_with_qmin) {
2759 TEST_REQUIRES_ARM_NEON;
2760 for (size_t channels = 1; channels <= 120; channels += 23) {
2761 DWConvMicrokernelTester()
2762 .cr(24)
2763 .kr(9)
2764 .channels(channels)
2765 .width(3)
2766 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002767 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002768 }
2769 }
2770
2771 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X9__NEON_MUL16, multipixel_with_qmax) {
2772 TEST_REQUIRES_ARM_NEON;
2773 for (size_t channels = 1; channels <= 120; channels += 23) {
2774 DWConvMicrokernelTester()
2775 .cr(24)
2776 .kr(9)
2777 .channels(channels)
2778 .width(3)
2779 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002780 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002781 }
2782 }
2783
2784 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X9__NEON_MUL16, input_offset) {
2785 TEST_REQUIRES_ARM_NEON;
2786 for (uint32_t channels = 48; channels < 384; channels += 72) {
2787 DWConvMicrokernelTester()
2788 .cr(24)
2789 .kr(9)
2790 .channels(channels)
2791 .input_offset(464)
Marat Dukhan50323b82022-01-11 00:12:01 -08002792 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002793 }
2794 }
2795
2796 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X9__NEON_MUL16, zero) {
2797 TEST_REQUIRES_ARM_NEON;
2798 for (uint32_t mz = 0; mz < 9; mz++) {
2799 for (uint32_t channels = 48; channels < 384; channels += 72) {
2800 DWConvMicrokernelTester()
2801 .cr(24)
2802 .kr(9)
2803 .channels(channels)
2804 .input_offset(464)
2805 .zero_index(mz)
Marat Dukhan50323b82022-01-11 00:12:01 -08002806 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002807 }
2808 }
2809 }
2810#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
2811
2812
2813#if XNN_ARCH_ARM || XNN_ARCH_ARM64
2814 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X9__NEON_MUL16, c_eq_32) {
2815 TEST_REQUIRES_ARM_NEON;
2816 DWConvMicrokernelTester()
2817 .cr(32)
2818 .kr(9)
2819 .channels(32)
Marat Dukhan50323b82022-01-11 00:12:01 -08002820 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002821 }
2822
2823 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X9__NEON_MUL16, c_div_32) {
2824 TEST_REQUIRES_ARM_NEON;
2825 for (uint32_t channels = 64; channels < 512; channels += 96) {
2826 DWConvMicrokernelTester()
2827 .cr(32)
2828 .kr(9)
2829 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08002830 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002831 }
2832 }
2833
2834 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X9__NEON_MUL16, c_div_32_with_qmin) {
2835 TEST_REQUIRES_ARM_NEON;
2836 for (uint32_t channels = 64; channels < 512; channels += 96) {
2837 DWConvMicrokernelTester()
2838 .cr(32)
2839 .kr(9)
2840 .channels(channels)
2841 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002842 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002843 }
2844 }
2845
2846 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X9__NEON_MUL16, c_div_32_with_qmax) {
2847 TEST_REQUIRES_ARM_NEON;
2848 for (uint32_t channels = 64; channels < 512; channels += 96) {
2849 DWConvMicrokernelTester()
2850 .cr(32)
2851 .kr(9)
2852 .channels(channels)
2853 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002854 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002855 }
2856 }
2857
2858 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X9__NEON_MUL16, c_lt_32) {
2859 TEST_REQUIRES_ARM_NEON;
2860 for (uint32_t channels = 1; channels < 32; channels++) {
2861 DWConvMicrokernelTester()
2862 .cr(32)
2863 .kr(9)
2864 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08002865 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002866 }
2867 }
2868
2869 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X9__NEON_MUL16, c_gt_32) {
2870 TEST_REQUIRES_ARM_NEON;
2871 for (uint32_t channels = 33; channels < 64; channels++) {
2872 DWConvMicrokernelTester()
2873 .cr(32)
2874 .kr(9)
2875 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08002876 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002877 }
2878 }
2879
2880 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X9__NEON_MUL16, c_gt_32_with_qmin) {
2881 TEST_REQUIRES_ARM_NEON;
2882 for (uint32_t channels = 33; channels < 64; channels++) {
2883 DWConvMicrokernelTester()
2884 .cr(32)
2885 .kr(9)
2886 .channels(channels)
2887 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002888 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002889 }
2890 }
2891
2892 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X9__NEON_MUL16, c_gt_32_with_qmax) {
2893 TEST_REQUIRES_ARM_NEON;
2894 for (uint32_t channels = 33; channels < 64; channels++) {
2895 DWConvMicrokernelTester()
2896 .cr(32)
2897 .kr(9)
2898 .channels(channels)
2899 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002900 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002901 }
2902 }
2903
2904 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X9__NEON_MUL16, multipixel) {
2905 TEST_REQUIRES_ARM_NEON;
2906 for (size_t channels = 1; channels <= 160; channels += 31) {
2907 DWConvMicrokernelTester()
2908 .cr(32)
2909 .kr(9)
2910 .channels(channels)
2911 .width(3)
Marat Dukhan50323b82022-01-11 00:12:01 -08002912 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002913 }
2914 }
2915
2916 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X9__NEON_MUL16, multipixel_with_step) {
2917 TEST_REQUIRES_ARM_NEON;
2918 for (size_t channels = 1; channels <= 160; channels += 31) {
2919 for (size_t step = 2; step <= 9; step++) {
2920 DWConvMicrokernelTester()
2921 .cr(32)
2922 .kr(9)
2923 .channels(channels)
2924 .width(3)
2925 .step(step)
Marat Dukhan50323b82022-01-11 00:12:01 -08002926 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002927 }
2928 }
2929 }
2930
2931 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X9__NEON_MUL16, multipixel_with_output_stride) {
2932 TEST_REQUIRES_ARM_NEON;
2933 for (size_t channels = 1; channels <= 160; channels += 31) {
2934 DWConvMicrokernelTester()
2935 .cr(32)
2936 .kr(9)
2937 .channels(32)
2938 .width(5)
2939 .output_stride(163)
Marat Dukhan50323b82022-01-11 00:12:01 -08002940 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002941 }
2942 }
2943
2944 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X9__NEON_MUL16, multipixel_with_qmin) {
2945 TEST_REQUIRES_ARM_NEON;
2946 for (size_t channels = 1; channels <= 160; channels += 31) {
2947 DWConvMicrokernelTester()
2948 .cr(32)
2949 .kr(9)
2950 .channels(channels)
2951 .width(3)
2952 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002953 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002954 }
2955 }
2956
2957 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X9__NEON_MUL16, multipixel_with_qmax) {
2958 TEST_REQUIRES_ARM_NEON;
2959 for (size_t channels = 1; channels <= 160; channels += 31) {
2960 DWConvMicrokernelTester()
2961 .cr(32)
2962 .kr(9)
2963 .channels(channels)
2964 .width(3)
2965 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08002966 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002967 }
2968 }
2969
2970 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X9__NEON_MUL16, input_offset) {
2971 TEST_REQUIRES_ARM_NEON;
2972 for (uint32_t channels = 64; channels < 512; channels += 96) {
2973 DWConvMicrokernelTester()
2974 .cr(32)
2975 .kr(9)
2976 .channels(channels)
2977 .input_offset(592)
Marat Dukhan50323b82022-01-11 00:12:01 -08002978 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002979 }
2980 }
2981
2982 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X9__NEON_MUL16, zero) {
2983 TEST_REQUIRES_ARM_NEON;
2984 for (uint32_t mz = 0; mz < 9; mz++) {
2985 for (uint32_t channels = 64; channels < 512; channels += 96) {
2986 DWConvMicrokernelTester()
2987 .cr(32)
2988 .kr(9)
2989 .channels(channels)
2990 .input_offset(592)
2991 .zero_index(mz)
Marat Dukhan50323b82022-01-11 00:12:01 -08002992 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x9__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07002993 }
2994 }
2995 }
2996#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
2997
2998
2999#if XNN_ARCH_ARM || XNN_ARCH_ARM64
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003000 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL16, c_eq_8) {
3001 TEST_REQUIRES_ARM_NEON;
3002 DWConvMicrokernelTester()
3003 .cr(8)
3004 .kr(25)
3005 .channels(8)
Marat Dukhan50323b82022-01-11 00:12:01 -08003006 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003007 }
3008
3009 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL16, c_div_8) {
3010 TEST_REQUIRES_ARM_NEON;
3011 for (uint32_t channels = 16; channels < 128; channels += 24) {
3012 DWConvMicrokernelTester()
3013 .cr(8)
3014 .kr(25)
3015 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08003016 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003017 }
3018 }
3019
3020 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL16, c_div_8_with_qmin) {
3021 TEST_REQUIRES_ARM_NEON;
3022 for (uint32_t channels = 16; channels < 128; channels += 24) {
3023 DWConvMicrokernelTester()
3024 .cr(8)
3025 .kr(25)
3026 .channels(channels)
3027 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003028 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003029 }
3030 }
3031
3032 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL16, c_div_8_with_qmax) {
3033 TEST_REQUIRES_ARM_NEON;
3034 for (uint32_t channels = 16; channels < 128; channels += 24) {
3035 DWConvMicrokernelTester()
3036 .cr(8)
3037 .kr(25)
3038 .channels(channels)
3039 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003040 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003041 }
3042 }
3043
3044 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL16, c_lt_8) {
3045 TEST_REQUIRES_ARM_NEON;
3046 for (uint32_t channels = 1; channels < 8; channels++) {
3047 DWConvMicrokernelTester()
3048 .cr(8)
3049 .kr(25)
3050 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08003051 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003052 }
3053 }
3054
3055 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL16, c_gt_8) {
3056 TEST_REQUIRES_ARM_NEON;
3057 for (uint32_t channels = 9; channels < 16; channels++) {
3058 DWConvMicrokernelTester()
3059 .cr(8)
3060 .kr(25)
3061 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08003062 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003063 }
3064 }
3065
3066 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL16, c_gt_8_with_qmin) {
3067 TEST_REQUIRES_ARM_NEON;
3068 for (uint32_t channels = 9; channels < 16; channels++) {
3069 DWConvMicrokernelTester()
3070 .cr(8)
3071 .kr(25)
3072 .channels(channels)
3073 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003074 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003075 }
3076 }
3077
3078 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL16, c_gt_8_with_qmax) {
3079 TEST_REQUIRES_ARM_NEON;
3080 for (uint32_t channels = 9; channels < 16; channels++) {
3081 DWConvMicrokernelTester()
3082 .cr(8)
3083 .kr(25)
3084 .channels(channels)
3085 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003086 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003087 }
3088 }
3089
3090 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL16, multipixel) {
3091 TEST_REQUIRES_ARM_NEON;
3092 for (size_t channels = 1; channels <= 40; channels += 7) {
3093 DWConvMicrokernelTester()
3094 .cr(8)
3095 .kr(25)
3096 .channels(channels)
3097 .width(3)
Marat Dukhan50323b82022-01-11 00:12:01 -08003098 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003099 }
3100 }
3101
3102 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL16, multipixel_with_step) {
3103 TEST_REQUIRES_ARM_NEON;
3104 for (size_t channels = 1; channels <= 40; channels += 7) {
3105 for (size_t step = 2; step <= 25; step++) {
3106 DWConvMicrokernelTester()
3107 .cr(8)
3108 .kr(25)
3109 .channels(channels)
3110 .width(3)
3111 .step(step)
Marat Dukhan50323b82022-01-11 00:12:01 -08003112 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003113 }
3114 }
3115 }
3116
3117 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL16, multipixel_with_output_stride) {
3118 TEST_REQUIRES_ARM_NEON;
3119 for (size_t channels = 1; channels <= 40; channels += 7) {
3120 DWConvMicrokernelTester()
3121 .cr(8)
3122 .kr(25)
3123 .channels(8)
3124 .width(5)
3125 .output_stride(43)
Marat Dukhan50323b82022-01-11 00:12:01 -08003126 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003127 }
3128 }
3129
3130 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL16, multipixel_with_qmin) {
3131 TEST_REQUIRES_ARM_NEON;
3132 for (size_t channels = 1; channels <= 40; channels += 7) {
3133 DWConvMicrokernelTester()
3134 .cr(8)
3135 .kr(25)
3136 .channels(channels)
3137 .width(3)
3138 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003139 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003140 }
3141 }
3142
3143 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL16, multipixel_with_qmax) {
3144 TEST_REQUIRES_ARM_NEON;
3145 for (size_t channels = 1; channels <= 40; channels += 7) {
3146 DWConvMicrokernelTester()
3147 .cr(8)
3148 .kr(25)
3149 .channels(channels)
3150 .width(3)
3151 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003152 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003153 }
3154 }
3155
3156 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL16, input_offset) {
3157 TEST_REQUIRES_ARM_NEON;
3158 for (uint32_t channels = 16; channels < 128; channels += 24) {
3159 DWConvMicrokernelTester()
3160 .cr(8)
3161 .kr(25)
3162 .channels(channels)
3163 .input_offset(176)
Marat Dukhan50323b82022-01-11 00:12:01 -08003164 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003165 }
3166 }
3167
3168 TEST(QS8_DWCONV_MINMAX_RNDNU_UP8X25__NEON_MUL16, zero) {
3169 TEST_REQUIRES_ARM_NEON;
3170 for (uint32_t mz = 0; mz < 25; mz++) {
3171 for (uint32_t channels = 16; channels < 128; channels += 24) {
3172 DWConvMicrokernelTester()
3173 .cr(8)
3174 .kr(25)
3175 .channels(channels)
3176 .input_offset(176)
3177 .zero_index(mz)
Marat Dukhan50323b82022-01-11 00:12:01 -08003178 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up8x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003179 }
3180 }
3181 }
3182#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
3183
3184
3185#if XNN_ARCH_ARM || XNN_ARCH_ARM64
3186 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL16, c_eq_16) {
3187 TEST_REQUIRES_ARM_NEON;
3188 DWConvMicrokernelTester()
3189 .cr(16)
3190 .kr(25)
3191 .channels(16)
Marat Dukhan50323b82022-01-11 00:12:01 -08003192 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003193 }
3194
3195 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL16, c_div_16) {
3196 TEST_REQUIRES_ARM_NEON;
3197 for (uint32_t channels = 32; channels < 256; channels += 48) {
3198 DWConvMicrokernelTester()
3199 .cr(16)
3200 .kr(25)
3201 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08003202 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003203 }
3204 }
3205
3206 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL16, c_div_16_with_qmin) {
3207 TEST_REQUIRES_ARM_NEON;
3208 for (uint32_t channels = 32; channels < 256; channels += 48) {
3209 DWConvMicrokernelTester()
3210 .cr(16)
3211 .kr(25)
3212 .channels(channels)
3213 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003214 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003215 }
3216 }
3217
3218 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL16, c_div_16_with_qmax) {
3219 TEST_REQUIRES_ARM_NEON;
3220 for (uint32_t channels = 32; channels < 256; channels += 48) {
3221 DWConvMicrokernelTester()
3222 .cr(16)
3223 .kr(25)
3224 .channels(channels)
3225 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003226 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003227 }
3228 }
3229
3230 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL16, c_lt_16) {
3231 TEST_REQUIRES_ARM_NEON;
3232 for (uint32_t channels = 1; channels < 16; channels++) {
3233 DWConvMicrokernelTester()
3234 .cr(16)
3235 .kr(25)
3236 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08003237 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003238 }
3239 }
3240
3241 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL16, c_gt_16) {
3242 TEST_REQUIRES_ARM_NEON;
3243 for (uint32_t channels = 17; channels < 32; channels++) {
3244 DWConvMicrokernelTester()
3245 .cr(16)
3246 .kr(25)
3247 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08003248 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003249 }
3250 }
3251
3252 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL16, c_gt_16_with_qmin) {
3253 TEST_REQUIRES_ARM_NEON;
3254 for (uint32_t channels = 17; channels < 32; channels++) {
3255 DWConvMicrokernelTester()
3256 .cr(16)
3257 .kr(25)
3258 .channels(channels)
3259 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003260 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003261 }
3262 }
3263
3264 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL16, c_gt_16_with_qmax) {
3265 TEST_REQUIRES_ARM_NEON;
3266 for (uint32_t channels = 17; channels < 32; channels++) {
3267 DWConvMicrokernelTester()
3268 .cr(16)
3269 .kr(25)
3270 .channels(channels)
3271 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003272 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003273 }
3274 }
3275
3276 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL16, multipixel) {
3277 TEST_REQUIRES_ARM_NEON;
3278 for (size_t channels = 1; channels <= 80; channels += 15) {
3279 DWConvMicrokernelTester()
3280 .cr(16)
3281 .kr(25)
3282 .channels(channels)
3283 .width(3)
Marat Dukhan50323b82022-01-11 00:12:01 -08003284 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003285 }
3286 }
3287
3288 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL16, multipixel_with_step) {
3289 TEST_REQUIRES_ARM_NEON;
3290 for (size_t channels = 1; channels <= 80; channels += 15) {
3291 for (size_t step = 2; step <= 25; step++) {
3292 DWConvMicrokernelTester()
3293 .cr(16)
3294 .kr(25)
3295 .channels(channels)
3296 .width(3)
3297 .step(step)
Marat Dukhan50323b82022-01-11 00:12:01 -08003298 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003299 }
3300 }
3301 }
3302
3303 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL16, multipixel_with_output_stride) {
3304 TEST_REQUIRES_ARM_NEON;
3305 for (size_t channels = 1; channels <= 80; channels += 15) {
3306 DWConvMicrokernelTester()
3307 .cr(16)
3308 .kr(25)
3309 .channels(16)
3310 .width(5)
3311 .output_stride(83)
Marat Dukhan50323b82022-01-11 00:12:01 -08003312 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003313 }
3314 }
3315
3316 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL16, multipixel_with_qmin) {
3317 TEST_REQUIRES_ARM_NEON;
3318 for (size_t channels = 1; channels <= 80; channels += 15) {
3319 DWConvMicrokernelTester()
3320 .cr(16)
3321 .kr(25)
3322 .channels(channels)
3323 .width(3)
3324 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003325 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003326 }
3327 }
3328
3329 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL16, multipixel_with_qmax) {
3330 TEST_REQUIRES_ARM_NEON;
3331 for (size_t channels = 1; channels <= 80; channels += 15) {
3332 DWConvMicrokernelTester()
3333 .cr(16)
3334 .kr(25)
3335 .channels(channels)
3336 .width(3)
3337 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003338 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003339 }
3340 }
3341
3342 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL16, input_offset) {
3343 TEST_REQUIRES_ARM_NEON;
3344 for (uint32_t channels = 32; channels < 256; channels += 48) {
3345 DWConvMicrokernelTester()
3346 .cr(16)
3347 .kr(25)
3348 .channels(channels)
3349 .input_offset(304)
Marat Dukhan50323b82022-01-11 00:12:01 -08003350 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003351 }
3352 }
3353
3354 TEST(QS8_DWCONV_MINMAX_RNDNU_UP16X25__NEON_MUL16, zero) {
3355 TEST_REQUIRES_ARM_NEON;
3356 for (uint32_t mz = 0; mz < 25; mz++) {
3357 for (uint32_t channels = 32; channels < 256; channels += 48) {
3358 DWConvMicrokernelTester()
3359 .cr(16)
3360 .kr(25)
3361 .channels(channels)
3362 .input_offset(304)
3363 .zero_index(mz)
Marat Dukhan50323b82022-01-11 00:12:01 -08003364 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up16x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07003365 }
3366 }
3367 }
3368#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003369
3370
3371#if XNN_ARCH_ARM || XNN_ARCH_ARM64
3372 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X25__NEON_MUL16, c_eq_24) {
3373 TEST_REQUIRES_ARM_NEON;
3374 DWConvMicrokernelTester()
3375 .cr(24)
3376 .kr(25)
3377 .channels(24)
Marat Dukhan50323b82022-01-11 00:12:01 -08003378 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003379 }
3380
3381 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X25__NEON_MUL16, c_div_24) {
3382 TEST_REQUIRES_ARM_NEON;
3383 for (uint32_t channels = 48; channels < 384; channels += 72) {
3384 DWConvMicrokernelTester()
3385 .cr(24)
3386 .kr(25)
3387 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08003388 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003389 }
3390 }
3391
3392 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X25__NEON_MUL16, c_div_24_with_qmin) {
3393 TEST_REQUIRES_ARM_NEON;
3394 for (uint32_t channels = 48; channels < 384; channels += 72) {
3395 DWConvMicrokernelTester()
3396 .cr(24)
3397 .kr(25)
3398 .channels(channels)
3399 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003400 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003401 }
3402 }
3403
3404 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X25__NEON_MUL16, c_div_24_with_qmax) {
3405 TEST_REQUIRES_ARM_NEON;
3406 for (uint32_t channels = 48; channels < 384; channels += 72) {
3407 DWConvMicrokernelTester()
3408 .cr(24)
3409 .kr(25)
3410 .channels(channels)
3411 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003412 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003413 }
3414 }
3415
3416 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X25__NEON_MUL16, c_lt_24) {
3417 TEST_REQUIRES_ARM_NEON;
3418 for (uint32_t channels = 1; channels < 24; channels++) {
3419 DWConvMicrokernelTester()
3420 .cr(24)
3421 .kr(25)
3422 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08003423 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003424 }
3425 }
3426
3427 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X25__NEON_MUL16, c_gt_24) {
3428 TEST_REQUIRES_ARM_NEON;
3429 for (uint32_t channels = 25; channels < 48; channels++) {
3430 DWConvMicrokernelTester()
3431 .cr(24)
3432 .kr(25)
3433 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08003434 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003435 }
3436 }
3437
3438 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X25__NEON_MUL16, c_gt_24_with_qmin) {
3439 TEST_REQUIRES_ARM_NEON;
3440 for (uint32_t channels = 25; channels < 48; channels++) {
3441 DWConvMicrokernelTester()
3442 .cr(24)
3443 .kr(25)
3444 .channels(channels)
3445 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003446 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003447 }
3448 }
3449
3450 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X25__NEON_MUL16, c_gt_24_with_qmax) {
3451 TEST_REQUIRES_ARM_NEON;
3452 for (uint32_t channels = 25; channels < 48; channels++) {
3453 DWConvMicrokernelTester()
3454 .cr(24)
3455 .kr(25)
3456 .channels(channels)
3457 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003458 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003459 }
3460 }
3461
3462 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X25__NEON_MUL16, multipixel) {
3463 TEST_REQUIRES_ARM_NEON;
3464 for (size_t channels = 1; channels <= 120; channels += 23) {
3465 DWConvMicrokernelTester()
3466 .cr(24)
3467 .kr(25)
3468 .channels(channels)
3469 .width(3)
Marat Dukhan50323b82022-01-11 00:12:01 -08003470 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003471 }
3472 }
3473
3474 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X25__NEON_MUL16, multipixel_with_step) {
3475 TEST_REQUIRES_ARM_NEON;
3476 for (size_t channels = 1; channels <= 120; channels += 23) {
3477 for (size_t step = 2; step <= 25; step++) {
3478 DWConvMicrokernelTester()
3479 .cr(24)
3480 .kr(25)
3481 .channels(channels)
3482 .width(3)
3483 .step(step)
Marat Dukhan50323b82022-01-11 00:12:01 -08003484 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003485 }
3486 }
3487 }
3488
3489 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X25__NEON_MUL16, multipixel_with_output_stride) {
3490 TEST_REQUIRES_ARM_NEON;
3491 for (size_t channels = 1; channels <= 120; channels += 23) {
3492 DWConvMicrokernelTester()
3493 .cr(24)
3494 .kr(25)
3495 .channels(24)
3496 .width(5)
3497 .output_stride(127)
Marat Dukhan50323b82022-01-11 00:12:01 -08003498 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003499 }
3500 }
3501
3502 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X25__NEON_MUL16, multipixel_with_qmin) {
3503 TEST_REQUIRES_ARM_NEON;
3504 for (size_t channels = 1; channels <= 120; channels += 23) {
3505 DWConvMicrokernelTester()
3506 .cr(24)
3507 .kr(25)
3508 .channels(channels)
3509 .width(3)
3510 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003511 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003512 }
3513 }
3514
3515 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X25__NEON_MUL16, multipixel_with_qmax) {
3516 TEST_REQUIRES_ARM_NEON;
3517 for (size_t channels = 1; channels <= 120; channels += 23) {
3518 DWConvMicrokernelTester()
3519 .cr(24)
3520 .kr(25)
3521 .channels(channels)
3522 .width(3)
3523 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003524 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003525 }
3526 }
3527
3528 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X25__NEON_MUL16, input_offset) {
3529 TEST_REQUIRES_ARM_NEON;
3530 for (uint32_t channels = 48; channels < 384; channels += 72) {
3531 DWConvMicrokernelTester()
3532 .cr(24)
3533 .kr(25)
3534 .channels(channels)
3535 .input_offset(464)
Marat Dukhan50323b82022-01-11 00:12:01 -08003536 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003537 }
3538 }
3539
3540 TEST(QS8_DWCONV_MINMAX_RNDNU_UP24X25__NEON_MUL16, zero) {
3541 TEST_REQUIRES_ARM_NEON;
3542 for (uint32_t mz = 0; mz < 25; mz++) {
3543 for (uint32_t channels = 48; channels < 384; channels += 72) {
3544 DWConvMicrokernelTester()
3545 .cr(24)
3546 .kr(25)
3547 .channels(channels)
3548 .input_offset(464)
3549 .zero_index(mz)
Marat Dukhan50323b82022-01-11 00:12:01 -08003550 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up24x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003551 }
3552 }
3553 }
3554#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
3555
3556
3557#if XNN_ARCH_ARM || XNN_ARCH_ARM64
3558 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X25__NEON_MUL16, c_eq_32) {
3559 TEST_REQUIRES_ARM_NEON;
3560 DWConvMicrokernelTester()
3561 .cr(32)
3562 .kr(25)
3563 .channels(32)
Marat Dukhan50323b82022-01-11 00:12:01 -08003564 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003565 }
3566
3567 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X25__NEON_MUL16, c_div_32) {
3568 TEST_REQUIRES_ARM_NEON;
3569 for (uint32_t channels = 64; channels < 512; channels += 96) {
3570 DWConvMicrokernelTester()
3571 .cr(32)
3572 .kr(25)
3573 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08003574 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003575 }
3576 }
3577
3578 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X25__NEON_MUL16, c_div_32_with_qmin) {
3579 TEST_REQUIRES_ARM_NEON;
3580 for (uint32_t channels = 64; channels < 512; channels += 96) {
3581 DWConvMicrokernelTester()
3582 .cr(32)
3583 .kr(25)
3584 .channels(channels)
3585 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003586 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003587 }
3588 }
3589
3590 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X25__NEON_MUL16, c_div_32_with_qmax) {
3591 TEST_REQUIRES_ARM_NEON;
3592 for (uint32_t channels = 64; channels < 512; channels += 96) {
3593 DWConvMicrokernelTester()
3594 .cr(32)
3595 .kr(25)
3596 .channels(channels)
3597 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003598 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003599 }
3600 }
3601
3602 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X25__NEON_MUL16, c_lt_32) {
3603 TEST_REQUIRES_ARM_NEON;
3604 for (uint32_t channels = 1; channels < 32; channels++) {
3605 DWConvMicrokernelTester()
3606 .cr(32)
3607 .kr(25)
3608 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08003609 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003610 }
3611 }
3612
3613 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X25__NEON_MUL16, c_gt_32) {
3614 TEST_REQUIRES_ARM_NEON;
3615 for (uint32_t channels = 33; channels < 64; channels++) {
3616 DWConvMicrokernelTester()
3617 .cr(32)
3618 .kr(25)
3619 .channels(channels)
Marat Dukhan50323b82022-01-11 00:12:01 -08003620 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003621 }
3622 }
3623
3624 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X25__NEON_MUL16, c_gt_32_with_qmin) {
3625 TEST_REQUIRES_ARM_NEON;
3626 for (uint32_t channels = 33; channels < 64; channels++) {
3627 DWConvMicrokernelTester()
3628 .cr(32)
3629 .kr(25)
3630 .channels(channels)
3631 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003632 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003633 }
3634 }
3635
3636 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X25__NEON_MUL16, c_gt_32_with_qmax) {
3637 TEST_REQUIRES_ARM_NEON;
3638 for (uint32_t channels = 33; channels < 64; channels++) {
3639 DWConvMicrokernelTester()
3640 .cr(32)
3641 .kr(25)
3642 .channels(channels)
3643 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003644 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003645 }
3646 }
3647
3648 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X25__NEON_MUL16, multipixel) {
3649 TEST_REQUIRES_ARM_NEON;
3650 for (size_t channels = 1; channels <= 160; channels += 31) {
3651 DWConvMicrokernelTester()
3652 .cr(32)
3653 .kr(25)
3654 .channels(channels)
3655 .width(3)
Marat Dukhan50323b82022-01-11 00:12:01 -08003656 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003657 }
3658 }
3659
3660 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X25__NEON_MUL16, multipixel_with_step) {
3661 TEST_REQUIRES_ARM_NEON;
3662 for (size_t channels = 1; channels <= 160; channels += 31) {
3663 for (size_t step = 2; step <= 25; step++) {
3664 DWConvMicrokernelTester()
3665 .cr(32)
3666 .kr(25)
3667 .channels(channels)
3668 .width(3)
3669 .step(step)
Marat Dukhan50323b82022-01-11 00:12:01 -08003670 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003671 }
3672 }
3673 }
3674
3675 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X25__NEON_MUL16, multipixel_with_output_stride) {
3676 TEST_REQUIRES_ARM_NEON;
3677 for (size_t channels = 1; channels <= 160; channels += 31) {
3678 DWConvMicrokernelTester()
3679 .cr(32)
3680 .kr(25)
3681 .channels(32)
3682 .width(5)
3683 .output_stride(163)
Marat Dukhan50323b82022-01-11 00:12:01 -08003684 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003685 }
3686 }
3687
3688 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X25__NEON_MUL16, multipixel_with_qmin) {
3689 TEST_REQUIRES_ARM_NEON;
3690 for (size_t channels = 1; channels <= 160; channels += 31) {
3691 DWConvMicrokernelTester()
3692 .cr(32)
3693 .kr(25)
3694 .channels(channels)
3695 .width(3)
3696 .qmin(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003697 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003698 }
3699 }
3700
3701 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X25__NEON_MUL16, multipixel_with_qmax) {
3702 TEST_REQUIRES_ARM_NEON;
3703 for (size_t channels = 1; channels <= 160; channels += 31) {
3704 DWConvMicrokernelTester()
3705 .cr(32)
3706 .kr(25)
3707 .channels(channels)
3708 .width(3)
3709 .qmax(128)
Marat Dukhan50323b82022-01-11 00:12:01 -08003710 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003711 }
3712 }
3713
3714 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X25__NEON_MUL16, input_offset) {
3715 TEST_REQUIRES_ARM_NEON;
3716 for (uint32_t channels = 64; channels < 512; channels += 96) {
3717 DWConvMicrokernelTester()
3718 .cr(32)
3719 .kr(25)
3720 .channels(channels)
3721 .input_offset(592)
Marat Dukhan50323b82022-01-11 00:12:01 -08003722 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003723 }
3724 }
3725
3726 TEST(QS8_DWCONV_MINMAX_RNDNU_UP32X25__NEON_MUL16, zero) {
3727 TEST_REQUIRES_ARM_NEON;
3728 for (uint32_t mz = 0; mz < 25; mz++) {
3729 for (uint32_t channels = 64; channels < 512; channels += 96) {
3730 DWConvMicrokernelTester()
3731 .cr(32)
3732 .kr(25)
3733 .channels(channels)
3734 .input_offset(592)
3735 .zero_index(mz)
Marat Dukhan50323b82022-01-11 00:12:01 -08003736 .Test(xnn_qs8_dwconv_minmax_rndnu_ukernel_up32x25__neon_mul16, xnn_init_qs8_conv_minmax_rndnu_neon_params, xnn_qs8_requantize_rndnu);
Frank Barchard2aa2e2a2021-09-16 14:59:13 -07003737 }
3738 }
3739 }
3740#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64