Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1 | // Copyright 2019 Google LLC |
| 2 | // |
| 3 | // This source code is licensed under the BSD-style license found in the |
| 4 | // LICENSE file in the root directory of this source tree. |
| 5 | // |
| 6 | // Auto-generated file. Do not edit! |
| 7 | // Specification: test/qs8-vaddc-minmax.yaml |
| 8 | // Generator: tools/generate-vbinary-test.py |
| 9 | |
| 10 | |
| 11 | #include <gtest/gtest.h> |
| 12 | |
| 13 | #include <xnnpack/common.h> |
| 14 | #include <xnnpack/isa-checks.h> |
| 15 | |
Marat Dukhan | 87bd511 | 2021-08-02 11:43:53 -0700 | [diff] [blame] | 16 | #include <xnnpack/params-init.h> |
Marat Dukhan | 6428725 | 2021-09-07 16:20:03 -0700 | [diff] [blame] | 17 | #include <xnnpack/vaddsub.h> |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 18 | #include "vaddc-microkernel-tester.h" |
| 19 | |
| 20 | |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 21 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 22 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X8, batch_eq_8) { |
| 23 | TEST_REQUIRES_ARM_NEON; |
| 24 | VAddCMicrokernelTester() |
| 25 | .batch_size(8) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 26 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x8, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 27 | } |
| 28 | |
| 29 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X8, batch_div_8) { |
| 30 | TEST_REQUIRES_ARM_NEON; |
| 31 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 32 | VAddCMicrokernelTester() |
| 33 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 34 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x8, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 35 | } |
| 36 | } |
| 37 | |
| 38 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X8, batch_lt_8) { |
| 39 | TEST_REQUIRES_ARM_NEON; |
| 40 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 41 | VAddCMicrokernelTester() |
| 42 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 43 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x8, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 44 | } |
| 45 | } |
| 46 | |
| 47 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X8, batch_gt_8) { |
| 48 | TEST_REQUIRES_ARM_NEON; |
| 49 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 50 | VAddCMicrokernelTester() |
| 51 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 52 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x8, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 53 | } |
| 54 | } |
| 55 | |
| 56 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X8, inplace) { |
| 57 | TEST_REQUIRES_ARM_NEON; |
| 58 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 59 | VAddCMicrokernelTester() |
| 60 | .batch_size(batch_size) |
| 61 | .inplace(true) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 62 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x8, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 63 | } |
| 64 | } |
| 65 | |
| 66 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X8, a_zero_point) { |
| 67 | TEST_REQUIRES_ARM_NEON; |
| 68 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 69 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 70 | VAddCMicrokernelTester() |
| 71 | .batch_size(batch_size) |
| 72 | .a_zero_point(a_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 73 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x8, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 74 | } |
| 75 | } |
| 76 | } |
| 77 | |
| 78 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X8, b_zero_point) { |
| 79 | TEST_REQUIRES_ARM_NEON; |
| 80 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 81 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 82 | VAddCMicrokernelTester() |
| 83 | .batch_size(batch_size) |
| 84 | .b_zero_point(b_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 85 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x8, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 86 | } |
| 87 | } |
| 88 | } |
| 89 | |
| 90 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X8, y_zero_point) { |
| 91 | TEST_REQUIRES_ARM_NEON; |
| 92 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 93 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 94 | VAddCMicrokernelTester() |
| 95 | .batch_size(batch_size) |
| 96 | .y_zero_point(y_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 97 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x8, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 98 | } |
| 99 | } |
| 100 | } |
| 101 | |
| 102 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X8, a_scale) { |
| 103 | TEST_REQUIRES_ARM_NEON; |
| 104 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 105 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 106 | VAddCMicrokernelTester() |
| 107 | .batch_size(batch_size) |
| 108 | .a_scale(a_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 109 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x8, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 110 | } |
| 111 | } |
| 112 | } |
| 113 | |
| 114 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X8, b_scale) { |
| 115 | TEST_REQUIRES_ARM_NEON; |
| 116 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 117 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 118 | VAddCMicrokernelTester() |
| 119 | .batch_size(batch_size) |
| 120 | .b_scale(b_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 121 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x8, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 122 | } |
| 123 | } |
| 124 | } |
| 125 | |
| 126 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X8, y_scale) { |
| 127 | TEST_REQUIRES_ARM_NEON; |
| 128 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 129 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 130 | VAddCMicrokernelTester() |
| 131 | .batch_size(batch_size) |
| 132 | .y_scale(y_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 133 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x8, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 134 | } |
| 135 | } |
| 136 | } |
| 137 | |
| 138 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X8, qmin) { |
| 139 | TEST_REQUIRES_ARM_NEON; |
| 140 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 141 | VAddCMicrokernelTester() |
| 142 | .batch_size(batch_size) |
| 143 | .qmin(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 144 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x8, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 145 | } |
| 146 | } |
| 147 | |
| 148 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X8, qmax) { |
| 149 | TEST_REQUIRES_ARM_NEON; |
| 150 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 151 | VAddCMicrokernelTester() |
| 152 | .batch_size(batch_size) |
| 153 | .qmax(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 154 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x8, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 155 | } |
| 156 | } |
| 157 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 158 | |
| 159 | |
| 160 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 161 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X16, batch_eq_16) { |
| 162 | TEST_REQUIRES_ARM_NEON; |
| 163 | VAddCMicrokernelTester() |
| 164 | .batch_size(16) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 165 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x16, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 166 | } |
| 167 | |
| 168 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X16, batch_div_16) { |
| 169 | TEST_REQUIRES_ARM_NEON; |
| 170 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 171 | VAddCMicrokernelTester() |
| 172 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 173 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x16, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 174 | } |
| 175 | } |
| 176 | |
| 177 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X16, batch_lt_16) { |
| 178 | TEST_REQUIRES_ARM_NEON; |
| 179 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 180 | VAddCMicrokernelTester() |
| 181 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 182 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x16, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 183 | } |
| 184 | } |
| 185 | |
| 186 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X16, batch_gt_16) { |
| 187 | TEST_REQUIRES_ARM_NEON; |
| 188 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 189 | VAddCMicrokernelTester() |
| 190 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 191 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x16, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 192 | } |
| 193 | } |
| 194 | |
| 195 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X16, inplace) { |
| 196 | TEST_REQUIRES_ARM_NEON; |
| 197 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 198 | VAddCMicrokernelTester() |
| 199 | .batch_size(batch_size) |
| 200 | .inplace(true) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 201 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x16, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 202 | } |
| 203 | } |
| 204 | |
| 205 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X16, a_zero_point) { |
| 206 | TEST_REQUIRES_ARM_NEON; |
| 207 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 208 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 209 | VAddCMicrokernelTester() |
| 210 | .batch_size(batch_size) |
| 211 | .a_zero_point(a_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 212 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x16, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 213 | } |
| 214 | } |
| 215 | } |
| 216 | |
| 217 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X16, b_zero_point) { |
| 218 | TEST_REQUIRES_ARM_NEON; |
| 219 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 220 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 221 | VAddCMicrokernelTester() |
| 222 | .batch_size(batch_size) |
| 223 | .b_zero_point(b_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 224 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x16, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 225 | } |
| 226 | } |
| 227 | } |
| 228 | |
| 229 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X16, y_zero_point) { |
| 230 | TEST_REQUIRES_ARM_NEON; |
| 231 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 232 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 233 | VAddCMicrokernelTester() |
| 234 | .batch_size(batch_size) |
| 235 | .y_zero_point(y_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 236 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x16, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 237 | } |
| 238 | } |
| 239 | } |
| 240 | |
| 241 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X16, a_scale) { |
| 242 | TEST_REQUIRES_ARM_NEON; |
| 243 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 244 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 245 | VAddCMicrokernelTester() |
| 246 | .batch_size(batch_size) |
| 247 | .a_scale(a_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 248 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x16, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 249 | } |
| 250 | } |
| 251 | } |
| 252 | |
| 253 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X16, b_scale) { |
| 254 | TEST_REQUIRES_ARM_NEON; |
| 255 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 256 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 257 | VAddCMicrokernelTester() |
| 258 | .batch_size(batch_size) |
| 259 | .b_scale(b_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 260 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x16, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 261 | } |
| 262 | } |
| 263 | } |
| 264 | |
| 265 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X16, y_scale) { |
| 266 | TEST_REQUIRES_ARM_NEON; |
| 267 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 268 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 269 | VAddCMicrokernelTester() |
| 270 | .batch_size(batch_size) |
| 271 | .y_scale(y_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 272 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x16, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 273 | } |
| 274 | } |
| 275 | } |
| 276 | |
| 277 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X16, qmin) { |
| 278 | TEST_REQUIRES_ARM_NEON; |
| 279 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 280 | VAddCMicrokernelTester() |
| 281 | .batch_size(batch_size) |
| 282 | .qmin(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 283 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x16, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 284 | } |
| 285 | } |
| 286 | |
| 287 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X16, qmax) { |
| 288 | TEST_REQUIRES_ARM_NEON; |
| 289 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 290 | VAddCMicrokernelTester() |
| 291 | .batch_size(batch_size) |
| 292 | .qmax(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 293 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x16, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 294 | } |
| 295 | } |
| 296 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 297 | |
| 298 | |
| 299 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 300 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X24, batch_eq_24) { |
| 301 | TEST_REQUIRES_ARM_NEON; |
| 302 | VAddCMicrokernelTester() |
| 303 | .batch_size(24) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 304 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x24, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 305 | } |
| 306 | |
| 307 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X24, batch_div_24) { |
| 308 | TEST_REQUIRES_ARM_NEON; |
| 309 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 310 | VAddCMicrokernelTester() |
| 311 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 312 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x24, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 313 | } |
| 314 | } |
| 315 | |
| 316 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X24, batch_lt_24) { |
| 317 | TEST_REQUIRES_ARM_NEON; |
| 318 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 319 | VAddCMicrokernelTester() |
| 320 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 321 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x24, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 322 | } |
| 323 | } |
| 324 | |
| 325 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X24, batch_gt_24) { |
| 326 | TEST_REQUIRES_ARM_NEON; |
| 327 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 328 | VAddCMicrokernelTester() |
| 329 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 330 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x24, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 331 | } |
| 332 | } |
| 333 | |
| 334 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X24, inplace) { |
| 335 | TEST_REQUIRES_ARM_NEON; |
| 336 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 337 | VAddCMicrokernelTester() |
| 338 | .batch_size(batch_size) |
| 339 | .inplace(true) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 340 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x24, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 341 | } |
| 342 | } |
| 343 | |
| 344 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X24, a_zero_point) { |
| 345 | TEST_REQUIRES_ARM_NEON; |
| 346 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 347 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 348 | VAddCMicrokernelTester() |
| 349 | .batch_size(batch_size) |
| 350 | .a_zero_point(a_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 351 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x24, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 352 | } |
| 353 | } |
| 354 | } |
| 355 | |
| 356 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X24, b_zero_point) { |
| 357 | TEST_REQUIRES_ARM_NEON; |
| 358 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 359 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 360 | VAddCMicrokernelTester() |
| 361 | .batch_size(batch_size) |
| 362 | .b_zero_point(b_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 363 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x24, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 364 | } |
| 365 | } |
| 366 | } |
| 367 | |
| 368 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X24, y_zero_point) { |
| 369 | TEST_REQUIRES_ARM_NEON; |
| 370 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 371 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 372 | VAddCMicrokernelTester() |
| 373 | .batch_size(batch_size) |
| 374 | .y_zero_point(y_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 375 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x24, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 376 | } |
| 377 | } |
| 378 | } |
| 379 | |
| 380 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X24, a_scale) { |
| 381 | TEST_REQUIRES_ARM_NEON; |
| 382 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 383 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 384 | VAddCMicrokernelTester() |
| 385 | .batch_size(batch_size) |
| 386 | .a_scale(a_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 387 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x24, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 388 | } |
| 389 | } |
| 390 | } |
| 391 | |
| 392 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X24, b_scale) { |
| 393 | TEST_REQUIRES_ARM_NEON; |
| 394 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 395 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 396 | VAddCMicrokernelTester() |
| 397 | .batch_size(batch_size) |
| 398 | .b_scale(b_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 399 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x24, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 400 | } |
| 401 | } |
| 402 | } |
| 403 | |
| 404 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X24, y_scale) { |
| 405 | TEST_REQUIRES_ARM_NEON; |
| 406 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 407 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 408 | VAddCMicrokernelTester() |
| 409 | .batch_size(batch_size) |
| 410 | .y_scale(y_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 411 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x24, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 412 | } |
| 413 | } |
| 414 | } |
| 415 | |
| 416 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X24, qmin) { |
| 417 | TEST_REQUIRES_ARM_NEON; |
| 418 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 419 | VAddCMicrokernelTester() |
| 420 | .batch_size(batch_size) |
| 421 | .qmin(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 422 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x24, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 423 | } |
| 424 | } |
| 425 | |
| 426 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X24, qmax) { |
| 427 | TEST_REQUIRES_ARM_NEON; |
| 428 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 429 | VAddCMicrokernelTester() |
| 430 | .batch_size(batch_size) |
| 431 | .qmax(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 432 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x24, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 433 | } |
| 434 | } |
| 435 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 436 | |
| 437 | |
| 438 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 439 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X32, batch_eq_32) { |
| 440 | TEST_REQUIRES_ARM_NEON; |
| 441 | VAddCMicrokernelTester() |
| 442 | .batch_size(32) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 443 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x32, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 444 | } |
| 445 | |
| 446 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X32, batch_div_32) { |
| 447 | TEST_REQUIRES_ARM_NEON; |
| 448 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 449 | VAddCMicrokernelTester() |
| 450 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 451 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x32, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 452 | } |
| 453 | } |
| 454 | |
| 455 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X32, batch_lt_32) { |
| 456 | TEST_REQUIRES_ARM_NEON; |
| 457 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 458 | VAddCMicrokernelTester() |
| 459 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 460 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x32, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 461 | } |
| 462 | } |
| 463 | |
| 464 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X32, batch_gt_32) { |
| 465 | TEST_REQUIRES_ARM_NEON; |
| 466 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 467 | VAddCMicrokernelTester() |
| 468 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 469 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x32, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 470 | } |
| 471 | } |
| 472 | |
| 473 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X32, inplace) { |
| 474 | TEST_REQUIRES_ARM_NEON; |
| 475 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 476 | VAddCMicrokernelTester() |
| 477 | .batch_size(batch_size) |
| 478 | .inplace(true) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 479 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x32, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 480 | } |
| 481 | } |
| 482 | |
| 483 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X32, a_zero_point) { |
| 484 | TEST_REQUIRES_ARM_NEON; |
| 485 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 486 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 487 | VAddCMicrokernelTester() |
| 488 | .batch_size(batch_size) |
| 489 | .a_zero_point(a_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 490 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x32, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 491 | } |
| 492 | } |
| 493 | } |
| 494 | |
| 495 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X32, b_zero_point) { |
| 496 | TEST_REQUIRES_ARM_NEON; |
| 497 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 498 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 499 | VAddCMicrokernelTester() |
| 500 | .batch_size(batch_size) |
| 501 | .b_zero_point(b_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 502 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x32, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 503 | } |
| 504 | } |
| 505 | } |
| 506 | |
| 507 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X32, y_zero_point) { |
| 508 | TEST_REQUIRES_ARM_NEON; |
| 509 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 510 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 511 | VAddCMicrokernelTester() |
| 512 | .batch_size(batch_size) |
| 513 | .y_zero_point(y_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 514 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x32, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 515 | } |
| 516 | } |
| 517 | } |
| 518 | |
| 519 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X32, a_scale) { |
| 520 | TEST_REQUIRES_ARM_NEON; |
| 521 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 522 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 523 | VAddCMicrokernelTester() |
| 524 | .batch_size(batch_size) |
| 525 | .a_scale(a_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 526 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x32, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 527 | } |
| 528 | } |
| 529 | } |
| 530 | |
| 531 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X32, b_scale) { |
| 532 | TEST_REQUIRES_ARM_NEON; |
| 533 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 534 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 535 | VAddCMicrokernelTester() |
| 536 | .batch_size(batch_size) |
| 537 | .b_scale(b_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 538 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x32, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 539 | } |
| 540 | } |
| 541 | } |
| 542 | |
| 543 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X32, y_scale) { |
| 544 | TEST_REQUIRES_ARM_NEON; |
| 545 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 546 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 547 | VAddCMicrokernelTester() |
| 548 | .batch_size(batch_size) |
| 549 | .y_scale(y_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 550 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x32, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 551 | } |
| 552 | } |
| 553 | } |
| 554 | |
| 555 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X32, qmin) { |
| 556 | TEST_REQUIRES_ARM_NEON; |
| 557 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 558 | VAddCMicrokernelTester() |
| 559 | .batch_size(batch_size) |
| 560 | .qmin(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 561 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x32, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 562 | } |
| 563 | } |
| 564 | |
| 565 | TEST(QS8_VADDC_MINMAX__NEON_LD64_X32, qmax) { |
| 566 | TEST_REQUIRES_ARM_NEON; |
| 567 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 568 | VAddCMicrokernelTester() |
| 569 | .batch_size(batch_size) |
| 570 | .qmax(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 571 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld64_x32, xnn_init_qs8_add_minmax_neon_params); |
Marat Dukhan | ba7b279 | 2020-09-02 14:26:45 -0700 | [diff] [blame] | 572 | } |
| 573 | } |
| 574 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 575 | |
| 576 | |
Marat Dukhan | eb3cff3 | 2021-07-30 11:35:27 -0700 | [diff] [blame] | 577 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 578 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X16, batch_eq_16) { |
| 579 | TEST_REQUIRES_ARM_NEON; |
| 580 | VAddCMicrokernelTester() |
| 581 | .batch_size(16) |
| 582 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x16, xnn_init_qs8_add_minmax_neon_params); |
| 583 | } |
| 584 | |
| 585 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X16, batch_div_16) { |
| 586 | TEST_REQUIRES_ARM_NEON; |
| 587 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 588 | VAddCMicrokernelTester() |
| 589 | .batch_size(batch_size) |
| 590 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x16, xnn_init_qs8_add_minmax_neon_params); |
| 591 | } |
| 592 | } |
| 593 | |
| 594 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X16, batch_lt_16) { |
| 595 | TEST_REQUIRES_ARM_NEON; |
| 596 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 597 | VAddCMicrokernelTester() |
| 598 | .batch_size(batch_size) |
| 599 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x16, xnn_init_qs8_add_minmax_neon_params); |
| 600 | } |
| 601 | } |
| 602 | |
| 603 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X16, batch_gt_16) { |
| 604 | TEST_REQUIRES_ARM_NEON; |
| 605 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 606 | VAddCMicrokernelTester() |
| 607 | .batch_size(batch_size) |
| 608 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x16, xnn_init_qs8_add_minmax_neon_params); |
| 609 | } |
| 610 | } |
| 611 | |
| 612 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X16, inplace) { |
| 613 | TEST_REQUIRES_ARM_NEON; |
| 614 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 615 | VAddCMicrokernelTester() |
| 616 | .batch_size(batch_size) |
| 617 | .inplace(true) |
| 618 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x16, xnn_init_qs8_add_minmax_neon_params); |
| 619 | } |
| 620 | } |
| 621 | |
| 622 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X16, a_zero_point) { |
| 623 | TEST_REQUIRES_ARM_NEON; |
| 624 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 625 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 626 | VAddCMicrokernelTester() |
| 627 | .batch_size(batch_size) |
| 628 | .a_zero_point(a_zero_point) |
| 629 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x16, xnn_init_qs8_add_minmax_neon_params); |
| 630 | } |
| 631 | } |
| 632 | } |
| 633 | |
| 634 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X16, b_zero_point) { |
| 635 | TEST_REQUIRES_ARM_NEON; |
| 636 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 637 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 638 | VAddCMicrokernelTester() |
| 639 | .batch_size(batch_size) |
| 640 | .b_zero_point(b_zero_point) |
| 641 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x16, xnn_init_qs8_add_minmax_neon_params); |
| 642 | } |
| 643 | } |
| 644 | } |
| 645 | |
| 646 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X16, y_zero_point) { |
| 647 | TEST_REQUIRES_ARM_NEON; |
| 648 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 649 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 650 | VAddCMicrokernelTester() |
| 651 | .batch_size(batch_size) |
| 652 | .y_zero_point(y_zero_point) |
| 653 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x16, xnn_init_qs8_add_minmax_neon_params); |
| 654 | } |
| 655 | } |
| 656 | } |
| 657 | |
| 658 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X16, a_scale) { |
| 659 | TEST_REQUIRES_ARM_NEON; |
| 660 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 661 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 662 | VAddCMicrokernelTester() |
| 663 | .batch_size(batch_size) |
| 664 | .a_scale(a_scale) |
| 665 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x16, xnn_init_qs8_add_minmax_neon_params); |
| 666 | } |
| 667 | } |
| 668 | } |
| 669 | |
| 670 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X16, b_scale) { |
| 671 | TEST_REQUIRES_ARM_NEON; |
| 672 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 673 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 674 | VAddCMicrokernelTester() |
| 675 | .batch_size(batch_size) |
| 676 | .b_scale(b_scale) |
| 677 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x16, xnn_init_qs8_add_minmax_neon_params); |
| 678 | } |
| 679 | } |
| 680 | } |
| 681 | |
| 682 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X16, y_scale) { |
| 683 | TEST_REQUIRES_ARM_NEON; |
| 684 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 685 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 686 | VAddCMicrokernelTester() |
| 687 | .batch_size(batch_size) |
| 688 | .y_scale(y_scale) |
| 689 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x16, xnn_init_qs8_add_minmax_neon_params); |
| 690 | } |
| 691 | } |
| 692 | } |
| 693 | |
| 694 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X16, qmin) { |
| 695 | TEST_REQUIRES_ARM_NEON; |
| 696 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 697 | VAddCMicrokernelTester() |
| 698 | .batch_size(batch_size) |
| 699 | .qmin(128) |
| 700 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x16, xnn_init_qs8_add_minmax_neon_params); |
| 701 | } |
| 702 | } |
| 703 | |
| 704 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X16, qmax) { |
| 705 | TEST_REQUIRES_ARM_NEON; |
| 706 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 707 | VAddCMicrokernelTester() |
| 708 | .batch_size(batch_size) |
| 709 | .qmax(128) |
| 710 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x16, xnn_init_qs8_add_minmax_neon_params); |
| 711 | } |
| 712 | } |
| 713 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 714 | |
| 715 | |
| 716 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 717 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X32, batch_eq_32) { |
| 718 | TEST_REQUIRES_ARM_NEON; |
| 719 | VAddCMicrokernelTester() |
| 720 | .batch_size(32) |
| 721 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x32, xnn_init_qs8_add_minmax_neon_params); |
| 722 | } |
| 723 | |
| 724 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X32, batch_div_32) { |
| 725 | TEST_REQUIRES_ARM_NEON; |
| 726 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 727 | VAddCMicrokernelTester() |
| 728 | .batch_size(batch_size) |
| 729 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x32, xnn_init_qs8_add_minmax_neon_params); |
| 730 | } |
| 731 | } |
| 732 | |
| 733 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X32, batch_lt_32) { |
| 734 | TEST_REQUIRES_ARM_NEON; |
| 735 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 736 | VAddCMicrokernelTester() |
| 737 | .batch_size(batch_size) |
| 738 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x32, xnn_init_qs8_add_minmax_neon_params); |
| 739 | } |
| 740 | } |
| 741 | |
| 742 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X32, batch_gt_32) { |
| 743 | TEST_REQUIRES_ARM_NEON; |
| 744 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 745 | VAddCMicrokernelTester() |
| 746 | .batch_size(batch_size) |
| 747 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x32, xnn_init_qs8_add_minmax_neon_params); |
| 748 | } |
| 749 | } |
| 750 | |
| 751 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X32, inplace) { |
| 752 | TEST_REQUIRES_ARM_NEON; |
| 753 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 754 | VAddCMicrokernelTester() |
| 755 | .batch_size(batch_size) |
| 756 | .inplace(true) |
| 757 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x32, xnn_init_qs8_add_minmax_neon_params); |
| 758 | } |
| 759 | } |
| 760 | |
| 761 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X32, a_zero_point) { |
| 762 | TEST_REQUIRES_ARM_NEON; |
| 763 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 764 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 765 | VAddCMicrokernelTester() |
| 766 | .batch_size(batch_size) |
| 767 | .a_zero_point(a_zero_point) |
| 768 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x32, xnn_init_qs8_add_minmax_neon_params); |
| 769 | } |
| 770 | } |
| 771 | } |
| 772 | |
| 773 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X32, b_zero_point) { |
| 774 | TEST_REQUIRES_ARM_NEON; |
| 775 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 776 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 777 | VAddCMicrokernelTester() |
| 778 | .batch_size(batch_size) |
| 779 | .b_zero_point(b_zero_point) |
| 780 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x32, xnn_init_qs8_add_minmax_neon_params); |
| 781 | } |
| 782 | } |
| 783 | } |
| 784 | |
| 785 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X32, y_zero_point) { |
| 786 | TEST_REQUIRES_ARM_NEON; |
| 787 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 788 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 789 | VAddCMicrokernelTester() |
| 790 | .batch_size(batch_size) |
| 791 | .y_zero_point(y_zero_point) |
| 792 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x32, xnn_init_qs8_add_minmax_neon_params); |
| 793 | } |
| 794 | } |
| 795 | } |
| 796 | |
| 797 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X32, a_scale) { |
| 798 | TEST_REQUIRES_ARM_NEON; |
| 799 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 800 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 801 | VAddCMicrokernelTester() |
| 802 | .batch_size(batch_size) |
| 803 | .a_scale(a_scale) |
| 804 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x32, xnn_init_qs8_add_minmax_neon_params); |
| 805 | } |
| 806 | } |
| 807 | } |
| 808 | |
| 809 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X32, b_scale) { |
| 810 | TEST_REQUIRES_ARM_NEON; |
| 811 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 812 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 813 | VAddCMicrokernelTester() |
| 814 | .batch_size(batch_size) |
| 815 | .b_scale(b_scale) |
| 816 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x32, xnn_init_qs8_add_minmax_neon_params); |
| 817 | } |
| 818 | } |
| 819 | } |
| 820 | |
| 821 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X32, y_scale) { |
| 822 | TEST_REQUIRES_ARM_NEON; |
| 823 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 824 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 825 | VAddCMicrokernelTester() |
| 826 | .batch_size(batch_size) |
| 827 | .y_scale(y_scale) |
| 828 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x32, xnn_init_qs8_add_minmax_neon_params); |
| 829 | } |
| 830 | } |
| 831 | } |
| 832 | |
| 833 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X32, qmin) { |
| 834 | TEST_REQUIRES_ARM_NEON; |
| 835 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 836 | VAddCMicrokernelTester() |
| 837 | .batch_size(batch_size) |
| 838 | .qmin(128) |
| 839 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x32, xnn_init_qs8_add_minmax_neon_params); |
| 840 | } |
| 841 | } |
| 842 | |
| 843 | TEST(QS8_VADDC_MINMAX__NEON_LD128_X32, qmax) { |
| 844 | TEST_REQUIRES_ARM_NEON; |
| 845 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 846 | VAddCMicrokernelTester() |
| 847 | .batch_size(batch_size) |
| 848 | .qmax(128) |
| 849 | .Test(xnn_qs8_vaddc_minmax_ukernel__neon_ld128_x32, xnn_init_qs8_add_minmax_neon_params); |
| 850 | } |
| 851 | } |
| 852 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 853 | |
| 854 | |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 855 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 856 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X8, batch_eq_8) { |
| 857 | TEST_REQUIRES_X86_SSE2; |
| 858 | VAddCMicrokernelTester() |
| 859 | .batch_size(8) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 860 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 861 | } |
| 862 | |
| 863 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X8, batch_div_8) { |
| 864 | TEST_REQUIRES_X86_SSE2; |
| 865 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 866 | VAddCMicrokernelTester() |
| 867 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 868 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 869 | } |
| 870 | } |
| 871 | |
| 872 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X8, batch_lt_8) { |
| 873 | TEST_REQUIRES_X86_SSE2; |
| 874 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 875 | VAddCMicrokernelTester() |
| 876 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 877 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 878 | } |
| 879 | } |
| 880 | |
| 881 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X8, batch_gt_8) { |
| 882 | TEST_REQUIRES_X86_SSE2; |
| 883 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 884 | VAddCMicrokernelTester() |
| 885 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 886 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 887 | } |
| 888 | } |
| 889 | |
| 890 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X8, inplace) { |
| 891 | TEST_REQUIRES_X86_SSE2; |
| 892 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 893 | VAddCMicrokernelTester() |
| 894 | .batch_size(batch_size) |
| 895 | .inplace(true) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 896 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 897 | } |
| 898 | } |
| 899 | |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 900 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X8, a_zero_point) { |
| 901 | TEST_REQUIRES_X86_SSE2; |
| 902 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 903 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 904 | VAddCMicrokernelTester() |
| 905 | .batch_size(batch_size) |
| 906 | .a_zero_point(a_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 907 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 908 | } |
| 909 | } |
| 910 | } |
| 911 | |
| 912 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X8, b_zero_point) { |
| 913 | TEST_REQUIRES_X86_SSE2; |
| 914 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 915 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 916 | VAddCMicrokernelTester() |
| 917 | .batch_size(batch_size) |
| 918 | .b_zero_point(b_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 919 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 920 | } |
| 921 | } |
| 922 | } |
| 923 | |
| 924 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X8, y_zero_point) { |
| 925 | TEST_REQUIRES_X86_SSE2; |
| 926 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 927 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 928 | VAddCMicrokernelTester() |
| 929 | .batch_size(batch_size) |
| 930 | .y_zero_point(y_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 931 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 932 | } |
| 933 | } |
| 934 | } |
| 935 | |
| 936 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X8, a_scale) { |
| 937 | TEST_REQUIRES_X86_SSE2; |
| 938 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 939 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 940 | VAddCMicrokernelTester() |
| 941 | .batch_size(batch_size) |
| 942 | .a_scale(a_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 943 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 944 | } |
| 945 | } |
| 946 | } |
| 947 | |
| 948 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X8, b_scale) { |
| 949 | TEST_REQUIRES_X86_SSE2; |
| 950 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 951 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 952 | VAddCMicrokernelTester() |
| 953 | .batch_size(batch_size) |
| 954 | .b_scale(b_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 955 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 956 | } |
| 957 | } |
| 958 | } |
| 959 | |
| 960 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X8, y_scale) { |
| 961 | TEST_REQUIRES_X86_SSE2; |
| 962 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 963 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 964 | VAddCMicrokernelTester() |
| 965 | .batch_size(batch_size) |
| 966 | .y_scale(y_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 967 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 968 | } |
| 969 | } |
| 970 | } |
| 971 | |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 972 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X8, qmin) { |
| 973 | TEST_REQUIRES_X86_SSE2; |
| 974 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 975 | VAddCMicrokernelTester() |
| 976 | .batch_size(batch_size) |
| 977 | .qmin(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 978 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 979 | } |
| 980 | } |
| 981 | |
| 982 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X8, qmax) { |
| 983 | TEST_REQUIRES_X86_SSE2; |
| 984 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 985 | VAddCMicrokernelTester() |
| 986 | .batch_size(batch_size) |
| 987 | .qmax(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 988 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 989 | } |
| 990 | } |
| 991 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 992 | |
| 993 | |
| 994 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 995 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X16, batch_eq_16) { |
| 996 | TEST_REQUIRES_X86_SSE2; |
| 997 | VAddCMicrokernelTester() |
| 998 | .batch_size(16) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 999 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1000 | } |
| 1001 | |
| 1002 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X16, batch_div_16) { |
| 1003 | TEST_REQUIRES_X86_SSE2; |
| 1004 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 1005 | VAddCMicrokernelTester() |
| 1006 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1007 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1008 | } |
| 1009 | } |
| 1010 | |
| 1011 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X16, batch_lt_16) { |
| 1012 | TEST_REQUIRES_X86_SSE2; |
| 1013 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 1014 | VAddCMicrokernelTester() |
| 1015 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1016 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1017 | } |
| 1018 | } |
| 1019 | |
| 1020 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X16, batch_gt_16) { |
| 1021 | TEST_REQUIRES_X86_SSE2; |
| 1022 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 1023 | VAddCMicrokernelTester() |
| 1024 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1025 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1026 | } |
| 1027 | } |
| 1028 | |
| 1029 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X16, inplace) { |
| 1030 | TEST_REQUIRES_X86_SSE2; |
| 1031 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1032 | VAddCMicrokernelTester() |
| 1033 | .batch_size(batch_size) |
| 1034 | .inplace(true) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1035 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1036 | } |
| 1037 | } |
| 1038 | |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1039 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X16, a_zero_point) { |
| 1040 | TEST_REQUIRES_X86_SSE2; |
| 1041 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1042 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 1043 | VAddCMicrokernelTester() |
| 1044 | .batch_size(batch_size) |
| 1045 | .a_zero_point(a_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1046 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1047 | } |
| 1048 | } |
| 1049 | } |
| 1050 | |
| 1051 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X16, b_zero_point) { |
| 1052 | TEST_REQUIRES_X86_SSE2; |
| 1053 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1054 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 1055 | VAddCMicrokernelTester() |
| 1056 | .batch_size(batch_size) |
| 1057 | .b_zero_point(b_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1058 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1059 | } |
| 1060 | } |
| 1061 | } |
| 1062 | |
| 1063 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X16, y_zero_point) { |
| 1064 | TEST_REQUIRES_X86_SSE2; |
| 1065 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1066 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 1067 | VAddCMicrokernelTester() |
| 1068 | .batch_size(batch_size) |
| 1069 | .y_zero_point(y_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1070 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1071 | } |
| 1072 | } |
| 1073 | } |
| 1074 | |
| 1075 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X16, a_scale) { |
| 1076 | TEST_REQUIRES_X86_SSE2; |
| 1077 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1078 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 1079 | VAddCMicrokernelTester() |
| 1080 | .batch_size(batch_size) |
| 1081 | .a_scale(a_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1082 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1083 | } |
| 1084 | } |
| 1085 | } |
| 1086 | |
| 1087 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X16, b_scale) { |
| 1088 | TEST_REQUIRES_X86_SSE2; |
| 1089 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1090 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 1091 | VAddCMicrokernelTester() |
| 1092 | .batch_size(batch_size) |
| 1093 | .b_scale(b_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1094 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1095 | } |
| 1096 | } |
| 1097 | } |
| 1098 | |
| 1099 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X16, y_scale) { |
| 1100 | TEST_REQUIRES_X86_SSE2; |
| 1101 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1102 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 1103 | VAddCMicrokernelTester() |
| 1104 | .batch_size(batch_size) |
| 1105 | .y_scale(y_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1106 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1107 | } |
| 1108 | } |
| 1109 | } |
| 1110 | |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1111 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X16, qmin) { |
| 1112 | TEST_REQUIRES_X86_SSE2; |
| 1113 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1114 | VAddCMicrokernelTester() |
| 1115 | .batch_size(batch_size) |
| 1116 | .qmin(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1117 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1118 | } |
| 1119 | } |
| 1120 | |
| 1121 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X16, qmax) { |
| 1122 | TEST_REQUIRES_X86_SSE2; |
| 1123 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1124 | VAddCMicrokernelTester() |
| 1125 | .batch_size(batch_size) |
| 1126 | .qmax(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1127 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1128 | } |
| 1129 | } |
| 1130 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1131 | |
| 1132 | |
| 1133 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1134 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X24, batch_eq_24) { |
| 1135 | TEST_REQUIRES_X86_SSE2; |
| 1136 | VAddCMicrokernelTester() |
| 1137 | .batch_size(24) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1138 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1139 | } |
| 1140 | |
| 1141 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X24, batch_div_24) { |
| 1142 | TEST_REQUIRES_X86_SSE2; |
| 1143 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 1144 | VAddCMicrokernelTester() |
| 1145 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1146 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1147 | } |
| 1148 | } |
| 1149 | |
| 1150 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X24, batch_lt_24) { |
| 1151 | TEST_REQUIRES_X86_SSE2; |
| 1152 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 1153 | VAddCMicrokernelTester() |
| 1154 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1155 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1156 | } |
| 1157 | } |
| 1158 | |
| 1159 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X24, batch_gt_24) { |
| 1160 | TEST_REQUIRES_X86_SSE2; |
| 1161 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 1162 | VAddCMicrokernelTester() |
| 1163 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1164 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1165 | } |
| 1166 | } |
| 1167 | |
| 1168 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X24, inplace) { |
| 1169 | TEST_REQUIRES_X86_SSE2; |
| 1170 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1171 | VAddCMicrokernelTester() |
| 1172 | .batch_size(batch_size) |
| 1173 | .inplace(true) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1174 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1175 | } |
| 1176 | } |
| 1177 | |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1178 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X24, a_zero_point) { |
| 1179 | TEST_REQUIRES_X86_SSE2; |
| 1180 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1181 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 1182 | VAddCMicrokernelTester() |
| 1183 | .batch_size(batch_size) |
| 1184 | .a_zero_point(a_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1185 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1186 | } |
| 1187 | } |
| 1188 | } |
| 1189 | |
| 1190 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X24, b_zero_point) { |
| 1191 | TEST_REQUIRES_X86_SSE2; |
| 1192 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1193 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 1194 | VAddCMicrokernelTester() |
| 1195 | .batch_size(batch_size) |
| 1196 | .b_zero_point(b_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1197 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1198 | } |
| 1199 | } |
| 1200 | } |
| 1201 | |
| 1202 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X24, y_zero_point) { |
| 1203 | TEST_REQUIRES_X86_SSE2; |
| 1204 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1205 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 1206 | VAddCMicrokernelTester() |
| 1207 | .batch_size(batch_size) |
| 1208 | .y_zero_point(y_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1209 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1210 | } |
| 1211 | } |
| 1212 | } |
| 1213 | |
| 1214 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X24, a_scale) { |
| 1215 | TEST_REQUIRES_X86_SSE2; |
| 1216 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1217 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 1218 | VAddCMicrokernelTester() |
| 1219 | .batch_size(batch_size) |
| 1220 | .a_scale(a_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1221 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1222 | } |
| 1223 | } |
| 1224 | } |
| 1225 | |
| 1226 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X24, b_scale) { |
| 1227 | TEST_REQUIRES_X86_SSE2; |
| 1228 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1229 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 1230 | VAddCMicrokernelTester() |
| 1231 | .batch_size(batch_size) |
| 1232 | .b_scale(b_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1233 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1234 | } |
| 1235 | } |
| 1236 | } |
| 1237 | |
| 1238 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X24, y_scale) { |
| 1239 | TEST_REQUIRES_X86_SSE2; |
| 1240 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1241 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 1242 | VAddCMicrokernelTester() |
| 1243 | .batch_size(batch_size) |
| 1244 | .y_scale(y_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1245 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1246 | } |
| 1247 | } |
| 1248 | } |
| 1249 | |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1250 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X24, qmin) { |
| 1251 | TEST_REQUIRES_X86_SSE2; |
| 1252 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1253 | VAddCMicrokernelTester() |
| 1254 | .batch_size(batch_size) |
| 1255 | .qmin(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1256 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1257 | } |
| 1258 | } |
| 1259 | |
| 1260 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X24, qmax) { |
| 1261 | TEST_REQUIRES_X86_SSE2; |
| 1262 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1263 | VAddCMicrokernelTester() |
| 1264 | .batch_size(batch_size) |
| 1265 | .qmax(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1266 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1267 | } |
| 1268 | } |
| 1269 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1270 | |
| 1271 | |
| 1272 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1273 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X32, batch_eq_32) { |
| 1274 | TEST_REQUIRES_X86_SSE2; |
| 1275 | VAddCMicrokernelTester() |
| 1276 | .batch_size(32) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1277 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1278 | } |
| 1279 | |
| 1280 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X32, batch_div_32) { |
| 1281 | TEST_REQUIRES_X86_SSE2; |
| 1282 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 1283 | VAddCMicrokernelTester() |
| 1284 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1285 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1286 | } |
| 1287 | } |
| 1288 | |
| 1289 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X32, batch_lt_32) { |
| 1290 | TEST_REQUIRES_X86_SSE2; |
| 1291 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 1292 | VAddCMicrokernelTester() |
| 1293 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1294 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1295 | } |
| 1296 | } |
| 1297 | |
| 1298 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X32, batch_gt_32) { |
| 1299 | TEST_REQUIRES_X86_SSE2; |
| 1300 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 1301 | VAddCMicrokernelTester() |
| 1302 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1303 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1304 | } |
| 1305 | } |
| 1306 | |
| 1307 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X32, inplace) { |
| 1308 | TEST_REQUIRES_X86_SSE2; |
| 1309 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 1310 | VAddCMicrokernelTester() |
| 1311 | .batch_size(batch_size) |
| 1312 | .inplace(true) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1313 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1314 | } |
| 1315 | } |
| 1316 | |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1317 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X32, a_zero_point) { |
| 1318 | TEST_REQUIRES_X86_SSE2; |
| 1319 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 1320 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 1321 | VAddCMicrokernelTester() |
| 1322 | .batch_size(batch_size) |
| 1323 | .a_zero_point(a_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1324 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1325 | } |
| 1326 | } |
| 1327 | } |
| 1328 | |
| 1329 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X32, b_zero_point) { |
| 1330 | TEST_REQUIRES_X86_SSE2; |
| 1331 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 1332 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 1333 | VAddCMicrokernelTester() |
| 1334 | .batch_size(batch_size) |
| 1335 | .b_zero_point(b_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1336 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1337 | } |
| 1338 | } |
| 1339 | } |
| 1340 | |
| 1341 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X32, y_zero_point) { |
| 1342 | TEST_REQUIRES_X86_SSE2; |
| 1343 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 1344 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 1345 | VAddCMicrokernelTester() |
| 1346 | .batch_size(batch_size) |
| 1347 | .y_zero_point(y_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1348 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1349 | } |
| 1350 | } |
| 1351 | } |
| 1352 | |
| 1353 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X32, a_scale) { |
| 1354 | TEST_REQUIRES_X86_SSE2; |
| 1355 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 1356 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 1357 | VAddCMicrokernelTester() |
| 1358 | .batch_size(batch_size) |
| 1359 | .a_scale(a_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1360 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1361 | } |
| 1362 | } |
| 1363 | } |
| 1364 | |
| 1365 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X32, b_scale) { |
| 1366 | TEST_REQUIRES_X86_SSE2; |
| 1367 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 1368 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 1369 | VAddCMicrokernelTester() |
| 1370 | .batch_size(batch_size) |
| 1371 | .b_scale(b_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1372 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1373 | } |
| 1374 | } |
| 1375 | } |
| 1376 | |
| 1377 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X32, y_scale) { |
| 1378 | TEST_REQUIRES_X86_SSE2; |
| 1379 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 1380 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 1381 | VAddCMicrokernelTester() |
| 1382 | .batch_size(batch_size) |
| 1383 | .y_scale(y_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1384 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1385 | } |
| 1386 | } |
| 1387 | } |
| 1388 | |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1389 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X32, qmin) { |
| 1390 | TEST_REQUIRES_X86_SSE2; |
| 1391 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 1392 | VAddCMicrokernelTester() |
| 1393 | .batch_size(batch_size) |
| 1394 | .qmin(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1395 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1396 | } |
| 1397 | } |
| 1398 | |
| 1399 | TEST(QS8_VADDC_MINMAX__SSE2_MUL16_LD64_X32, qmax) { |
| 1400 | TEST_REQUIRES_X86_SSE2; |
| 1401 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 1402 | VAddCMicrokernelTester() |
| 1403 | .batch_size(batch_size) |
| 1404 | .qmax(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 1405 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse2_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse2_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1406 | } |
| 1407 | } |
| 1408 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1409 | |
| 1410 | |
| 1411 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1412 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X8, batch_eq_8) { |
| 1413 | TEST_REQUIRES_X86_SSE41; |
| 1414 | VAddCMicrokernelTester() |
| 1415 | .batch_size(8) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1416 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1417 | } |
| 1418 | |
| 1419 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X8, batch_div_8) { |
| 1420 | TEST_REQUIRES_X86_SSE41; |
| 1421 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 1422 | VAddCMicrokernelTester() |
| 1423 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1424 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1425 | } |
| 1426 | } |
| 1427 | |
| 1428 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X8, batch_lt_8) { |
| 1429 | TEST_REQUIRES_X86_SSE41; |
| 1430 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 1431 | VAddCMicrokernelTester() |
| 1432 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1433 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1434 | } |
| 1435 | } |
| 1436 | |
| 1437 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X8, batch_gt_8) { |
| 1438 | TEST_REQUIRES_X86_SSE41; |
| 1439 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 1440 | VAddCMicrokernelTester() |
| 1441 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1442 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1443 | } |
| 1444 | } |
| 1445 | |
| 1446 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X8, inplace) { |
| 1447 | TEST_REQUIRES_X86_SSE41; |
| 1448 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 1449 | VAddCMicrokernelTester() |
| 1450 | .batch_size(batch_size) |
| 1451 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1452 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1453 | } |
| 1454 | } |
| 1455 | |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1456 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X8, a_zero_point) { |
| 1457 | TEST_REQUIRES_X86_SSE41; |
| 1458 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 1459 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 1460 | VAddCMicrokernelTester() |
| 1461 | .batch_size(batch_size) |
| 1462 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1463 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1464 | } |
| 1465 | } |
| 1466 | } |
| 1467 | |
| 1468 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X8, b_zero_point) { |
| 1469 | TEST_REQUIRES_X86_SSE41; |
| 1470 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 1471 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 1472 | VAddCMicrokernelTester() |
| 1473 | .batch_size(batch_size) |
| 1474 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1475 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1476 | } |
| 1477 | } |
| 1478 | } |
| 1479 | |
| 1480 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X8, y_zero_point) { |
| 1481 | TEST_REQUIRES_X86_SSE41; |
| 1482 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 1483 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 1484 | VAddCMicrokernelTester() |
| 1485 | .batch_size(batch_size) |
| 1486 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1487 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1488 | } |
| 1489 | } |
| 1490 | } |
| 1491 | |
| 1492 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X8, a_scale) { |
| 1493 | TEST_REQUIRES_X86_SSE41; |
| 1494 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 1495 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 1496 | VAddCMicrokernelTester() |
| 1497 | .batch_size(batch_size) |
| 1498 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1499 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1500 | } |
| 1501 | } |
| 1502 | } |
| 1503 | |
| 1504 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X8, b_scale) { |
| 1505 | TEST_REQUIRES_X86_SSE41; |
| 1506 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 1507 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 1508 | VAddCMicrokernelTester() |
| 1509 | .batch_size(batch_size) |
| 1510 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1511 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1512 | } |
| 1513 | } |
| 1514 | } |
| 1515 | |
| 1516 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X8, y_scale) { |
| 1517 | TEST_REQUIRES_X86_SSE41; |
| 1518 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 1519 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 1520 | VAddCMicrokernelTester() |
| 1521 | .batch_size(batch_size) |
| 1522 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1523 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1524 | } |
| 1525 | } |
| 1526 | } |
| 1527 | |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1528 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X8, qmin) { |
| 1529 | TEST_REQUIRES_X86_SSE41; |
| 1530 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 1531 | VAddCMicrokernelTester() |
| 1532 | .batch_size(batch_size) |
| 1533 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1534 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1535 | } |
| 1536 | } |
| 1537 | |
| 1538 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X8, qmax) { |
| 1539 | TEST_REQUIRES_X86_SSE41; |
| 1540 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 1541 | VAddCMicrokernelTester() |
| 1542 | .batch_size(batch_size) |
| 1543 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1544 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1545 | } |
| 1546 | } |
| 1547 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1548 | |
| 1549 | |
| 1550 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1551 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X16, batch_eq_16) { |
| 1552 | TEST_REQUIRES_X86_SSE41; |
| 1553 | VAddCMicrokernelTester() |
| 1554 | .batch_size(16) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1555 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1556 | } |
| 1557 | |
| 1558 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X16, batch_div_16) { |
| 1559 | TEST_REQUIRES_X86_SSE41; |
| 1560 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 1561 | VAddCMicrokernelTester() |
| 1562 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1563 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1564 | } |
| 1565 | } |
| 1566 | |
| 1567 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X16, batch_lt_16) { |
| 1568 | TEST_REQUIRES_X86_SSE41; |
| 1569 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 1570 | VAddCMicrokernelTester() |
| 1571 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1572 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1573 | } |
| 1574 | } |
| 1575 | |
| 1576 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X16, batch_gt_16) { |
| 1577 | TEST_REQUIRES_X86_SSE41; |
| 1578 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 1579 | VAddCMicrokernelTester() |
| 1580 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1581 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1582 | } |
| 1583 | } |
| 1584 | |
| 1585 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X16, inplace) { |
| 1586 | TEST_REQUIRES_X86_SSE41; |
| 1587 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1588 | VAddCMicrokernelTester() |
| 1589 | .batch_size(batch_size) |
| 1590 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1591 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1592 | } |
| 1593 | } |
| 1594 | |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1595 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X16, a_zero_point) { |
| 1596 | TEST_REQUIRES_X86_SSE41; |
| 1597 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1598 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 1599 | VAddCMicrokernelTester() |
| 1600 | .batch_size(batch_size) |
| 1601 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1602 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1603 | } |
| 1604 | } |
| 1605 | } |
| 1606 | |
| 1607 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X16, b_zero_point) { |
| 1608 | TEST_REQUIRES_X86_SSE41; |
| 1609 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1610 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 1611 | VAddCMicrokernelTester() |
| 1612 | .batch_size(batch_size) |
| 1613 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1614 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1615 | } |
| 1616 | } |
| 1617 | } |
| 1618 | |
| 1619 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X16, y_zero_point) { |
| 1620 | TEST_REQUIRES_X86_SSE41; |
| 1621 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1622 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 1623 | VAddCMicrokernelTester() |
| 1624 | .batch_size(batch_size) |
| 1625 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1626 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1627 | } |
| 1628 | } |
| 1629 | } |
| 1630 | |
| 1631 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X16, a_scale) { |
| 1632 | TEST_REQUIRES_X86_SSE41; |
| 1633 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1634 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 1635 | VAddCMicrokernelTester() |
| 1636 | .batch_size(batch_size) |
| 1637 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1638 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1639 | } |
| 1640 | } |
| 1641 | } |
| 1642 | |
| 1643 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X16, b_scale) { |
| 1644 | TEST_REQUIRES_X86_SSE41; |
| 1645 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1646 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 1647 | VAddCMicrokernelTester() |
| 1648 | .batch_size(batch_size) |
| 1649 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1650 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1651 | } |
| 1652 | } |
| 1653 | } |
| 1654 | |
| 1655 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X16, y_scale) { |
| 1656 | TEST_REQUIRES_X86_SSE41; |
| 1657 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1658 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 1659 | VAddCMicrokernelTester() |
| 1660 | .batch_size(batch_size) |
| 1661 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1662 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1663 | } |
| 1664 | } |
| 1665 | } |
| 1666 | |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1667 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X16, qmin) { |
| 1668 | TEST_REQUIRES_X86_SSE41; |
| 1669 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1670 | VAddCMicrokernelTester() |
| 1671 | .batch_size(batch_size) |
| 1672 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1673 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1674 | } |
| 1675 | } |
| 1676 | |
| 1677 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X16, qmax) { |
| 1678 | TEST_REQUIRES_X86_SSE41; |
| 1679 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 1680 | VAddCMicrokernelTester() |
| 1681 | .batch_size(batch_size) |
| 1682 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1683 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1684 | } |
| 1685 | } |
| 1686 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1687 | |
| 1688 | |
| 1689 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1690 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X24, batch_eq_24) { |
| 1691 | TEST_REQUIRES_X86_SSE41; |
| 1692 | VAddCMicrokernelTester() |
| 1693 | .batch_size(24) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1694 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1695 | } |
| 1696 | |
| 1697 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X24, batch_div_24) { |
| 1698 | TEST_REQUIRES_X86_SSE41; |
| 1699 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 1700 | VAddCMicrokernelTester() |
| 1701 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1702 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1703 | } |
| 1704 | } |
| 1705 | |
| 1706 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X24, batch_lt_24) { |
| 1707 | TEST_REQUIRES_X86_SSE41; |
| 1708 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 1709 | VAddCMicrokernelTester() |
| 1710 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1711 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1712 | } |
| 1713 | } |
| 1714 | |
| 1715 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X24, batch_gt_24) { |
| 1716 | TEST_REQUIRES_X86_SSE41; |
| 1717 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 1718 | VAddCMicrokernelTester() |
| 1719 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1720 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1721 | } |
| 1722 | } |
| 1723 | |
| 1724 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X24, inplace) { |
| 1725 | TEST_REQUIRES_X86_SSE41; |
| 1726 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1727 | VAddCMicrokernelTester() |
| 1728 | .batch_size(batch_size) |
| 1729 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1730 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1731 | } |
| 1732 | } |
| 1733 | |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1734 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X24, a_zero_point) { |
| 1735 | TEST_REQUIRES_X86_SSE41; |
| 1736 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1737 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 1738 | VAddCMicrokernelTester() |
| 1739 | .batch_size(batch_size) |
| 1740 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1741 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1742 | } |
| 1743 | } |
| 1744 | } |
| 1745 | |
| 1746 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X24, b_zero_point) { |
| 1747 | TEST_REQUIRES_X86_SSE41; |
| 1748 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1749 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 1750 | VAddCMicrokernelTester() |
| 1751 | .batch_size(batch_size) |
| 1752 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1753 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1754 | } |
| 1755 | } |
| 1756 | } |
| 1757 | |
| 1758 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X24, y_zero_point) { |
| 1759 | TEST_REQUIRES_X86_SSE41; |
| 1760 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1761 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 1762 | VAddCMicrokernelTester() |
| 1763 | .batch_size(batch_size) |
| 1764 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1765 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1766 | } |
| 1767 | } |
| 1768 | } |
| 1769 | |
| 1770 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X24, a_scale) { |
| 1771 | TEST_REQUIRES_X86_SSE41; |
| 1772 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1773 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 1774 | VAddCMicrokernelTester() |
| 1775 | .batch_size(batch_size) |
| 1776 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1777 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1778 | } |
| 1779 | } |
| 1780 | } |
| 1781 | |
| 1782 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X24, b_scale) { |
| 1783 | TEST_REQUIRES_X86_SSE41; |
| 1784 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1785 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 1786 | VAddCMicrokernelTester() |
| 1787 | .batch_size(batch_size) |
| 1788 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1789 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1790 | } |
| 1791 | } |
| 1792 | } |
| 1793 | |
| 1794 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X24, y_scale) { |
| 1795 | TEST_REQUIRES_X86_SSE41; |
| 1796 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1797 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 1798 | VAddCMicrokernelTester() |
| 1799 | .batch_size(batch_size) |
| 1800 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1801 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1802 | } |
| 1803 | } |
| 1804 | } |
| 1805 | |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1806 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X24, qmin) { |
| 1807 | TEST_REQUIRES_X86_SSE41; |
| 1808 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1809 | VAddCMicrokernelTester() |
| 1810 | .batch_size(batch_size) |
| 1811 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1812 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1813 | } |
| 1814 | } |
| 1815 | |
| 1816 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X24, qmax) { |
| 1817 | TEST_REQUIRES_X86_SSE41; |
| 1818 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 1819 | VAddCMicrokernelTester() |
| 1820 | .batch_size(batch_size) |
| 1821 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1822 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1823 | } |
| 1824 | } |
| 1825 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1826 | |
| 1827 | |
| 1828 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 1829 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X32, batch_eq_32) { |
| 1830 | TEST_REQUIRES_X86_SSE41; |
| 1831 | VAddCMicrokernelTester() |
| 1832 | .batch_size(32) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1833 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1834 | } |
| 1835 | |
| 1836 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X32, batch_div_32) { |
| 1837 | TEST_REQUIRES_X86_SSE41; |
| 1838 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 1839 | VAddCMicrokernelTester() |
| 1840 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1841 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1842 | } |
| 1843 | } |
| 1844 | |
| 1845 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X32, batch_lt_32) { |
| 1846 | TEST_REQUIRES_X86_SSE41; |
| 1847 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 1848 | VAddCMicrokernelTester() |
| 1849 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1850 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1851 | } |
| 1852 | } |
| 1853 | |
| 1854 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X32, batch_gt_32) { |
| 1855 | TEST_REQUIRES_X86_SSE41; |
| 1856 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 1857 | VAddCMicrokernelTester() |
| 1858 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1859 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1860 | } |
| 1861 | } |
| 1862 | |
| 1863 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X32, inplace) { |
| 1864 | TEST_REQUIRES_X86_SSE41; |
| 1865 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 1866 | VAddCMicrokernelTester() |
| 1867 | .batch_size(batch_size) |
| 1868 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1869 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1870 | } |
| 1871 | } |
| 1872 | |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1873 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X32, a_zero_point) { |
| 1874 | TEST_REQUIRES_X86_SSE41; |
| 1875 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 1876 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 1877 | VAddCMicrokernelTester() |
| 1878 | .batch_size(batch_size) |
| 1879 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1880 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1881 | } |
| 1882 | } |
| 1883 | } |
| 1884 | |
| 1885 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X32, b_zero_point) { |
| 1886 | TEST_REQUIRES_X86_SSE41; |
| 1887 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 1888 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 1889 | VAddCMicrokernelTester() |
| 1890 | .batch_size(batch_size) |
| 1891 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1892 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1893 | } |
| 1894 | } |
| 1895 | } |
| 1896 | |
| 1897 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X32, y_zero_point) { |
| 1898 | TEST_REQUIRES_X86_SSE41; |
| 1899 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 1900 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 1901 | VAddCMicrokernelTester() |
| 1902 | .batch_size(batch_size) |
| 1903 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1904 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1905 | } |
| 1906 | } |
| 1907 | } |
| 1908 | |
| 1909 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X32, a_scale) { |
| 1910 | TEST_REQUIRES_X86_SSE41; |
| 1911 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 1912 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 1913 | VAddCMicrokernelTester() |
| 1914 | .batch_size(batch_size) |
| 1915 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1916 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1917 | } |
| 1918 | } |
| 1919 | } |
| 1920 | |
| 1921 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X32, b_scale) { |
| 1922 | TEST_REQUIRES_X86_SSE41; |
| 1923 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 1924 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 1925 | VAddCMicrokernelTester() |
| 1926 | .batch_size(batch_size) |
| 1927 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1928 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1929 | } |
| 1930 | } |
| 1931 | } |
| 1932 | |
| 1933 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X32, y_scale) { |
| 1934 | TEST_REQUIRES_X86_SSE41; |
| 1935 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 1936 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 1937 | VAddCMicrokernelTester() |
| 1938 | .batch_size(batch_size) |
| 1939 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1940 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 95caee5 | 2020-09-02 03:41:32 -0700 | [diff] [blame] | 1941 | } |
| 1942 | } |
| 1943 | } |
| 1944 | |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1945 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X32, qmin) { |
| 1946 | TEST_REQUIRES_X86_SSE41; |
| 1947 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 1948 | VAddCMicrokernelTester() |
| 1949 | .batch_size(batch_size) |
| 1950 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1951 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1952 | } |
| 1953 | } |
| 1954 | |
| 1955 | TEST(QS8_VADDC_MINMAX__SSE41_MUL16_LD64_X32, qmax) { |
| 1956 | TEST_REQUIRES_X86_SSE41; |
| 1957 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 1958 | VAddCMicrokernelTester() |
| 1959 | .batch_size(batch_size) |
| 1960 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1961 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | 0270d9f | 2020-08-11 00:56:46 -0700 | [diff] [blame] | 1962 | } |
| 1963 | } |
| 1964 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 1965 | |
| 1966 | |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 1967 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 1968 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X8, batch_eq_8) { |
| 1969 | TEST_REQUIRES_X86_AVX; |
| 1970 | VAddCMicrokernelTester() |
| 1971 | .batch_size(8) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1972 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 1973 | } |
| 1974 | |
| 1975 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X8, batch_div_8) { |
| 1976 | TEST_REQUIRES_X86_AVX; |
| 1977 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 1978 | VAddCMicrokernelTester() |
| 1979 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1980 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 1981 | } |
| 1982 | } |
| 1983 | |
| 1984 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X8, batch_lt_8) { |
| 1985 | TEST_REQUIRES_X86_AVX; |
| 1986 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 1987 | VAddCMicrokernelTester() |
| 1988 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1989 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 1990 | } |
| 1991 | } |
| 1992 | |
| 1993 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X8, batch_gt_8) { |
| 1994 | TEST_REQUIRES_X86_AVX; |
| 1995 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 1996 | VAddCMicrokernelTester() |
| 1997 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 1998 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 1999 | } |
| 2000 | } |
| 2001 | |
| 2002 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X8, inplace) { |
| 2003 | TEST_REQUIRES_X86_AVX; |
| 2004 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 2005 | VAddCMicrokernelTester() |
| 2006 | .batch_size(batch_size) |
| 2007 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2008 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2009 | } |
| 2010 | } |
| 2011 | |
| 2012 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X8, a_zero_point) { |
| 2013 | TEST_REQUIRES_X86_AVX; |
| 2014 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 2015 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 2016 | VAddCMicrokernelTester() |
| 2017 | .batch_size(batch_size) |
| 2018 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2019 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2020 | } |
| 2021 | } |
| 2022 | } |
| 2023 | |
| 2024 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X8, b_zero_point) { |
| 2025 | TEST_REQUIRES_X86_AVX; |
| 2026 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 2027 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 2028 | VAddCMicrokernelTester() |
| 2029 | .batch_size(batch_size) |
| 2030 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2031 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2032 | } |
| 2033 | } |
| 2034 | } |
| 2035 | |
| 2036 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X8, y_zero_point) { |
| 2037 | TEST_REQUIRES_X86_AVX; |
| 2038 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 2039 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 2040 | VAddCMicrokernelTester() |
| 2041 | .batch_size(batch_size) |
| 2042 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2043 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2044 | } |
| 2045 | } |
| 2046 | } |
| 2047 | |
| 2048 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X8, a_scale) { |
| 2049 | TEST_REQUIRES_X86_AVX; |
| 2050 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 2051 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 2052 | VAddCMicrokernelTester() |
| 2053 | .batch_size(batch_size) |
| 2054 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2055 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2056 | } |
| 2057 | } |
| 2058 | } |
| 2059 | |
| 2060 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X8, b_scale) { |
| 2061 | TEST_REQUIRES_X86_AVX; |
| 2062 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 2063 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 2064 | VAddCMicrokernelTester() |
| 2065 | .batch_size(batch_size) |
| 2066 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2067 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2068 | } |
| 2069 | } |
| 2070 | } |
| 2071 | |
| 2072 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X8, y_scale) { |
| 2073 | TEST_REQUIRES_X86_AVX; |
| 2074 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 2075 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 2076 | VAddCMicrokernelTester() |
| 2077 | .batch_size(batch_size) |
| 2078 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2079 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2080 | } |
| 2081 | } |
| 2082 | } |
| 2083 | |
| 2084 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X8, qmin) { |
| 2085 | TEST_REQUIRES_X86_AVX; |
| 2086 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 2087 | VAddCMicrokernelTester() |
| 2088 | .batch_size(batch_size) |
| 2089 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2090 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2091 | } |
| 2092 | } |
| 2093 | |
| 2094 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X8, qmax) { |
| 2095 | TEST_REQUIRES_X86_AVX; |
| 2096 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 2097 | VAddCMicrokernelTester() |
| 2098 | .batch_size(batch_size) |
| 2099 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2100 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x8, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2101 | } |
| 2102 | } |
| 2103 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2104 | |
| 2105 | |
| 2106 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2107 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X16, batch_eq_16) { |
| 2108 | TEST_REQUIRES_X86_AVX; |
| 2109 | VAddCMicrokernelTester() |
| 2110 | .batch_size(16) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2111 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2112 | } |
| 2113 | |
| 2114 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X16, batch_div_16) { |
| 2115 | TEST_REQUIRES_X86_AVX; |
| 2116 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 2117 | VAddCMicrokernelTester() |
| 2118 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2119 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2120 | } |
| 2121 | } |
| 2122 | |
| 2123 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X16, batch_lt_16) { |
| 2124 | TEST_REQUIRES_X86_AVX; |
| 2125 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 2126 | VAddCMicrokernelTester() |
| 2127 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2128 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2129 | } |
| 2130 | } |
| 2131 | |
| 2132 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X16, batch_gt_16) { |
| 2133 | TEST_REQUIRES_X86_AVX; |
| 2134 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 2135 | VAddCMicrokernelTester() |
| 2136 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2137 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2138 | } |
| 2139 | } |
| 2140 | |
| 2141 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X16, inplace) { |
| 2142 | TEST_REQUIRES_X86_AVX; |
| 2143 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 2144 | VAddCMicrokernelTester() |
| 2145 | .batch_size(batch_size) |
| 2146 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2147 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2148 | } |
| 2149 | } |
| 2150 | |
| 2151 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X16, a_zero_point) { |
| 2152 | TEST_REQUIRES_X86_AVX; |
| 2153 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 2154 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 2155 | VAddCMicrokernelTester() |
| 2156 | .batch_size(batch_size) |
| 2157 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2158 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2159 | } |
| 2160 | } |
| 2161 | } |
| 2162 | |
| 2163 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X16, b_zero_point) { |
| 2164 | TEST_REQUIRES_X86_AVX; |
| 2165 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 2166 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 2167 | VAddCMicrokernelTester() |
| 2168 | .batch_size(batch_size) |
| 2169 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2170 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2171 | } |
| 2172 | } |
| 2173 | } |
| 2174 | |
| 2175 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X16, y_zero_point) { |
| 2176 | TEST_REQUIRES_X86_AVX; |
| 2177 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 2178 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 2179 | VAddCMicrokernelTester() |
| 2180 | .batch_size(batch_size) |
| 2181 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2182 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2183 | } |
| 2184 | } |
| 2185 | } |
| 2186 | |
| 2187 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X16, a_scale) { |
| 2188 | TEST_REQUIRES_X86_AVX; |
| 2189 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 2190 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 2191 | VAddCMicrokernelTester() |
| 2192 | .batch_size(batch_size) |
| 2193 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2194 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2195 | } |
| 2196 | } |
| 2197 | } |
| 2198 | |
| 2199 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X16, b_scale) { |
| 2200 | TEST_REQUIRES_X86_AVX; |
| 2201 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 2202 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 2203 | VAddCMicrokernelTester() |
| 2204 | .batch_size(batch_size) |
| 2205 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2206 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2207 | } |
| 2208 | } |
| 2209 | } |
| 2210 | |
| 2211 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X16, y_scale) { |
| 2212 | TEST_REQUIRES_X86_AVX; |
| 2213 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 2214 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 2215 | VAddCMicrokernelTester() |
| 2216 | .batch_size(batch_size) |
| 2217 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2218 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2219 | } |
| 2220 | } |
| 2221 | } |
| 2222 | |
| 2223 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X16, qmin) { |
| 2224 | TEST_REQUIRES_X86_AVX; |
| 2225 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 2226 | VAddCMicrokernelTester() |
| 2227 | .batch_size(batch_size) |
| 2228 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2229 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2230 | } |
| 2231 | } |
| 2232 | |
| 2233 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X16, qmax) { |
| 2234 | TEST_REQUIRES_X86_AVX; |
| 2235 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 2236 | VAddCMicrokernelTester() |
| 2237 | .batch_size(batch_size) |
| 2238 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2239 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x16, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2240 | } |
| 2241 | } |
| 2242 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2243 | |
| 2244 | |
| 2245 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2246 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X24, batch_eq_24) { |
| 2247 | TEST_REQUIRES_X86_AVX; |
| 2248 | VAddCMicrokernelTester() |
| 2249 | .batch_size(24) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2250 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2251 | } |
| 2252 | |
| 2253 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X24, batch_div_24) { |
| 2254 | TEST_REQUIRES_X86_AVX; |
| 2255 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 2256 | VAddCMicrokernelTester() |
| 2257 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2258 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2259 | } |
| 2260 | } |
| 2261 | |
| 2262 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X24, batch_lt_24) { |
| 2263 | TEST_REQUIRES_X86_AVX; |
| 2264 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 2265 | VAddCMicrokernelTester() |
| 2266 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2267 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2268 | } |
| 2269 | } |
| 2270 | |
| 2271 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X24, batch_gt_24) { |
| 2272 | TEST_REQUIRES_X86_AVX; |
| 2273 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 2274 | VAddCMicrokernelTester() |
| 2275 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2276 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2277 | } |
| 2278 | } |
| 2279 | |
| 2280 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X24, inplace) { |
| 2281 | TEST_REQUIRES_X86_AVX; |
| 2282 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 2283 | VAddCMicrokernelTester() |
| 2284 | .batch_size(batch_size) |
| 2285 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2286 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2287 | } |
| 2288 | } |
| 2289 | |
| 2290 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X24, a_zero_point) { |
| 2291 | TEST_REQUIRES_X86_AVX; |
| 2292 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 2293 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 2294 | VAddCMicrokernelTester() |
| 2295 | .batch_size(batch_size) |
| 2296 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2297 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2298 | } |
| 2299 | } |
| 2300 | } |
| 2301 | |
| 2302 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X24, b_zero_point) { |
| 2303 | TEST_REQUIRES_X86_AVX; |
| 2304 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 2305 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 2306 | VAddCMicrokernelTester() |
| 2307 | .batch_size(batch_size) |
| 2308 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2309 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2310 | } |
| 2311 | } |
| 2312 | } |
| 2313 | |
| 2314 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X24, y_zero_point) { |
| 2315 | TEST_REQUIRES_X86_AVX; |
| 2316 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 2317 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 2318 | VAddCMicrokernelTester() |
| 2319 | .batch_size(batch_size) |
| 2320 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2321 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2322 | } |
| 2323 | } |
| 2324 | } |
| 2325 | |
| 2326 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X24, a_scale) { |
| 2327 | TEST_REQUIRES_X86_AVX; |
| 2328 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 2329 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 2330 | VAddCMicrokernelTester() |
| 2331 | .batch_size(batch_size) |
| 2332 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2333 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2334 | } |
| 2335 | } |
| 2336 | } |
| 2337 | |
| 2338 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X24, b_scale) { |
| 2339 | TEST_REQUIRES_X86_AVX; |
| 2340 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 2341 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 2342 | VAddCMicrokernelTester() |
| 2343 | .batch_size(batch_size) |
| 2344 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2345 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2346 | } |
| 2347 | } |
| 2348 | } |
| 2349 | |
| 2350 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X24, y_scale) { |
| 2351 | TEST_REQUIRES_X86_AVX; |
| 2352 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 2353 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 2354 | VAddCMicrokernelTester() |
| 2355 | .batch_size(batch_size) |
| 2356 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2357 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2358 | } |
| 2359 | } |
| 2360 | } |
| 2361 | |
| 2362 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X24, qmin) { |
| 2363 | TEST_REQUIRES_X86_AVX; |
| 2364 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 2365 | VAddCMicrokernelTester() |
| 2366 | .batch_size(batch_size) |
| 2367 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2368 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2369 | } |
| 2370 | } |
| 2371 | |
| 2372 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X24, qmax) { |
| 2373 | TEST_REQUIRES_X86_AVX; |
| 2374 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 2375 | VAddCMicrokernelTester() |
| 2376 | .batch_size(batch_size) |
| 2377 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2378 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x24, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2379 | } |
| 2380 | } |
| 2381 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2382 | |
| 2383 | |
| 2384 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2385 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X32, batch_eq_32) { |
| 2386 | TEST_REQUIRES_X86_AVX; |
| 2387 | VAddCMicrokernelTester() |
| 2388 | .batch_size(32) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2389 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2390 | } |
| 2391 | |
| 2392 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X32, batch_div_32) { |
| 2393 | TEST_REQUIRES_X86_AVX; |
| 2394 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 2395 | VAddCMicrokernelTester() |
| 2396 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2397 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2398 | } |
| 2399 | } |
| 2400 | |
| 2401 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X32, batch_lt_32) { |
| 2402 | TEST_REQUIRES_X86_AVX; |
| 2403 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 2404 | VAddCMicrokernelTester() |
| 2405 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2406 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2407 | } |
| 2408 | } |
| 2409 | |
| 2410 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X32, batch_gt_32) { |
| 2411 | TEST_REQUIRES_X86_AVX; |
| 2412 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 2413 | VAddCMicrokernelTester() |
| 2414 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2415 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2416 | } |
| 2417 | } |
| 2418 | |
| 2419 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X32, inplace) { |
| 2420 | TEST_REQUIRES_X86_AVX; |
| 2421 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 2422 | VAddCMicrokernelTester() |
| 2423 | .batch_size(batch_size) |
| 2424 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2425 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2426 | } |
| 2427 | } |
| 2428 | |
| 2429 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X32, a_zero_point) { |
| 2430 | TEST_REQUIRES_X86_AVX; |
| 2431 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 2432 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 2433 | VAddCMicrokernelTester() |
| 2434 | .batch_size(batch_size) |
| 2435 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2436 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2437 | } |
| 2438 | } |
| 2439 | } |
| 2440 | |
| 2441 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X32, b_zero_point) { |
| 2442 | TEST_REQUIRES_X86_AVX; |
| 2443 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 2444 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 2445 | VAddCMicrokernelTester() |
| 2446 | .batch_size(batch_size) |
| 2447 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2448 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2449 | } |
| 2450 | } |
| 2451 | } |
| 2452 | |
| 2453 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X32, y_zero_point) { |
| 2454 | TEST_REQUIRES_X86_AVX; |
| 2455 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 2456 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 2457 | VAddCMicrokernelTester() |
| 2458 | .batch_size(batch_size) |
| 2459 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2460 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2461 | } |
| 2462 | } |
| 2463 | } |
| 2464 | |
| 2465 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X32, a_scale) { |
| 2466 | TEST_REQUIRES_X86_AVX; |
| 2467 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 2468 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 2469 | VAddCMicrokernelTester() |
| 2470 | .batch_size(batch_size) |
| 2471 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2472 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2473 | } |
| 2474 | } |
| 2475 | } |
| 2476 | |
| 2477 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X32, b_scale) { |
| 2478 | TEST_REQUIRES_X86_AVX; |
| 2479 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 2480 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 2481 | VAddCMicrokernelTester() |
| 2482 | .batch_size(batch_size) |
| 2483 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2484 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2485 | } |
| 2486 | } |
| 2487 | } |
| 2488 | |
| 2489 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X32, y_scale) { |
| 2490 | TEST_REQUIRES_X86_AVX; |
| 2491 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 2492 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 2493 | VAddCMicrokernelTester() |
| 2494 | .batch_size(batch_size) |
| 2495 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2496 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2497 | } |
| 2498 | } |
| 2499 | } |
| 2500 | |
| 2501 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X32, qmin) { |
| 2502 | TEST_REQUIRES_X86_AVX; |
| 2503 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 2504 | VAddCMicrokernelTester() |
| 2505 | .batch_size(batch_size) |
| 2506 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2507 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2508 | } |
| 2509 | } |
| 2510 | |
| 2511 | TEST(QS8_VADDC_MINMAX__AVX_MUL16_LD64_X32, qmax) { |
| 2512 | TEST_REQUIRES_X86_AVX; |
| 2513 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 2514 | VAddCMicrokernelTester() |
| 2515 | .batch_size(batch_size) |
| 2516 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2517 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul16_ld64_x32, xnn_init_qs8_add_minmax_sse4_mul16_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 2518 | } |
| 2519 | } |
| 2520 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2521 | |
| 2522 | |
| 2523 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2524 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X8, batch_eq_8) { |
| 2525 | TEST_REQUIRES_X86_SSE41; |
| 2526 | VAddCMicrokernelTester() |
| 2527 | .batch_size(8) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2528 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2529 | } |
| 2530 | |
| 2531 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X8, batch_div_8) { |
| 2532 | TEST_REQUIRES_X86_SSE41; |
| 2533 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 2534 | VAddCMicrokernelTester() |
| 2535 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2536 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2537 | } |
| 2538 | } |
| 2539 | |
| 2540 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X8, batch_lt_8) { |
| 2541 | TEST_REQUIRES_X86_SSE41; |
| 2542 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 2543 | VAddCMicrokernelTester() |
| 2544 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2545 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2546 | } |
| 2547 | } |
| 2548 | |
| 2549 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X8, batch_gt_8) { |
| 2550 | TEST_REQUIRES_X86_SSE41; |
| 2551 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 2552 | VAddCMicrokernelTester() |
| 2553 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2554 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2555 | } |
| 2556 | } |
| 2557 | |
| 2558 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X8, inplace) { |
| 2559 | TEST_REQUIRES_X86_SSE41; |
| 2560 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 2561 | VAddCMicrokernelTester() |
| 2562 | .batch_size(batch_size) |
| 2563 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2564 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2565 | } |
| 2566 | } |
| 2567 | |
| 2568 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X8, a_zero_point) { |
| 2569 | TEST_REQUIRES_X86_SSE41; |
| 2570 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 2571 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 2572 | VAddCMicrokernelTester() |
| 2573 | .batch_size(batch_size) |
| 2574 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2575 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2576 | } |
| 2577 | } |
| 2578 | } |
| 2579 | |
| 2580 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X8, b_zero_point) { |
| 2581 | TEST_REQUIRES_X86_SSE41; |
| 2582 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 2583 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 2584 | VAddCMicrokernelTester() |
| 2585 | .batch_size(batch_size) |
| 2586 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2587 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2588 | } |
| 2589 | } |
| 2590 | } |
| 2591 | |
| 2592 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X8, y_zero_point) { |
| 2593 | TEST_REQUIRES_X86_SSE41; |
| 2594 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 2595 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 2596 | VAddCMicrokernelTester() |
| 2597 | .batch_size(batch_size) |
| 2598 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2599 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2600 | } |
| 2601 | } |
| 2602 | } |
| 2603 | |
| 2604 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X8, a_scale) { |
| 2605 | TEST_REQUIRES_X86_SSE41; |
| 2606 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 2607 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 2608 | VAddCMicrokernelTester() |
| 2609 | .batch_size(batch_size) |
| 2610 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2611 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2612 | } |
| 2613 | } |
| 2614 | } |
| 2615 | |
| 2616 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X8, b_scale) { |
| 2617 | TEST_REQUIRES_X86_SSE41; |
| 2618 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 2619 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 2620 | VAddCMicrokernelTester() |
| 2621 | .batch_size(batch_size) |
| 2622 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2623 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2624 | } |
| 2625 | } |
| 2626 | } |
| 2627 | |
| 2628 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X8, y_scale) { |
| 2629 | TEST_REQUIRES_X86_SSE41; |
| 2630 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 2631 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 2632 | VAddCMicrokernelTester() |
| 2633 | .batch_size(batch_size) |
| 2634 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2635 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2636 | } |
| 2637 | } |
| 2638 | } |
| 2639 | |
| 2640 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X8, qmin) { |
| 2641 | TEST_REQUIRES_X86_SSE41; |
| 2642 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 2643 | VAddCMicrokernelTester() |
| 2644 | .batch_size(batch_size) |
| 2645 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2646 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2647 | } |
| 2648 | } |
| 2649 | |
| 2650 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X8, qmax) { |
| 2651 | TEST_REQUIRES_X86_SSE41; |
| 2652 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 2653 | VAddCMicrokernelTester() |
| 2654 | .batch_size(batch_size) |
| 2655 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2656 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2657 | } |
| 2658 | } |
| 2659 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2660 | |
| 2661 | |
| 2662 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2663 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X16, batch_eq_16) { |
| 2664 | TEST_REQUIRES_X86_SSE41; |
| 2665 | VAddCMicrokernelTester() |
| 2666 | .batch_size(16) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2667 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2668 | } |
| 2669 | |
| 2670 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X16, batch_div_16) { |
| 2671 | TEST_REQUIRES_X86_SSE41; |
| 2672 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 2673 | VAddCMicrokernelTester() |
| 2674 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2675 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2676 | } |
| 2677 | } |
| 2678 | |
| 2679 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X16, batch_lt_16) { |
| 2680 | TEST_REQUIRES_X86_SSE41; |
| 2681 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 2682 | VAddCMicrokernelTester() |
| 2683 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2684 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2685 | } |
| 2686 | } |
| 2687 | |
| 2688 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X16, batch_gt_16) { |
| 2689 | TEST_REQUIRES_X86_SSE41; |
| 2690 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 2691 | VAddCMicrokernelTester() |
| 2692 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2693 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2694 | } |
| 2695 | } |
| 2696 | |
| 2697 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X16, inplace) { |
| 2698 | TEST_REQUIRES_X86_SSE41; |
| 2699 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 2700 | VAddCMicrokernelTester() |
| 2701 | .batch_size(batch_size) |
| 2702 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2703 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2704 | } |
| 2705 | } |
| 2706 | |
| 2707 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X16, a_zero_point) { |
| 2708 | TEST_REQUIRES_X86_SSE41; |
| 2709 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 2710 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 2711 | VAddCMicrokernelTester() |
| 2712 | .batch_size(batch_size) |
| 2713 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2714 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2715 | } |
| 2716 | } |
| 2717 | } |
| 2718 | |
| 2719 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X16, b_zero_point) { |
| 2720 | TEST_REQUIRES_X86_SSE41; |
| 2721 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 2722 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 2723 | VAddCMicrokernelTester() |
| 2724 | .batch_size(batch_size) |
| 2725 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2726 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2727 | } |
| 2728 | } |
| 2729 | } |
| 2730 | |
| 2731 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X16, y_zero_point) { |
| 2732 | TEST_REQUIRES_X86_SSE41; |
| 2733 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 2734 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 2735 | VAddCMicrokernelTester() |
| 2736 | .batch_size(batch_size) |
| 2737 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2738 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2739 | } |
| 2740 | } |
| 2741 | } |
| 2742 | |
| 2743 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X16, a_scale) { |
| 2744 | TEST_REQUIRES_X86_SSE41; |
| 2745 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 2746 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 2747 | VAddCMicrokernelTester() |
| 2748 | .batch_size(batch_size) |
| 2749 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2750 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2751 | } |
| 2752 | } |
| 2753 | } |
| 2754 | |
| 2755 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X16, b_scale) { |
| 2756 | TEST_REQUIRES_X86_SSE41; |
| 2757 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 2758 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 2759 | VAddCMicrokernelTester() |
| 2760 | .batch_size(batch_size) |
| 2761 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2762 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2763 | } |
| 2764 | } |
| 2765 | } |
| 2766 | |
| 2767 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X16, y_scale) { |
| 2768 | TEST_REQUIRES_X86_SSE41; |
| 2769 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 2770 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 2771 | VAddCMicrokernelTester() |
| 2772 | .batch_size(batch_size) |
| 2773 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2774 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2775 | } |
| 2776 | } |
| 2777 | } |
| 2778 | |
| 2779 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X16, qmin) { |
| 2780 | TEST_REQUIRES_X86_SSE41; |
| 2781 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 2782 | VAddCMicrokernelTester() |
| 2783 | .batch_size(batch_size) |
| 2784 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2785 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2786 | } |
| 2787 | } |
| 2788 | |
| 2789 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X16, qmax) { |
| 2790 | TEST_REQUIRES_X86_SSE41; |
| 2791 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 2792 | VAddCMicrokernelTester() |
| 2793 | .batch_size(batch_size) |
| 2794 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2795 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2796 | } |
| 2797 | } |
| 2798 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2799 | |
| 2800 | |
| 2801 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2802 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X24, batch_eq_24) { |
| 2803 | TEST_REQUIRES_X86_SSE41; |
| 2804 | VAddCMicrokernelTester() |
| 2805 | .batch_size(24) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2806 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2807 | } |
| 2808 | |
| 2809 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X24, batch_div_24) { |
| 2810 | TEST_REQUIRES_X86_SSE41; |
| 2811 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 2812 | VAddCMicrokernelTester() |
| 2813 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2814 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2815 | } |
| 2816 | } |
| 2817 | |
| 2818 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X24, batch_lt_24) { |
| 2819 | TEST_REQUIRES_X86_SSE41; |
| 2820 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 2821 | VAddCMicrokernelTester() |
| 2822 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2823 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2824 | } |
| 2825 | } |
| 2826 | |
| 2827 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X24, batch_gt_24) { |
| 2828 | TEST_REQUIRES_X86_SSE41; |
| 2829 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 2830 | VAddCMicrokernelTester() |
| 2831 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2832 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2833 | } |
| 2834 | } |
| 2835 | |
| 2836 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X24, inplace) { |
| 2837 | TEST_REQUIRES_X86_SSE41; |
| 2838 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 2839 | VAddCMicrokernelTester() |
| 2840 | .batch_size(batch_size) |
| 2841 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2842 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2843 | } |
| 2844 | } |
| 2845 | |
| 2846 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X24, a_zero_point) { |
| 2847 | TEST_REQUIRES_X86_SSE41; |
| 2848 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 2849 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 2850 | VAddCMicrokernelTester() |
| 2851 | .batch_size(batch_size) |
| 2852 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2853 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2854 | } |
| 2855 | } |
| 2856 | } |
| 2857 | |
| 2858 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X24, b_zero_point) { |
| 2859 | TEST_REQUIRES_X86_SSE41; |
| 2860 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 2861 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 2862 | VAddCMicrokernelTester() |
| 2863 | .batch_size(batch_size) |
| 2864 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2865 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2866 | } |
| 2867 | } |
| 2868 | } |
| 2869 | |
| 2870 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X24, y_zero_point) { |
| 2871 | TEST_REQUIRES_X86_SSE41; |
| 2872 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 2873 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 2874 | VAddCMicrokernelTester() |
| 2875 | .batch_size(batch_size) |
| 2876 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2877 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2878 | } |
| 2879 | } |
| 2880 | } |
| 2881 | |
| 2882 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X24, a_scale) { |
| 2883 | TEST_REQUIRES_X86_SSE41; |
| 2884 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 2885 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 2886 | VAddCMicrokernelTester() |
| 2887 | .batch_size(batch_size) |
| 2888 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2889 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2890 | } |
| 2891 | } |
| 2892 | } |
| 2893 | |
| 2894 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X24, b_scale) { |
| 2895 | TEST_REQUIRES_X86_SSE41; |
| 2896 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 2897 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 2898 | VAddCMicrokernelTester() |
| 2899 | .batch_size(batch_size) |
| 2900 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2901 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2902 | } |
| 2903 | } |
| 2904 | } |
| 2905 | |
| 2906 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X24, y_scale) { |
| 2907 | TEST_REQUIRES_X86_SSE41; |
| 2908 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 2909 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 2910 | VAddCMicrokernelTester() |
| 2911 | .batch_size(batch_size) |
| 2912 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2913 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2914 | } |
| 2915 | } |
| 2916 | } |
| 2917 | |
| 2918 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X24, qmin) { |
| 2919 | TEST_REQUIRES_X86_SSE41; |
| 2920 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 2921 | VAddCMicrokernelTester() |
| 2922 | .batch_size(batch_size) |
| 2923 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2924 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2925 | } |
| 2926 | } |
| 2927 | |
| 2928 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X24, qmax) { |
| 2929 | TEST_REQUIRES_X86_SSE41; |
| 2930 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 2931 | VAddCMicrokernelTester() |
| 2932 | .batch_size(batch_size) |
| 2933 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2934 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2935 | } |
| 2936 | } |
| 2937 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2938 | |
| 2939 | |
| 2940 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 2941 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X32, batch_eq_32) { |
| 2942 | TEST_REQUIRES_X86_SSE41; |
| 2943 | VAddCMicrokernelTester() |
| 2944 | .batch_size(32) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2945 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2946 | } |
| 2947 | |
| 2948 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X32, batch_div_32) { |
| 2949 | TEST_REQUIRES_X86_SSE41; |
| 2950 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 2951 | VAddCMicrokernelTester() |
| 2952 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2953 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2954 | } |
| 2955 | } |
| 2956 | |
| 2957 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X32, batch_lt_32) { |
| 2958 | TEST_REQUIRES_X86_SSE41; |
| 2959 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 2960 | VAddCMicrokernelTester() |
| 2961 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2962 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2963 | } |
| 2964 | } |
| 2965 | |
| 2966 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X32, batch_gt_32) { |
| 2967 | TEST_REQUIRES_X86_SSE41; |
| 2968 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 2969 | VAddCMicrokernelTester() |
| 2970 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2971 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2972 | } |
| 2973 | } |
| 2974 | |
| 2975 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X32, inplace) { |
| 2976 | TEST_REQUIRES_X86_SSE41; |
| 2977 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 2978 | VAddCMicrokernelTester() |
| 2979 | .batch_size(batch_size) |
| 2980 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2981 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2982 | } |
| 2983 | } |
| 2984 | |
| 2985 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X32, a_zero_point) { |
| 2986 | TEST_REQUIRES_X86_SSE41; |
| 2987 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 2988 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 2989 | VAddCMicrokernelTester() |
| 2990 | .batch_size(batch_size) |
| 2991 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 2992 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 2993 | } |
| 2994 | } |
| 2995 | } |
| 2996 | |
| 2997 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X32, b_zero_point) { |
| 2998 | TEST_REQUIRES_X86_SSE41; |
| 2999 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 3000 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 3001 | VAddCMicrokernelTester() |
| 3002 | .batch_size(batch_size) |
| 3003 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3004 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3005 | } |
| 3006 | } |
| 3007 | } |
| 3008 | |
| 3009 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X32, y_zero_point) { |
| 3010 | TEST_REQUIRES_X86_SSE41; |
| 3011 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 3012 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 3013 | VAddCMicrokernelTester() |
| 3014 | .batch_size(batch_size) |
| 3015 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3016 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3017 | } |
| 3018 | } |
| 3019 | } |
| 3020 | |
| 3021 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X32, a_scale) { |
| 3022 | TEST_REQUIRES_X86_SSE41; |
| 3023 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 3024 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 3025 | VAddCMicrokernelTester() |
| 3026 | .batch_size(batch_size) |
| 3027 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3028 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3029 | } |
| 3030 | } |
| 3031 | } |
| 3032 | |
| 3033 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X32, b_scale) { |
| 3034 | TEST_REQUIRES_X86_SSE41; |
| 3035 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 3036 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 3037 | VAddCMicrokernelTester() |
| 3038 | .batch_size(batch_size) |
| 3039 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3040 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3041 | } |
| 3042 | } |
| 3043 | } |
| 3044 | |
| 3045 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X32, y_scale) { |
| 3046 | TEST_REQUIRES_X86_SSE41; |
| 3047 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 3048 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 3049 | VAddCMicrokernelTester() |
| 3050 | .batch_size(batch_size) |
| 3051 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3052 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3053 | } |
| 3054 | } |
| 3055 | } |
| 3056 | |
| 3057 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X32, qmin) { |
| 3058 | TEST_REQUIRES_X86_SSE41; |
| 3059 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 3060 | VAddCMicrokernelTester() |
| 3061 | .batch_size(batch_size) |
| 3062 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3063 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3064 | } |
| 3065 | } |
| 3066 | |
| 3067 | TEST(QS8_VADDC_MINMAX__SSE41_MUL32_LD32_X32, qmax) { |
| 3068 | TEST_REQUIRES_X86_SSE41; |
| 3069 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 3070 | VAddCMicrokernelTester() |
| 3071 | .batch_size(batch_size) |
| 3072 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3073 | .Test(xnn_qs8_vaddc_minmax_ukernel__sse41_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3074 | } |
| 3075 | } |
| 3076 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 3077 | |
| 3078 | |
| 3079 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3080 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X8, batch_eq_8) { |
| 3081 | TEST_REQUIRES_X86_AVX; |
| 3082 | VAddCMicrokernelTester() |
| 3083 | .batch_size(8) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3084 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3085 | } |
| 3086 | |
| 3087 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X8, batch_div_8) { |
| 3088 | TEST_REQUIRES_X86_AVX; |
| 3089 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 3090 | VAddCMicrokernelTester() |
| 3091 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3092 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3093 | } |
| 3094 | } |
| 3095 | |
| 3096 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X8, batch_lt_8) { |
| 3097 | TEST_REQUIRES_X86_AVX; |
| 3098 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 3099 | VAddCMicrokernelTester() |
| 3100 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3101 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3102 | } |
| 3103 | } |
| 3104 | |
| 3105 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X8, batch_gt_8) { |
| 3106 | TEST_REQUIRES_X86_AVX; |
| 3107 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 3108 | VAddCMicrokernelTester() |
| 3109 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3110 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3111 | } |
| 3112 | } |
| 3113 | |
| 3114 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X8, inplace) { |
| 3115 | TEST_REQUIRES_X86_AVX; |
| 3116 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 3117 | VAddCMicrokernelTester() |
| 3118 | .batch_size(batch_size) |
| 3119 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3120 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3121 | } |
| 3122 | } |
| 3123 | |
| 3124 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X8, a_zero_point) { |
| 3125 | TEST_REQUIRES_X86_AVX; |
| 3126 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 3127 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 3128 | VAddCMicrokernelTester() |
| 3129 | .batch_size(batch_size) |
| 3130 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3131 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3132 | } |
| 3133 | } |
| 3134 | } |
| 3135 | |
| 3136 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X8, b_zero_point) { |
| 3137 | TEST_REQUIRES_X86_AVX; |
| 3138 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 3139 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 3140 | VAddCMicrokernelTester() |
| 3141 | .batch_size(batch_size) |
| 3142 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3143 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3144 | } |
| 3145 | } |
| 3146 | } |
| 3147 | |
| 3148 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X8, y_zero_point) { |
| 3149 | TEST_REQUIRES_X86_AVX; |
| 3150 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 3151 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 3152 | VAddCMicrokernelTester() |
| 3153 | .batch_size(batch_size) |
| 3154 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3155 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3156 | } |
| 3157 | } |
| 3158 | } |
| 3159 | |
| 3160 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X8, a_scale) { |
| 3161 | TEST_REQUIRES_X86_AVX; |
| 3162 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 3163 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 3164 | VAddCMicrokernelTester() |
| 3165 | .batch_size(batch_size) |
| 3166 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3167 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3168 | } |
| 3169 | } |
| 3170 | } |
| 3171 | |
| 3172 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X8, b_scale) { |
| 3173 | TEST_REQUIRES_X86_AVX; |
| 3174 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 3175 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 3176 | VAddCMicrokernelTester() |
| 3177 | .batch_size(batch_size) |
| 3178 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3179 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3180 | } |
| 3181 | } |
| 3182 | } |
| 3183 | |
| 3184 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X8, y_scale) { |
| 3185 | TEST_REQUIRES_X86_AVX; |
| 3186 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 3187 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 3188 | VAddCMicrokernelTester() |
| 3189 | .batch_size(batch_size) |
| 3190 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3191 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3192 | } |
| 3193 | } |
| 3194 | } |
| 3195 | |
| 3196 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X8, qmin) { |
| 3197 | TEST_REQUIRES_X86_AVX; |
| 3198 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 3199 | VAddCMicrokernelTester() |
| 3200 | .batch_size(batch_size) |
| 3201 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3202 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3203 | } |
| 3204 | } |
| 3205 | |
| 3206 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X8, qmax) { |
| 3207 | TEST_REQUIRES_X86_AVX; |
| 3208 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 3209 | VAddCMicrokernelTester() |
| 3210 | .batch_size(batch_size) |
| 3211 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3212 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3213 | } |
| 3214 | } |
| 3215 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 3216 | |
| 3217 | |
| 3218 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 3219 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X16, batch_eq_16) { |
| 3220 | TEST_REQUIRES_X86_AVX; |
| 3221 | VAddCMicrokernelTester() |
| 3222 | .batch_size(16) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3223 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3224 | } |
| 3225 | |
| 3226 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X16, batch_div_16) { |
| 3227 | TEST_REQUIRES_X86_AVX; |
| 3228 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 3229 | VAddCMicrokernelTester() |
| 3230 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3231 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3232 | } |
| 3233 | } |
| 3234 | |
| 3235 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X16, batch_lt_16) { |
| 3236 | TEST_REQUIRES_X86_AVX; |
| 3237 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 3238 | VAddCMicrokernelTester() |
| 3239 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3240 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3241 | } |
| 3242 | } |
| 3243 | |
| 3244 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X16, batch_gt_16) { |
| 3245 | TEST_REQUIRES_X86_AVX; |
| 3246 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 3247 | VAddCMicrokernelTester() |
| 3248 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3249 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3250 | } |
| 3251 | } |
| 3252 | |
| 3253 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X16, inplace) { |
| 3254 | TEST_REQUIRES_X86_AVX; |
| 3255 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 3256 | VAddCMicrokernelTester() |
| 3257 | .batch_size(batch_size) |
| 3258 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3259 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3260 | } |
| 3261 | } |
| 3262 | |
| 3263 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X16, a_zero_point) { |
| 3264 | TEST_REQUIRES_X86_AVX; |
| 3265 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 3266 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 3267 | VAddCMicrokernelTester() |
| 3268 | .batch_size(batch_size) |
| 3269 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3270 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3271 | } |
| 3272 | } |
| 3273 | } |
| 3274 | |
| 3275 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X16, b_zero_point) { |
| 3276 | TEST_REQUIRES_X86_AVX; |
| 3277 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 3278 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 3279 | VAddCMicrokernelTester() |
| 3280 | .batch_size(batch_size) |
| 3281 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3282 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3283 | } |
| 3284 | } |
| 3285 | } |
| 3286 | |
| 3287 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X16, y_zero_point) { |
| 3288 | TEST_REQUIRES_X86_AVX; |
| 3289 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 3290 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 3291 | VAddCMicrokernelTester() |
| 3292 | .batch_size(batch_size) |
| 3293 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3294 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3295 | } |
| 3296 | } |
| 3297 | } |
| 3298 | |
| 3299 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X16, a_scale) { |
| 3300 | TEST_REQUIRES_X86_AVX; |
| 3301 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 3302 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 3303 | VAddCMicrokernelTester() |
| 3304 | .batch_size(batch_size) |
| 3305 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3306 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3307 | } |
| 3308 | } |
| 3309 | } |
| 3310 | |
| 3311 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X16, b_scale) { |
| 3312 | TEST_REQUIRES_X86_AVX; |
| 3313 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 3314 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 3315 | VAddCMicrokernelTester() |
| 3316 | .batch_size(batch_size) |
| 3317 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3318 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3319 | } |
| 3320 | } |
| 3321 | } |
| 3322 | |
| 3323 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X16, y_scale) { |
| 3324 | TEST_REQUIRES_X86_AVX; |
| 3325 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 3326 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 3327 | VAddCMicrokernelTester() |
| 3328 | .batch_size(batch_size) |
| 3329 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3330 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3331 | } |
| 3332 | } |
| 3333 | } |
| 3334 | |
| 3335 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X16, qmin) { |
| 3336 | TEST_REQUIRES_X86_AVX; |
| 3337 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 3338 | VAddCMicrokernelTester() |
| 3339 | .batch_size(batch_size) |
| 3340 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3341 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3342 | } |
| 3343 | } |
| 3344 | |
| 3345 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X16, qmax) { |
| 3346 | TEST_REQUIRES_X86_AVX; |
| 3347 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 3348 | VAddCMicrokernelTester() |
| 3349 | .batch_size(batch_size) |
| 3350 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3351 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3352 | } |
| 3353 | } |
| 3354 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 3355 | |
| 3356 | |
| 3357 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 3358 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X24, batch_eq_24) { |
| 3359 | TEST_REQUIRES_X86_AVX; |
| 3360 | VAddCMicrokernelTester() |
| 3361 | .batch_size(24) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3362 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3363 | } |
| 3364 | |
| 3365 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X24, batch_div_24) { |
| 3366 | TEST_REQUIRES_X86_AVX; |
| 3367 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 3368 | VAddCMicrokernelTester() |
| 3369 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3370 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3371 | } |
| 3372 | } |
| 3373 | |
| 3374 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X24, batch_lt_24) { |
| 3375 | TEST_REQUIRES_X86_AVX; |
| 3376 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 3377 | VAddCMicrokernelTester() |
| 3378 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3379 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3380 | } |
| 3381 | } |
| 3382 | |
| 3383 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X24, batch_gt_24) { |
| 3384 | TEST_REQUIRES_X86_AVX; |
| 3385 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 3386 | VAddCMicrokernelTester() |
| 3387 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3388 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3389 | } |
| 3390 | } |
| 3391 | |
| 3392 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X24, inplace) { |
| 3393 | TEST_REQUIRES_X86_AVX; |
| 3394 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 3395 | VAddCMicrokernelTester() |
| 3396 | .batch_size(batch_size) |
| 3397 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3398 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3399 | } |
| 3400 | } |
| 3401 | |
| 3402 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X24, a_zero_point) { |
| 3403 | TEST_REQUIRES_X86_AVX; |
| 3404 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 3405 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 3406 | VAddCMicrokernelTester() |
| 3407 | .batch_size(batch_size) |
| 3408 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3409 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3410 | } |
| 3411 | } |
| 3412 | } |
| 3413 | |
| 3414 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X24, b_zero_point) { |
| 3415 | TEST_REQUIRES_X86_AVX; |
| 3416 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 3417 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 3418 | VAddCMicrokernelTester() |
| 3419 | .batch_size(batch_size) |
| 3420 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3421 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3422 | } |
| 3423 | } |
| 3424 | } |
| 3425 | |
| 3426 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X24, y_zero_point) { |
| 3427 | TEST_REQUIRES_X86_AVX; |
| 3428 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 3429 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 3430 | VAddCMicrokernelTester() |
| 3431 | .batch_size(batch_size) |
| 3432 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3433 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3434 | } |
| 3435 | } |
| 3436 | } |
| 3437 | |
| 3438 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X24, a_scale) { |
| 3439 | TEST_REQUIRES_X86_AVX; |
| 3440 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 3441 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 3442 | VAddCMicrokernelTester() |
| 3443 | .batch_size(batch_size) |
| 3444 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3445 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3446 | } |
| 3447 | } |
| 3448 | } |
| 3449 | |
| 3450 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X24, b_scale) { |
| 3451 | TEST_REQUIRES_X86_AVX; |
| 3452 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 3453 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 3454 | VAddCMicrokernelTester() |
| 3455 | .batch_size(batch_size) |
| 3456 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3457 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3458 | } |
| 3459 | } |
| 3460 | } |
| 3461 | |
| 3462 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X24, y_scale) { |
| 3463 | TEST_REQUIRES_X86_AVX; |
| 3464 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 3465 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 3466 | VAddCMicrokernelTester() |
| 3467 | .batch_size(batch_size) |
| 3468 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3469 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3470 | } |
| 3471 | } |
| 3472 | } |
| 3473 | |
| 3474 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X24, qmin) { |
| 3475 | TEST_REQUIRES_X86_AVX; |
| 3476 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 3477 | VAddCMicrokernelTester() |
| 3478 | .batch_size(batch_size) |
| 3479 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3480 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3481 | } |
| 3482 | } |
| 3483 | |
| 3484 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X24, qmax) { |
| 3485 | TEST_REQUIRES_X86_AVX; |
| 3486 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 3487 | VAddCMicrokernelTester() |
| 3488 | .batch_size(batch_size) |
| 3489 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3490 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3491 | } |
| 3492 | } |
| 3493 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 3494 | |
| 3495 | |
| 3496 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 3497 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X32, batch_eq_32) { |
| 3498 | TEST_REQUIRES_X86_AVX; |
| 3499 | VAddCMicrokernelTester() |
| 3500 | .batch_size(32) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3501 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3502 | } |
| 3503 | |
| 3504 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X32, batch_div_32) { |
| 3505 | TEST_REQUIRES_X86_AVX; |
| 3506 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 3507 | VAddCMicrokernelTester() |
| 3508 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3509 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3510 | } |
| 3511 | } |
| 3512 | |
| 3513 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X32, batch_lt_32) { |
| 3514 | TEST_REQUIRES_X86_AVX; |
| 3515 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 3516 | VAddCMicrokernelTester() |
| 3517 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3518 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3519 | } |
| 3520 | } |
| 3521 | |
| 3522 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X32, batch_gt_32) { |
| 3523 | TEST_REQUIRES_X86_AVX; |
| 3524 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 3525 | VAddCMicrokernelTester() |
| 3526 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3527 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3528 | } |
| 3529 | } |
| 3530 | |
| 3531 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X32, inplace) { |
| 3532 | TEST_REQUIRES_X86_AVX; |
| 3533 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 3534 | VAddCMicrokernelTester() |
| 3535 | .batch_size(batch_size) |
| 3536 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3537 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3538 | } |
| 3539 | } |
| 3540 | |
| 3541 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X32, a_zero_point) { |
| 3542 | TEST_REQUIRES_X86_AVX; |
| 3543 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 3544 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 3545 | VAddCMicrokernelTester() |
| 3546 | .batch_size(batch_size) |
| 3547 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3548 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3549 | } |
| 3550 | } |
| 3551 | } |
| 3552 | |
| 3553 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X32, b_zero_point) { |
| 3554 | TEST_REQUIRES_X86_AVX; |
| 3555 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 3556 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 3557 | VAddCMicrokernelTester() |
| 3558 | .batch_size(batch_size) |
| 3559 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3560 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3561 | } |
| 3562 | } |
| 3563 | } |
| 3564 | |
| 3565 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X32, y_zero_point) { |
| 3566 | TEST_REQUIRES_X86_AVX; |
| 3567 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 3568 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 3569 | VAddCMicrokernelTester() |
| 3570 | .batch_size(batch_size) |
| 3571 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3572 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3573 | } |
| 3574 | } |
| 3575 | } |
| 3576 | |
| 3577 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X32, a_scale) { |
| 3578 | TEST_REQUIRES_X86_AVX; |
| 3579 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 3580 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 3581 | VAddCMicrokernelTester() |
| 3582 | .batch_size(batch_size) |
| 3583 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3584 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3585 | } |
| 3586 | } |
| 3587 | } |
| 3588 | |
| 3589 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X32, b_scale) { |
| 3590 | TEST_REQUIRES_X86_AVX; |
| 3591 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 3592 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 3593 | VAddCMicrokernelTester() |
| 3594 | .batch_size(batch_size) |
| 3595 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3596 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3597 | } |
| 3598 | } |
| 3599 | } |
| 3600 | |
| 3601 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X32, y_scale) { |
| 3602 | TEST_REQUIRES_X86_AVX; |
| 3603 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 3604 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 3605 | VAddCMicrokernelTester() |
| 3606 | .batch_size(batch_size) |
| 3607 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3608 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3609 | } |
| 3610 | } |
| 3611 | } |
| 3612 | |
| 3613 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X32, qmin) { |
| 3614 | TEST_REQUIRES_X86_AVX; |
| 3615 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 3616 | VAddCMicrokernelTester() |
| 3617 | .batch_size(batch_size) |
| 3618 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3619 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3620 | } |
| 3621 | } |
| 3622 | |
| 3623 | TEST(QS8_VADDC_MINMAX__AVX_MUL32_LD32_X32, qmax) { |
| 3624 | TEST_REQUIRES_X86_AVX; |
| 3625 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 3626 | VAddCMicrokernelTester() |
| 3627 | .batch_size(batch_size) |
| 3628 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3629 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | e9c4b96 | 2021-04-02 16:56:55 -0700 | [diff] [blame] | 3630 | } |
| 3631 | } |
| 3632 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 3633 | |
| 3634 | |
| 3635 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3636 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X8, batch_eq_8) { |
| 3637 | TEST_REQUIRES_X86_XOP; |
| 3638 | VAddCMicrokernelTester() |
| 3639 | .batch_size(8) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3640 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3641 | } |
| 3642 | |
| 3643 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X8, batch_div_8) { |
| 3644 | TEST_REQUIRES_X86_XOP; |
| 3645 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 3646 | VAddCMicrokernelTester() |
| 3647 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3648 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3649 | } |
| 3650 | } |
| 3651 | |
| 3652 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X8, batch_lt_8) { |
| 3653 | TEST_REQUIRES_X86_XOP; |
| 3654 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 3655 | VAddCMicrokernelTester() |
| 3656 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3657 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3658 | } |
| 3659 | } |
| 3660 | |
| 3661 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X8, batch_gt_8) { |
| 3662 | TEST_REQUIRES_X86_XOP; |
| 3663 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 3664 | VAddCMicrokernelTester() |
| 3665 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3666 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3667 | } |
| 3668 | } |
| 3669 | |
| 3670 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X8, inplace) { |
| 3671 | TEST_REQUIRES_X86_XOP; |
| 3672 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 3673 | VAddCMicrokernelTester() |
| 3674 | .batch_size(batch_size) |
| 3675 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3676 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3677 | } |
| 3678 | } |
| 3679 | |
| 3680 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X8, a_zero_point) { |
| 3681 | TEST_REQUIRES_X86_XOP; |
| 3682 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 3683 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 3684 | VAddCMicrokernelTester() |
| 3685 | .batch_size(batch_size) |
| 3686 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3687 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3688 | } |
| 3689 | } |
| 3690 | } |
| 3691 | |
| 3692 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X8, b_zero_point) { |
| 3693 | TEST_REQUIRES_X86_XOP; |
| 3694 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 3695 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 3696 | VAddCMicrokernelTester() |
| 3697 | .batch_size(batch_size) |
| 3698 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3699 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3700 | } |
| 3701 | } |
| 3702 | } |
| 3703 | |
| 3704 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X8, y_zero_point) { |
| 3705 | TEST_REQUIRES_X86_XOP; |
| 3706 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 3707 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 3708 | VAddCMicrokernelTester() |
| 3709 | .batch_size(batch_size) |
| 3710 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3711 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3712 | } |
| 3713 | } |
| 3714 | } |
| 3715 | |
| 3716 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X8, a_scale) { |
| 3717 | TEST_REQUIRES_X86_XOP; |
| 3718 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 3719 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 3720 | VAddCMicrokernelTester() |
| 3721 | .batch_size(batch_size) |
| 3722 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3723 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3724 | } |
| 3725 | } |
| 3726 | } |
| 3727 | |
| 3728 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X8, b_scale) { |
| 3729 | TEST_REQUIRES_X86_XOP; |
| 3730 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 3731 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 3732 | VAddCMicrokernelTester() |
| 3733 | .batch_size(batch_size) |
| 3734 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3735 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3736 | } |
| 3737 | } |
| 3738 | } |
| 3739 | |
| 3740 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X8, y_scale) { |
| 3741 | TEST_REQUIRES_X86_XOP; |
| 3742 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 3743 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 3744 | VAddCMicrokernelTester() |
| 3745 | .batch_size(batch_size) |
| 3746 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3747 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3748 | } |
| 3749 | } |
| 3750 | } |
| 3751 | |
| 3752 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X8, qmin) { |
| 3753 | TEST_REQUIRES_X86_XOP; |
| 3754 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 3755 | VAddCMicrokernelTester() |
| 3756 | .batch_size(batch_size) |
| 3757 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3758 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3759 | } |
| 3760 | } |
| 3761 | |
| 3762 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X8, qmax) { |
| 3763 | TEST_REQUIRES_X86_XOP; |
| 3764 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 3765 | VAddCMicrokernelTester() |
| 3766 | .batch_size(batch_size) |
| 3767 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3768 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x8, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3769 | } |
| 3770 | } |
| 3771 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 3772 | |
| 3773 | |
| 3774 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 3775 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X16, batch_eq_16) { |
| 3776 | TEST_REQUIRES_X86_XOP; |
| 3777 | VAddCMicrokernelTester() |
| 3778 | .batch_size(16) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3779 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3780 | } |
| 3781 | |
| 3782 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X16, batch_div_16) { |
| 3783 | TEST_REQUIRES_X86_XOP; |
| 3784 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 3785 | VAddCMicrokernelTester() |
| 3786 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3787 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3788 | } |
| 3789 | } |
| 3790 | |
| 3791 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X16, batch_lt_16) { |
| 3792 | TEST_REQUIRES_X86_XOP; |
| 3793 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 3794 | VAddCMicrokernelTester() |
| 3795 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3796 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3797 | } |
| 3798 | } |
| 3799 | |
| 3800 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X16, batch_gt_16) { |
| 3801 | TEST_REQUIRES_X86_XOP; |
| 3802 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 3803 | VAddCMicrokernelTester() |
| 3804 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3805 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3806 | } |
| 3807 | } |
| 3808 | |
| 3809 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X16, inplace) { |
| 3810 | TEST_REQUIRES_X86_XOP; |
| 3811 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 3812 | VAddCMicrokernelTester() |
| 3813 | .batch_size(batch_size) |
| 3814 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3815 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3816 | } |
| 3817 | } |
| 3818 | |
| 3819 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X16, a_zero_point) { |
| 3820 | TEST_REQUIRES_X86_XOP; |
| 3821 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 3822 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 3823 | VAddCMicrokernelTester() |
| 3824 | .batch_size(batch_size) |
| 3825 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3826 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3827 | } |
| 3828 | } |
| 3829 | } |
| 3830 | |
| 3831 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X16, b_zero_point) { |
| 3832 | TEST_REQUIRES_X86_XOP; |
| 3833 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 3834 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 3835 | VAddCMicrokernelTester() |
| 3836 | .batch_size(batch_size) |
| 3837 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3838 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3839 | } |
| 3840 | } |
| 3841 | } |
| 3842 | |
| 3843 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X16, y_zero_point) { |
| 3844 | TEST_REQUIRES_X86_XOP; |
| 3845 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 3846 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 3847 | VAddCMicrokernelTester() |
| 3848 | .batch_size(batch_size) |
| 3849 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3850 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3851 | } |
| 3852 | } |
| 3853 | } |
| 3854 | |
| 3855 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X16, a_scale) { |
| 3856 | TEST_REQUIRES_X86_XOP; |
| 3857 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 3858 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 3859 | VAddCMicrokernelTester() |
| 3860 | .batch_size(batch_size) |
| 3861 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3862 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3863 | } |
| 3864 | } |
| 3865 | } |
| 3866 | |
| 3867 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X16, b_scale) { |
| 3868 | TEST_REQUIRES_X86_XOP; |
| 3869 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 3870 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 3871 | VAddCMicrokernelTester() |
| 3872 | .batch_size(batch_size) |
| 3873 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3874 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3875 | } |
| 3876 | } |
| 3877 | } |
| 3878 | |
| 3879 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X16, y_scale) { |
| 3880 | TEST_REQUIRES_X86_XOP; |
| 3881 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 3882 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 3883 | VAddCMicrokernelTester() |
| 3884 | .batch_size(batch_size) |
| 3885 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3886 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3887 | } |
| 3888 | } |
| 3889 | } |
| 3890 | |
| 3891 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X16, qmin) { |
| 3892 | TEST_REQUIRES_X86_XOP; |
| 3893 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 3894 | VAddCMicrokernelTester() |
| 3895 | .batch_size(batch_size) |
| 3896 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3897 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3898 | } |
| 3899 | } |
| 3900 | |
| 3901 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X16, qmax) { |
| 3902 | TEST_REQUIRES_X86_XOP; |
| 3903 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 3904 | VAddCMicrokernelTester() |
| 3905 | .batch_size(batch_size) |
| 3906 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3907 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x16, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3908 | } |
| 3909 | } |
| 3910 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 3911 | |
| 3912 | |
| 3913 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 3914 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X24, batch_eq_24) { |
| 3915 | TEST_REQUIRES_X86_XOP; |
| 3916 | VAddCMicrokernelTester() |
| 3917 | .batch_size(24) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3918 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3919 | } |
| 3920 | |
| 3921 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X24, batch_div_24) { |
| 3922 | TEST_REQUIRES_X86_XOP; |
| 3923 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 3924 | VAddCMicrokernelTester() |
| 3925 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3926 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3927 | } |
| 3928 | } |
| 3929 | |
| 3930 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X24, batch_lt_24) { |
| 3931 | TEST_REQUIRES_X86_XOP; |
| 3932 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 3933 | VAddCMicrokernelTester() |
| 3934 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3935 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3936 | } |
| 3937 | } |
| 3938 | |
| 3939 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X24, batch_gt_24) { |
| 3940 | TEST_REQUIRES_X86_XOP; |
| 3941 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 3942 | VAddCMicrokernelTester() |
| 3943 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3944 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3945 | } |
| 3946 | } |
| 3947 | |
| 3948 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X24, inplace) { |
| 3949 | TEST_REQUIRES_X86_XOP; |
| 3950 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 3951 | VAddCMicrokernelTester() |
| 3952 | .batch_size(batch_size) |
| 3953 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3954 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3955 | } |
| 3956 | } |
| 3957 | |
| 3958 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X24, a_zero_point) { |
| 3959 | TEST_REQUIRES_X86_XOP; |
| 3960 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 3961 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 3962 | VAddCMicrokernelTester() |
| 3963 | .batch_size(batch_size) |
| 3964 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3965 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3966 | } |
| 3967 | } |
| 3968 | } |
| 3969 | |
| 3970 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X24, b_zero_point) { |
| 3971 | TEST_REQUIRES_X86_XOP; |
| 3972 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 3973 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 3974 | VAddCMicrokernelTester() |
| 3975 | .batch_size(batch_size) |
| 3976 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3977 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3978 | } |
| 3979 | } |
| 3980 | } |
| 3981 | |
| 3982 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X24, y_zero_point) { |
| 3983 | TEST_REQUIRES_X86_XOP; |
| 3984 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 3985 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 3986 | VAddCMicrokernelTester() |
| 3987 | .batch_size(batch_size) |
| 3988 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 3989 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 3990 | } |
| 3991 | } |
| 3992 | } |
| 3993 | |
| 3994 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X24, a_scale) { |
| 3995 | TEST_REQUIRES_X86_XOP; |
| 3996 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 3997 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 3998 | VAddCMicrokernelTester() |
| 3999 | .batch_size(batch_size) |
| 4000 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4001 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 4002 | } |
| 4003 | } |
| 4004 | } |
| 4005 | |
| 4006 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X24, b_scale) { |
| 4007 | TEST_REQUIRES_X86_XOP; |
| 4008 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 4009 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 4010 | VAddCMicrokernelTester() |
| 4011 | .batch_size(batch_size) |
| 4012 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4013 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 4014 | } |
| 4015 | } |
| 4016 | } |
| 4017 | |
| 4018 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X24, y_scale) { |
| 4019 | TEST_REQUIRES_X86_XOP; |
| 4020 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 4021 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 4022 | VAddCMicrokernelTester() |
| 4023 | .batch_size(batch_size) |
| 4024 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4025 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 4026 | } |
| 4027 | } |
| 4028 | } |
| 4029 | |
| 4030 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X24, qmin) { |
| 4031 | TEST_REQUIRES_X86_XOP; |
| 4032 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 4033 | VAddCMicrokernelTester() |
| 4034 | .batch_size(batch_size) |
| 4035 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4036 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 4037 | } |
| 4038 | } |
| 4039 | |
| 4040 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X24, qmax) { |
| 4041 | TEST_REQUIRES_X86_XOP; |
| 4042 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 4043 | VAddCMicrokernelTester() |
| 4044 | .batch_size(batch_size) |
| 4045 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4046 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x24, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 4047 | } |
| 4048 | } |
| 4049 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4050 | |
| 4051 | |
| 4052 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4053 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X32, batch_eq_32) { |
| 4054 | TEST_REQUIRES_X86_XOP; |
| 4055 | VAddCMicrokernelTester() |
| 4056 | .batch_size(32) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4057 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 4058 | } |
| 4059 | |
| 4060 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X32, batch_div_32) { |
| 4061 | TEST_REQUIRES_X86_XOP; |
| 4062 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 4063 | VAddCMicrokernelTester() |
| 4064 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4065 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 4066 | } |
| 4067 | } |
| 4068 | |
| 4069 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X32, batch_lt_32) { |
| 4070 | TEST_REQUIRES_X86_XOP; |
| 4071 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 4072 | VAddCMicrokernelTester() |
| 4073 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4074 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 4075 | } |
| 4076 | } |
| 4077 | |
| 4078 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X32, batch_gt_32) { |
| 4079 | TEST_REQUIRES_X86_XOP; |
| 4080 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 4081 | VAddCMicrokernelTester() |
| 4082 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4083 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 4084 | } |
| 4085 | } |
| 4086 | |
| 4087 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X32, inplace) { |
| 4088 | TEST_REQUIRES_X86_XOP; |
| 4089 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4090 | VAddCMicrokernelTester() |
| 4091 | .batch_size(batch_size) |
| 4092 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4093 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 4094 | } |
| 4095 | } |
| 4096 | |
| 4097 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X32, a_zero_point) { |
| 4098 | TEST_REQUIRES_X86_XOP; |
| 4099 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4100 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 4101 | VAddCMicrokernelTester() |
| 4102 | .batch_size(batch_size) |
| 4103 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4104 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 4105 | } |
| 4106 | } |
| 4107 | } |
| 4108 | |
| 4109 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X32, b_zero_point) { |
| 4110 | TEST_REQUIRES_X86_XOP; |
| 4111 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4112 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 4113 | VAddCMicrokernelTester() |
| 4114 | .batch_size(batch_size) |
| 4115 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4116 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 4117 | } |
| 4118 | } |
| 4119 | } |
| 4120 | |
| 4121 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X32, y_zero_point) { |
| 4122 | TEST_REQUIRES_X86_XOP; |
| 4123 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4124 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 4125 | VAddCMicrokernelTester() |
| 4126 | .batch_size(batch_size) |
| 4127 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4128 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 4129 | } |
| 4130 | } |
| 4131 | } |
| 4132 | |
| 4133 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X32, a_scale) { |
| 4134 | TEST_REQUIRES_X86_XOP; |
| 4135 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4136 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 4137 | VAddCMicrokernelTester() |
| 4138 | .batch_size(batch_size) |
| 4139 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4140 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 4141 | } |
| 4142 | } |
| 4143 | } |
| 4144 | |
| 4145 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X32, b_scale) { |
| 4146 | TEST_REQUIRES_X86_XOP; |
| 4147 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4148 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 4149 | VAddCMicrokernelTester() |
| 4150 | .batch_size(batch_size) |
| 4151 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4152 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 4153 | } |
| 4154 | } |
| 4155 | } |
| 4156 | |
| 4157 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X32, y_scale) { |
| 4158 | TEST_REQUIRES_X86_XOP; |
| 4159 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4160 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 4161 | VAddCMicrokernelTester() |
| 4162 | .batch_size(batch_size) |
| 4163 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4164 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 4165 | } |
| 4166 | } |
| 4167 | } |
| 4168 | |
| 4169 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X32, qmin) { |
| 4170 | TEST_REQUIRES_X86_XOP; |
| 4171 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4172 | VAddCMicrokernelTester() |
| 4173 | .batch_size(batch_size) |
| 4174 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4175 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 4176 | } |
| 4177 | } |
| 4178 | |
| 4179 | TEST(QS8_VADDC_MINMAX__XOP_MUL32_LD32_X32, qmax) { |
| 4180 | TEST_REQUIRES_X86_XOP; |
| 4181 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4182 | VAddCMicrokernelTester() |
| 4183 | .batch_size(batch_size) |
| 4184 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4185 | .Test(xnn_qs8_vaddc_minmax_ukernel__xop_mul32_ld32_x32, xnn_init_qs8_add_minmax_sse4_mul32_params); |
Marat Dukhan | bb9225e | 2020-09-06 22:40:56 -0700 | [diff] [blame] | 4186 | } |
| 4187 | } |
| 4188 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4189 | |
| 4190 | |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4191 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4192 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X8, batch_eq_8) { |
| 4193 | TEST_REQUIRES_X86_AVX2; |
| 4194 | VAddCMicrokernelTester() |
| 4195 | .batch_size(8) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4196 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x8, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4197 | } |
| 4198 | |
| 4199 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X8, batch_div_8) { |
| 4200 | TEST_REQUIRES_X86_AVX2; |
| 4201 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 4202 | VAddCMicrokernelTester() |
| 4203 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4204 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x8, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4205 | } |
| 4206 | } |
| 4207 | |
| 4208 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X8, batch_lt_8) { |
| 4209 | TEST_REQUIRES_X86_AVX2; |
| 4210 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 4211 | VAddCMicrokernelTester() |
| 4212 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4213 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x8, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4214 | } |
| 4215 | } |
| 4216 | |
| 4217 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X8, batch_gt_8) { |
| 4218 | TEST_REQUIRES_X86_AVX2; |
| 4219 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 4220 | VAddCMicrokernelTester() |
| 4221 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4222 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x8, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4223 | } |
| 4224 | } |
| 4225 | |
| 4226 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X8, inplace) { |
| 4227 | TEST_REQUIRES_X86_AVX2; |
| 4228 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 4229 | VAddCMicrokernelTester() |
| 4230 | .batch_size(batch_size) |
| 4231 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4232 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x8, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4233 | } |
| 4234 | } |
| 4235 | |
| 4236 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X8, a_zero_point) { |
| 4237 | TEST_REQUIRES_X86_AVX2; |
| 4238 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 4239 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 4240 | VAddCMicrokernelTester() |
| 4241 | .batch_size(batch_size) |
| 4242 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4243 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x8, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4244 | } |
| 4245 | } |
| 4246 | } |
| 4247 | |
| 4248 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X8, b_zero_point) { |
| 4249 | TEST_REQUIRES_X86_AVX2; |
| 4250 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 4251 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 4252 | VAddCMicrokernelTester() |
| 4253 | .batch_size(batch_size) |
| 4254 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4255 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x8, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4256 | } |
| 4257 | } |
| 4258 | } |
| 4259 | |
| 4260 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X8, y_zero_point) { |
| 4261 | TEST_REQUIRES_X86_AVX2; |
| 4262 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 4263 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 4264 | VAddCMicrokernelTester() |
| 4265 | .batch_size(batch_size) |
| 4266 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4267 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x8, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4268 | } |
| 4269 | } |
| 4270 | } |
| 4271 | |
| 4272 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X8, a_scale) { |
| 4273 | TEST_REQUIRES_X86_AVX2; |
| 4274 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 4275 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 4276 | VAddCMicrokernelTester() |
| 4277 | .batch_size(batch_size) |
| 4278 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4279 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x8, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4280 | } |
| 4281 | } |
| 4282 | } |
| 4283 | |
| 4284 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X8, b_scale) { |
| 4285 | TEST_REQUIRES_X86_AVX2; |
| 4286 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 4287 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 4288 | VAddCMicrokernelTester() |
| 4289 | .batch_size(batch_size) |
| 4290 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4291 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x8, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4292 | } |
| 4293 | } |
| 4294 | } |
| 4295 | |
| 4296 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X8, y_scale) { |
| 4297 | TEST_REQUIRES_X86_AVX2; |
| 4298 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 4299 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 4300 | VAddCMicrokernelTester() |
| 4301 | .batch_size(batch_size) |
| 4302 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4303 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x8, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4304 | } |
| 4305 | } |
| 4306 | } |
| 4307 | |
| 4308 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X8, qmin) { |
| 4309 | TEST_REQUIRES_X86_AVX2; |
| 4310 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 4311 | VAddCMicrokernelTester() |
| 4312 | .batch_size(batch_size) |
| 4313 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4314 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x8, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4315 | } |
| 4316 | } |
| 4317 | |
| 4318 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X8, qmax) { |
| 4319 | TEST_REQUIRES_X86_AVX2; |
| 4320 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 4321 | VAddCMicrokernelTester() |
| 4322 | .batch_size(batch_size) |
| 4323 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4324 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x8, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4325 | } |
| 4326 | } |
| 4327 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4328 | |
| 4329 | |
| 4330 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4331 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X16, batch_eq_16) { |
| 4332 | TEST_REQUIRES_X86_AVX2; |
| 4333 | VAddCMicrokernelTester() |
| 4334 | .batch_size(16) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4335 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x16, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4336 | } |
| 4337 | |
| 4338 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X16, batch_div_16) { |
| 4339 | TEST_REQUIRES_X86_AVX2; |
| 4340 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 4341 | VAddCMicrokernelTester() |
| 4342 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4343 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x16, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4344 | } |
| 4345 | } |
| 4346 | |
| 4347 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X16, batch_lt_16) { |
| 4348 | TEST_REQUIRES_X86_AVX2; |
| 4349 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 4350 | VAddCMicrokernelTester() |
| 4351 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4352 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x16, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4353 | } |
| 4354 | } |
| 4355 | |
| 4356 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X16, batch_gt_16) { |
| 4357 | TEST_REQUIRES_X86_AVX2; |
| 4358 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 4359 | VAddCMicrokernelTester() |
| 4360 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4361 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x16, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4362 | } |
| 4363 | } |
| 4364 | |
| 4365 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X16, inplace) { |
| 4366 | TEST_REQUIRES_X86_AVX2; |
| 4367 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 4368 | VAddCMicrokernelTester() |
| 4369 | .batch_size(batch_size) |
| 4370 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4371 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x16, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4372 | } |
| 4373 | } |
| 4374 | |
| 4375 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X16, a_zero_point) { |
| 4376 | TEST_REQUIRES_X86_AVX2; |
| 4377 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 4378 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 4379 | VAddCMicrokernelTester() |
| 4380 | .batch_size(batch_size) |
| 4381 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4382 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x16, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4383 | } |
| 4384 | } |
| 4385 | } |
| 4386 | |
| 4387 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X16, b_zero_point) { |
| 4388 | TEST_REQUIRES_X86_AVX2; |
| 4389 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 4390 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 4391 | VAddCMicrokernelTester() |
| 4392 | .batch_size(batch_size) |
| 4393 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4394 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x16, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4395 | } |
| 4396 | } |
| 4397 | } |
| 4398 | |
| 4399 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X16, y_zero_point) { |
| 4400 | TEST_REQUIRES_X86_AVX2; |
| 4401 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 4402 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 4403 | VAddCMicrokernelTester() |
| 4404 | .batch_size(batch_size) |
| 4405 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4406 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x16, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4407 | } |
| 4408 | } |
| 4409 | } |
| 4410 | |
| 4411 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X16, a_scale) { |
| 4412 | TEST_REQUIRES_X86_AVX2; |
| 4413 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 4414 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 4415 | VAddCMicrokernelTester() |
| 4416 | .batch_size(batch_size) |
| 4417 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4418 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x16, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4419 | } |
| 4420 | } |
| 4421 | } |
| 4422 | |
| 4423 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X16, b_scale) { |
| 4424 | TEST_REQUIRES_X86_AVX2; |
| 4425 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 4426 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 4427 | VAddCMicrokernelTester() |
| 4428 | .batch_size(batch_size) |
| 4429 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4430 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x16, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4431 | } |
| 4432 | } |
| 4433 | } |
| 4434 | |
| 4435 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X16, y_scale) { |
| 4436 | TEST_REQUIRES_X86_AVX2; |
| 4437 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 4438 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 4439 | VAddCMicrokernelTester() |
| 4440 | .batch_size(batch_size) |
| 4441 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4442 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x16, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4443 | } |
| 4444 | } |
| 4445 | } |
| 4446 | |
| 4447 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X16, qmin) { |
| 4448 | TEST_REQUIRES_X86_AVX2; |
| 4449 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 4450 | VAddCMicrokernelTester() |
| 4451 | .batch_size(batch_size) |
| 4452 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4453 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x16, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4454 | } |
| 4455 | } |
| 4456 | |
| 4457 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X16, qmax) { |
| 4458 | TEST_REQUIRES_X86_AVX2; |
| 4459 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 4460 | VAddCMicrokernelTester() |
| 4461 | .batch_size(batch_size) |
| 4462 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4463 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x16, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4464 | } |
| 4465 | } |
| 4466 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4467 | |
| 4468 | |
| 4469 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4470 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X24, batch_eq_24) { |
| 4471 | TEST_REQUIRES_X86_AVX2; |
| 4472 | VAddCMicrokernelTester() |
| 4473 | .batch_size(24) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4474 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x24, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4475 | } |
| 4476 | |
| 4477 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X24, batch_div_24) { |
| 4478 | TEST_REQUIRES_X86_AVX2; |
| 4479 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 4480 | VAddCMicrokernelTester() |
| 4481 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4482 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x24, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4483 | } |
| 4484 | } |
| 4485 | |
| 4486 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X24, batch_lt_24) { |
| 4487 | TEST_REQUIRES_X86_AVX2; |
| 4488 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 4489 | VAddCMicrokernelTester() |
| 4490 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4491 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x24, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4492 | } |
| 4493 | } |
| 4494 | |
| 4495 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X24, batch_gt_24) { |
| 4496 | TEST_REQUIRES_X86_AVX2; |
| 4497 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 4498 | VAddCMicrokernelTester() |
| 4499 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4500 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x24, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4501 | } |
| 4502 | } |
| 4503 | |
| 4504 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X24, inplace) { |
| 4505 | TEST_REQUIRES_X86_AVX2; |
| 4506 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 4507 | VAddCMicrokernelTester() |
| 4508 | .batch_size(batch_size) |
| 4509 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4510 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x24, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4511 | } |
| 4512 | } |
| 4513 | |
| 4514 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X24, a_zero_point) { |
| 4515 | TEST_REQUIRES_X86_AVX2; |
| 4516 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 4517 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 4518 | VAddCMicrokernelTester() |
| 4519 | .batch_size(batch_size) |
| 4520 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4521 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x24, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4522 | } |
| 4523 | } |
| 4524 | } |
| 4525 | |
| 4526 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X24, b_zero_point) { |
| 4527 | TEST_REQUIRES_X86_AVX2; |
| 4528 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 4529 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 4530 | VAddCMicrokernelTester() |
| 4531 | .batch_size(batch_size) |
| 4532 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4533 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x24, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4534 | } |
| 4535 | } |
| 4536 | } |
| 4537 | |
| 4538 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X24, y_zero_point) { |
| 4539 | TEST_REQUIRES_X86_AVX2; |
| 4540 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 4541 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 4542 | VAddCMicrokernelTester() |
| 4543 | .batch_size(batch_size) |
| 4544 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4545 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x24, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4546 | } |
| 4547 | } |
| 4548 | } |
| 4549 | |
| 4550 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X24, a_scale) { |
| 4551 | TEST_REQUIRES_X86_AVX2; |
| 4552 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 4553 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 4554 | VAddCMicrokernelTester() |
| 4555 | .batch_size(batch_size) |
| 4556 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4557 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x24, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4558 | } |
| 4559 | } |
| 4560 | } |
| 4561 | |
| 4562 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X24, b_scale) { |
| 4563 | TEST_REQUIRES_X86_AVX2; |
| 4564 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 4565 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 4566 | VAddCMicrokernelTester() |
| 4567 | .batch_size(batch_size) |
| 4568 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4569 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x24, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4570 | } |
| 4571 | } |
| 4572 | } |
| 4573 | |
| 4574 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X24, y_scale) { |
| 4575 | TEST_REQUIRES_X86_AVX2; |
| 4576 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 4577 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 4578 | VAddCMicrokernelTester() |
| 4579 | .batch_size(batch_size) |
| 4580 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4581 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x24, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4582 | } |
| 4583 | } |
| 4584 | } |
| 4585 | |
| 4586 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X24, qmin) { |
| 4587 | TEST_REQUIRES_X86_AVX2; |
| 4588 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 4589 | VAddCMicrokernelTester() |
| 4590 | .batch_size(batch_size) |
| 4591 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4592 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x24, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4593 | } |
| 4594 | } |
| 4595 | |
| 4596 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X24, qmax) { |
| 4597 | TEST_REQUIRES_X86_AVX2; |
| 4598 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 4599 | VAddCMicrokernelTester() |
| 4600 | .batch_size(batch_size) |
| 4601 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4602 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x24, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4603 | } |
| 4604 | } |
| 4605 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4606 | |
| 4607 | |
| 4608 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4609 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X32, batch_eq_32) { |
| 4610 | TEST_REQUIRES_X86_AVX2; |
| 4611 | VAddCMicrokernelTester() |
| 4612 | .batch_size(32) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4613 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x32, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4614 | } |
| 4615 | |
| 4616 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X32, batch_div_32) { |
| 4617 | TEST_REQUIRES_X86_AVX2; |
| 4618 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 4619 | VAddCMicrokernelTester() |
| 4620 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4621 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x32, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4622 | } |
| 4623 | } |
| 4624 | |
| 4625 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X32, batch_lt_32) { |
| 4626 | TEST_REQUIRES_X86_AVX2; |
| 4627 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 4628 | VAddCMicrokernelTester() |
| 4629 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4630 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x32, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4631 | } |
| 4632 | } |
| 4633 | |
| 4634 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X32, batch_gt_32) { |
| 4635 | TEST_REQUIRES_X86_AVX2; |
| 4636 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 4637 | VAddCMicrokernelTester() |
| 4638 | .batch_size(batch_size) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4639 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x32, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4640 | } |
| 4641 | } |
| 4642 | |
| 4643 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X32, inplace) { |
| 4644 | TEST_REQUIRES_X86_AVX2; |
| 4645 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4646 | VAddCMicrokernelTester() |
| 4647 | .batch_size(batch_size) |
| 4648 | .inplace(true) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4649 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x32, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4650 | } |
| 4651 | } |
| 4652 | |
| 4653 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X32, a_zero_point) { |
| 4654 | TEST_REQUIRES_X86_AVX2; |
| 4655 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4656 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 4657 | VAddCMicrokernelTester() |
| 4658 | .batch_size(batch_size) |
| 4659 | .a_zero_point(a_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4660 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x32, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4661 | } |
| 4662 | } |
| 4663 | } |
| 4664 | |
| 4665 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X32, b_zero_point) { |
| 4666 | TEST_REQUIRES_X86_AVX2; |
| 4667 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4668 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 4669 | VAddCMicrokernelTester() |
| 4670 | .batch_size(batch_size) |
| 4671 | .b_zero_point(b_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4672 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x32, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4673 | } |
| 4674 | } |
| 4675 | } |
| 4676 | |
| 4677 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X32, y_zero_point) { |
| 4678 | TEST_REQUIRES_X86_AVX2; |
| 4679 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4680 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 4681 | VAddCMicrokernelTester() |
| 4682 | .batch_size(batch_size) |
| 4683 | .y_zero_point(y_zero_point) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4684 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x32, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4685 | } |
| 4686 | } |
| 4687 | } |
| 4688 | |
| 4689 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X32, a_scale) { |
| 4690 | TEST_REQUIRES_X86_AVX2; |
| 4691 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4692 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 4693 | VAddCMicrokernelTester() |
| 4694 | .batch_size(batch_size) |
| 4695 | .a_scale(a_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4696 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x32, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4697 | } |
| 4698 | } |
| 4699 | } |
| 4700 | |
| 4701 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X32, b_scale) { |
| 4702 | TEST_REQUIRES_X86_AVX2; |
| 4703 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4704 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 4705 | VAddCMicrokernelTester() |
| 4706 | .batch_size(batch_size) |
| 4707 | .b_scale(b_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4708 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x32, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4709 | } |
| 4710 | } |
| 4711 | } |
| 4712 | |
| 4713 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X32, y_scale) { |
| 4714 | TEST_REQUIRES_X86_AVX2; |
| 4715 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4716 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 4717 | VAddCMicrokernelTester() |
| 4718 | .batch_size(batch_size) |
| 4719 | .y_scale(y_scale) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4720 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x32, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4721 | } |
| 4722 | } |
| 4723 | } |
| 4724 | |
| 4725 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X32, qmin) { |
| 4726 | TEST_REQUIRES_X86_AVX2; |
| 4727 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4728 | VAddCMicrokernelTester() |
| 4729 | .batch_size(batch_size) |
| 4730 | .qmin(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4731 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x32, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4732 | } |
| 4733 | } |
| 4734 | |
| 4735 | TEST(QS8_VADDC_MINMAX__AVX2_MUL32_LD64_X32, qmax) { |
| 4736 | TEST_REQUIRES_X86_AVX2; |
| 4737 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4738 | VAddCMicrokernelTester() |
| 4739 | .batch_size(batch_size) |
| 4740 | .qmax(128) |
Marat Dukhan | 7679b1e | 2021-07-20 18:32:23 -0700 | [diff] [blame] | 4741 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx2_mul32_ld64_x32, xnn_init_qs8_add_minmax_avx2_params); |
Marat Dukhan | e6dc0b6 | 2020-09-08 23:57:14 -0700 | [diff] [blame] | 4742 | } |
| 4743 | } |
| 4744 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4745 | |
| 4746 | |
Marat Dukhan | e76049a | 2021-07-22 14:48:59 -0700 | [diff] [blame] | 4747 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4748 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X16, batch_eq_16) { |
| 4749 | TEST_REQUIRES_X86_AVX512SKX; |
| 4750 | VAddCMicrokernelTester() |
| 4751 | .batch_size(16) |
| 4752 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x16, xnn_init_qs8_add_minmax_avx512_params); |
| 4753 | } |
| 4754 | |
| 4755 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X16, batch_div_16) { |
| 4756 | TEST_REQUIRES_X86_AVX512SKX; |
| 4757 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 4758 | VAddCMicrokernelTester() |
| 4759 | .batch_size(batch_size) |
| 4760 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x16, xnn_init_qs8_add_minmax_avx512_params); |
| 4761 | } |
| 4762 | } |
| 4763 | |
| 4764 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X16, batch_lt_16) { |
| 4765 | TEST_REQUIRES_X86_AVX512SKX; |
| 4766 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 4767 | VAddCMicrokernelTester() |
| 4768 | .batch_size(batch_size) |
| 4769 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x16, xnn_init_qs8_add_minmax_avx512_params); |
| 4770 | } |
| 4771 | } |
| 4772 | |
| 4773 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X16, batch_gt_16) { |
| 4774 | TEST_REQUIRES_X86_AVX512SKX; |
| 4775 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 4776 | VAddCMicrokernelTester() |
| 4777 | .batch_size(batch_size) |
| 4778 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x16, xnn_init_qs8_add_minmax_avx512_params); |
| 4779 | } |
| 4780 | } |
| 4781 | |
| 4782 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X16, inplace) { |
| 4783 | TEST_REQUIRES_X86_AVX512SKX; |
| 4784 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 4785 | VAddCMicrokernelTester() |
| 4786 | .batch_size(batch_size) |
| 4787 | .inplace(true) |
| 4788 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x16, xnn_init_qs8_add_minmax_avx512_params); |
| 4789 | } |
| 4790 | } |
| 4791 | |
| 4792 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X16, a_zero_point) { |
| 4793 | TEST_REQUIRES_X86_AVX512SKX; |
| 4794 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 4795 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 4796 | VAddCMicrokernelTester() |
| 4797 | .batch_size(batch_size) |
| 4798 | .a_zero_point(a_zero_point) |
| 4799 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x16, xnn_init_qs8_add_minmax_avx512_params); |
| 4800 | } |
| 4801 | } |
| 4802 | } |
| 4803 | |
| 4804 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X16, b_zero_point) { |
| 4805 | TEST_REQUIRES_X86_AVX512SKX; |
| 4806 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 4807 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 4808 | VAddCMicrokernelTester() |
| 4809 | .batch_size(batch_size) |
| 4810 | .b_zero_point(b_zero_point) |
| 4811 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x16, xnn_init_qs8_add_minmax_avx512_params); |
| 4812 | } |
| 4813 | } |
| 4814 | } |
| 4815 | |
| 4816 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X16, y_zero_point) { |
| 4817 | TEST_REQUIRES_X86_AVX512SKX; |
| 4818 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 4819 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 4820 | VAddCMicrokernelTester() |
| 4821 | .batch_size(batch_size) |
| 4822 | .y_zero_point(y_zero_point) |
| 4823 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x16, xnn_init_qs8_add_minmax_avx512_params); |
| 4824 | } |
| 4825 | } |
| 4826 | } |
| 4827 | |
| 4828 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X16, a_scale) { |
| 4829 | TEST_REQUIRES_X86_AVX512SKX; |
| 4830 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 4831 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 4832 | VAddCMicrokernelTester() |
| 4833 | .batch_size(batch_size) |
| 4834 | .a_scale(a_scale) |
| 4835 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x16, xnn_init_qs8_add_minmax_avx512_params); |
| 4836 | } |
| 4837 | } |
| 4838 | } |
| 4839 | |
| 4840 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X16, b_scale) { |
| 4841 | TEST_REQUIRES_X86_AVX512SKX; |
| 4842 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 4843 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 4844 | VAddCMicrokernelTester() |
| 4845 | .batch_size(batch_size) |
| 4846 | .b_scale(b_scale) |
| 4847 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x16, xnn_init_qs8_add_minmax_avx512_params); |
| 4848 | } |
| 4849 | } |
| 4850 | } |
| 4851 | |
| 4852 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X16, y_scale) { |
| 4853 | TEST_REQUIRES_X86_AVX512SKX; |
| 4854 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 4855 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 4856 | VAddCMicrokernelTester() |
| 4857 | .batch_size(batch_size) |
| 4858 | .y_scale(y_scale) |
| 4859 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x16, xnn_init_qs8_add_minmax_avx512_params); |
| 4860 | } |
| 4861 | } |
| 4862 | } |
| 4863 | |
| 4864 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X16, qmin) { |
| 4865 | TEST_REQUIRES_X86_AVX512SKX; |
| 4866 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 4867 | VAddCMicrokernelTester() |
| 4868 | .batch_size(batch_size) |
| 4869 | .qmin(128) |
| 4870 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x16, xnn_init_qs8_add_minmax_avx512_params); |
| 4871 | } |
| 4872 | } |
| 4873 | |
| 4874 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X16, qmax) { |
| 4875 | TEST_REQUIRES_X86_AVX512SKX; |
| 4876 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 4877 | VAddCMicrokernelTester() |
| 4878 | .batch_size(batch_size) |
| 4879 | .qmax(128) |
| 4880 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x16, xnn_init_qs8_add_minmax_avx512_params); |
| 4881 | } |
| 4882 | } |
| 4883 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4884 | |
| 4885 | |
| 4886 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 4887 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X32, batch_eq_32) { |
| 4888 | TEST_REQUIRES_X86_AVX512SKX; |
| 4889 | VAddCMicrokernelTester() |
| 4890 | .batch_size(32) |
| 4891 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x32, xnn_init_qs8_add_minmax_avx512_params); |
| 4892 | } |
| 4893 | |
| 4894 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X32, batch_div_32) { |
| 4895 | TEST_REQUIRES_X86_AVX512SKX; |
| 4896 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 4897 | VAddCMicrokernelTester() |
| 4898 | .batch_size(batch_size) |
| 4899 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x32, xnn_init_qs8_add_minmax_avx512_params); |
| 4900 | } |
| 4901 | } |
| 4902 | |
| 4903 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X32, batch_lt_32) { |
| 4904 | TEST_REQUIRES_X86_AVX512SKX; |
| 4905 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 4906 | VAddCMicrokernelTester() |
| 4907 | .batch_size(batch_size) |
| 4908 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x32, xnn_init_qs8_add_minmax_avx512_params); |
| 4909 | } |
| 4910 | } |
| 4911 | |
| 4912 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X32, batch_gt_32) { |
| 4913 | TEST_REQUIRES_X86_AVX512SKX; |
| 4914 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 4915 | VAddCMicrokernelTester() |
| 4916 | .batch_size(batch_size) |
| 4917 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x32, xnn_init_qs8_add_minmax_avx512_params); |
| 4918 | } |
| 4919 | } |
| 4920 | |
| 4921 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X32, inplace) { |
| 4922 | TEST_REQUIRES_X86_AVX512SKX; |
| 4923 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4924 | VAddCMicrokernelTester() |
| 4925 | .batch_size(batch_size) |
| 4926 | .inplace(true) |
| 4927 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x32, xnn_init_qs8_add_minmax_avx512_params); |
| 4928 | } |
| 4929 | } |
| 4930 | |
| 4931 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X32, a_zero_point) { |
| 4932 | TEST_REQUIRES_X86_AVX512SKX; |
| 4933 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4934 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 4935 | VAddCMicrokernelTester() |
| 4936 | .batch_size(batch_size) |
| 4937 | .a_zero_point(a_zero_point) |
| 4938 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x32, xnn_init_qs8_add_minmax_avx512_params); |
| 4939 | } |
| 4940 | } |
| 4941 | } |
| 4942 | |
| 4943 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X32, b_zero_point) { |
| 4944 | TEST_REQUIRES_X86_AVX512SKX; |
| 4945 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4946 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 4947 | VAddCMicrokernelTester() |
| 4948 | .batch_size(batch_size) |
| 4949 | .b_zero_point(b_zero_point) |
| 4950 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x32, xnn_init_qs8_add_minmax_avx512_params); |
| 4951 | } |
| 4952 | } |
| 4953 | } |
| 4954 | |
| 4955 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X32, y_zero_point) { |
| 4956 | TEST_REQUIRES_X86_AVX512SKX; |
| 4957 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4958 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 4959 | VAddCMicrokernelTester() |
| 4960 | .batch_size(batch_size) |
| 4961 | .y_zero_point(y_zero_point) |
| 4962 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x32, xnn_init_qs8_add_minmax_avx512_params); |
| 4963 | } |
| 4964 | } |
| 4965 | } |
| 4966 | |
| 4967 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X32, a_scale) { |
| 4968 | TEST_REQUIRES_X86_AVX512SKX; |
| 4969 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4970 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 4971 | VAddCMicrokernelTester() |
| 4972 | .batch_size(batch_size) |
| 4973 | .a_scale(a_scale) |
| 4974 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x32, xnn_init_qs8_add_minmax_avx512_params); |
| 4975 | } |
| 4976 | } |
| 4977 | } |
| 4978 | |
| 4979 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X32, b_scale) { |
| 4980 | TEST_REQUIRES_X86_AVX512SKX; |
| 4981 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4982 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 4983 | VAddCMicrokernelTester() |
| 4984 | .batch_size(batch_size) |
| 4985 | .b_scale(b_scale) |
| 4986 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x32, xnn_init_qs8_add_minmax_avx512_params); |
| 4987 | } |
| 4988 | } |
| 4989 | } |
| 4990 | |
| 4991 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X32, y_scale) { |
| 4992 | TEST_REQUIRES_X86_AVX512SKX; |
| 4993 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 4994 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 4995 | VAddCMicrokernelTester() |
| 4996 | .batch_size(batch_size) |
| 4997 | .y_scale(y_scale) |
| 4998 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x32, xnn_init_qs8_add_minmax_avx512_params); |
| 4999 | } |
| 5000 | } |
| 5001 | } |
| 5002 | |
| 5003 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X32, qmin) { |
| 5004 | TEST_REQUIRES_X86_AVX512SKX; |
| 5005 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 5006 | VAddCMicrokernelTester() |
| 5007 | .batch_size(batch_size) |
| 5008 | .qmin(128) |
| 5009 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x32, xnn_init_qs8_add_minmax_avx512_params); |
| 5010 | } |
| 5011 | } |
| 5012 | |
| 5013 | TEST(QS8_VADDC_MINMAX__AVX512SKX_MUL32_LD128_X32, qmax) { |
| 5014 | TEST_REQUIRES_X86_AVX512SKX; |
| 5015 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 5016 | VAddCMicrokernelTester() |
| 5017 | .batch_size(batch_size) |
| 5018 | .qmax(128) |
| 5019 | .Test(xnn_qs8_vaddc_minmax_ukernel__avx512skx_mul32_ld128_x32, xnn_init_qs8_add_minmax_avx512_params); |
| 5020 | } |
| 5021 | } |
| 5022 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5023 | |
| 5024 | |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 5025 | #if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5026 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X8, batch_eq_8) { |
| 5027 | VAddCMicrokernelTester() |
| 5028 | .batch_size(8) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5029 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x8, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5030 | } |
| 5031 | |
| 5032 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X8, batch_div_8) { |
| 5033 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 5034 | VAddCMicrokernelTester() |
| 5035 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5036 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x8, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5037 | } |
| 5038 | } |
| 5039 | |
| 5040 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X8, batch_lt_8) { |
| 5041 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 5042 | VAddCMicrokernelTester() |
| 5043 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5044 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x8, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5045 | } |
| 5046 | } |
| 5047 | |
| 5048 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X8, batch_gt_8) { |
| 5049 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 5050 | VAddCMicrokernelTester() |
| 5051 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5052 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x8, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5053 | } |
| 5054 | } |
| 5055 | |
| 5056 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X8, inplace) { |
| 5057 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 5058 | VAddCMicrokernelTester() |
| 5059 | .batch_size(batch_size) |
| 5060 | .inplace(true) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5061 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x8, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5062 | } |
| 5063 | } |
| 5064 | |
| 5065 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X8, a_zero_point) { |
| 5066 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 5067 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 5068 | VAddCMicrokernelTester() |
| 5069 | .batch_size(batch_size) |
| 5070 | .a_zero_point(a_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5071 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x8, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5072 | } |
| 5073 | } |
| 5074 | } |
| 5075 | |
| 5076 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X8, b_zero_point) { |
| 5077 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 5078 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 5079 | VAddCMicrokernelTester() |
| 5080 | .batch_size(batch_size) |
| 5081 | .b_zero_point(b_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5082 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x8, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5083 | } |
| 5084 | } |
| 5085 | } |
| 5086 | |
| 5087 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X8, y_zero_point) { |
| 5088 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 5089 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 5090 | VAddCMicrokernelTester() |
| 5091 | .batch_size(batch_size) |
| 5092 | .y_zero_point(y_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5093 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x8, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5094 | } |
| 5095 | } |
| 5096 | } |
| 5097 | |
| 5098 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X8, a_scale) { |
| 5099 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 5100 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 5101 | VAddCMicrokernelTester() |
| 5102 | .batch_size(batch_size) |
| 5103 | .a_scale(a_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5104 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x8, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5105 | } |
| 5106 | } |
| 5107 | } |
| 5108 | |
| 5109 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X8, b_scale) { |
| 5110 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 5111 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 5112 | VAddCMicrokernelTester() |
| 5113 | .batch_size(batch_size) |
| 5114 | .b_scale(b_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5115 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x8, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5116 | } |
| 5117 | } |
| 5118 | } |
| 5119 | |
| 5120 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X8, y_scale) { |
| 5121 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 5122 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 5123 | VAddCMicrokernelTester() |
| 5124 | .batch_size(batch_size) |
| 5125 | .y_scale(y_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5126 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x8, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5127 | } |
| 5128 | } |
| 5129 | } |
| 5130 | |
| 5131 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X8, qmin) { |
| 5132 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 5133 | VAddCMicrokernelTester() |
| 5134 | .batch_size(batch_size) |
| 5135 | .qmin(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5136 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x8, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5137 | } |
| 5138 | } |
| 5139 | |
| 5140 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X8, qmax) { |
| 5141 | for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) { |
| 5142 | VAddCMicrokernelTester() |
| 5143 | .batch_size(batch_size) |
| 5144 | .qmax(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5145 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x8, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5146 | } |
| 5147 | } |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 5148 | #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5149 | |
| 5150 | |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 5151 | #if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5152 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X16, batch_eq_16) { |
| 5153 | VAddCMicrokernelTester() |
| 5154 | .batch_size(16) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5155 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x16, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5156 | } |
| 5157 | |
| 5158 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X16, batch_div_16) { |
| 5159 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 5160 | VAddCMicrokernelTester() |
| 5161 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5162 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x16, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5163 | } |
| 5164 | } |
| 5165 | |
| 5166 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X16, batch_lt_16) { |
| 5167 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 5168 | VAddCMicrokernelTester() |
| 5169 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5170 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x16, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5171 | } |
| 5172 | } |
| 5173 | |
| 5174 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X16, batch_gt_16) { |
| 5175 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 5176 | VAddCMicrokernelTester() |
| 5177 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5178 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x16, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5179 | } |
| 5180 | } |
| 5181 | |
| 5182 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X16, inplace) { |
| 5183 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 5184 | VAddCMicrokernelTester() |
| 5185 | .batch_size(batch_size) |
| 5186 | .inplace(true) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5187 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x16, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5188 | } |
| 5189 | } |
| 5190 | |
| 5191 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X16, a_zero_point) { |
| 5192 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 5193 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 5194 | VAddCMicrokernelTester() |
| 5195 | .batch_size(batch_size) |
| 5196 | .a_zero_point(a_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5197 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x16, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5198 | } |
| 5199 | } |
| 5200 | } |
| 5201 | |
| 5202 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X16, b_zero_point) { |
| 5203 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 5204 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 5205 | VAddCMicrokernelTester() |
| 5206 | .batch_size(batch_size) |
| 5207 | .b_zero_point(b_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5208 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x16, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5209 | } |
| 5210 | } |
| 5211 | } |
| 5212 | |
| 5213 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X16, y_zero_point) { |
| 5214 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 5215 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 5216 | VAddCMicrokernelTester() |
| 5217 | .batch_size(batch_size) |
| 5218 | .y_zero_point(y_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5219 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x16, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5220 | } |
| 5221 | } |
| 5222 | } |
| 5223 | |
| 5224 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X16, a_scale) { |
| 5225 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 5226 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 5227 | VAddCMicrokernelTester() |
| 5228 | .batch_size(batch_size) |
| 5229 | .a_scale(a_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5230 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x16, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5231 | } |
| 5232 | } |
| 5233 | } |
| 5234 | |
| 5235 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X16, b_scale) { |
| 5236 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 5237 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 5238 | VAddCMicrokernelTester() |
| 5239 | .batch_size(batch_size) |
| 5240 | .b_scale(b_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5241 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x16, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5242 | } |
| 5243 | } |
| 5244 | } |
| 5245 | |
| 5246 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X16, y_scale) { |
| 5247 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 5248 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 5249 | VAddCMicrokernelTester() |
| 5250 | .batch_size(batch_size) |
| 5251 | .y_scale(y_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5252 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x16, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5253 | } |
| 5254 | } |
| 5255 | } |
| 5256 | |
| 5257 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X16, qmin) { |
| 5258 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 5259 | VAddCMicrokernelTester() |
| 5260 | .batch_size(batch_size) |
| 5261 | .qmin(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5262 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x16, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5263 | } |
| 5264 | } |
| 5265 | |
| 5266 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X16, qmax) { |
| 5267 | for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) { |
| 5268 | VAddCMicrokernelTester() |
| 5269 | .batch_size(batch_size) |
| 5270 | .qmax(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5271 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x16, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5272 | } |
| 5273 | } |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 5274 | #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5275 | |
| 5276 | |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 5277 | #if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5278 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X24, batch_eq_24) { |
| 5279 | VAddCMicrokernelTester() |
| 5280 | .batch_size(24) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5281 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x24, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5282 | } |
| 5283 | |
| 5284 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X24, batch_div_24) { |
| 5285 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 5286 | VAddCMicrokernelTester() |
| 5287 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5288 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x24, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5289 | } |
| 5290 | } |
| 5291 | |
| 5292 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X24, batch_lt_24) { |
| 5293 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 5294 | VAddCMicrokernelTester() |
| 5295 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5296 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x24, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5297 | } |
| 5298 | } |
| 5299 | |
| 5300 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X24, batch_gt_24) { |
| 5301 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 5302 | VAddCMicrokernelTester() |
| 5303 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5304 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x24, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5305 | } |
| 5306 | } |
| 5307 | |
| 5308 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X24, inplace) { |
| 5309 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 5310 | VAddCMicrokernelTester() |
| 5311 | .batch_size(batch_size) |
| 5312 | .inplace(true) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5313 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x24, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5314 | } |
| 5315 | } |
| 5316 | |
| 5317 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X24, a_zero_point) { |
| 5318 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 5319 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 5320 | VAddCMicrokernelTester() |
| 5321 | .batch_size(batch_size) |
| 5322 | .a_zero_point(a_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5323 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x24, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5324 | } |
| 5325 | } |
| 5326 | } |
| 5327 | |
| 5328 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X24, b_zero_point) { |
| 5329 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 5330 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 5331 | VAddCMicrokernelTester() |
| 5332 | .batch_size(batch_size) |
| 5333 | .b_zero_point(b_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5334 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x24, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5335 | } |
| 5336 | } |
| 5337 | } |
| 5338 | |
| 5339 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X24, y_zero_point) { |
| 5340 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 5341 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 5342 | VAddCMicrokernelTester() |
| 5343 | .batch_size(batch_size) |
| 5344 | .y_zero_point(y_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5345 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x24, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5346 | } |
| 5347 | } |
| 5348 | } |
| 5349 | |
| 5350 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X24, a_scale) { |
| 5351 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 5352 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 5353 | VAddCMicrokernelTester() |
| 5354 | .batch_size(batch_size) |
| 5355 | .a_scale(a_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5356 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x24, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5357 | } |
| 5358 | } |
| 5359 | } |
| 5360 | |
| 5361 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X24, b_scale) { |
| 5362 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 5363 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 5364 | VAddCMicrokernelTester() |
| 5365 | .batch_size(batch_size) |
| 5366 | .b_scale(b_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5367 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x24, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5368 | } |
| 5369 | } |
| 5370 | } |
| 5371 | |
| 5372 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X24, y_scale) { |
| 5373 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 5374 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 5375 | VAddCMicrokernelTester() |
| 5376 | .batch_size(batch_size) |
| 5377 | .y_scale(y_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5378 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x24, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5379 | } |
| 5380 | } |
| 5381 | } |
| 5382 | |
| 5383 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X24, qmin) { |
| 5384 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 5385 | VAddCMicrokernelTester() |
| 5386 | .batch_size(batch_size) |
| 5387 | .qmin(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5388 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x24, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5389 | } |
| 5390 | } |
| 5391 | |
| 5392 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X24, qmax) { |
| 5393 | for (size_t batch_size = 1; batch_size <= 120; batch_size += 23) { |
| 5394 | VAddCMicrokernelTester() |
| 5395 | .batch_size(batch_size) |
| 5396 | .qmax(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5397 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x24, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5398 | } |
| 5399 | } |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 5400 | #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5401 | |
| 5402 | |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 5403 | #if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5404 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X32, batch_eq_32) { |
| 5405 | VAddCMicrokernelTester() |
| 5406 | .batch_size(32) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5407 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x32, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5408 | } |
| 5409 | |
| 5410 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X32, batch_div_32) { |
| 5411 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 5412 | VAddCMicrokernelTester() |
| 5413 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5414 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x32, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5415 | } |
| 5416 | } |
| 5417 | |
| 5418 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X32, batch_lt_32) { |
| 5419 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 5420 | VAddCMicrokernelTester() |
| 5421 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5422 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x32, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5423 | } |
| 5424 | } |
| 5425 | |
| 5426 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X32, batch_gt_32) { |
| 5427 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 5428 | VAddCMicrokernelTester() |
| 5429 | .batch_size(batch_size) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5430 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x32, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5431 | } |
| 5432 | } |
| 5433 | |
| 5434 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X32, inplace) { |
| 5435 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 5436 | VAddCMicrokernelTester() |
| 5437 | .batch_size(batch_size) |
| 5438 | .inplace(true) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5439 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x32, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5440 | } |
| 5441 | } |
| 5442 | |
| 5443 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X32, a_zero_point) { |
| 5444 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 5445 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 5446 | VAddCMicrokernelTester() |
| 5447 | .batch_size(batch_size) |
| 5448 | .a_zero_point(a_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5449 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x32, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5450 | } |
| 5451 | } |
| 5452 | } |
| 5453 | |
| 5454 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X32, b_zero_point) { |
| 5455 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 5456 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 5457 | VAddCMicrokernelTester() |
| 5458 | .batch_size(batch_size) |
| 5459 | .b_zero_point(b_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5460 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x32, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5461 | } |
| 5462 | } |
| 5463 | } |
| 5464 | |
| 5465 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X32, y_zero_point) { |
| 5466 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 5467 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 5468 | VAddCMicrokernelTester() |
| 5469 | .batch_size(batch_size) |
| 5470 | .y_zero_point(y_zero_point) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5471 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x32, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5472 | } |
| 5473 | } |
| 5474 | } |
| 5475 | |
| 5476 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X32, a_scale) { |
| 5477 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 5478 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 5479 | VAddCMicrokernelTester() |
| 5480 | .batch_size(batch_size) |
| 5481 | .a_scale(a_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5482 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x32, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5483 | } |
| 5484 | } |
| 5485 | } |
| 5486 | |
| 5487 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X32, b_scale) { |
| 5488 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 5489 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 5490 | VAddCMicrokernelTester() |
| 5491 | .batch_size(batch_size) |
| 5492 | .b_scale(b_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5493 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x32, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5494 | } |
| 5495 | } |
| 5496 | } |
| 5497 | |
| 5498 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X32, y_scale) { |
| 5499 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 5500 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 5501 | VAddCMicrokernelTester() |
| 5502 | .batch_size(batch_size) |
| 5503 | .y_scale(y_scale) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5504 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x32, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5505 | } |
| 5506 | } |
| 5507 | } |
| 5508 | |
| 5509 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X32, qmin) { |
| 5510 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 5511 | VAddCMicrokernelTester() |
| 5512 | .batch_size(batch_size) |
| 5513 | .qmin(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5514 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x32, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5515 | } |
| 5516 | } |
| 5517 | |
| 5518 | TEST(QS8_VADDC_MINMAX__WASMSIMD_X32, qmax) { |
| 5519 | for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) { |
| 5520 | VAddCMicrokernelTester() |
| 5521 | .batch_size(batch_size) |
| 5522 | .qmax(128) |
Marat Dukhan | 6691324 | 2021-07-20 16:11:23 -0700 | [diff] [blame] | 5523 | .Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x32, xnn_init_qs8_add_minmax_wasmsimd_params); |
Marat Dukhan | 5df27f8 | 2020-09-02 23:59:21 -0700 | [diff] [blame] | 5524 | } |
| 5525 | } |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 5526 | #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5527 | |
| 5528 | |
| 5529 | TEST(QS8_VADDC_MINMAX__SCALAR_X1, batch_eq_1) { |
| 5530 | VAddCMicrokernelTester() |
| 5531 | .batch_size(1) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5532 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x1, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5533 | } |
| 5534 | |
| 5535 | TEST(QS8_VADDC_MINMAX__SCALAR_X1, batch_gt_1) { |
| 5536 | for (size_t batch_size = 2; batch_size < 10; batch_size++) { |
| 5537 | VAddCMicrokernelTester() |
| 5538 | .batch_size(batch_size) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5539 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x1, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5540 | } |
| 5541 | } |
| 5542 | |
| 5543 | TEST(QS8_VADDC_MINMAX__SCALAR_X1, inplace) { |
| 5544 | for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) { |
| 5545 | VAddCMicrokernelTester() |
| 5546 | .batch_size(batch_size) |
| 5547 | .inplace(true) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5548 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x1, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5549 | } |
| 5550 | } |
| 5551 | |
| 5552 | TEST(QS8_VADDC_MINMAX__SCALAR_X1, a_zero_point) { |
| 5553 | for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) { |
| 5554 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 5555 | VAddCMicrokernelTester() |
| 5556 | .batch_size(batch_size) |
| 5557 | .a_zero_point(a_zero_point) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5558 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x1, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5559 | } |
| 5560 | } |
| 5561 | } |
| 5562 | |
| 5563 | TEST(QS8_VADDC_MINMAX__SCALAR_X1, b_zero_point) { |
| 5564 | for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) { |
| 5565 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 5566 | VAddCMicrokernelTester() |
| 5567 | .batch_size(batch_size) |
| 5568 | .b_zero_point(b_zero_point) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5569 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x1, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5570 | } |
| 5571 | } |
| 5572 | } |
| 5573 | |
| 5574 | TEST(QS8_VADDC_MINMAX__SCALAR_X1, y_zero_point) { |
| 5575 | for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) { |
| 5576 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 5577 | VAddCMicrokernelTester() |
| 5578 | .batch_size(batch_size) |
| 5579 | .y_zero_point(y_zero_point) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5580 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x1, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5581 | } |
| 5582 | } |
| 5583 | } |
| 5584 | |
| 5585 | TEST(QS8_VADDC_MINMAX__SCALAR_X1, a_scale) { |
| 5586 | for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) { |
| 5587 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 5588 | VAddCMicrokernelTester() |
| 5589 | .batch_size(batch_size) |
| 5590 | .a_scale(a_scale) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5591 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x1, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5592 | } |
| 5593 | } |
| 5594 | } |
| 5595 | |
| 5596 | TEST(QS8_VADDC_MINMAX__SCALAR_X1, b_scale) { |
| 5597 | for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) { |
| 5598 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 5599 | VAddCMicrokernelTester() |
| 5600 | .batch_size(batch_size) |
| 5601 | .b_scale(b_scale) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5602 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x1, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5603 | } |
| 5604 | } |
| 5605 | } |
| 5606 | |
| 5607 | TEST(QS8_VADDC_MINMAX__SCALAR_X1, y_scale) { |
| 5608 | for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) { |
| 5609 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 5610 | VAddCMicrokernelTester() |
| 5611 | .batch_size(batch_size) |
| 5612 | .y_scale(y_scale) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5613 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x1, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5614 | } |
| 5615 | } |
| 5616 | } |
| 5617 | |
| 5618 | TEST(QS8_VADDC_MINMAX__SCALAR_X1, qmin) { |
| 5619 | for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) { |
| 5620 | VAddCMicrokernelTester() |
| 5621 | .batch_size(batch_size) |
| 5622 | .qmin(128) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5623 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x1, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5624 | } |
| 5625 | } |
| 5626 | |
| 5627 | TEST(QS8_VADDC_MINMAX__SCALAR_X1, qmax) { |
| 5628 | for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) { |
| 5629 | VAddCMicrokernelTester() |
| 5630 | .batch_size(batch_size) |
| 5631 | .qmax(128) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5632 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x1, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5633 | } |
| 5634 | } |
| 5635 | |
| 5636 | TEST(QS8_VADDC_MINMAX__SCALAR_X2, batch_eq_2) { |
| 5637 | VAddCMicrokernelTester() |
| 5638 | .batch_size(2) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5639 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x2, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5640 | } |
| 5641 | |
| 5642 | TEST(QS8_VADDC_MINMAX__SCALAR_X2, batch_div_2) { |
| 5643 | for (size_t batch_size = 4; batch_size < 20; batch_size += 2) { |
| 5644 | VAddCMicrokernelTester() |
| 5645 | .batch_size(batch_size) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5646 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x2, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5647 | } |
| 5648 | } |
| 5649 | |
| 5650 | TEST(QS8_VADDC_MINMAX__SCALAR_X2, batch_lt_2) { |
| 5651 | for (size_t batch_size = 1; batch_size < 2; batch_size++) { |
| 5652 | VAddCMicrokernelTester() |
| 5653 | .batch_size(batch_size) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5654 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x2, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5655 | } |
| 5656 | } |
| 5657 | |
| 5658 | TEST(QS8_VADDC_MINMAX__SCALAR_X2, batch_gt_2) { |
| 5659 | for (size_t batch_size = 3; batch_size < 4; batch_size++) { |
| 5660 | VAddCMicrokernelTester() |
| 5661 | .batch_size(batch_size) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5662 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x2, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5663 | } |
| 5664 | } |
| 5665 | |
| 5666 | TEST(QS8_VADDC_MINMAX__SCALAR_X2, inplace) { |
| 5667 | for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) { |
| 5668 | VAddCMicrokernelTester() |
| 5669 | .batch_size(batch_size) |
| 5670 | .inplace(true) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5671 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x2, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5672 | } |
| 5673 | } |
| 5674 | |
| 5675 | TEST(QS8_VADDC_MINMAX__SCALAR_X2, a_zero_point) { |
| 5676 | for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) { |
| 5677 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 5678 | VAddCMicrokernelTester() |
| 5679 | .batch_size(batch_size) |
| 5680 | .a_zero_point(a_zero_point) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5681 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x2, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5682 | } |
| 5683 | } |
| 5684 | } |
| 5685 | |
| 5686 | TEST(QS8_VADDC_MINMAX__SCALAR_X2, b_zero_point) { |
| 5687 | for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) { |
| 5688 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 5689 | VAddCMicrokernelTester() |
| 5690 | .batch_size(batch_size) |
| 5691 | .b_zero_point(b_zero_point) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5692 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x2, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5693 | } |
| 5694 | } |
| 5695 | } |
| 5696 | |
| 5697 | TEST(QS8_VADDC_MINMAX__SCALAR_X2, y_zero_point) { |
| 5698 | for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) { |
| 5699 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 5700 | VAddCMicrokernelTester() |
| 5701 | .batch_size(batch_size) |
| 5702 | .y_zero_point(y_zero_point) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5703 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x2, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5704 | } |
| 5705 | } |
| 5706 | } |
| 5707 | |
| 5708 | TEST(QS8_VADDC_MINMAX__SCALAR_X2, a_scale) { |
| 5709 | for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) { |
| 5710 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 5711 | VAddCMicrokernelTester() |
| 5712 | .batch_size(batch_size) |
| 5713 | .a_scale(a_scale) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5714 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x2, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5715 | } |
| 5716 | } |
| 5717 | } |
| 5718 | |
| 5719 | TEST(QS8_VADDC_MINMAX__SCALAR_X2, b_scale) { |
| 5720 | for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) { |
| 5721 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 5722 | VAddCMicrokernelTester() |
| 5723 | .batch_size(batch_size) |
| 5724 | .b_scale(b_scale) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5725 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x2, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5726 | } |
| 5727 | } |
| 5728 | } |
| 5729 | |
| 5730 | TEST(QS8_VADDC_MINMAX__SCALAR_X2, y_scale) { |
| 5731 | for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) { |
| 5732 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 5733 | VAddCMicrokernelTester() |
| 5734 | .batch_size(batch_size) |
| 5735 | .y_scale(y_scale) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5736 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x2, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5737 | } |
| 5738 | } |
| 5739 | } |
| 5740 | |
| 5741 | TEST(QS8_VADDC_MINMAX__SCALAR_X2, qmin) { |
| 5742 | for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) { |
| 5743 | VAddCMicrokernelTester() |
| 5744 | .batch_size(batch_size) |
| 5745 | .qmin(128) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5746 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x2, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5747 | } |
| 5748 | } |
| 5749 | |
| 5750 | TEST(QS8_VADDC_MINMAX__SCALAR_X2, qmax) { |
| 5751 | for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) { |
| 5752 | VAddCMicrokernelTester() |
| 5753 | .batch_size(batch_size) |
| 5754 | .qmax(128) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5755 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x2, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5756 | } |
| 5757 | } |
| 5758 | |
| 5759 | TEST(QS8_VADDC_MINMAX__SCALAR_X4, batch_eq_4) { |
| 5760 | VAddCMicrokernelTester() |
| 5761 | .batch_size(4) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5762 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x4, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5763 | } |
| 5764 | |
| 5765 | TEST(QS8_VADDC_MINMAX__SCALAR_X4, batch_div_4) { |
| 5766 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 5767 | VAddCMicrokernelTester() |
| 5768 | .batch_size(batch_size) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5769 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x4, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5770 | } |
| 5771 | } |
| 5772 | |
| 5773 | TEST(QS8_VADDC_MINMAX__SCALAR_X4, batch_lt_4) { |
| 5774 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 5775 | VAddCMicrokernelTester() |
| 5776 | .batch_size(batch_size) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5777 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x4, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5778 | } |
| 5779 | } |
| 5780 | |
| 5781 | TEST(QS8_VADDC_MINMAX__SCALAR_X4, batch_gt_4) { |
| 5782 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 5783 | VAddCMicrokernelTester() |
| 5784 | .batch_size(batch_size) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5785 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x4, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5786 | } |
| 5787 | } |
| 5788 | |
| 5789 | TEST(QS8_VADDC_MINMAX__SCALAR_X4, inplace) { |
| 5790 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 5791 | VAddCMicrokernelTester() |
| 5792 | .batch_size(batch_size) |
| 5793 | .inplace(true) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5794 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x4, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5795 | } |
| 5796 | } |
| 5797 | |
| 5798 | TEST(QS8_VADDC_MINMAX__SCALAR_X4, a_zero_point) { |
| 5799 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 5800 | for (int32_t a_zero_point = -128; a_zero_point <= 127; a_zero_point += 51) { |
| 5801 | VAddCMicrokernelTester() |
| 5802 | .batch_size(batch_size) |
| 5803 | .a_zero_point(a_zero_point) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5804 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x4, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5805 | } |
| 5806 | } |
| 5807 | } |
| 5808 | |
| 5809 | TEST(QS8_VADDC_MINMAX__SCALAR_X4, b_zero_point) { |
| 5810 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 5811 | for (int32_t b_zero_point = -128; b_zero_point <= 127; b_zero_point += 51) { |
| 5812 | VAddCMicrokernelTester() |
| 5813 | .batch_size(batch_size) |
| 5814 | .b_zero_point(b_zero_point) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5815 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x4, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5816 | } |
| 5817 | } |
| 5818 | } |
| 5819 | |
| 5820 | TEST(QS8_VADDC_MINMAX__SCALAR_X4, y_zero_point) { |
| 5821 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 5822 | for (int32_t y_zero_point = -128; y_zero_point <= 127; y_zero_point += 51) { |
| 5823 | VAddCMicrokernelTester() |
| 5824 | .batch_size(batch_size) |
| 5825 | .y_zero_point(y_zero_point) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5826 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x4, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5827 | } |
| 5828 | } |
| 5829 | } |
| 5830 | |
| 5831 | TEST(QS8_VADDC_MINMAX__SCALAR_X4, a_scale) { |
| 5832 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 5833 | for (float a_scale = 0.1f; a_scale <= 10.0f; a_scale *= 3.14f) { |
| 5834 | VAddCMicrokernelTester() |
| 5835 | .batch_size(batch_size) |
| 5836 | .a_scale(a_scale) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5837 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x4, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5838 | } |
| 5839 | } |
| 5840 | } |
| 5841 | |
| 5842 | TEST(QS8_VADDC_MINMAX__SCALAR_X4, b_scale) { |
| 5843 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 5844 | for (float b_scale = 0.1f; b_scale <= 10.0f; b_scale *= 3.14f) { |
| 5845 | VAddCMicrokernelTester() |
| 5846 | .batch_size(batch_size) |
| 5847 | .b_scale(b_scale) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5848 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x4, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5849 | } |
| 5850 | } |
| 5851 | } |
| 5852 | |
| 5853 | TEST(QS8_VADDC_MINMAX__SCALAR_X4, y_scale) { |
| 5854 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 5855 | for (float y_scale = 0.1f; y_scale <= 10.0f; y_scale *= 3.14f) { |
| 5856 | VAddCMicrokernelTester() |
| 5857 | .batch_size(batch_size) |
| 5858 | .y_scale(y_scale) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5859 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x4, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5860 | } |
| 5861 | } |
| 5862 | } |
| 5863 | |
| 5864 | TEST(QS8_VADDC_MINMAX__SCALAR_X4, qmin) { |
| 5865 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 5866 | VAddCMicrokernelTester() |
| 5867 | .batch_size(batch_size) |
| 5868 | .qmin(128) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5869 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x4, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5870 | } |
| 5871 | } |
| 5872 | |
| 5873 | TEST(QS8_VADDC_MINMAX__SCALAR_X4, qmax) { |
| 5874 | for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) { |
| 5875 | VAddCMicrokernelTester() |
| 5876 | .batch_size(batch_size) |
| 5877 | .qmax(128) |
Marat Dukhan | 6e0fc39 | 2021-07-19 18:38:24 -0700 | [diff] [blame] | 5878 | .Test(xnn_qs8_vaddc_minmax_ukernel__scalar_x4, xnn_init_qs8_add_minmax_scalar_params); |
Marat Dukhan | d481c28 | 2021-05-11 23:48:31 -0700 | [diff] [blame] | 5879 | } |
| 5880 | } |