| Christophe Lyon | 073831a | 2011-01-24 17:37:40 +0100 | [diff] [blame] | 1 | ; Copyright ARM Ltd 2005. All rights reserved. |
| 2 | |
| 3 | ;================================================================== |
| 4 | ; This code provides basic global enable for a Cortex-A8 cache |
| 5 | ; and program flow prediction |
| 6 | ; This code must be run from a privileged mode |
| 7 | ;================================================================== |
| 8 | |
| 9 | AREA CORTEXA8CACHE, CODE, READONLY |
| 10 | EXPORT core_init |
| 11 | |
| 12 | core_init |
| 13 | |
| 14 | ;================================================================== |
| 15 | ; Global Enable for Cortex-A8 Instruction and Data Caching |
| 16 | ;================================================================== |
| 17 | |
| 18 | MRC p15, 0, r0, c1, c0, 0 ; read CP15 register 1 into r0 |
| 19 | ORR r0, r0, #(0x1 <<12) ; enable I Cache |
| 20 | ;BIC r0, r0, #(0x1 <<12) ; Clear bit 0 |
| 21 | ORR r0, r0, #(0x1 <<2) ; enable D Cache |
| 22 | ;BIC r0, r0, #(0x1 << 2) ; Clear bit 0 |
| 23 | ORR r0, r0, #0x1 ; enable MMU |
| 24 | MCR p15, 0, r0, c1, c0, 0 ; write CP15 register 1 |
| 25 | |
| 26 | ;================================================================== |
| 27 | ; Enable Cortex-A8 Level2 Unified Cache |
| 28 | ;================================================================== |
| 29 | |
| 30 | MRC p15, 0, r0, c1, c0, 1 ; Read Auxiliary Control Register |
| 31 | ORR r0, r0, #2 ; L2EN bit, enable L2 cache |
| 32 | ;BIC r0, r0, #(0x1 << 1) ; L2EN bit, disable L2 cache |
| 33 | ;ORR r0, r0, #(0x1 << 4) ;Enables speculative accesses on AXI |
| 34 | ORR r0, r0, #(0x1 << 4) ;Enables speculative accesses on AXI |
| 35 | ORR r0, r0, #(0x1 << 5) ;Enables caching NEON data within the L1 data cache |
| 36 | MCR p15, 0, r0, c1, c0, 1 ; Write Auxiliary Control Register |
| 37 | |
| 38 | ;================================================================== |
| 39 | ; Cortex-A8 program flow prediction |
| 40 | ;================================================================== |
| 41 | |
| 42 | MRC p15, 0, r0, c1, c0, 0 ; read CP15 register 1 into r0 |
| 43 | ORR r0, r0, #(0x1 <<11) ; Enable all forms of branch prediction |
| 44 | ;BIC r0, r0, #(0x1 << 11) ; Disable all forms of branch prediction |
| 45 | MCR p15, 0, r0, c1, c0, 0 ; write CP15 register 1 |
| 46 | |
| 47 | ;================================================================== |
| 48 | |
| 49 | BX lr |
| 50 | |
| 51 | END ; mark the end of this file |
| 52 | |