blob: 142b5c999429bce4f22a9f17d55f5d0f5a255440 [file] [log] [blame]
/*
* Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <drivers/arm/cci.h>
#include <drivers/console.h>
#include <lib/mmio.h>
#include <lib/smccc.h>
#include <lib/xlat_tables/xlat_tables.h>
#include <plat/common/platform.h>
#include <services/arm_arch_svc.h>
#include <mtk_plat_common.h>
#include <mtk_sip_svc.h>
#include <plat_private.h>
struct atf_arg_t gteearg;
void clean_top_32b_of_param(uint32_t smc_fid,
u_register_t *px1,
u_register_t *px2,
u_register_t *px3,
u_register_t *px4)
{
/* if parameters from SMC32. Clean top 32 bits */
if (0 == (smc_fid & SMC_AARCH64_BIT)) {
*px1 = *px1 & SMC32_PARAM_MASK;
*px2 = *px2 & SMC32_PARAM_MASK;
*px3 = *px3 & SMC32_PARAM_MASK;
*px4 = *px4 & SMC32_PARAM_MASK;
}
}
#if MTK_SIP_KERNEL_BOOT_ENABLE
static struct kernel_info k_info;
static void save_kernel_info(uint64_t pc,
uint64_t r0,
uint64_t r1,
uint64_t k32_64)
{
k_info.k32_64 = k32_64;
k_info.pc = pc;
if (LINUX_KERNEL_32 == k32_64) {
/* for 32 bits kernel */
k_info.r0 = 0;
/* machtype */
k_info.r1 = r0;
/* tags */
k_info.r2 = r1;
} else {
/* for 64 bits kernel */
k_info.r0 = r0;
k_info.r1 = r1;
}
}
uint64_t get_kernel_info_pc(void)
{
return k_info.pc;
}
uint64_t get_kernel_info_r0(void)
{
return k_info.r0;
}
uint64_t get_kernel_info_r1(void)
{
return k_info.r1;
}
uint64_t get_kernel_info_r2(void)
{
return k_info.r2;
}
void boot_to_kernel(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4)
{
static uint8_t kernel_boot_once_flag;
/* only support in booting flow */
if (0 == kernel_boot_once_flag) {
kernel_boot_once_flag = 1;
console_init(gteearg.atf_log_port,
UART_CLOCK, UART_BAUDRATE);
INFO("save kernel info\n");
save_kernel_info(x1, x2, x3, x4);
bl31_prepare_kernel_entry(x4);
INFO("el3_exit\n");
console_uninit();
}
}
#endif
uint32_t plat_get_spsr_for_bl33_entry(void)
{
unsigned int mode;
uint32_t spsr;
unsigned int ee;
unsigned long daif;
INFO("Secondary bootloader is AArch32\n");
mode = MODE32_svc;
ee = 0;
/*
* TODO: Choose async. exception bits if HYP mode is not
* implemented according to the values of SCR.{AW, FW} bits
*/
daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT;
spsr = SPSR_MODE32(mode, 0, ee, daif);
return spsr;
}
/*****************************************************************************
* plat_is_smccc_feature_available() - This function checks whether SMCCC
* feature is availabile for platform.
* @fid: SMCCC function id
*
* Return SMC_OK if SMCCC feature is available and SMC_ARCH_CALL_NOT_SUPPORTED
* otherwise.
*****************************************************************************/
int32_t plat_is_smccc_feature_available(u_register_t fid)
{
switch (fid) {
case SMCCC_ARCH_SOC_ID:
return SMC_ARCH_CALL_SUCCESS;
default:
return SMC_ARCH_CALL_NOT_SUPPORTED;
}
}
int32_t plat_get_soc_version(void)
{
uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_MTK_BKID, JEDEC_MTK_MFID);
return (int32_t)(manfid | (SOC_CHIP_ID & SOC_ID_IMPL_DEF_MASK));
}
int32_t plat_get_soc_revision(void)
{
return 0;
}