| /* |
| * Copyright (c) 2020, MediaTek Inc. All rights reserved. |
| * |
| * SPDX-License-Identifier: BSD-3-Clause |
| */ |
| |
| /**************************************************************** |
| * Auto generated by DE, please DO NOT modify this file directly. |
| *****************************************************************/ |
| #ifndef MT_SPM_REG |
| #define MT_SPM_REG |
| |
| #include "pcm_def.h" |
| #include <platform_def.h> |
| #include "sleep_def.h" |
| |
| /************************************** |
| * Define and Declare |
| **************************************/ |
| #define POWERON_CONFIG_EN (SPM_BASE + 0x000) |
| #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004) |
| #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008) |
| #define SPM_CLK_CON (SPM_BASE + 0x00C) |
| #define SPM_CLK_SETTLE (SPM_BASE + 0x010) |
| #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014) |
| #define PCM_CON0 (SPM_BASE + 0x018) |
| #define PCM_CON1 (SPM_BASE + 0x01C) |
| #define SPM_POWER_ON_VAL2 (SPM_BASE + 0x020) |
| #define SPM_POWER_ON_VAL3 (SPM_BASE + 0x024) |
| #define PCM_REG_DATA_INI (SPM_BASE + 0x028) |
| #define PCM_PWR_IO_EN (SPM_BASE + 0x02C) |
| #define PCM_TIMER_VAL (SPM_BASE + 0x030) |
| #define PCM_WDT_VAL (SPM_BASE + 0x034) |
| #define SPM_SRC6_MASK (SPM_BASE + 0x038) |
| #define SPM_SW_RST_CON (SPM_BASE + 0x040) |
| #define SPM_SW_RST_CON_SET (SPM_BASE + 0x044) |
| #define SPM_SW_RST_CON_CLR (SPM_BASE + 0x048) |
| #define VS1_PSR_MASK_B (SPM_BASE + 0x04C) |
| #define VS2_PSR_MASK_B (SPM_BASE + 0x050) |
| #define MD32_CLK_CON (SPM_BASE + 0x084) |
| #define SPM_SRAM_RSV_CON (SPM_BASE + 0x088) |
| #define SPM_SWINT (SPM_BASE + 0x08C) |
| #define SPM_SWINT_SET (SPM_BASE + 0x090) |
| #define SPM_SWINT_CLR (SPM_BASE + 0x094) |
| #define SPM_SCP_MAILBOX (SPM_BASE + 0x098) |
| #define SCP_SPM_MAILBOX (SPM_BASE + 0x09C) |
| #define SPM_TWAM_CON (SPM_BASE + 0x0A0) |
| #define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x0A4) |
| #define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x0A8) |
| #define SPM_SCP_IRQ (SPM_BASE + 0x0AC) |
| #define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x0B0) |
| #define SPM_IRQ_MASK (SPM_BASE + 0x0B4) |
| #define SPM_SRC_REQ (SPM_BASE + 0x0B8) |
| #define SPM_SRC_MASK (SPM_BASE + 0x0BC) |
| #define SPM_SRC2_MASK (SPM_BASE + 0x0C0) |
| #define SPM_SRC3_MASK (SPM_BASE + 0x0C4) |
| #define SPM_SRC4_MASK (SPM_BASE + 0x0C8) |
| #define SPM_SRC5_MASK (SPM_BASE + 0x0CC) |
| #define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x0D0) |
| #define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x0D4) |
| #define SPM_TWAM_EVENT_CLEAR (SPM_BASE + 0x0D8) |
| #define SCP_CLK_CON (SPM_BASE + 0x0DC) |
| #define PCM_DEBUG_CON (SPM_BASE + 0x0E0) |
| #define AHB_BUS_CON (SPM_BASE + 0x0E4) |
| #define DDR_EN_DBC_CON0 (SPM_BASE + 0x0E8) |
| #define DDR_EN_DBC_CON1 (SPM_BASE + 0x0EC) |
| #define SPM_RESOURCE_ACK_CON0 (SPM_BASE + 0x0F0) |
| #define SPM_RESOURCE_ACK_CON1 (SPM_BASE + 0x0F4) |
| #define SPM_RESOURCE_ACK_CON2 (SPM_BASE + 0x0F8) |
| #define SPM_RESOURCE_ACK_CON3 (SPM_BASE + 0x0FC) |
| #define PCM_REG0_DATA (SPM_BASE + 0x100) |
| #define PCM_REG2_DATA (SPM_BASE + 0x104) |
| #define PCM_REG6_DATA (SPM_BASE + 0x108) |
| #define PCM_REG7_DATA (SPM_BASE + 0x10C) |
| #define PCM_REG13_DATA (SPM_BASE + 0x110) |
| #define SRC_REQ_STA_0 (SPM_BASE + 0x114) |
| #define SRC_REQ_STA_1 (SPM_BASE + 0x118) |
| #define SRC_REQ_STA_2 (SPM_BASE + 0x11C) |
| #define PCM_TIMER_OUT (SPM_BASE + 0x120) |
| #define PCM_WDT_OUT (SPM_BASE + 0x124) |
| #define SPM_IRQ_STA (SPM_BASE + 0x128) |
| #define SRC_REQ_STA_4 (SPM_BASE + 0x12C) |
| #define MD32PCM_WAKEUP_STA (SPM_BASE + 0x130) |
| #define MD32PCM_EVENT_STA (SPM_BASE + 0x134) |
| #define SPM_WAKEUP_STA (SPM_BASE + 0x138) |
| #define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x13C) |
| #define SPM_WAKEUP_MISC (SPM_BASE + 0x140) |
| #define MM_DVFS_HALT (SPM_BASE + 0x144) |
| #define BUS_PROTECT_RDY (SPM_BASE + 0x150) |
| #define BUS_PROTECT1_RDY (SPM_BASE + 0x154) |
| #define BUS_PROTECT2_RDY (SPM_BASE + 0x158) |
| #define BUS_PROTECT3_RDY (SPM_BASE + 0x15C) |
| #define SUBSYS_IDLE_STA (SPM_BASE + 0x160) |
| #define PCM_STA (SPM_BASE + 0x164) |
| #define SRC_REQ_STA_3 (SPM_BASE + 0x168) |
| #define PWR_STATUS (SPM_BASE + 0x16C) |
| #define PWR_STATUS_2ND (SPM_BASE + 0x170) |
| #define CPU_PWR_STATUS (SPM_BASE + 0x174) |
| #define OTHER_PWR_STATUS (SPM_BASE + 0x178) |
| #define SPM_VTCXO_EVENT_COUNT_STA (SPM_BASE + 0x17C) |
| #define SPM_INFRA_EVENT_COUNT_STA (SPM_BASE + 0x180) |
| #define SPM_VRF18_EVENT_COUNT_STA (SPM_BASE + 0x184) |
| #define SPM_APSRC_EVENT_COUNT_STA (SPM_BASE + 0x188) |
| #define SPM_DDREN_EVENT_COUNT_STA (SPM_BASE + 0x18C) |
| #define MD32PCM_STA (SPM_BASE + 0x190) |
| #define MD32PCM_PC (SPM_BASE + 0x194) |
| #define DVFSRC_EVENT_STA (SPM_BASE + 0x1A4) |
| #define BUS_PROTECT4_RDY (SPM_BASE + 0x1A8) |
| #define BUS_PROTECT5_RDY (SPM_BASE + 0x1AC) |
| #define BUS_PROTECT6_RDY (SPM_BASE + 0x1B0) |
| #define BUS_PROTECT7_RDY (SPM_BASE + 0x1B4) |
| #define BUS_PROTECT8_RDY (SPM_BASE + 0x1B8) |
| #define SPM_TWAM_LAST_STA0 (SPM_BASE + 0x1D0) |
| #define SPM_TWAM_LAST_STA1 (SPM_BASE + 0x1D4) |
| #define SPM_TWAM_LAST_STA2 (SPM_BASE + 0x1D8) |
| #define SPM_TWAM_LAST_STA3 (SPM_BASE + 0x1DC) |
| #define SPM_TWAM_CURR_STA0 (SPM_BASE + 0x1E0) |
| #define SPM_TWAM_CURR_STA1 (SPM_BASE + 0x1E4) |
| #define SPM_TWAM_CURR_STA2 (SPM_BASE + 0x1E8) |
| #define SPM_TWAM_CURR_STA3 (SPM_BASE + 0x1EC) |
| #define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x1F0) |
| #define SPM_CG_CHECK_STA (SPM_BASE + 0x1F4) |
| #define SPM_DVFS_STA (SPM_BASE + 0x1F8) |
| #define SPM_DVFS_OPP_STA (SPM_BASE + 0x1FC) |
| #define SPM_MCUSYS_PWR_CON (SPM_BASE + 0x200) |
| #define SPM_CPUTOP_PWR_CON (SPM_BASE + 0x204) |
| #define SPM_CPU0_PWR_CON (SPM_BASE + 0x208) |
| #define SPM_CPU1_PWR_CON (SPM_BASE + 0x20C) |
| #define SPM_CPU2_PWR_CON (SPM_BASE + 0x210) |
| #define SPM_CPU3_PWR_CON (SPM_BASE + 0x214) |
| #define SPM_CPU4_PWR_CON (SPM_BASE + 0x218) |
| #define SPM_CPU5_PWR_CON (SPM_BASE + 0x21C) |
| #define SPM_CPU6_PWR_CON (SPM_BASE + 0x220) |
| #define SPM_CPU7_PWR_CON (SPM_BASE + 0x224) |
| #define ARMPLL_CLK_CON (SPM_BASE + 0x22C) |
| #define MCUSYS_IDLE_STA (SPM_BASE + 0x230) |
| #define GIC_WAKEUP_STA (SPM_BASE + 0x234) |
| #define CPU_SPARE_CON (SPM_BASE + 0x238) |
| #define CPU_SPARE_CON_SET (SPM_BASE + 0x23C) |
| #define CPU_SPARE_CON_CLR (SPM_BASE + 0x240) |
| #define ARMPLL_CLK_SEL (SPM_BASE + 0x244) |
| #define EXT_INT_WAKEUP_REQ (SPM_BASE + 0x248) |
| #define EXT_INT_WAKEUP_REQ_SET (SPM_BASE + 0x24C) |
| #define EXT_INT_WAKEUP_REQ_CLR (SPM_BASE + 0x250) |
| #define MP0_CPU0_IRQ_MASK (SPM_BASE + 0x260) |
| #define MP0_CPU1_IRQ_MASK (SPM_BASE + 0x264) |
| #define MP0_CPU2_IRQ_MASK (SPM_BASE + 0x268) |
| #define MP0_CPU3_IRQ_MASK (SPM_BASE + 0x26C) |
| #define MP1_CPU0_IRQ_MASK (SPM_BASE + 0x270) |
| #define MP1_CPU1_IRQ_MASK (SPM_BASE + 0x274) |
| #define MP1_CPU2_IRQ_MASK (SPM_BASE + 0x278) |
| #define MP1_CPU3_IRQ_MASK (SPM_BASE + 0x27C) |
| #define MP0_CPU0_WFI_EN (SPM_BASE + 0x280) |
| #define MP0_CPU1_WFI_EN (SPM_BASE + 0x284) |
| #define MP0_CPU2_WFI_EN (SPM_BASE + 0x288) |
| #define MP0_CPU3_WFI_EN (SPM_BASE + 0x28C) |
| #define MP0_CPU4_WFI_EN (SPM_BASE + 0x290) |
| #define MP0_CPU5_WFI_EN (SPM_BASE + 0x294) |
| #define MP0_CPU6_WFI_EN (SPM_BASE + 0x298) |
| #define MP0_CPU7_WFI_EN (SPM_BASE + 0x29C) |
| #define ROOT_CPUTOP_ADDR (SPM_BASE + 0x2A0) |
| #define ROOT_CORE_ADDR (SPM_BASE + 0x2A4) |
| #define SPM2SW_MAILBOX_0 (SPM_BASE + 0x2D0) |
| #define SPM2SW_MAILBOX_1 (SPM_BASE + 0x2D4) |
| #define SPM2SW_MAILBOX_2 (SPM_BASE + 0x2D8) |
| #define SPM2SW_MAILBOX_3 (SPM_BASE + 0x2DC) |
| #define SW2SPM_INT (SPM_BASE + 0x2E0) |
| #define SW2SPM_INT_SET (SPM_BASE + 0x2E4) |
| #define SW2SPM_INT_CLR (SPM_BASE + 0x2E8) |
| #define SW2SPM_MAILBOX_0 (SPM_BASE + 0x2EC) |
| #define SW2SPM_MAILBOX_1 (SPM_BASE + 0x2F0) |
| #define SW2SPM_MAILBOX_2 (SPM_BASE + 0x2F4) |
| #define SW2SPM_MAILBOX_3 (SPM_BASE + 0x2F8) |
| #define SW2SPM_CFG (SPM_BASE + 0x2FC) |
| #define MD1_PWR_CON (SPM_BASE + 0x300) |
| #define CONN_PWR_CON (SPM_BASE + 0x304) |
| #define MFG0_PWR_CON (SPM_BASE + 0x308) |
| #define MFG1_PWR_CON (SPM_BASE + 0x30C) |
| #define MFG2_PWR_CON (SPM_BASE + 0x310) |
| #define MFG3_PWR_CON (SPM_BASE + 0x314) |
| #define MFG4_PWR_CON (SPM_BASE + 0x318) |
| #define MFG5_PWR_CON (SPM_BASE + 0x31C) |
| #define MFG6_PWR_CON (SPM_BASE + 0x320) |
| #define IFR_PWR_CON (SPM_BASE + 0x324) |
| #define IFR_SUB_PWR_CON (SPM_BASE + 0x328) |
| #define DPY_PWR_CON (SPM_BASE + 0x32C) |
| #define ISP_PWR_CON (SPM_BASE + 0x330) |
| #define ISP2_PWR_CON (SPM_BASE + 0x334) |
| #define IPE_PWR_CON (SPM_BASE + 0x338) |
| #define VDE_PWR_CON (SPM_BASE + 0x33C) |
| #define VDE2_PWR_CON (SPM_BASE + 0x340) |
| #define VEN_PWR_CON (SPM_BASE + 0x344) |
| #define VEN_CORE1_PWR_CON (SPM_BASE + 0x348) |
| #define MDP_PWR_CON (SPM_BASE + 0x34C) |
| #define DIS_PWR_CON (SPM_BASE + 0x350) |
| #define AUDIO_PWR_CON (SPM_BASE + 0x354) |
| #define ADSP_PWR_CON (SPM_BASE + 0x358) |
| #define CAM_PWR_CON (SPM_BASE + 0x35C) |
| #define CAM_RAWA_PWR_CON (SPM_BASE + 0x360) |
| #define CAM_RAWB_PWR_CON (SPM_BASE + 0x364) |
| #define CAM_RAWC_PWR_CON (SPM_BASE + 0x368) |
| #define SYSRAM_CON (SPM_BASE + 0x36C) |
| #define SYSROM_CON (SPM_BASE + 0x370) |
| #define SSPM_SRAM_CON (SPM_BASE + 0x374) |
| #define SCP_SRAM_CON (SPM_BASE + 0x378) |
| #define DPY_SHU_SRAM_CON (SPM_BASE + 0x37C) |
| #define UFS_SRAM_CON (SPM_BASE + 0x380) |
| #define DEVAPC_IFR_SRAM_CON (SPM_BASE + 0x384) |
| #define DEVAPC_SUBIFR_SRAM_CON (SPM_BASE + 0x388) |
| #define DEVAPC_ACP_SRAM_CON (SPM_BASE + 0x38C) |
| #define USB_SRAM_CON (SPM_BASE + 0x390) |
| #define DUMMY_SRAM_CON (SPM_BASE + 0x394) |
| #define MD_EXT_BUCK_ISO_CON (SPM_BASE + 0x398) |
| #define EXT_BUCK_ISO (SPM_BASE + 0x39C) |
| #define DXCC_SRAM_CON (SPM_BASE + 0x3A0) |
| #define MSDC_SRAM_CON (SPM_BASE + 0x3A4) |
| #define DEBUGTOP_SRAM_CON (SPM_BASE + 0x3A8) |
| #define DP_TX_PWR_CON (SPM_BASE + 0x3AC) |
| #define DPMAIF_SRAM_CON (SPM_BASE + 0x3B0) |
| #define DPY_SHU2_SRAM_CON (SPM_BASE + 0x3B4) |
| #define DRAMC_MCU2_SRAM_CON (SPM_BASE + 0x3B8) |
| #define DRAMC_MCU_SRAM_CON (SPM_BASE + 0x3BC) |
| #define MCUPM_SRAM_CON (SPM_BASE + 0x3C0) |
| #define DPY2_PWR_CON (SPM_BASE + 0x3C4) |
| #define PERI_PWR_CON (SPM_BASE + 0x3C8) |
| #define SPM_MEM_CK_SEL (SPM_BASE + 0x400) |
| #define SPM_BUS_PROTECT_MASK_B (SPM_BASE + 0x404) |
| #define SPM_BUS_PROTECT1_MASK_B (SPM_BASE + 0x408) |
| #define SPM_BUS_PROTECT2_MASK_B (SPM_BASE + 0x40C) |
| #define SPM_BUS_PROTECT3_MASK_B (SPM_BASE + 0x410) |
| #define SPM_BUS_PROTECT4_MASK_B (SPM_BASE + 0x414) |
| #define SPM_EMI_BW_MODE (SPM_BASE + 0x418) |
| #define AP2MD_PEER_WAKEUP (SPM_BASE + 0x41C) |
| #define ULPOSC_CON (SPM_BASE + 0x420) |
| #define SPM2MM_CON (SPM_BASE + 0x424) |
| #define SPM_BUS_PROTECT5_MASK_B (SPM_BASE + 0x428) |
| #define SPM2MCUPM_CON (SPM_BASE + 0x42C) |
| #define AP_MDSRC_REQ (SPM_BASE + 0x430) |
| #define SPM2EMI_ENTER_ULPM (SPM_BASE + 0x434) |
| #define SPM2MD_DVFS_CON (SPM_BASE + 0x438) |
| #define MD2SPM_DVFS_CON (SPM_BASE + 0x43C) |
| #define SPM_BUS_PROTECT6_MASK_B (SPM_BASE + 0x440) |
| #define SPM_BUS_PROTECT7_MASK_B (SPM_BASE + 0x444) |
| #define SPM_BUS_PROTECT8_MASK_B (SPM_BASE + 0x448) |
| #define SPM_PLL_CON (SPM_BASE + 0x44C) |
| #define CPU_DVFS_REQ (SPM_BASE + 0x450) |
| #define SPM_DRAM_MCU_SW_CON_0 (SPM_BASE + 0x454) |
| #define SPM_DRAM_MCU_SW_CON_1 (SPM_BASE + 0x458) |
| #define SPM_DRAM_MCU_SW_CON_2 (SPM_BASE + 0x45C) |
| #define SPM_DRAM_MCU_SW_CON_3 (SPM_BASE + 0x460) |
| #define SPM_DRAM_MCU_SW_CON_4 (SPM_BASE + 0x464) |
| #define SPM_DRAM_MCU_STA_0 (SPM_BASE + 0x468) |
| #define SPM_DRAM_MCU_STA_1 (SPM_BASE + 0x46C) |
| #define SPM_DRAM_MCU_STA_2 (SPM_BASE + 0x470) |
| #define SPM_DRAM_MCU_SW_SEL_0 (SPM_BASE + 0x474) |
| #define RELAY_DVFS_LEVEL (SPM_BASE + 0x478) |
| #define DRAMC_DPY_CLK_SW_CON_0 (SPM_BASE + 0x480) |
| #define DRAMC_DPY_CLK_SW_CON_1 (SPM_BASE + 0x484) |
| #define DRAMC_DPY_CLK_SW_CON_2 (SPM_BASE + 0x488) |
| #define DRAMC_DPY_CLK_SW_CON_3 (SPM_BASE + 0x48C) |
| #define DRAMC_DPY_CLK_SW_SEL_0 (SPM_BASE + 0x490) |
| #define DRAMC_DPY_CLK_SW_SEL_1 (SPM_BASE + 0x494) |
| #define DRAMC_DPY_CLK_SW_SEL_2 (SPM_BASE + 0x498) |
| #define DRAMC_DPY_CLK_SW_SEL_3 (SPM_BASE + 0x49C) |
| #define DRAMC_DPY_CLK_SPM_CON (SPM_BASE + 0x4A0) |
| #define SPM_DVFS_LEVEL (SPM_BASE + 0x4A4) |
| #define SPM_CIRQ_CON (SPM_BASE + 0x4A8) |
| #define SPM_DVFS_MISC (SPM_BASE + 0x4AC) |
| #define SPM_VS1_VS2_RC_CON (SPM_BASE + 0x4B0) |
| #define RG_MODULE_SW_CG_0_MASK_REQ_0 (SPM_BASE + 0x4B4) |
| #define RG_MODULE_SW_CG_0_MASK_REQ_1 (SPM_BASE + 0x4B8) |
| #define RG_MODULE_SW_CG_0_MASK_REQ_2 (SPM_BASE + 0x4BC) |
| #define RG_MODULE_SW_CG_1_MASK_REQ_0 (SPM_BASE + 0x4C0) |
| #define RG_MODULE_SW_CG_1_MASK_REQ_1 (SPM_BASE + 0x4C4) |
| #define RG_MODULE_SW_CG_1_MASK_REQ_2 (SPM_BASE + 0x4C8) |
| #define RG_MODULE_SW_CG_2_MASK_REQ_0 (SPM_BASE + 0x4CC) |
| #define RG_MODULE_SW_CG_2_MASK_REQ_1 (SPM_BASE + 0x4D0) |
| #define RG_MODULE_SW_CG_2_MASK_REQ_2 (SPM_BASE + 0x4D4) |
| #define RG_MODULE_SW_CG_3_MASK_REQ_0 (SPM_BASE + 0x4D8) |
| #define RG_MODULE_SW_CG_3_MASK_REQ_1 (SPM_BASE + 0x4DC) |
| #define RG_MODULE_SW_CG_3_MASK_REQ_2 (SPM_BASE + 0x4E0) |
| #define PWR_STATUS_MASK_REQ_0 (SPM_BASE + 0x4E4) |
| #define PWR_STATUS_MASK_REQ_1 (SPM_BASE + 0x4E8) |
| #define PWR_STATUS_MASK_REQ_2 (SPM_BASE + 0x4EC) |
| #define SPM_CG_CHECK_CON (SPM_BASE + 0x4F0) |
| #define SPM_SRC_RDY_STA (SPM_BASE + 0x4F4) |
| #define SPM_DVS_DFS_LEVEL (SPM_BASE + 0x4F8) |
| #define SPM_FORCE_DVFS (SPM_BASE + 0x4FC) |
| #define SRCLKEN_RC_CFG (SPM_BASE + 0x500) |
| #define RC_CENTRAL_CFG1 (SPM_BASE + 0x504) |
| #define RC_CENTRAL_CFG2 (SPM_BASE + 0x508) |
| #define RC_CMD_ARB_CFG (SPM_BASE + 0x50C) |
| #define RC_PMIC_RCEN_ADDR (SPM_BASE + 0x510) |
| #define RC_PMIC_RCEN_SET_CLR_ADDR (SPM_BASE + 0x514) |
| #define RC_DCXO_FPM_CFG (SPM_BASE + 0x518) |
| #define RC_CENTRAL_CFG3 (SPM_BASE + 0x51C) |
| #define RC_M00_SRCLKEN_CFG (SPM_BASE + 0x520) |
| #define RC_M01_SRCLKEN_CFG (SPM_BASE + 0x524) |
| #define RC_M02_SRCLKEN_CFG (SPM_BASE + 0x528) |
| #define RC_M03_SRCLKEN_CFG (SPM_BASE + 0x52C) |
| #define RC_M04_SRCLKEN_CFG (SPM_BASE + 0x530) |
| #define RC_M05_SRCLKEN_CFG (SPM_BASE + 0x534) |
| #define RC_M06_SRCLKEN_CFG (SPM_BASE + 0x538) |
| #define RC_M07_SRCLKEN_CFG (SPM_BASE + 0x53C) |
| #define RC_M08_SRCLKEN_CFG (SPM_BASE + 0x540) |
| #define RC_M09_SRCLKEN_CFG (SPM_BASE + 0x544) |
| #define RC_M10_SRCLKEN_CFG (SPM_BASE + 0x548) |
| #define RC_M11_SRCLKEN_CFG (SPM_BASE + 0x54C) |
| #define RC_M12_SRCLKEN_CFG (SPM_BASE + 0x550) |
| #define RC_SRCLKEN_SW_CON_CFG (SPM_BASE + 0x554) |
| #define RC_CENTRAL_CFG4 (SPM_BASE + 0x558) |
| #define RC_PROTOCOL_CHK_CFG (SPM_BASE + 0x560) |
| #define RC_DEBUG_CFG (SPM_BASE + 0x564) |
| #define RC_MISC_0 (SPM_BASE + 0x5B4) |
| #define RC_SPM_CTRL (SPM_BASE + 0x5B8) |
| #define SUBSYS_INTF_CFG (SPM_BASE + 0x5BC) |
| #define PCM_WDT_LATCH_25 (SPM_BASE + 0x5C0) |
| #define PCM_WDT_LATCH_26 (SPM_BASE + 0x5C4) |
| #define PCM_WDT_LATCH_27 (SPM_BASE + 0x5C8) |
| #define PCM_WDT_LATCH_28 (SPM_BASE + 0x5CC) |
| #define PCM_WDT_LATCH_29 (SPM_BASE + 0x5D0) |
| #define PCM_WDT_LATCH_30 (SPM_BASE + 0x5D4) |
| #define PCM_WDT_LATCH_31 (SPM_BASE + 0x5D8) |
| #define PCM_WDT_LATCH_32 (SPM_BASE + 0x5DC) |
| #define PCM_WDT_LATCH_33 (SPM_BASE + 0x5E0) |
| #define PCM_WDT_LATCH_34 (SPM_BASE + 0x5E4) |
| #define PCM_WDT_LATCH_35 (SPM_BASE + 0x5EC) |
| #define PCM_WDT_LATCH_36 (SPM_BASE + 0x5F0) |
| #define PCM_WDT_LATCH_37 (SPM_BASE + 0x5F4) |
| #define PCM_WDT_LATCH_38 (SPM_BASE + 0x5F8) |
| #define PCM_WDT_LATCH_39 (SPM_BASE + 0x5FC) |
| #define SPM_SW_FLAG_0 (SPM_BASE + 0x600) |
| #define SPM_SW_DEBUG_0 (SPM_BASE + 0x604) |
| #define SPM_SW_FLAG_1 (SPM_BASE + 0x608) |
| #define SPM_SW_DEBUG_1 (SPM_BASE + 0x60C) |
| #define SPM_SW_RSV_0 (SPM_BASE + 0x610) |
| #define SPM_SW_RSV_1 (SPM_BASE + 0x614) |
| #define SPM_SW_RSV_2 (SPM_BASE + 0x618) |
| #define SPM_SW_RSV_3 (SPM_BASE + 0x61C) |
| #define SPM_SW_RSV_4 (SPM_BASE + 0x620) |
| #define SPM_SW_RSV_5 (SPM_BASE + 0x624) |
| #define SPM_SW_RSV_6 (SPM_BASE + 0x628) |
| #define SPM_SW_RSV_7 (SPM_BASE + 0x62C) |
| #define SPM_SW_RSV_8 (SPM_BASE + 0x630) |
| #define SPM_BK_WAKE_EVENT (SPM_BASE + 0x634) |
| #define SPM_BK_VTCXO_DUR (SPM_BASE + 0x638) |
| #define SPM_BK_WAKE_MISC (SPM_BASE + 0x63C) |
| #define SPM_BK_PCM_TIMER (SPM_BASE + 0x640) |
| #define SPM_RSV_CON_0 (SPM_BASE + 0x650) |
| #define SPM_RSV_CON_1 (SPM_BASE + 0x654) |
| #define SPM_RSV_STA_0 (SPM_BASE + 0x658) |
| #define SPM_RSV_STA_1 (SPM_BASE + 0x65C) |
| #define SPM_SPARE_CON (SPM_BASE + 0x660) |
| #define SPM_SPARE_CON_SET (SPM_BASE + 0x664) |
| #define SPM_SPARE_CON_CLR (SPM_BASE + 0x668) |
| #define SPM_CROSS_WAKE_M00_REQ (SPM_BASE + 0x66C) |
| #define SPM_CROSS_WAKE_M01_REQ (SPM_BASE + 0x670) |
| #define SPM_CROSS_WAKE_M02_REQ (SPM_BASE + 0x674) |
| #define SPM_CROSS_WAKE_M03_REQ (SPM_BASE + 0x678) |
| #define SCP_VCORE_LEVEL (SPM_BASE + 0x67C) |
| #define SC_MM_CK_SEL_CON (SPM_BASE + 0x680) |
| #define SPARE_ACK_MASK (SPM_BASE + 0x684) |
| #define SPM_CROSS_WAKE_M04_REQ (SPM_BASE + 0x688) |
| #define SPM_DV_CON_0 (SPM_BASE + 0x68C) |
| #define SPM_DV_CON_1 (SPM_BASE + 0x690) |
| #define SPM_DV_STA (SPM_BASE + 0x694) |
| #define CONN_XOWCN_DEBUG_EN (SPM_BASE + 0x698) |
| #define SPM_SEMA_M0 (SPM_BASE + 0x69C) |
| #define SPM_SEMA_M1 (SPM_BASE + 0x6A0) |
| #define SPM_SEMA_M2 (SPM_BASE + 0x6A4) |
| #define SPM_SEMA_M3 (SPM_BASE + 0x6A8) |
| #define SPM_SEMA_M4 (SPM_BASE + 0x6AC) |
| #define SPM_SEMA_M5 (SPM_BASE + 0x6B0) |
| #define SPM_SEMA_M6 (SPM_BASE + 0x6B4) |
| #define SPM_SEMA_M7 (SPM_BASE + 0x6B8) |
| #define SPM2ADSP_MAILBOX (SPM_BASE + 0x6BC) |
| #define ADSP2SPM_MAILBOX (SPM_BASE + 0x6C0) |
| #define SPM_ADSP_IRQ (SPM_BASE + 0x6C4) |
| #define SPM_MD32_IRQ (SPM_BASE + 0x6C8) |
| #define SPM2PMCU_MAILBOX_0 (SPM_BASE + 0x6CC) |
| #define SPM2PMCU_MAILBOX_1 (SPM_BASE + 0x6D0) |
| #define SPM2PMCU_MAILBOX_2 (SPM_BASE + 0x6D4) |
| #define SPM2PMCU_MAILBOX_3 (SPM_BASE + 0x6D8) |
| #define PMCU2SPM_MAILBOX_0 (SPM_BASE + 0x6DC) |
| #define PMCU2SPM_MAILBOX_1 (SPM_BASE + 0x6E0) |
| #define PMCU2SPM_MAILBOX_2 (SPM_BASE + 0x6E4) |
| #define PMCU2SPM_MAILBOX_3 (SPM_BASE + 0x6E8) |
| #define UFS_PSRI_SW (SPM_BASE + 0x6EC) |
| #define UFS_PSRI_SW_SET (SPM_BASE + 0x6F0) |
| #define UFS_PSRI_SW_CLR (SPM_BASE + 0x6F4) |
| #define SPM_AP_SEMA (SPM_BASE + 0x6F8) |
| #define SPM_SPM_SEMA (SPM_BASE + 0x6FC) |
| #define SPM_DVFS_CON (SPM_BASE + 0x700) |
| #define SPM_DVFS_CON_STA (SPM_BASE + 0x704) |
| #define SPM_PMIC_SPMI_CON (SPM_BASE + 0x708) |
| #define SPM_DVFS_CMD0 (SPM_BASE + 0x710) |
| #define SPM_DVFS_CMD1 (SPM_BASE + 0x714) |
| #define SPM_DVFS_CMD2 (SPM_BASE + 0x718) |
| #define SPM_DVFS_CMD3 (SPM_BASE + 0x71C) |
| #define SPM_DVFS_CMD4 (SPM_BASE + 0x720) |
| #define SPM_DVFS_CMD5 (SPM_BASE + 0x724) |
| #define SPM_DVFS_CMD6 (SPM_BASE + 0x728) |
| #define SPM_DVFS_CMD7 (SPM_BASE + 0x72C) |
| #define SPM_DVFS_CMD8 (SPM_BASE + 0x730) |
| #define SPM_DVFS_CMD9 (SPM_BASE + 0x734) |
| #define SPM_DVFS_CMD10 (SPM_BASE + 0x738) |
| #define SPM_DVFS_CMD11 (SPM_BASE + 0x73C) |
| #define SPM_DVFS_CMD12 (SPM_BASE + 0x740) |
| #define SPM_DVFS_CMD13 (SPM_BASE + 0x744) |
| #define SPM_DVFS_CMD14 (SPM_BASE + 0x748) |
| #define SPM_DVFS_CMD15 (SPM_BASE + 0x74C) |
| #define SPM_DVFS_CMD16 (SPM_BASE + 0x750) |
| #define SPM_DVFS_CMD17 (SPM_BASE + 0x754) |
| #define SPM_DVFS_CMD18 (SPM_BASE + 0x758) |
| #define SPM_DVFS_CMD19 (SPM_BASE + 0x75C) |
| #define SPM_DVFS_CMD20 (SPM_BASE + 0x760) |
| #define SPM_DVFS_CMD21 (SPM_BASE + 0x764) |
| #define SPM_DVFS_CMD22 (SPM_BASE + 0x768) |
| #define SPM_DVFS_CMD23 (SPM_BASE + 0x76C) |
| #define SYS_TIMER_VALUE_L (SPM_BASE + 0x770) |
| #define SYS_TIMER_VALUE_H (SPM_BASE + 0x774) |
| #define SYS_TIMER_START_L (SPM_BASE + 0x778) |
| #define SYS_TIMER_START_H (SPM_BASE + 0x77C) |
| #define SYS_TIMER_LATCH_L_00 (SPM_BASE + 0x780) |
| #define SYS_TIMER_LATCH_H_00 (SPM_BASE + 0x784) |
| #define SYS_TIMER_LATCH_L_01 (SPM_BASE + 0x788) |
| #define SYS_TIMER_LATCH_H_01 (SPM_BASE + 0x78C) |
| #define SYS_TIMER_LATCH_L_02 (SPM_BASE + 0x790) |
| #define SYS_TIMER_LATCH_H_02 (SPM_BASE + 0x794) |
| #define SYS_TIMER_LATCH_L_03 (SPM_BASE + 0x798) |
| #define SYS_TIMER_LATCH_H_03 (SPM_BASE + 0x79C) |
| #define SYS_TIMER_LATCH_L_04 (SPM_BASE + 0x7A0) |
| #define SYS_TIMER_LATCH_H_04 (SPM_BASE + 0x7A4) |
| #define SYS_TIMER_LATCH_L_05 (SPM_BASE + 0x7A8) |
| #define SYS_TIMER_LATCH_H_05 (SPM_BASE + 0x7AC) |
| #define SYS_TIMER_LATCH_L_06 (SPM_BASE + 0x7B0) |
| #define SYS_TIMER_LATCH_H_06 (SPM_BASE + 0x7B4) |
| #define SYS_TIMER_LATCH_L_07 (SPM_BASE + 0x7B8) |
| #define SYS_TIMER_LATCH_H_07 (SPM_BASE + 0x7BC) |
| #define SYS_TIMER_LATCH_L_08 (SPM_BASE + 0x7C0) |
| #define SYS_TIMER_LATCH_H_08 (SPM_BASE + 0x7C4) |
| #define SYS_TIMER_LATCH_L_09 (SPM_BASE + 0x7C8) |
| #define SYS_TIMER_LATCH_H_09 (SPM_BASE + 0x7CC) |
| #define SYS_TIMER_LATCH_L_10 (SPM_BASE + 0x7D0) |
| #define SYS_TIMER_LATCH_H_10 (SPM_BASE + 0x7D4) |
| #define SYS_TIMER_LATCH_L_11 (SPM_BASE + 0x7D8) |
| #define SYS_TIMER_LATCH_H_11 (SPM_BASE + 0x7DC) |
| #define SYS_TIMER_LATCH_L_12 (SPM_BASE + 0x7E0) |
| #define SYS_TIMER_LATCH_H_12 (SPM_BASE + 0x7E4) |
| #define SYS_TIMER_LATCH_L_13 (SPM_BASE + 0x7E8) |
| #define SYS_TIMER_LATCH_H_13 (SPM_BASE + 0x7EC) |
| #define SYS_TIMER_LATCH_L_14 (SPM_BASE + 0x7F0) |
| #define SYS_TIMER_LATCH_H_14 (SPM_BASE + 0x7F4) |
| #define SYS_TIMER_LATCH_L_15 (SPM_BASE + 0x7F8) |
| #define SYS_TIMER_LATCH_H_15 (SPM_BASE + 0x7FC) |
| #define PCM_WDT_LATCH_0 (SPM_BASE + 0x800) |
| #define PCM_WDT_LATCH_1 (SPM_BASE + 0x804) |
| #define PCM_WDT_LATCH_2 (SPM_BASE + 0x808) |
| #define PCM_WDT_LATCH_3 (SPM_BASE + 0x80C) |
| #define PCM_WDT_LATCH_4 (SPM_BASE + 0x810) |
| #define PCM_WDT_LATCH_5 (SPM_BASE + 0x814) |
| #define PCM_WDT_LATCH_6 (SPM_BASE + 0x818) |
| #define PCM_WDT_LATCH_7 (SPM_BASE + 0x81C) |
| #define PCM_WDT_LATCH_8 (SPM_BASE + 0x820) |
| #define PCM_WDT_LATCH_9 (SPM_BASE + 0x824) |
| #define PCM_WDT_LATCH_10 (SPM_BASE + 0x828) |
| #define PCM_WDT_LATCH_11 (SPM_BASE + 0x82C) |
| #define PCM_WDT_LATCH_12 (SPM_BASE + 0x830) |
| #define PCM_WDT_LATCH_13 (SPM_BASE + 0x834) |
| #define PCM_WDT_LATCH_14 (SPM_BASE + 0x838) |
| #define PCM_WDT_LATCH_15 (SPM_BASE + 0x83C) |
| #define PCM_WDT_LATCH_16 (SPM_BASE + 0x840) |
| #define PCM_WDT_LATCH_17 (SPM_BASE + 0x844) |
| #define PCM_WDT_LATCH_18 (SPM_BASE + 0x848) |
| #define PCM_WDT_LATCH_SPARE_0 (SPM_BASE + 0x84C) |
| #define PCM_WDT_LATCH_SPARE_1 (SPM_BASE + 0x850) |
| #define PCM_WDT_LATCH_SPARE_2 (SPM_BASE + 0x854) |
| #define PCM_WDT_LATCH_CONN_0 (SPM_BASE + 0x870) |
| #define PCM_WDT_LATCH_CONN_1 (SPM_BASE + 0x874) |
| #define PCM_WDT_LATCH_CONN_2 (SPM_BASE + 0x878) |
| #define DRAMC_GATING_ERR_LATCH_CH0_0 (SPM_BASE + 0x8A0) |
| #define DRAMC_GATING_ERR_LATCH_CH0_1 (SPM_BASE + 0x8A4) |
| #define DRAMC_GATING_ERR_LATCH_CH0_2 (SPM_BASE + 0x8A8) |
| #define DRAMC_GATING_ERR_LATCH_CH0_3 (SPM_BASE + 0x8AC) |
| #define DRAMC_GATING_ERR_LATCH_CH0_4 (SPM_BASE + 0x8B0) |
| #define DRAMC_GATING_ERR_LATCH_CH0_5 (SPM_BASE + 0x8B4) |
| #define DRAMC_GATING_ERR_LATCH_CH0_6 (SPM_BASE + 0x8B8) |
| #define DRAMC_GATING_ERR_LATCH_SPARE_0 (SPM_BASE + 0x8F4) |
| #define SPM_ACK_CHK_CON_0 (SPM_BASE + 0x900) |
| #define SPM_ACK_CHK_PC_0 (SPM_BASE + 0x904) |
| #define SPM_ACK_CHK_SEL_0 (SPM_BASE + 0x908) |
| #define SPM_ACK_CHK_TIMER_0 (SPM_BASE + 0x90C) |
| #define SPM_ACK_CHK_STA_0 (SPM_BASE + 0x910) |
| #define SPM_ACK_CHK_SWINT_0 (SPM_BASE + 0x914) |
| #define SPM_ACK_CHK_CON_1 (SPM_BASE + 0x920) |
| #define SPM_ACK_CHK_PC_1 (SPM_BASE + 0x924) |
| #define SPM_ACK_CHK_SEL_1 (SPM_BASE + 0x928) |
| #define SPM_ACK_CHK_TIMER_1 (SPM_BASE + 0x92C) |
| #define SPM_ACK_CHK_STA_1 (SPM_BASE + 0x930) |
| #define SPM_ACK_CHK_SWINT_1 (SPM_BASE + 0x934) |
| #define SPM_ACK_CHK_CON_2 (SPM_BASE + 0x940) |
| #define SPM_ACK_CHK_PC_2 (SPM_BASE + 0x944) |
| #define SPM_ACK_CHK_SEL_2 (SPM_BASE + 0x948) |
| #define SPM_ACK_CHK_TIMER_2 (SPM_BASE + 0x94C) |
| #define SPM_ACK_CHK_STA_2 (SPM_BASE + 0x950) |
| #define SPM_ACK_CHK_SWINT_2 (SPM_BASE + 0x954) |
| #define SPM_ACK_CHK_CON_3 (SPM_BASE + 0x960) |
| #define SPM_ACK_CHK_PC_3 (SPM_BASE + 0x964) |
| #define SPM_ACK_CHK_SEL_3 (SPM_BASE + 0x968) |
| #define SPM_ACK_CHK_TIMER_3 (SPM_BASE + 0x96C) |
| #define SPM_ACK_CHK_STA_3 (SPM_BASE + 0x970) |
| #define SPM_ACK_CHK_SWINT_3 (SPM_BASE + 0x974) |
| #define SPM_COUNTER_0 (SPM_BASE + 0x978) |
| #define SPM_COUNTER_1 (SPM_BASE + 0x97C) |
| #define SPM_COUNTER_2 (SPM_BASE + 0x980) |
| #define SYS_TIMER_CON (SPM_BASE + 0x98C) |
| #define RC_FSM_STA_0 (SPM_BASE + 0xE00) |
| #define RC_CMD_STA_0 (SPM_BASE + 0xE04) |
| #define RC_CMD_STA_1 (SPM_BASE + 0xE08) |
| #define RC_SPI_STA_0 (SPM_BASE + 0xE0C) |
| #define RC_PI_PO_STA_0 (SPM_BASE + 0xE10) |
| #define RC_M00_REQ_STA_0 (SPM_BASE + 0xE14) |
| #define RC_M01_REQ_STA_0 (SPM_BASE + 0xE1C) |
| #define RC_M02_REQ_STA_0 (SPM_BASE + 0xE20) |
| #define RC_M03_REQ_STA_0 (SPM_BASE + 0xE24) |
| #define RC_M04_REQ_STA_0 (SPM_BASE + 0xE28) |
| #define RC_M05_REQ_STA_0 (SPM_BASE + 0xE2C) |
| #define RC_M06_REQ_STA_0 (SPM_BASE + 0xE30) |
| #define RC_M07_REQ_STA_0 (SPM_BASE + 0xE34) |
| #define RC_M08_REQ_STA_0 (SPM_BASE + 0xE38) |
| #define RC_M09_REQ_STA_0 (SPM_BASE + 0xE3C) |
| #define RC_M10_REQ_STA_0 (SPM_BASE + 0xE40) |
| #define RC_M11_REQ_STA_0 (SPM_BASE + 0xE44) |
| #define RC_M12_REQ_STA_0 (SPM_BASE + 0xE48) |
| #define RC_DEBUG_STA_0 (SPM_BASE + 0xE4C) |
| #define RC_DEBUG_TRACE_0_LSB (SPM_BASE + 0xE50) |
| #define RC_DEBUG_TRACE_0_MSB (SPM_BASE + 0xE54) |
| #define RC_DEBUG_TRACE_1_LSB (SPM_BASE + 0xE5C) |
| #define RC_DEBUG_TRACE_1_MSB (SPM_BASE + 0xE60) |
| #define RC_DEBUG_TRACE_2_LSB (SPM_BASE + 0xE64) |
| #define RC_DEBUG_TRACE_2_MSB (SPM_BASE + 0xE6C) |
| #define RC_DEBUG_TRACE_3_LSB (SPM_BASE + 0xE70) |
| #define RC_DEBUG_TRACE_3_MSB (SPM_BASE + 0xE74) |
| #define RC_DEBUG_TRACE_4_LSB (SPM_BASE + 0xE78) |
| #define RC_DEBUG_TRACE_4_MSB (SPM_BASE + 0xE7C) |
| #define RC_DEBUG_TRACE_5_LSB (SPM_BASE + 0xE80) |
| #define RC_DEBUG_TRACE_5_MSB (SPM_BASE + 0xE84) |
| #define RC_DEBUG_TRACE_6_LSB (SPM_BASE + 0xE88) |
| #define RC_DEBUG_TRACE_6_MSB (SPM_BASE + 0xE8C) |
| #define RC_DEBUG_TRACE_7_LSB (SPM_BASE + 0xE90) |
| #define RC_DEBUG_TRACE_7_MSB (SPM_BASE + 0xE94) |
| #define RC_SYS_TIMER_LATCH_0_LSB (SPM_BASE + 0xE98) |
| #define RC_SYS_TIMER_LATCH_0_MSB (SPM_BASE + 0xE9C) |
| #define RC_SYS_TIMER_LATCH_1_LSB (SPM_BASE + 0xEA0) |
| #define RC_SYS_TIMER_LATCH_1_MSB (SPM_BASE + 0xEA4) |
| #define RC_SYS_TIMER_LATCH_2_LSB (SPM_BASE + 0xEA8) |
| #define RC_SYS_TIMER_LATCH_2_MSB (SPM_BASE + 0xEAC) |
| #define RC_SYS_TIMER_LATCH_3_LSB (SPM_BASE + 0xEB0) |
| #define RC_SYS_TIMER_LATCH_3_MSB (SPM_BASE + 0xEB4) |
| #define RC_SYS_TIMER_LATCH_4_LSB (SPM_BASE + 0xEB8) |
| #define RC_SYS_TIMER_LATCH_4_MSB (SPM_BASE + 0xEBC) |
| #define RC_SYS_TIMER_LATCH_5_LSB (SPM_BASE + 0xEC0) |
| #define RC_SYS_TIMER_LATCH_5_MSB (SPM_BASE + 0xEC4) |
| #define RC_SYS_TIMER_LATCH_6_LSB (SPM_BASE + 0xEC8) |
| #define RC_SYS_TIMER_LATCH_6_MSB (SPM_BASE + 0xECC) |
| #define RC_SYS_TIMER_LATCH_7_LSB (SPM_BASE + 0xED0) |
| #define RC_SYS_TIMER_LATCH_7_MSB (SPM_BASE + 0xED4) |
| #define PCM_WDT_LATCH_19 (SPM_BASE + 0xED8) |
| #define PCM_WDT_LATCH_20 (SPM_BASE + 0xEDC) |
| #define PCM_WDT_LATCH_21 (SPM_BASE + 0xEE0) |
| #define PCM_WDT_LATCH_22 (SPM_BASE + 0xEE4) |
| #define PCM_WDT_LATCH_23 (SPM_BASE + 0xEE8) |
| #define PCM_WDT_LATCH_24 (SPM_BASE + 0xEEC) |
| #define PMSR_LAST_DAT (SPM_BASE + 0xF00) |
| #define PMSR_LAST_CNT (SPM_BASE + 0xF04) |
| #define PMSR_LAST_ACK (SPM_BASE + 0xF08) |
| #define SPM_PMSR_SEL_CON0 (SPM_BASE + 0xF10) |
| #define SPM_PMSR_SEL_CON1 (SPM_BASE + 0xF14) |
| #define SPM_PMSR_SEL_CON2 (SPM_BASE + 0xF18) |
| #define SPM_PMSR_SEL_CON3 (SPM_BASE + 0xF1C) |
| #define SPM_PMSR_SEL_CON4 (SPM_BASE + 0xF20) |
| #define SPM_PMSR_SEL_CON5 (SPM_BASE + 0xF24) |
| #define SPM_PMSR_SEL_CON6 (SPM_BASE + 0xF28) |
| #define SPM_PMSR_SEL_CON7 (SPM_BASE + 0xF2C) |
| #define SPM_PMSR_SEL_CON8 (SPM_BASE + 0xF30) |
| #define SPM_PMSR_SEL_CON9 (SPM_BASE + 0xF34) |
| #define SPM_PMSR_SEL_CON10 (SPM_BASE + 0xF3C) |
| #define SPM_PMSR_SEL_CON11 (SPM_BASE + 0xF40) |
| #define SPM_PMSR_TIEMR_STA0 (SPM_BASE + 0xFB8) |
| #define SPM_PMSR_TIEMR_STA1 (SPM_BASE + 0xFBC) |
| #define SPM_PMSR_TIEMR_STA2 (SPM_BASE + 0xFC0) |
| #define SPM_PMSR_GENERAL_CON0 (SPM_BASE + 0xFC4) |
| #define SPM_PMSR_GENERAL_CON1 (SPM_BASE + 0xFC8) |
| #define SPM_PMSR_GENERAL_CON2 (SPM_BASE + 0xFCC) |
| #define SPM_PMSR_GENERAL_CON3 (SPM_BASE + 0xFD0) |
| #define SPM_PMSR_GENERAL_CON4 (SPM_BASE + 0xFD4) |
| #define SPM_PMSR_GENERAL_CON5 (SPM_BASE + 0xFD8) |
| #define SPM_PMSR_SW_RESET (SPM_BASE + 0xFDC) |
| #define SPM_PMSR_MON_CON0 (SPM_BASE + 0xFE0) |
| #define SPM_PMSR_MON_CON1 (SPM_BASE + 0xFE4) |
| #define SPM_PMSR_MON_CON2 (SPM_BASE + 0xFE8) |
| #define SPM_PMSR_LEN_CON0 (SPM_BASE + 0xFEC) |
| #define SPM_PMSR_LEN_CON1 (SPM_BASE + 0xFF0) |
| #define SPM_PMSR_LEN_CON2 (SPM_BASE + 0xFF4) |
| |
| /* POWERON_CONFIG_EN (0x10006000+0x000) */ |
| #define BCLK_CG_EN_LSB (1U << 0) /* 1b */ |
| #define PROJECT_CODE_LSB (1U << 16) /* 16b */ |
| /* SPM_POWER_ON_VAL0 (0x10006000+0x004) */ |
| #define POWER_ON_VAL0_LSB (1U << 0) /* 32b */ |
| /* SPM_POWER_ON_VAL1 (0x10006000+0x008) */ |
| #define POWER_ON_VAL1_LSB (1U << 0) /* 32b */ |
| /* SPM_CLK_CON (0x10006000+0x00C) */ |
| #define REG_SRCCLKEN0_CTL_LSB (1U << 0) /* 2b */ |
| #define REG_SRCCLKEN1_CTL_LSB (1U << 2) /* 2b */ |
| #define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */ |
| #define REG_SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */ |
| #define REG_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */ |
| #define REG_MD1_C32RM_EN_LSB (1U << 9) /* 1b */ |
| #define REG_MD2_C32RM_EN_LSB (1U << 10) /* 1b */ |
| #define REG_CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */ |
| #define REG_CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */ |
| #define REG_SRCCLKEN0_EN_LSB (1U << 13) /* 1b */ |
| #define REG_SRCCLKEN1_EN_LSB (1U << 14) /* 1b */ |
| #define SCP_DCM_EN_LSB (1U << 15) /* 1b */ |
| #define REG_SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 8b */ |
| #define REG_SYSCLK1_SRC_MASK_B_LSB (1U << 24) /* 8b */ |
| /* SPM_CLK_SETTLE (0x10006000+0x010) */ |
| #define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */ |
| /* SPM_AP_STANDBY_CON (0x10006000+0x014) */ |
| #define REG_WFI_OP_LSB (1U << 0) /* 1b */ |
| #define REG_WFI_TYPE_LSB (1U << 1) /* 1b */ |
| #define REG_MP0_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */ |
| #define REG_MP1_CPUTOP_IDLE_MASK_LSB (1U << 3) /* 1b */ |
| #define REG_MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */ |
| #define REG_MD_APSRC_1_SEL_LSB (1U << 25) /* 1b */ |
| #define REG_MD_APSRC_0_SEL_LSB (1U << 26) /* 1b */ |
| #define REG_CONN_APSRC_SEL_LSB (1U << 29) /* 1b */ |
| /* PCM_CON0 (0x10006000+0x018) */ |
| #define PCM_CK_EN_LSB (1U << 2) /* 1b */ |
| #define RG_EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */ |
| #define PCM_CK_FROM_CKSYS_LSB (1U << 4) /* 1b */ |
| #define PCM_SW_RESET_LSB (1U << 15) /* 1b */ |
| #define PCM_CON0_PROJECT_CODE_LSB (1U << 16) /* 16b */ |
| /* PCM_CON1 (0x10006000+0x01C) */ |
| #define RG_IM_SLAVE_LSB (1U << 0) /* 1b */ |
| #define RG_IM_SLEEP_LSB (1U << 1) /* 1b */ |
| #define REG_SPM_SRAM_CTRL_MUX_LSB (1U << 2) /* 1b */ |
| #define RG_AHBMIF_APBEN_LSB (1U << 3) /* 1b */ |
| #define RG_IM_PDN_LSB (1U << 4) /* 1b */ |
| #define RG_PCM_TIMER_EN_LSB (1U << 5) /* 1b */ |
| #define SPM_EVENT_COUNTER_CLR_LSB (1U << 6) /* 1b */ |
| #define RG_DIS_MIF_PROT_LSB (1U << 7) /* 1b */ |
| #define RG_PCM_WDT_EN_LSB (1U << 8) /* 1b */ |
| #define RG_PCM_WDT_WAKE_LSB (1U << 9) /* 1b */ |
| #define REG_SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */ |
| #define REG_SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */ |
| #define REG_EVENT_LOCK_EN_LSB (1U << 12) /* 1b */ |
| #define REG_SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */ |
| #define REG_MD32_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */ |
| #define RG_PCM_IRQ_MSK_LSB (1U << 15) /* 1b */ |
| #define PCM_CON1_PROJECT_CODE_LSB (1U << 16) /* 16b */ |
| /* SPM_POWER_ON_VAL2 (0x10006000+0x020) */ |
| #define POWER_ON_VAL2_LSB (1U << 0) /* 32b */ |
| /* SPM_POWER_ON_VAL3 (0x10006000+0x024) */ |
| #define POWER_ON_VAL3_LSB (1U << 0) /* 32b */ |
| /* PCM_REG_DATA_INI (0x10006000+0x028) */ |
| #define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */ |
| /* PCM_PWR_IO_EN (0x10006000+0x02C) */ |
| #define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */ |
| #define RG_RF_SYNC_EN_LSB (1U << 16) /* 8b */ |
| /* PCM_TIMER_VAL (0x10006000+0x030) */ |
| #define REG_PCM_TIMER_VAL_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_VAL (0x10006000+0x034) */ |
| #define RG_PCM_WDT_VAL_LSB (1U << 0) /* 32b */ |
| /* SPM_SRC6_MASK (0x10006000+0x038) */ |
| #define REG_DPMAIF_SRCCLKENA_MASK_B_LSB (1U << 0) /* 1b */ |
| #define REG_DPMAIF_INFRA_REQ_MASK_B_LSB (1U << 1) /* 1b */ |
| #define REG_DPMAIF_APSRC_REQ_MASK_B_LSB (1U << 2) /* 1b */ |
| #define REG_DPMAIF_VRF18_REQ_MASK_B_LSB (1U << 3) /* 1b */ |
| #define REG_DPMAIF_DDR_EN_MASK_B_LSB (1U << 4) /* 1b */ |
| /* SPM_SW_RST_CON (0x10006000+0x040) */ |
| #define SPM_SW_RST_CON_LSB (1U << 0) /* 16b */ |
| #define SPM_SW_RST_CON_PROJECT_CODE_LSB (1U << 16) /* 16b */ |
| /* SPM_SW_RST_CON_SET (0x10006000+0x044) */ |
| #define SPM_SW_RST_CON_SET_LSB (1U << 0) /* 16b */ |
| #define SPM_SW_RST_CON_SET_PROJECT_CODE_LSB (1U << 16) /* 16b */ |
| /* SPM_SW_RST_CON_CLR (0x10006000+0x048) */ |
| #define SPM_SW_RST_CON_CLR_LSB (1U << 0) /* 16b */ |
| #define SPM_SW_RST_CON_CLR_PROJECT_CODE_LSB (1U << 16) /* 16b */ |
| /* VS1_PSR_MASK_B (0x10006000+0x04C) */ |
| #define VS1_OPP0_PSR_MASK_B_LSB (1U << 0) /* 8b */ |
| #define VS1_OPP1_PSR_MASK_B_LSB (1U << 8) /* 8b */ |
| /* VS2_PSR_MASK_B (0x10006000+0x050) */ |
| #define VS2_OPP0_PSR_MASK_B_LSB (1U << 0) /* 8b */ |
| #define VS2_OPP1_PSR_MASK_B_LSB (1U << 8) /* 8b */ |
| #define VS2_OPP2_PSR_MASK_B_LSB (1U << 16) /* 8b */ |
| /* MD32_CLK_CON (0x10006000+0x084) */ |
| #define REG_MD32_26M_CK_SEL_LSB (1U << 0) /* 1b */ |
| #define REG_MD32_DCM_EN_LSB (1U << 1) /* 1b */ |
| /* SPM_SRAM_RSV_CON (0x10006000+0x088) */ |
| #define SPM_SRAM_SLEEP_B_ECO_EN_LSB (1U << 0) /* 1b */ |
| /* SPM_SWINT (0x10006000+0x08C) */ |
| #define SPM_SWINT_LSB (1U << 0) /* 32b */ |
| /* SPM_SWINT_SET (0x10006000+0x090) */ |
| #define SPM_SWINT_SET_LSB (1U << 0) /* 32b */ |
| /* SPM_SWINT_CLR (0x10006000+0x094) */ |
| #define SPM_SWINT_CLR_LSB (1U << 0) /* 32b */ |
| /* SPM_SCP_MAILBOX (0x10006000+0x098) */ |
| #define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */ |
| /* SCP_SPM_MAILBOX (0x10006000+0x09C) */ |
| #define SCP_SPM_MAILBOX_LSB (1U << 0) /* 32b */ |
| /* SPM_TWAM_CON (0x10006000+0x0A0) */ |
| #define REG_TWAM_ENABLE_LSB (1U << 0) /* 1b */ |
| #define REG_TWAM_SPEED_MODE_EN_LSB (1U << 1) /* 1b */ |
| #define REG_TWAM_SW_RST_LSB (1U << 2) /* 1b */ |
| #define REG_TWAM_IRQ_MASK_LSB (1U << 3) /* 1b */ |
| #define REG_TWAM_MON_TYPE_0_LSB (1U << 4) /* 2b */ |
| #define REG_TWAM_MON_TYPE_1_LSB (1U << 6) /* 2b */ |
| #define REG_TWAM_MON_TYPE_2_LSB (1U << 8) /* 2b */ |
| #define REG_TWAM_MON_TYPE_3_LSB (1U << 10) /* 2b */ |
| /* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */ |
| #define REG_TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */ |
| /* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */ |
| #define REG_TWAM_SIG_SEL_0_LSB (1U << 0) /* 7b */ |
| #define REG_TWAM_SIG_SEL_1_LSB (1U << 8) /* 7b */ |
| #define REG_TWAM_SIG_SEL_2_LSB (1U << 16) /* 7b */ |
| #define REG_TWAM_SIG_SEL_3_LSB (1U << 24) /* 7b */ |
| /* SPM_SCP_IRQ (0x10006000+0x0AC) */ |
| #define SC_SPM2SCP_WAKEUP_LSB (1U << 0) /* 1b */ |
| #define SC_SCP2SPM_WAKEUP_LSB (1U << 4) /* 1b */ |
| /* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */ |
| #define REG_CPU_WAKEUP_LSB (1U << 0) /* 1b */ |
| /* SPM_IRQ_MASK (0x10006000+0x0B4) */ |
| #define REG_SPM_IRQ_MASK_LSB (1U << 0) /* 32b */ |
| /* SPM_SRC_REQ (0x10006000+0x0B8) */ |
| #define REG_SPM_APSRC_REQ_LSB (1U << 0) /* 1b */ |
| #define REG_SPM_F26M_REQ_LSB (1U << 1) /* 1b */ |
| #define REG_SPM_INFRA_REQ_LSB (1U << 3) /* 1b */ |
| #define REG_SPM_VRF18_REQ_LSB (1U << 4) /* 1b */ |
| #define REG_SPM_DDR_EN_REQ_LSB (1U << 7) /* 1b */ |
| #define REG_SPM_DVFS_REQ_LSB (1U << 8) /* 1b */ |
| #define REG_SPM_SW_MAILBOX_REQ_LSB (1U << 9) /* 1b */ |
| #define REG_SPM_SSPM_MAILBOX_REQ_LSB (1U << 10) /* 1b */ |
| #define REG_SPM_ADSP_MAILBOX_REQ_LSB (1U << 11) /* 1b */ |
| #define REG_SPM_SCP_MAILBOX_REQ_LSB (1U << 12) /* 1b */ |
| /* SPM_SRC_MASK (0x10006000+0x0BC) */ |
| #define REG_MD_SRCCLKENA_0_MASK_B_LSB (1U << 0) /* 1b */ |
| #define REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B_LSB (1U << 1) /* 1b */ |
| #define REG_MD_APSRC2INFRA_REQ_0_MASK_B_LSB (1U << 2) /* 1b */ |
| #define REG_MD_APSRC_REQ_0_MASK_B_LSB (1U << 3) /* 1b */ |
| #define REG_MD_VRF18_REQ_0_MASK_B_LSB (1U << 4) /* 1b */ |
| #define REG_MD_DDR_EN_0_MASK_B_LSB (1U << 5) /* 1b */ |
| #define REG_MD_SRCCLKENA_1_MASK_B_LSB (1U << 6) /* 1b */ |
| #define REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B_LSB (1U << 7) /* 1b */ |
| #define REG_MD_APSRC2INFRA_REQ_1_MASK_B_LSB (1U << 8) /* 1b */ |
| #define REG_MD_APSRC_REQ_1_MASK_B_LSB (1U << 9) /* 1b */ |
| #define REG_MD_VRF18_REQ_1_MASK_B_LSB (1U << 10) /* 1b */ |
| #define REG_MD_DDR_EN_1_MASK_B_LSB (1U << 11) /* 1b */ |
| #define REG_CONN_SRCCLKENA_MASK_B_LSB (1U << 12) /* 1b */ |
| #define REG_CONN_SRCCLKENB_MASK_B_LSB (1U << 13) /* 1b */ |
| #define REG_CONN_INFRA_REQ_MASK_B_LSB (1U << 14) /* 1b */ |
| #define REG_CONN_APSRC_REQ_MASK_B_LSB (1U << 15) /* 1b */ |
| #define REG_CONN_VRF18_REQ_MASK_B_LSB (1U << 16) /* 1b */ |
| #define REG_CONN_DDR_EN_MASK_B_LSB (1U << 17) /* 1b */ |
| #define REG_CONN_VFE28_MASK_B_LSB (1U << 18) /* 1b */ |
| #define REG_SRCCLKENI0_SRCCLKENA_MASK_B_LSB (1U << 19) /* 1b */ |
| #define REG_SRCCLKENI0_INFRA_REQ_MASK_B_LSB (1U << 20) /* 1b */ |
| #define REG_SRCCLKENI1_SRCCLKENA_MASK_B_LSB (1U << 21) /* 1b */ |
| #define REG_SRCCLKENI1_INFRA_REQ_MASK_B_LSB (1U << 22) /* 1b */ |
| #define REG_SRCCLKENI2_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */ |
| #define REG_SRCCLKENI2_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */ |
| #define REG_INFRASYS_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ |
| #define REG_INFRASYS_DDR_EN_MASK_B_LSB (1U << 26) /* 1b */ |
| #define REG_MD32_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */ |
| #define REG_MD32_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */ |
| #define REG_MD32_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */ |
| #define REG_MD32_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */ |
| #define REG_MD32_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */ |
| /* SPM_SRC2_MASK (0x10006000+0x0C0) */ |
| #define REG_SCP_SRCCLKENA_MASK_B_LSB (1U << 0) /* 1b */ |
| #define REG_SCP_INFRA_REQ_MASK_B_LSB (1U << 1) /* 1b */ |
| #define REG_SCP_APSRC_REQ_MASK_B_LSB (1U << 2) /* 1b */ |
| #define REG_SCP_VRF18_REQ_MASK_B_LSB (1U << 3) /* 1b */ |
| #define REG_SCP_DDR_EN_MASK_B_LSB (1U << 4) /* 1b */ |
| #define REG_AUDIO_DSP_SRCCLKENA_MASK_B_LSB (1U << 5) /* 1b */ |
| #define REG_AUDIO_DSP_INFRA_REQ_MASK_B_LSB (1U << 6) /* 1b */ |
| #define REG_AUDIO_DSP_APSRC_REQ_MASK_B_LSB (1U << 7) /* 1b */ |
| #define REG_AUDIO_DSP_VRF18_REQ_MASK_B_LSB (1U << 8) /* 1b */ |
| #define REG_AUDIO_DSP_DDR_EN_MASK_B_LSB (1U << 9) /* 1b */ |
| #define REG_UFS_SRCCLKENA_MASK_B_LSB (1U << 10) /* 1b */ |
| #define REG_UFS_INFRA_REQ_MASK_B_LSB (1U << 11) /* 1b */ |
| #define REG_UFS_APSRC_REQ_MASK_B_LSB (1U << 12) /* 1b */ |
| #define REG_UFS_VRF18_REQ_MASK_B_LSB (1U << 13) /* 1b */ |
| #define REG_UFS_DDR_EN_MASK_B_LSB (1U << 14) /* 1b */ |
| #define REG_DISP0_APSRC_REQ_MASK_B_LSB (1U << 15) /* 1b */ |
| #define REG_DISP0_DDR_EN_MASK_B_LSB (1U << 16) /* 1b */ |
| #define REG_DISP1_APSRC_REQ_MASK_B_LSB (1U << 17) /* 1b */ |
| #define REG_DISP1_DDR_EN_MASK_B_LSB (1U << 18) /* 1b */ |
| #define REG_GCE_INFRA_REQ_MASK_B_LSB (1U << 19) /* 1b */ |
| #define REG_GCE_APSRC_REQ_MASK_B_LSB (1U << 20) /* 1b */ |
| #define REG_GCE_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */ |
| #define REG_GCE_DDR_EN_MASK_B_LSB (1U << 22) /* 1b */ |
| #define REG_APU_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */ |
| #define REG_APU_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */ |
| #define REG_APU_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ |
| #define REG_APU_VRF18_REQ_MASK_B_LSB (1U << 26) /* 1b */ |
| #define REG_APU_DDR_EN_MASK_B_LSB (1U << 27) /* 1b */ |
| #define REG_CG_CHECK_SRCCLKENA_MASK_B_LSB (1U << 28) /* 1b */ |
| #define REG_CG_CHECK_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */ |
| #define REG_CG_CHECK_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */ |
| #define REG_CG_CHECK_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */ |
| /* SPM_SRC3_MASK (0x10006000+0x0C4) */ |
| #define REG_DVFSRC_EVENT_TRIGGER_MASK_B_LSB (1U << 0) /* 1b */ |
| #define REG_SW2SPM_INT0_MASK_B_LSB (1U << 1) /* 1b */ |
| #define REG_SW2SPM_INT1_MASK_B_LSB (1U << 2) /* 1b */ |
| #define REG_SW2SPM_INT2_MASK_B_LSB (1U << 3) /* 1b */ |
| #define REG_SW2SPM_INT3_MASK_B_LSB (1U << 4) /* 1b */ |
| #define REG_SC_ADSP2SPM_WAKEUP_MASK_B_LSB (1U << 5) /* 1b */ |
| #define REG_SC_SSPM2SPM_WAKEUP_MASK_B_LSB (1U << 6) /* 4b */ |
| #define REG_SC_SCP2SPM_WAKEUP_MASK_B_LSB (1U << 10) /* 1b */ |
| #define REG_CSYSPWRREQ_MASK_LSB (1U << 11) /* 1b */ |
| #define REG_SPM_SRCCLKENA_RESERVED_MASK_B_LSB (1U << 12) /* 1b */ |
| #define REG_SPM_INFRA_REQ_RESERVED_MASK_B_LSB (1U << 13) /* 1b */ |
| #define REG_SPM_APSRC_REQ_RESERVED_MASK_B_LSB (1U << 14) /* 1b */ |
| #define REG_SPM_VRF18_REQ_RESERVED_MASK_B_LSB (1U << 15) /* 1b */ |
| #define REG_SPM_DDR_EN_RESERVED_MASK_B_LSB (1U << 16) /* 1b */ |
| #define REG_MCUPM_SRCCLKENA_MASK_B_LSB (1U << 17) /* 1b */ |
| #define REG_MCUPM_INFRA_REQ_MASK_B_LSB (1U << 18) /* 1b */ |
| #define REG_MCUPM_APSRC_REQ_MASK_B_LSB (1U << 19) /* 1b */ |
| #define REG_MCUPM_VRF18_REQ_MASK_B_LSB (1U << 20) /* 1b */ |
| #define REG_MCUPM_DDR_EN_MASK_B_LSB (1U << 21) /* 1b */ |
| #define REG_MSDC0_SRCCLKENA_MASK_B_LSB (1U << 22) /* 1b */ |
| #define REG_MSDC0_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */ |
| #define REG_MSDC0_APSRC_REQ_MASK_B_LSB (1U << 24) /* 1b */ |
| #define REG_MSDC0_VRF18_REQ_MASK_B_LSB (1U << 25) /* 1b */ |
| #define REG_MSDC0_DDR_EN_MASK_B_LSB (1U << 26) /* 1b */ |
| #define REG_MSDC1_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */ |
| #define REG_MSDC1_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */ |
| #define REG_MSDC1_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */ |
| #define REG_MSDC1_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */ |
| #define REG_MSDC1_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */ |
| /* SPM_SRC4_MASK (0x10006000+0x0C8) */ |
| #define CCIF_EVENT_MASK_B_LSB (1U << 0) /* 16b */ |
| #define REG_BAK_PSRI_SRCCLKENA_MASK_B_LSB (1U << 16) /* 1b */ |
| #define REG_BAK_PSRI_INFRA_REQ_MASK_B_LSB (1U << 17) /* 1b */ |
| #define REG_BAK_PSRI_APSRC_REQ_MASK_B_LSB (1U << 18) /* 1b */ |
| #define REG_BAK_PSRI_VRF18_REQ_MASK_B_LSB (1U << 19) /* 1b */ |
| #define REG_BAK_PSRI_DDR_EN_MASK_B_LSB (1U << 20) /* 1b */ |
| #define REG_DRAMC0_MD32_INFRA_REQ_MASK_B_LSB (1U << 21) /* 1b */ |
| #define REG_DRAMC0_MD32_VRF18_REQ_MASK_B_LSB (1U << 22) /* 1b */ |
| #define REG_DRAMC1_MD32_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */ |
| #define REG_DRAMC1_MD32_VRF18_REQ_MASK_B_LSB (1U << 24) /* 1b */ |
| #define REG_CONN_SRCCLKENB2PWRAP_MASK_B_LSB (1U << 25) /* 1b */ |
| #define REG_DRAMC0_MD32_WAKEUP_MASK_LSB (1U << 26) /* 1b */ |
| #define REG_DRAMC1_MD32_WAKEUP_MASK_LSB (1U << 27) /* 1b */ |
| /* SPM_SRC5_MASK (0x10006000+0x0CC) */ |
| #define REG_MCUSYS_MERGE_APSRC_REQ_MASK_B_LSB (1U << 0) /* 9b */ |
| #define REG_MCUSYS_MERGE_DDR_EN_MASK_B_LSB (1U << 9) /* 9b */ |
| #define REG_MSDC2_SRCCLKENA_MASK_B_LSB (1U << 18) /* 1b */ |
| #define REG_MSDC2_INFRA_REQ_MASK_B_LSB (1U << 19) /* 1b */ |
| #define REG_MSDC2_APSRC_REQ_MASK_B_LSB (1U << 20) /* 1b */ |
| #define REG_MSDC2_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */ |
| #define REG_MSDC2_DDR_EN_MASK_B_LSB (1U << 22) /* 1b */ |
| #define REG_PCIE_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */ |
| #define REG_PCIE_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */ |
| #define REG_PCIE_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ |
| #define REG_PCIE_VRF18_REQ_MASK_B_LSB (1U << 26) /* 1b */ |
| #define REG_PCIE_DDR_EN_MASK_B_LSB (1U << 27) /* 1b */ |
| /* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0D0) */ |
| #define REG_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */ |
| /* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0D4) */ |
| #define REG_EXT_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */ |
| /* SPM_TWAM_EVENT_CLEAR (0x10006000+0x0D8) */ |
| #define SPM_TWAM_EVENT_CLEAR_LSB (1U << 0) /* 1b */ |
| /* SCP_CLK_CON (0x10006000+0x0DC) */ |
| #define REG_SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */ |
| #define REG_SCP_DCM_EN_LSB (1U << 1) /* 1b */ |
| #define SCP_SECURE_V_REQ_MASK_LSB (1U << 2) /* 1b */ |
| #define SCP_SLP_REQ_LSB (1U << 3) /* 1b */ |
| #define SCP_SLP_ACK_LSB (1U << 4) /* 1b */ |
| /* PCM_DEBUG_CON (0x10006000+0x0E0) */ |
| #define PCM_DEBUG_OUT_ENABLE_LSB (1U << 0) /* 1b */ |
| /* AHB_BUS_CON (0x10006000+0x0E4) */ |
| #define AHB_HADDR_EXT_LSB (1U << 0) /* 2b */ |
| #define REG_AHB_LOCK_LSB (1U << 8) /* 1b */ |
| /* DDR_EN_DBC_CON0 (0x10006000+0x0E8) */ |
| #define REG_ALL_DDR_EN_DBC_LEN_LSB (1U << 0) /* 10b */ |
| #define REG_MD_DDR_EN_0_DBC_LEN_LSB (1U << 10) /* 10b */ |
| #define REG_HW_S1_DBC_LEN_LSB (1U << 20) /* 10b */ |
| /* DDR_EN_DBC_CON1 (0x10006000+0x0EC) */ |
| #define REG_ALL_DDR_EN_DBC_EN_LSB (1U << 0) /* 1b */ |
| #define REG_MD_DDR_EN_0_DBC_EN_LSB (1U << 1) /* 1b */ |
| #define REG_HW_S1_DBC_EN_LSB (1U << 2) /* 1b */ |
| /* SPM_RESOURCE_ACK_CON0 (0x10006000+0x0F0) */ |
| #define REG_MD_SRCCLKENA_ACK_0_MASK_LSB (1U << 0) /* 1b */ |
| #define REG_MD_INFRA_ACK_0_MASK_LSB (1U << 1) /* 1b */ |
| #define REG_MD_APSRC_ACK_0_MASK_LSB (1U << 2) /* 1b */ |
| #define REG_MD_VRF18_ACK_0_MASK_LSB (1U << 3) /* 1b */ |
| #define REG_MD_DDR_EN_ACK_0_MASK_LSB (1U << 4) /* 1b */ |
| #define REG_MD_SRCCLKENA_ACK_1_MASK_LSB (1U << 5) /* 1b */ |
| #define REG_MD_INFRA_ACK_1_MASK_LSB (1U << 6) /* 1b */ |
| #define REG_MD_APSRC_ACK_1_MASK_LSB (1U << 7) /* 1b */ |
| #define REG_MD_VRF18_ACK_1_MASK_LSB (1U << 8) /* 1b */ |
| #define REG_MD_DDR_EN_ACK_1_MASK_LSB (1U << 9) /* 1b */ |
| #define REG_CONN_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */ |
| #define REG_CONN_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */ |
| #define REG_CONN_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */ |
| #define REG_CONN_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */ |
| #define REG_CONN_DDR_EN_ACK_MASK_LSB (1U << 14) /* 1b */ |
| #define REG_MD32_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */ |
| #define REG_MD32_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */ |
| #define REG_MD32_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */ |
| #define REG_MD32_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */ |
| #define REG_MD32_DDR_EN_ACK_MASK_LSB (1U << 19) /* 1b */ |
| #define REG_SCP_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */ |
| #define REG_SCP_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */ |
| #define REG_SCP_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */ |
| #define REG_SCP_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */ |
| #define REG_SCP_DDR_EN_ACK_MASK_LSB (1U << 24) /* 1b */ |
| #define REG_AUDIO_DSP_SRCCLKENA_ACK_MASK_LSB (1U << 25) /* 1b */ |
| #define REG_AUDIO_DSP_INFRA_ACK_MASK_LSB (1U << 26) /* 1b */ |
| #define REG_AUDIO_DSP_APSRC_ACK_MASK_LSB (1U << 27) /* 1b */ |
| #define REG_AUDIO_DSP_VRF18_ACK_MASK_LSB (1U << 28) /* 1b */ |
| #define REG_AUDIO_DSP_DDR_EN_ACK_MASK_LSB (1U << 29) /* 1b */ |
| #define REG_DISP0_DDR_EN_ACK_MASK_LSB (1U << 30) /* 1b */ |
| #define REG_DISP1_APSRC_ACK_MASK_LSB (1U << 31) /* 1b */ |
| /* SPM_RESOURCE_ACK_CON1 (0x10006000+0x0F4) */ |
| #define REG_UFS_SRCCLKENA_ACK_MASK_LSB (1U << 0) /* 1b */ |
| #define REG_UFS_INFRA_ACK_MASK_LSB (1U << 1) /* 1b */ |
| #define REG_UFS_APSRC_ACK_MASK_LSB (1U << 2) /* 1b */ |
| #define REG_UFS_VRF18_ACK_MASK_LSB (1U << 3) /* 1b */ |
| #define REG_UFS_DDR_EN_ACK_MASK_LSB (1U << 4) /* 1b */ |
| #define REG_APU_SRCCLKENA_ACK_MASK_LSB (1U << 5) /* 1b */ |
| #define REG_APU_INFRA_ACK_MASK_LSB (1U << 6) /* 1b */ |
| #define REG_APU_APSRC_ACK_MASK_LSB (1U << 7) /* 1b */ |
| #define REG_APU_VRF18_ACK_MASK_LSB (1U << 8) /* 1b */ |
| #define REG_APU_DDR_EN_ACK_MASK_LSB (1U << 9) /* 1b */ |
| #define REG_MCUPM_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */ |
| #define REG_MCUPM_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */ |
| #define REG_MCUPM_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */ |
| #define REG_MCUPM_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */ |
| #define REG_MCUPM_DDR_EN_ACK_MASK_LSB (1U << 14) /* 1b */ |
| #define REG_MSDC0_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */ |
| #define REG_MSDC0_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */ |
| #define REG_MSDC0_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */ |
| #define REG_MSDC0_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */ |
| #define REG_MSDC0_DDR_EN_ACK_MASK_LSB (1U << 19) /* 1b */ |
| #define REG_MSDC1_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */ |
| #define REG_MSDC1_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */ |
| #define REG_MSDC1_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */ |
| #define REG_MSDC1_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */ |
| #define REG_MSDC1_DDR_EN_ACK_MASK_LSB (1U << 24) /* 1b */ |
| #define REG_DISP0_APSRC_ACK_MASK_LSB (1U << 25) /* 1b */ |
| #define REG_DISP1_DDR_EN_ACK_MASK_LSB (1U << 26) /* 1b */ |
| #define REG_GCE_INFRA_ACK_MASK_LSB (1U << 27) /* 1b */ |
| #define REG_GCE_APSRC_ACK_MASK_LSB (1U << 28) /* 1b */ |
| #define REG_GCE_VRF18_ACK_MASK_LSB (1U << 29) /* 1b */ |
| #define REG_GCE_DDR_EN_ACK_MASK_LSB (1U << 30) /* 1b */ |
| /* SPM_RESOURCE_ACK_CON2 (0x10006000+0x0F8) */ |
| #define SPM_F26M_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */ |
| #define SPM_INFRA_ACK_WAIT_CYCLE_LSB (1U << 8) /* 8b */ |
| #define SPM_APSRC_ACK_WAIT_CYCLE_LSB (1U << 16) /* 8b */ |
| #define SPM_VRF18_ACK_WAIT_CYCLE_LSB (1U << 24) /* 8b */ |
| /* SPM_RESOURCE_ACK_CON3 (0x10006000+0x0FC) */ |
| #define SPM_DDR_EN_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */ |
| #define REG_BAK_PSRI_SRCCLKENA_ACK_MASK_LSB (1U << 8) /* 1b */ |
| #define REG_BAK_PSRI_INFRA_ACK_MASK_LSB (1U << 9) /* 1b */ |
| #define REG_BAK_PSRI_APSRC_ACK_MASK_LSB (1U << 10) /* 1b */ |
| #define REG_BAK_PSRI_VRF18_ACK_MASK_LSB (1U << 11) /* 1b */ |
| #define REG_BAK_PSRI_DDR_EN_ACK_MASK_LSB (1U << 12) /* 1b */ |
| #define REG_MSDC2_SRCCLKENA_ACK_MASK_LSB (1U << 13) /* 1b */ |
| #define REG_MSDC2_INFRA_ACK_MASK_LSB (1U << 14) /* 1b */ |
| #define REG_MSDC2_APSRC_ACK_MASK_LSB (1U << 15) /* 1b */ |
| #define REG_MSDC2_VRF18_ACK_MASK_LSB (1U << 16) /* 1b */ |
| #define REG_MSDC2_DDR_EN_ACK_MASK_LSB (1U << 17) /* 1b */ |
| #define REG_PCIE_SRCCLKENA_ACK_MASK_LSB (1U << 18) /* 1b */ |
| #define REG_PCIE_INFRA_ACK_MASK_LSB (1U << 19) /* 1b */ |
| #define REG_PCIE_APSRC_ACK_MASK_LSB (1U << 20) /* 1b */ |
| #define REG_PCIE_VRF18_ACK_MASK_LSB (1U << 21) /* 1b */ |
| #define REG_PCIE_DDR_EN_ACK_MASK_LSB (1U << 22) /* 1b */ |
| #define REG_DPMAIF_SRCCLKENA_ACK_MASK_LSB (1U << 23) /* 1b */ |
| #define REG_DPMAIF_INFRA_ACK_MASK_LSB (1U << 24) /* 1b */ |
| #define REG_DPMAIF_APSRC_ACK_MASK_LSB (1U << 25) /* 1b */ |
| #define REG_DPMAIF_VRF18_ACK_MASK_LSB (1U << 26) /* 1b */ |
| #define REG_DPMAIF_DDR_EN_ACK_MASK_LSB (1U << 27) /* 1b */ |
| /* PCM_REG0_DATA (0x10006000+0x100) */ |
| #define PCM_REG0_RF_LSB (1U << 0) /* 32b */ |
| /* PCM_REG2_DATA (0x10006000+0x104) */ |
| #define PCM_REG2_RF_LSB (1U << 0) /* 32b */ |
| /* PCM_REG6_DATA (0x10006000+0x108) */ |
| #define PCM_REG6_RF_LSB (1U << 0) /* 32b */ |
| /* PCM_REG7_DATA (0x10006000+0x10C) */ |
| #define PCM_REG7_RF_LSB (1U << 0) /* 32b */ |
| /* PCM_REG13_DATA (0x10006000+0x110) */ |
| #define PCM_REG13_RF_LSB (1U << 0) /* 32b */ |
| /* SRC_REQ_STA_0 (0x10006000+0x114) */ |
| #define MD_SRCCLKENA_0_LSB (1U << 0) /* 1b */ |
| #define MD_SRCCLKENA2INFRA_REQ_0_LSB (1U << 1) /* 1b */ |
| #define MD_APSRC2INFRA_REQ_0_LSB (1U << 2) /* 1b */ |
| #define MD_APSRC_REQ_0_LSB (1U << 3) /* 1b */ |
| #define MD_VRF18_REQ_0_LSB (1U << 4) /* 1b */ |
| #define MD_DDR_EN_0_LSB (1U << 5) /* 1b */ |
| #define MD_SRCCLKENA_1_LSB (1U << 6) /* 1b */ |
| #define MD_SRCCLKENA2INFRA_REQ_1_LSB (1U << 7) /* 1b */ |
| #define MD_APSRC2INFRA_REQ_1_LSB (1U << 8) /* 1b */ |
| #define MD_APSRC_REQ_1_LSB (1U << 9) /* 1b */ |
| #define MD_VRF18_REQ_1_LSB (1U << 10) /* 1b */ |
| #define MD_DDR_EN_1_LSB (1U << 11) /* 1b */ |
| #define CONN_SRCCLKENA_LSB (1U << 12) /* 1b */ |
| #define CONN_SRCCLKENB_LSB (1U << 13) /* 1b */ |
| #define CONN_INFRA_REQ_LSB (1U << 14) /* 1b */ |
| #define CONN_APSRC_REQ_LSB (1U << 15) /* 1b */ |
| #define CONN_VRF18_REQ_LSB (1U << 16) /* 1b */ |
| #define CONN_DDR_EN_LSB (1U << 17) /* 1b */ |
| #define SRCCLKENI_LSB (1U << 18) /* 3b */ |
| #define MD32_SRCCLKENA_LSB (1U << 21) /* 1b */ |
| #define MD32_INFRA_REQ_LSB (1U << 22) /* 1b */ |
| #define MD32_APSRC_REQ_LSB (1U << 23) /* 1b */ |
| #define MD32_VRF18_REQ_LSB (1U << 24) /* 1b */ |
| #define MD32_DDR_EN_LSB (1U << 25) /* 1b */ |
| #define DISP0_APSRC_REQ_LSB (1U << 26) /* 1b */ |
| #define DISP0_DDR_EN_LSB (1U << 27) /* 1b */ |
| #define DISP1_APSRC_REQ_LSB (1U << 28) /* 1b */ |
| #define DISP1_DDR_EN_LSB (1U << 29) /* 1b */ |
| #define DVFSRC_EVENT_TRIGGER_LSB (1U << 30) /* 1b */ |
| /* SRC_REQ_STA_1 (0x10006000+0x118) */ |
| #define SCP_SRCCLKENA_LSB (1U << 0) /* 1b */ |
| #define SCP_INFRA_REQ_LSB (1U << 1) /* 1b */ |
| #define SCP_APSRC_REQ_LSB (1U << 2) /* 1b */ |
| #define SCP_VRF18_REQ_LSB (1U << 3) /* 1b */ |
| #define SCP_DDR_EN_LSB (1U << 4) /* 1b */ |
| #define AUDIO_DSP_SRCCLKENA_LSB (1U << 5) /* 1b */ |
| #define AUDIO_DSP_INFRA_REQ_LSB (1U << 6) /* 1b */ |
| #define AUDIO_DSP_APSRC_REQ_LSB (1U << 7) /* 1b */ |
| #define AUDIO_DSP_VRF18_REQ_LSB (1U << 8) /* 1b */ |
| #define AUDIO_DSP_DDR_EN_LSB (1U << 9) /* 1b */ |
| #define UFS_SRCCLKENA_LSB (1U << 10) /* 1b */ |
| #define UFS_INFRA_REQ_LSB (1U << 11) /* 1b */ |
| #define UFS_APSRC_REQ_LSB (1U << 12) /* 1b */ |
| #define UFS_VRF18_REQ_LSB (1U << 13) /* 1b */ |
| #define UFS_DDR_EN_LSB (1U << 14) /* 1b */ |
| #define GCE_INFRA_REQ_LSB (1U << 15) /* 1b */ |
| #define GCE_APSRC_REQ_LSB (1U << 16) /* 1b */ |
| #define GCE_VRF18_REQ_LSB (1U << 17) /* 1b */ |
| #define GCE_DDR_EN_LSB (1U << 18) /* 1b */ |
| #define INFRASYS_APSRC_REQ_LSB (1U << 19) /* 1b */ |
| #define INFRASYS_DDR_EN_LSB (1U << 20) /* 1b */ |
| #define MSDC0_SRCCLKENA_LSB (1U << 21) /* 1b */ |
| #define MSDC0_INFRA_REQ_LSB (1U << 22) /* 1b */ |
| #define MSDC0_APSRC_REQ_LSB (1U << 23) /* 1b */ |
| #define MSDC0_VRF18_REQ_LSB (1U << 24) /* 1b */ |
| #define MSDC0_DDR_EN_LSB (1U << 25) /* 1b */ |
| #define MSDC1_SRCCLKENA_LSB (1U << 26) /* 1b */ |
| #define MSDC1_INFRA_REQ_LSB (1U << 27) /* 1b */ |
| #define MSDC1_APSRC_REQ_LSB (1U << 28) /* 1b */ |
| #define MSDC1_VRF18_REQ_LSB (1U << 29) /* 1b */ |
| #define MSDC1_DDR_EN_LSB (1U << 30) /* 1b */ |
| /* SRC_REQ_STA_2 (0x10006000+0x11C) */ |
| #define MCUSYS_MERGE_DDR_EN_LSB (1U << 0) /* 9b */ |
| #define EMI_SELF_REFRESH_CH_LSB (1U << 9) /* 2b */ |
| #define SW2SPM_INT_LSB (1U << 11) /* 4b */ |
| #define SC_ADSP2SPM_WAKEUP_LSB (1U << 15) /* 1b */ |
| #define SC_SSPM2SPM_WAKEUP_LSB (1U << 16) /* 4b */ |
| #define SRC_REQ_STA_2_SC_SCP2SPM_WAKEUP_LSB (1U << 20) /* 1b */ |
| #define SPM_SRCCLKENA_RESERVED_LSB (1U << 21) /* 1b */ |
| #define SPM_INFRA_REQ_RESERVED_LSB (1U << 22) /* 1b */ |
| #define SPM_APSRC_REQ_RESERVED_LSB (1U << 23) /* 1b */ |
| #define SPM_VRF18_REQ_RESERVED_LSB (1U << 24) /* 1b */ |
| #define SPM_DDR_EN_RESERVED_LSB (1U << 25) /* 1b */ |
| #define MCUPM_SRCCLKENA_LSB (1U << 26) /* 1b */ |
| #define MCUPM_INFRA_REQ_LSB (1U << 27) /* 1b */ |
| #define MCUPM_APSRC_REQ_LSB (1U << 28) /* 1b */ |
| #define MCUPM_VRF18_REQ_LSB (1U << 29) /* 1b */ |
| #define MCUPM_DDR_EN_LSB (1U << 30) /* 1b */ |
| /* PCM_TIMER_OUT (0x10006000+0x120) */ |
| #define PCM_TIMER_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_OUT (0x10006000+0x124) */ |
| #define PCM_WDT_TIMER_VAL_OUT_LSB (1U << 0) /* 32b */ |
| /* SPM_IRQ_STA (0x10006000+0x128) */ |
| #define TWAM_IRQ_LSB (1U << 2) /* 1b */ |
| #define PCM_IRQ_LSB (1U << 3) /* 1b */ |
| /* SRC_REQ_STA_4 (0x10006000+0x12C) */ |
| #define APU_SRCCLKENA_LSB (1U << 0) /* 1b */ |
| #define APU_INFRA_REQ_LSB (1U << 1) /* 1b */ |
| #define APU_APSRC_REQ_LSB (1U << 2) /* 1b */ |
| #define APU_VRF18_REQ_LSB (1U << 3) /* 1b */ |
| #define APU_DDR_EN_LSB (1U << 4) /* 1b */ |
| #define BAK_PSRI_SRCCLKENA_LSB (1U << 5) /* 1b */ |
| #define BAK_PSRI_INFRA_REQ_LSB (1U << 6) /* 1b */ |
| #define BAK_PSRI_APSRC_REQ_LSB (1U << 7) /* 1b */ |
| #define BAK_PSRI_VRF18_REQ_LSB (1U << 8) /* 1b */ |
| #define BAK_PSRI_DDR_EN_LSB (1U << 9) /* 1b */ |
| #define MSDC2_SRCCLKENA_LSB (1U << 10) /* 1b */ |
| #define MSDC2_INFRA_REQ_LSB (1U << 11) /* 1b */ |
| #define MSDC2_APSRC_REQ_LSB (1U << 12) /* 1b */ |
| #define MSDC2_VRF18_REQ_LSB (1U << 13) /* 1b */ |
| #define MSDC2_DDR_EN_LSB (1U << 14) /* 1b */ |
| #define PCIE_SRCCLKENA_LSB (1U << 15) /* 1b */ |
| #define PCIE_INFRA_REQ_LSB (1U << 16) /* 1b */ |
| #define PCIE_APSRC_REQ_LSB (1U << 17) /* 1b */ |
| #define PCIE_VRF18_REQ_LSB (1U << 18) /* 1b */ |
| #define PCIE_DDR_EN_LSB (1U << 19) /* 1b */ |
| #define DPMAIF_SRCCLKENA_LSB (1U << 20) /* 1b */ |
| #define DPMAIF_INFRA_REQ_LSB (1U << 21) /* 1b */ |
| #define DPMAIF_APSRC_REQ_LSB (1U << 22) /* 1b */ |
| #define DPMAIF_VRF18_REQ_LSB (1U << 23) /* 1b */ |
| #define DPMAIF_DDR_EN_LSB (1U << 24) /* 1b */ |
| /* MD32PCM_WAKEUP_STA (0x10006000+0x130) */ |
| #define MD32PCM_WAKEUP_STA_LSB (1U << 0) /* 32b */ |
| /* MD32PCM_EVENT_STA (0x10006000+0x134) */ |
| #define MD32PCM_EVENT_STA_LSB (1U << 0) /* 32b */ |
| /* SPM_WAKEUP_STA (0x10006000+0x138) */ |
| #define F32K_WAKEUP_EVENT_L_LSB (1U << 0) /* 16b */ |
| #define ASYN_WAKEUP_EVENT_L_LSB (1U << 16) /* 16b */ |
| /* SPM_WAKEUP_EXT_STA (0x10006000+0x13C) */ |
| #define EXT_WAKEUP_EVENT_LSB (1U << 0) /* 32b */ |
| /* SPM_WAKEUP_MISC (0x10006000+0x140) */ |
| #define GIC_WAKEUP_LSB (1U << 0) /* 10b */ |
| #define DVFSRC_IRQ_LSB (1U << 16) /* 1b */ |
| #define SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB (1U << 17) /* 1b */ |
| #define PCM_TIMER_EVENT_LSB (1U << 18) /* 1b */ |
| #define PMIC_EINT_OUT_B_LSB (1U << 19) /* 2b */ |
| #define TWAM_IRQ_B_LSB (1U << 21) /* 1b */ |
| #define PMSR_IRQ_B_SET0_LSB (1U << 22) /* 1b */ |
| #define PMSR_IRQ_B_SET1_LSB (1U << 23) /* 1b */ |
| #define PMSR_IRQ_B_SET2_LSB (1U << 24) /* 1b */ |
| #define SPM_ACK_CHK_WAKEUP_0_LSB (1U << 25) /* 1b */ |
| #define SPM_ACK_CHK_WAKEUP_1_LSB (1U << 26) /* 1b */ |
| #define SPM_ACK_CHK_WAKEUP_2_LSB (1U << 27) /* 1b */ |
| #define SPM_ACK_CHK_WAKEUP_3_LSB (1U << 28) /* 1b */ |
| #define SPM_ACK_CHK_WAKEUP_ALL_LSB (1U << 29) /* 1b */ |
| #define PMIC_IRQ_ACK_LSB (1U << 30) /* 1b */ |
| #define PMIC_SCP_IRQ_LSB (1U << 31) /* 1b */ |
| /* MM_DVFS_HALT (0x10006000+0x144) */ |
| #define MM_DVFS_HALT_LSB (1U << 0) /* 5b */ |
| /* BUS_PROTECT_RDY (0x10006000+0x150) */ |
| #define PROTECT_READY_LSB (1U << 0) /* 32b */ |
| /* BUS_PROTECT1_RDY (0x10006000+0x154) */ |
| #define PROTECT1_READY_LSB (1U << 0) /* 32b */ |
| /* BUS_PROTECT2_RDY (0x10006000+0x158) */ |
| #define PROTECT2_READY_LSB (1U << 0) /* 32b */ |
| /* BUS_PROTECT3_RDY (0x10006000+0x15C) */ |
| #define PROTECT3_READY_LSB (1U << 0) /* 32b */ |
| /* SUBSYS_IDLE_STA (0x10006000+0x160) */ |
| #define SUBSYS_IDLE_SIGNALS_LSB (1U << 0) /* 32b */ |
| /* PCM_STA (0x10006000+0x164) */ |
| #define PCM_CK_SEL_O_LSB (1U << 0) /* 4b */ |
| #define EXT_SRC_STA_LSB (1U << 4) /* 3b */ |
| /* SRC_REQ_STA_3 (0x10006000+0x168) */ |
| #define CCIF_EVENT_RAW_STATUS_LSB (1U << 0) /* 16b */ |
| #define F26M_STATE_LSB (1U << 16) /* 1b */ |
| #define INFRA_STATE_LSB (1U << 17) /* 1b */ |
| #define APSRC_STATE_LSB (1U << 18) /* 1b */ |
| #define VRF18_STATE_LSB (1U << 19) /* 1b */ |
| #define DDR_EN_STATE_LSB (1U << 20) /* 1b */ |
| #define DVFS_STATE_LSB (1U << 21) /* 1b */ |
| #define SW_MAILBOX_STATE_LSB (1U << 22) /* 1b */ |
| #define SSPM_MAILBOX_STATE_LSB (1U << 23) /* 1b */ |
| #define ADSP_MAILBOX_STATE_LSB (1U << 24) /* 1b */ |
| #define SCP_MAILBOX_STATE_LSB (1U << 25) /* 1b */ |
| /* PWR_STATUS (0x10006000+0x16C) */ |
| #define PWR_STATUS_LSB (1U << 0) /* 32b */ |
| /* PWR_STATUS_2ND (0x10006000+0x170) */ |
| #define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ |
| /* CPU_PWR_STATUS (0x10006000+0x174) */ |
| #define MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 0) /* 1b */ |
| #define MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 1) /* 1b */ |
| #define MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 2) /* 1b */ |
| #define MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 3) /* 1b */ |
| #define MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 4) /* 1b */ |
| #define MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 5) /* 1b */ |
| #define MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 6) /* 1b */ |
| #define MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 7) /* 1b */ |
| #define MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 8) /* 1b */ |
| #define MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 9) /* 1b */ |
| /* OTHER_PWR_STATUS (0x10006000+0x178) */ |
| #define OTHER_PWR_STATUS_LSB (1U << 0) /* 32b */ |
| /* SPM_VTCXO_EVENT_COUNT_STA (0x10006000+0x17C) */ |
| #define SPM_VTCXO_SLEEP_COUNT_LSB (1U << 0) /* 16b */ |
| #define SPM_VTCXO_WAKE_COUNT_LSB (1U << 16) /* 16b */ |
| /* SPM_INFRA_EVENT_COUNT_STA (0x10006000+0x180) */ |
| #define SPM_INFRA_SLEEP_COUNT_LSB (1U << 0) /* 16b */ |
| #define SPM_INFRA_WAKE_COUNT_LSB (1U << 16) /* 16b */ |
| /* SPM_VRF18_EVENT_COUNT_STA (0x10006000+0x184) */ |
| #define SPM_VRF18_SLEEP_COUNT_LSB (1U << 0) /* 16b */ |
| #define SPM_VRF18_WAKE_COUNT_LSB (1U << 16) /* 16b */ |
| /* SPM_APSRC_EVENT_COUNT_STA (0x10006000+0x188) */ |
| #define SPM_APSRC_SLEEP_COUNT_LSB (1U << 0) /* 16b */ |
| #define SPM_APSRC_WAKE_COUNT_LSB (1U << 16) /* 16b */ |
| /* SPM_DDREN_EVENT_COUNT_STA (0x10006000+0x18C) */ |
| #define SPM_DDREN_SLEEP_COUNT_LSB (1U << 0) /* 16b */ |
| #define SPM_DDREN_WAKE_COUNT_LSB (1U << 16) /* 16b */ |
| /* MD32PCM_STA (0x10006000+0x190) */ |
| #define MD32PCM_HALT_LSB (1U << 0) /* 1b */ |
| #define MD32PCM_GATED_LSB (1U << 1) /* 1b */ |
| /* MD32PCM_PC (0x10006000+0x194) */ |
| #define MON_PC_LSB (1U << 0) /* 32b */ |
| /* DVFSRC_EVENT_STA (0x10006000+0x1A4) */ |
| #define DVFSRC_EVENT_LSB (1U << 0) /* 32b */ |
| /* BUS_PROTECT4_RDY (0x10006000+0x1A8) */ |
| #define PROTECT4_READY_LSB (1U << 0) /* 32b */ |
| /* BUS_PROTECT5_RDY (0x10006000+0x1AC) */ |
| #define PROTECT5_READY_LSB (1U << 0) /* 32b */ |
| /* BUS_PROTECT6_RDY (0x10006000+0x1B0) */ |
| #define PROTECT6_READY_LSB (1U << 0) /* 32b */ |
| /* BUS_PROTECT7_RDY (0x10006000+0x1B4) */ |
| #define PROTECT7_READY_LSB (1U << 0) /* 32b */ |
| /* BUS_PROTECT8_RDY (0x10006000+0x1B8) */ |
| #define PROTECT8_READY_LSB (1U << 0) /* 32b */ |
| /* SPM_TWAM_LAST_STA0 (0x10006000+0x1D0) */ |
| #define LAST_IDLE_CNT_0_LSB (1U << 0) /* 32b */ |
| /* SPM_TWAM_LAST_STA1 (0x10006000+0x1D4) */ |
| #define LAST_IDLE_CNT_1_LSB (1U << 0) /* 32b */ |
| /* SPM_TWAM_LAST_STA2 (0x10006000+0x1D8) */ |
| #define LAST_IDLE_CNT_2_LSB (1U << 0) /* 32b */ |
| /* SPM_TWAM_LAST_STA3 (0x10006000+0x1DC) */ |
| #define LAST_IDLE_CNT_3_LSB (1U << 0) /* 32b */ |
| /* SPM_TWAM_CURR_STA0 (0x10006000+0x1E0) */ |
| #define CURRENT_IDLE_CNT_0_LSB (1U << 0) /* 32b */ |
| /* SPM_TWAM_CURR_STA1 (0x10006000+0x1E4) */ |
| #define CURRENT_IDLE_CNT_1_LSB (1U << 0) /* 32b */ |
| /* SPM_TWAM_CURR_STA2 (0x10006000+0x1E8) */ |
| #define CURRENT_IDLE_CNT_2_LSB (1U << 0) /* 32b */ |
| /* SPM_TWAM_CURR_STA3 (0x10006000+0x1EC) */ |
| #define CURRENT_IDLE_CNT_3_LSB (1U << 0) /* 32b */ |
| /* SPM_TWAM_TIMER_OUT (0x10006000+0x1F0) */ |
| #define TWAM_TIMER_LSB (1U << 0) /* 32b */ |
| /* SPM_CG_CHECK_STA (0x10006000+0x1F4) */ |
| #define SPM_CG_CHECK_SLEEP_REQ_0_LSB (1U << 0) /* 1b */ |
| #define SPM_CG_CHECK_SLEEP_REQ_1_LSB (1U << 1) /* 1b */ |
| #define SPM_CG_CHECK_SLEEP_REQ_2_LSB (1U << 2) /* 1b */ |
| /* SPM_DVFS_STA (0x10006000+0x1F8) */ |
| #define TARGET_DVFS_LEVEL_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_OPP_STA (0x10006000+0x1FC) */ |
| #define TARGET_DVFS_OPP_LSB (1U << 0) /* 5b */ |
| #define CURRENT_DVFS_OPP_LSB (1U << 5) /* 5b */ |
| #define RELAY_DVFS_OPP_LSB (1U << 10) /* 5b */ |
| /* SPM_MCUSYS_PWR_CON (0x10006000+0x200) */ |
| #define MCUSYS_SPMC_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define MCUSYS_SPMC_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define MCUSYS_SPMC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define MCUSYS_SPMC_RESETPWRON_CONFIG_LSB (1U << 5) /* 1b */ |
| #define MCUSYS_SPMC_DORMANT_EN_LSB (1U << 6) /* 1b */ |
| #define MCUSYS_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */ |
| #define SPM_MCUSYS_PWR_CON_MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 31) /* 1b */ |
| /* SPM_CPUTOP_PWR_CON (0x10006000+0x204) */ |
| #define MP0_SPMC_PWR_RST_B_CPUTOP_LSB (1U << 0) /* 1b */ |
| #define MP0_SPMC_PWR_ON_CPUTOP_LSB (1U << 2) /* 1b */ |
| #define MP0_SPMC_PWR_CLK_DIS_CPUTOP_LSB (1U << 4) /* 1b */ |
| #define MP0_SPMC_RESETPWRON_CONFIG_CPUTOP_LSB (1U << 5) /* 1b */ |
| #define MP0_SPMC_DORMANT_EN_CPUTOP_LSB (1U << 6) /* 1b */ |
| #define MP0_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */ |
| #define MP0_VSRAM_EXT_OFF_LSB (1U << 8) /* 1b */ |
| #define SPM_CPUTOP_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 31) /* 1b */ |
| /* SPM_CPU0_PWR_CON (0x10006000+0x208) */ |
| #define MP0_SPMC_PWR_RST_B_CPU0_LSB (1U << 0) /* 1b */ |
| #define MP0_SPMC_PWR_ON_CPU0_LSB (1U << 2) /* 1b */ |
| #define MP0_SPMC_RESETPWRON_CONFIG_CPU0_LSB (1U << 5) /* 1b */ |
| #define MP0_VPROC_EXT_OFF_CPU0_LSB (1U << 7) /* 1b */ |
| #define SPM_CPU0_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 31) /* 1b */ |
| /* SPM_CPU1_PWR_CON (0x10006000+0x20C) */ |
| #define MP0_SPMC_PWR_RST_B_CPU1_LSB (1U << 0) /* 1b */ |
| #define MP0_SPMC_PWR_ON_CPU1_LSB (1U << 2) /* 1b */ |
| #define MP0_SPMC_RESETPWRON_CONFIG_CPU1_LSB (1U << 5) /* 1b */ |
| #define MP0_VPROC_EXT_OFF_CPU1_LSB (1U << 7) /* 1b */ |
| #define SPM_CPU1_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 31) /* 1b */ |
| /* SPM_CPU2_PWR_CON (0x10006000+0x210) */ |
| #define MP0_SPMC_PWR_RST_B_CPU2_LSB (1U << 0) /* 1b */ |
| #define MP0_SPMC_PWR_ON_CPU2_LSB (1U << 2) /* 1b */ |
| #define MP0_SPMC_RESETPWRON_CONFIG_CPU2_LSB (1U << 5) /* 1b */ |
| #define MP0_VPROC_EXT_OFF_CPU2_LSB (1U << 7) /* 1b */ |
| #define SPM_CPU2_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 31) /* 1b */ |
| /* SPM_CPU3_PWR_CON (0x10006000+0x214) */ |
| #define MP0_SPMC_PWR_RST_B_CPU3_LSB (1U << 0) /* 1b */ |
| #define MP0_SPMC_PWR_ON_CPU3_LSB (1U << 2) /* 1b */ |
| #define MP0_SPMC_RESETPWRON_CONFIG_CPU3_LSB (1U << 5) /* 1b */ |
| #define MP0_VPROC_EXT_OFF_CPU3_LSB (1U << 7) /* 1b */ |
| #define SPM_CPU3_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 31) /* 1b */ |
| /* SPM_CPU4_PWR_CON (0x10006000+0x218) */ |
| #define MP0_SPMC_PWR_RST_B_CPU4_LSB (1U << 0) /* 1b */ |
| #define MP0_SPMC_PWR_ON_CPU4_LSB (1U << 2) /* 1b */ |
| #define MP0_SPMC_RESETPWRON_CONFIG_CPU4_LSB (1U << 5) /* 1b */ |
| #define MP0_VPROC_EXT_OFF_CPU4_LSB (1U << 7) /* 1b */ |
| #define SPM_CPU4_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 31) /* 1b */ |
| /* SPM_CPU5_PWR_CON (0x10006000+0x21C) */ |
| #define MP0_SPMC_PWR_RST_B_CPU5_LSB (1U << 0) /* 1b */ |
| #define MP0_SPMC_PWR_ON_CPU5_LSB (1U << 2) /* 1b */ |
| #define MP0_SPMC_RESETPWRON_CONFIG_CPU5_LSB (1U << 5) /* 1b */ |
| #define MP0_VPROC_EXT_OFF_CPU5_LSB (1U << 7) /* 1b */ |
| #define SPM_CPU5_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 31) /* 1b */ |
| /* SPM_CPU6_PWR_CON (0x10006000+0x220) */ |
| #define MP0_SPMC_PWR_RST_B_CPU6_LSB (1U << 0) /* 1b */ |
| #define MP0_SPMC_PWR_ON_CPU6_LSB (1U << 2) /* 1b */ |
| #define MP0_SPMC_RESETPWRON_CONFIG_CPU6_LSB (1U << 5) /* 1b */ |
| #define MP0_VPROC_EXT_OFF_CPU6_LSB (1U << 7) /* 1b */ |
| #define SPM_CPU6_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 31) /* 1b */ |
| /* SPM_CPU7_PWR_CON (0x10006000+0x224) */ |
| #define MP0_SPMC_PWR_RST_B_CPU7_LSB (1U << 0) /* 1b */ |
| #define MP0_SPMC_PWR_ON_CPU7_LSB (1U << 2) /* 1b */ |
| #define MP0_SPMC_RESETPWRON_CONFIG_CPU7_LSB (1U << 5) /* 1b */ |
| #define MP0_VPROC_EXT_OFF_CPU7_LSB (1U << 7) /* 1b */ |
| #define SPM_CPU7_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 31) /* 1b */ |
| /* ARMPLL_CLK_CON (0x10006000+0x22C) */ |
| #define SC_ARM_FHC_PAUSE_LSB (1U << 0) /* 6b */ |
| #define SC_ARM_CK_OFF_LSB (1U << 6) /* 6b */ |
| #define SC_ARMPLL_OFF_LSB (1U << 12) /* 1b */ |
| #define SC_ARMBPLL_OFF_LSB (1U << 13) /* 1b */ |
| #define SC_ARMBPLL1_OFF_LSB (1U << 14) /* 1b */ |
| #define SC_ARMBPLL2_OFF_LSB (1U << 15) /* 1b */ |
| #define SC_ARMBPLL3_OFF_LSB (1U << 16) /* 1b */ |
| #define SC_CCIPLL_CKOFF_LSB (1U << 17) /* 1b */ |
| #define SC_ARMDDS_OFF_LSB (1U << 18) /* 1b */ |
| #define SC_ARMBPLL_S_OFF_LSB (1U << 19) /* 1b */ |
| #define SC_ARMBPLL1_S_OFF_LSB (1U << 20) /* 1b */ |
| #define SC_ARMBPLL2_S_OFF_LSB (1U << 21) /* 1b */ |
| #define SC_ARMBPLL3_S_OFF_LSB (1U << 22) /* 1b */ |
| #define SC_CCIPLL_PWROFF_LSB (1U << 23) /* 1b */ |
| #define SC_ARMPLLOUT_OFF_LSB (1U << 24) /* 1b */ |
| #define SC_ARMBPLLOUT_OFF_LSB (1U << 25) /* 1b */ |
| #define SC_ARMBPLLOUT1_OFF_LSB (1U << 26) /* 1b */ |
| #define SC_ARMBPLLOUT2_OFF_LSB (1U << 27) /* 1b */ |
| #define SC_ARMBPLLOUT3_OFF_LSB (1U << 28) /* 1b */ |
| #define SC_CCIPLL_OUT_OFF_LSB (1U << 29) /* 1b */ |
| /* MCUSYS_IDLE_STA (0x10006000+0x230) */ |
| #define ARMBUS_IDLE_TO_26M_LSB (1U << 0) /* 1b */ |
| #define MP0_CLUSTER_IDLE_TO_PWR_OFF_LSB (1U << 1) /* 1b */ |
| #define MCUSYS_DDR_EN_0_LSB (1U << 2) /* 1b */ |
| #define MCUSYS_DDR_EN_1_LSB (1U << 3) /* 1b */ |
| #define MCUSYS_DDR_EN_2_LSB (1U << 4) /* 1b */ |
| #define MCUSYS_DDR_EN_3_LSB (1U << 5) /* 1b */ |
| #define MCUSYS_DDR_EN_4_LSB (1U << 6) /* 1b */ |
| #define MCUSYS_DDR_EN_5_LSB (1U << 7) /* 1b */ |
| #define MCUSYS_DDR_EN_6_LSB (1U << 8) /* 1b */ |
| #define MCUSYS_DDR_EN_7_LSB (1U << 9) /* 1b */ |
| #define MP0_CPU_IDLE_TO_PWR_OFF_LSB (1U << 16) /* 8b */ |
| #define WFI_AF_SEL_LSB (1U << 24) /* 8b */ |
| /* GIC_WAKEUP_STA (0x10006000+0x234) */ |
| #define GIC_WAKEUP_STA_GIC_WAKEUP_LSB (1U << 10) /* 10b */ |
| /* CPU_SPARE_CON (0x10006000+0x238) */ |
| #define CPU_SPARE_CON_LSB (1U << 0) /* 32b */ |
| /* CPU_SPARE_CON_SET (0x10006000+0x23C) */ |
| #define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */ |
| /* CPU_SPARE_CON_CLR (0x10006000+0x240) */ |
| #define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ |
| /* ARMPLL_CLK_SEL (0x10006000+0x244) */ |
| #define ARMPLL_CLK_SEL_LSB (1U << 0) /* 15b */ |
| /* EXT_INT_WAKEUP_REQ (0x10006000+0x248) */ |
| #define EXT_INT_WAKEUP_REQ_LSB (1U << 0) /* 10b */ |
| /* EXT_INT_WAKEUP_REQ_SET (0x10006000+0x24C) */ |
| #define EXT_INT_WAKEUP_REQ_SET_LSB (1U << 0) /* 10b */ |
| /* EXT_INT_WAKEUP_REQ_CLR (0x10006000+0x250) */ |
| #define EXT_INT_WAKEUP_REQ_CLR_LSB (1U << 0) /* 10b */ |
| /* MP0_CPU0_IRQ_MASK (0x10006000+0x260) */ |
| #define MP0_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ |
| #define MP0_CPU0_AUX_LSB (1U << 8) /* 11b */ |
| /* MP0_CPU1_IRQ_MASK (0x10006000+0x264) */ |
| #define MP0_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ |
| #define MP0_CPU1_AUX_LSB (1U << 8) /* 11b */ |
| /* MP0_CPU2_IRQ_MASK (0x10006000+0x268) */ |
| #define MP0_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ |
| #define MP0_CPU2_AUX_LSB (1U << 8) /* 11b */ |
| /* MP0_CPU3_IRQ_MASK (0x10006000+0x26C) */ |
| #define MP0_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ |
| #define MP0_CPU3_AUX_LSB (1U << 8) /* 11b */ |
| /* MP1_CPU0_IRQ_MASK (0x10006000+0x270) */ |
| #define MP1_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ |
| #define MP1_CPU0_AUX_LSB (1U << 8) /* 11b */ |
| /* MP1_CPU1_IRQ_MASK (0x10006000+0x274) */ |
| #define MP1_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ |
| #define MP1_CPU1_AUX_LSB (1U << 8) /* 11b */ |
| /* MP1_CPU2_IRQ_MASK (0x10006000+0x278) */ |
| #define MP1_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ |
| #define MP1_CPU2_AUX_LSB (1U << 8) /* 11b */ |
| /* MP1_CPU3_IRQ_MASK (0x10006000+0x27C) */ |
| #define MP1_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ |
| #define MP1_CPU3_AUX_LSB (1U << 8) /* 11b */ |
| /* MP0_CPU0_WFI_EN (0x10006000+0x280) */ |
| #define MP0_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ |
| /* MP0_CPU1_WFI_EN (0x10006000+0x284) */ |
| #define MP0_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ |
| /* MP0_CPU2_WFI_EN (0x10006000+0x288) */ |
| #define MP0_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ |
| /* MP0_CPU3_WFI_EN (0x10006000+0x28C) */ |
| #define MP0_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ |
| /* MP0_CPU4_WFI_EN (0x10006000+0x290) */ |
| #define MP0_CPU4_WFI_EN_LSB (1U << 0) /* 1b */ |
| /* MP0_CPU5_WFI_EN (0x10006000+0x294) */ |
| #define MP0_CPU5_WFI_EN_LSB (1U << 0) /* 1b */ |
| /* MP0_CPU6_WFI_EN (0x10006000+0x298) */ |
| #define MP0_CPU6_WFI_EN_LSB (1U << 0) /* 1b */ |
| /* MP0_CPU7_WFI_EN (0x10006000+0x29C) */ |
| #define MP0_CPU7_WFI_EN_LSB (1U << 0) /* 1b */ |
| /* ROOT_CPUTOP_ADDR (0x10006000+0x2A0) */ |
| #define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */ |
| /* ROOT_CORE_ADDR (0x10006000+0x2A4) */ |
| #define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */ |
| /* SPM2SW_MAILBOX_0 (0x10006000+0x2D0) */ |
| #define SPM2SW_MAILBOX_0_LSB (1U << 0) /* 32b */ |
| /* SPM2SW_MAILBOX_1 (0x10006000+0x2D4) */ |
| #define SPM2SW_MAILBOX_1_LSB (1U << 0) /* 32b */ |
| /* SPM2SW_MAILBOX_2 (0x10006000+0x2D8) */ |
| #define SPM2SW_MAILBOX_2_LSB (1U << 0) /* 32b */ |
| /* SPM2SW_MAILBOX_3 (0x10006000+0x2DC) */ |
| #define SPM2SW_MAILBOX_3_LSB (1U << 0) /* 32b */ |
| /* SW2SPM_INT (0x10006000+0x2E0) */ |
| #define SW2SPM_INT_SW2SPM_INT_LSB (1U << 0) /* 4b */ |
| /* SW2SPM_INT_SET (0x10006000+0x2E4) */ |
| #define SW2SPM_INT_SET_LSB (1U << 0) /* 4b */ |
| /* SW2SPM_INT_CLR (0x10006000+0x2E8) */ |
| #define SW2SPM_INT_CLR_LSB (1U << 0) /* 4b */ |
| /* SW2SPM_MAILBOX_0 (0x10006000+0x2EC) */ |
| #define SW2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ |
| /* SW2SPM_MAILBOX_1 (0x10006000+0x2F0) */ |
| #define SW2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ |
| /* SW2SPM_MAILBOX_2 (0x10006000+0x2F4) */ |
| #define SW2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ |
| /* SW2SPM_MAILBOX_3 (0x10006000+0x2F8) */ |
| #define SW2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ |
| /* SW2SPM_CFG (0x10006000+0x2FC) */ |
| #define SWU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */ |
| /* MD1_PWR_CON (0x10006000+0x300) */ |
| #define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define MD1_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define MD1_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_MD1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* CONN_PWR_CON (0x10006000+0x304) */ |
| #define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define CONN_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define CONN_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| /* MFG0_PWR_CON (0x10006000+0x308) */ |
| #define MFG0_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define MFG0_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define MFG0_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define MFG0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define MFG0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define MFG0_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_MFG0_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* MFG1_PWR_CON (0x10006000+0x30C) */ |
| #define MFG1_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define MFG1_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define MFG1_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define MFG1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define MFG1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define MFG1_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_MFG1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* MFG2_PWR_CON (0x10006000+0x310) */ |
| #define MFG2_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define MFG2_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define MFG2_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define MFG2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define MFG2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define MFG2_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_MFG2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* MFG3_PWR_CON (0x10006000+0x314) */ |
| #define MFG3_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define MFG3_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define MFG3_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define MFG3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define MFG3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define MFG3_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_MFG3_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* MFG4_PWR_CON (0x10006000+0x318) */ |
| #define MFG4_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define MFG4_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define MFG4_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define MFG4_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define MFG4_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define MFG4_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_MFG4_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* MFG5_PWR_CON (0x10006000+0x31C) */ |
| #define MFG5_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define MFG5_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define MFG5_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define MFG5_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define MFG5_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define MFG5_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_MFG5_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* MFG6_PWR_CON (0x10006000+0x320) */ |
| #define MFG6_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define MFG6_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define MFG6_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define MFG6_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define MFG6_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define MFG6_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_MFG6_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* IFR_PWR_CON (0x10006000+0x324) */ |
| #define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define IFR_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define IFR_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define IFR_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* IFR_SUB_PWR_CON (0x10006000+0x328) */ |
| #define IFR_SUB_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define IFR_SUB_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define IFR_SUB_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define IFR_SUB_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define IFR_SUB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define IFR_SUB_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_IFR_SUB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* DPY_PWR_CON (0x10006000+0x32C) */ |
| #define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define DPY_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define DPY_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define DPY_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* ISP_PWR_CON (0x10006000+0x330) */ |
| #define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define ISP_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define ISP_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define ISP_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* ISP2_PWR_CON (0x10006000+0x334) */ |
| #define ISP2_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define ISP2_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define ISP2_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define ISP2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define ISP2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define ISP2_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_ISP2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* IPE_PWR_CON (0x10006000+0x338) */ |
| #define IPE_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define IPE_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define IPE_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define IPE_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define IPE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define IPE_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_IPE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* VDE_PWR_CON (0x10006000+0x33C) */ |
| #define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define VDE_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define VDE_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define VDE_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* VDE2_PWR_CON (0x10006000+0x340) */ |
| #define VDE2_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define VDE2_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define VDE2_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define VDE2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define VDE2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define VDE2_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_VDE2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* VEN_PWR_CON (0x10006000+0x344) */ |
| #define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define VEN_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define VEN_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define VEN_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* VEN_CORE1_PWR_CON (0x10006000+0x348) */ |
| #define VEN_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define VEN_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define VEN_CORE1_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define VEN_CORE1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define VEN_CORE1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define VEN_CORE1_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_VEN_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* MDP_PWR_CON (0x10006000+0x34C) */ |
| #define MDP_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define MDP_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define MDP_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define MDP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define MDP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define MDP_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_MDP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* DIS_PWR_CON (0x10006000+0x350) */ |
| #define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define DIS_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define DIS_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define DIS_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* AUDIO_PWR_CON (0x10006000+0x354) */ |
| #define AUDIO_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define AUDIO_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define AUDIO_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define AUDIO_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define AUDIO_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define AUDIO_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_AUDIO_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* ADSP_PWR_CON (0x10006000+0x358) */ |
| #define ADSP_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define ADSP_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define ADSP_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define ADSP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define ADSP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define ADSP_SRAM_CKISO_LSB (1U << 5) /* 1b */ |
| #define ADSP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ |
| #define ADSP_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define ADSP_SRAM_SLEEP_B_LSB (1U << 9) /* 1b */ |
| #define SC_ADSP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| #define SC_ADSP_SRAM_SLEEP_B_ACK_LSB (1U << 13) /* 1b */ |
| /* CAM_PWR_CON (0x10006000+0x35C) */ |
| #define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define CAM_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define CAM_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define CAM_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* CAM_RAWA_PWR_CON (0x10006000+0x360) */ |
| #define CAM_RAWA_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define CAM_RAWA_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define CAM_RAWA_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define CAM_RAWA_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define CAM_RAWA_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define CAM_RAWA_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_CAM_RAWA_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* CAM_RAWB_PWR_CON (0x10006000+0x364) */ |
| #define CAM_RAWB_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define CAM_RAWB_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define CAM_RAWB_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define CAM_RAWB_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define CAM_RAWB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define CAM_RAWB_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_CAM_RAWB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* CAM_RAWC_PWR_CON (0x10006000+0x368) */ |
| #define CAM_RAWC_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define CAM_RAWC_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define CAM_RAWC_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define CAM_RAWC_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define CAM_RAWC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define CAM_RAWC_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_CAM_RAWC_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* SYSRAM_CON (0x10006000+0x36C) */ |
| #define SYSRAM_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| #define SYSRAM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| #define SYSRAM_SRAM_SLEEP_B_LSB (1U << 4) /* 4b */ |
| #define SYSRAM_SRAM_PDN_LSB (1U << 16) /* 4b */ |
| /* SYSROM_CON (0x10006000+0x370) */ |
| #define SYSROM_SRAM_PDN_LSB (1U << 0) /* 6b */ |
| /* SSPM_SRAM_CON (0x10006000+0x374) */ |
| #define SSPM_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| #define SSPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| #define SSPM_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ |
| #define SSPM_SRAM_PDN_LSB (1U << 16) /* 1b */ |
| /* SCP_SRAM_CON (0x10006000+0x378) */ |
| #define SCP_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| #define SCP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| #define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ |
| #define SCP_SRAM_PDN_LSB (1U << 16) /* 1b */ |
| /* DPY_SHU_SRAM_CON (0x10006000+0x37C) */ |
| #define DPY_SHU_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| #define DPY_SHU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| #define DPY_SHU_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */ |
| #define DPY_SHU_SRAM_PDN_LSB (1U << 16) /* 2b */ |
| /* UFS_SRAM_CON (0x10006000+0x380) */ |
| #define UFS_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| #define UFS_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| #define UFS_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */ |
| #define UFS_SRAM_PDN_LSB (1U << 16) /* 5b */ |
| /* DEVAPC_IFR_SRAM_CON (0x10006000+0x384) */ |
| #define DEVAPC_IFR_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| #define DEVAPC_IFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| #define DEVAPC_IFR_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */ |
| #define DEVAPC_IFR_SRAM_PDN_LSB (1U << 16) /* 6b */ |
| /* DEVAPC_SUBIFR_SRAM_CON (0x10006000+0x388) */ |
| #define DEVAPC_SUBIFR_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| #define DEVAPC_SUBIFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| #define DEVAPC_SUBIFR_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */ |
| #define DEVAPC_SUBIFR_SRAM_PDN_LSB (1U << 16) /* 6b */ |
| /* DEVAPC_ACP_SRAM_CON (0x10006000+0x38C) */ |
| #define DEVAPC_ACP_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| #define DEVAPC_ACP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| #define DEVAPC_ACP_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */ |
| #define DEVAPC_ACP_SRAM_PDN_LSB (1U << 16) /* 6b */ |
| /* USB_SRAM_CON (0x10006000+0x390) */ |
| #define USB_SRAM_PDN_LSB (1U << 0) /* 7b */ |
| /* DUMMY_SRAM_CON (0x10006000+0x394) */ |
| #define DUMMY_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| #define DUMMY_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| #define DUMMY_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */ |
| #define DUMMY_SRAM_PDN_LSB (1U << 16) /* 8b */ |
| /* MD_EXT_BUCK_ISO_CON (0x10006000+0x398) */ |
| #define VMODEM_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ |
| #define VMD_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */ |
| /* EXT_BUCK_ISO (0x10006000+0x39C) */ |
| #define VIMVO_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ |
| #define GPU_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */ |
| #define ADSP_EXT_BUCK_ISO_LSB (1U << 2) /* 1b */ |
| #define IPU_EXT_BUCK_ISO_LSB (1U << 5) /* 3b */ |
| /* DXCC_SRAM_CON (0x10006000+0x3A0) */ |
| #define DXCC_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| #define DXCC_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| #define DXCC_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ |
| #define DXCC_SRAM_PDN_LSB (1U << 16) /* 1b */ |
| /* MSDC_SRAM_CON (0x10006000+0x3A4) */ |
| #define MSDC_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define MSDC_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define MSDC_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define MSDC_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define MSDC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define MSDC_SRAM_CKISO_LSB (1U << 5) /* 1b */ |
| #define MSDC_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ |
| #define MSDC_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define MSDC_SRAM_SLEEP_B_LSB (1U << 9) /* 1b */ |
| #define SC_MSDC_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| #define SC_MSDC_SRAM_SLEEP_B_ACK_LSB (1U << 13) /* 1b */ |
| /* DEBUGTOP_SRAM_CON (0x10006000+0x3A8) */ |
| #define DEBUGTOP_SRAM_PDN_LSB (1U << 0) /* 1b */ |
| /* DP_TX_PWR_CON (0x10006000+0x3AC) */ |
| #define DP_TX_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define DP_TX_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define DP_TX_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define DP_TX_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define DP_TX_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define DP_TX_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_DP_TX_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* DPMAIF_SRAM_CON (0x10006000+0x3B0) */ |
| #define DPMAIF_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| #define DPMAIF_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| #define DPMAIF_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ |
| #define DPMAIF_SRAM_PDN_LSB (1U << 16) /* 1b */ |
| /* DPY_SHU2_SRAM_CON (0x10006000+0x3B4) */ |
| #define DPY_SHU2_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| #define DPY_SHU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| #define DPY_SHU2_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */ |
| #define DPY_SHU2_SRAM_PDN_LSB (1U << 16) /* 2b */ |
| /* DRAMC_MCU2_SRAM_CON (0x10006000+0x3B8) */ |
| #define DRAMC_MCU2_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| #define DRAMC_MCU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| #define DRAMC_MCU2_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ |
| #define DRAMC_MCU2_SRAM_PDN_LSB (1U << 16) /* 1b */ |
| /* DRAMC_MCU_SRAM_CON (0x10006000+0x3BC) */ |
| #define DRAMC_MCU_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| #define DRAMC_MCU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| #define DRAMC_MCU_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ |
| #define DRAMC_MCU_SRAM_PDN_LSB (1U << 16) /* 1b */ |
| /* MCUPM_SRAM_CON (0x10006000+0x3C0) */ |
| #define MCUPM_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define MCUPM_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define MCUPM_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define MCUPM_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define MCUPM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define MCUPM_SRAM_CKISO_LSB (1U << 5) /* 1b */ |
| #define MCUPM_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ |
| #define MCUPM_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define MCUPM_SRAM_SLEEP_B_LSB (1U << 9) /* 1b */ |
| #define SC_MCUPM_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| #define SC_MCUPM_SRAM_SLEEP_B_ACK_LSB (1U << 13) /* 1b */ |
| /* DPY2_PWR_CON (0x10006000+0x3C4) */ |
| #define DPY2_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define DPY2_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define DPY2_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define DPY2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define DPY2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define DPY2_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_DPY2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* PERI_PWR_CON (0x10006000+0x3C8) */ |
| #define PERI_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| #define PERI_PWR_ISO_LSB (1U << 1) /* 1b */ |
| #define PERI_PWR_ON_LSB (1U << 2) /* 1b */ |
| #define PERI_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| #define PERI_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| #define PERI_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| #define SC_PERI_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| /* SPM_MEM_CK_SEL (0x10006000+0x400) */ |
| #define SC_MEM_CK_SEL_LSB (1U << 0) /* 1b */ |
| #define SPM2CKSYS_MEM_CK_MUX_UPDATE_LSB (1U << 1) /* 1b */ |
| /* SPM_BUS_PROTECT_MASK_B (0x10006000+0X404) */ |
| #define SPM_BUS_PROTECT_MASK_B_LSB (1U << 0) /* 32b */ |
| /* SPM_BUS_PROTECT1_MASK_B (0x10006000+0x408) */ |
| #define SPM_BUS_PROTECT1_MASK_B_LSB (1U << 0) /* 32b */ |
| /* SPM_BUS_PROTECT2_MASK_B (0x10006000+0x40C) */ |
| #define SPM_BUS_PROTECT2_MASK_B_LSB (1U << 0) /* 32b */ |
| /* SPM_BUS_PROTECT3_MASK_B (0x10006000+0x410) */ |
| #define SPM_BUS_PROTECT3_MASK_B_LSB (1U << 0) /* 32b */ |
| /* SPM_BUS_PROTECT4_MASK_B (0x10006000+0x414) */ |
| #define SPM_BUS_PROTECT4_MASK_B_LSB (1U << 0) /* 32b */ |
| /* SPM_EMI_BW_MODE (0x10006000+0x418) */ |
| #define EMI_BW_MODE_LSB (1U << 0) /* 1b */ |
| #define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */ |
| #define EMI_BW_MODE_2_LSB (1U << 2) /* 1b */ |
| #define EMI_BOOST_MODE_2_LSB (1U << 3) /* 1b */ |
| /* AP2MD_PEER_WAKEUP (0x10006000+0x41C) */ |
| #define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */ |
| /* ULPOSC_CON (0x10006000+0x420) */ |
| #define ULPOSC_EN_LSB (1U << 0) /* 1b */ |
| #define ULPOSC_RST_LSB (1U << 1) /* 1b */ |
| #define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */ |
| #define ULPOSC_CLK_SEL_LSB (1U << 3) /* 1b */ |
| /* SPM2MM_CON (0x10006000+0x424) */ |
| #define SPM2MM_FORCE_ULTRA_LSB (1U << 0) /* 1b */ |
| #define SPM2MM_DBL_OSTD_ACT_LSB (1U << 1) /* 1b */ |
| #define SPM2MM_ULTRAREQ_LSB (1U << 2) /* 1b */ |
| #define SPM2MD_ULTRAREQ_LSB (1U << 3) /* 1b */ |
| #define SPM2ISP_ULTRAREQ_LSB (1U << 4) /* 1b */ |
| #define MM2SPM_FORCE_ULTRA_ACK_D2T_LSB (1U << 16) /* 1b */ |
| #define MM2SPM_DBL_OSTD_ACT_ACK_D2T_LSB (1U << 17) /* 1b */ |
| #define SPM2ISP_ULTRAACK_D2T_LSB (1U << 18) /* 1b */ |
| #define SPM2MM_ULTRAACK_D2T_LSB (1U << 19) /* 1b */ |
| #define SPM2MD_ULTRAACK_D2T_LSB (1U << 20) /* 1b */ |
| /* SPM_BUS_PROTECT5_MASK_B (0x10006000+0x428) */ |
| #define SPM_BUS_PROTECT5_MASK_B_LSB (1U << 0) /* 32b */ |
| /* SPM2MCUPM_CON (0x10006000+0x42C) */ |
| #define SPM2MCUPM_SW_RST_B_LSB (1U << 0) /* 1b */ |
| #define SPM2MCUPM_SW_INT_LSB (1U << 1) /* 1b */ |
| /* AP_MDSRC_REQ (0x10006000+0x430) */ |
| #define AP_MDSMSRC_REQ_LSB (1U << 0) /* 1b */ |
| #define AP_L1SMSRC_REQ_LSB (1U << 1) /* 1b */ |
| #define AP_MD2SRC_REQ_LSB (1U << 2) /* 1b */ |
| #define AP_MDSMSRC_ACK_LSB (1U << 4) /* 1b */ |
| #define AP_L1SMSRC_ACK_LSB (1U << 5) /* 1b */ |
| #define AP_MD2SRC_ACK_LSB (1U << 6) /* 1b */ |
| /* SPM2EMI_ENTER_ULPM (0x10006000+0x434) */ |
| #define SPM2EMI_ENTER_ULPM_LSB (1U << 0) /* 1b */ |
| /* SPM2MD_DVFS_CON (0x10006000+0x438) */ |
| #define SPM2MD_DVFS_CON_LSB (1U << 0) /* 32b */ |
| /* MD2SPM_DVFS_CON (0x10006000+0x43C) */ |
| #define MD2SPM_DVFS_CON_LSB (1U << 0) /* 32b */ |
| /* SPM_BUS_PROTECT6_MASK_B (0x10006000+0X440) */ |
| #define SPM_BUS_PROTECT6_MASK_B_LSB (1U << 0) /* 32b */ |
| /* SPM_BUS_PROTECT7_MASK_B (0x10006000+0x444) */ |
| #define SPM_BUS_PROTECT7_MASK_B_LSB (1U << 0) /* 32b */ |
| /* SPM_BUS_PROTECT8_MASK_B (0x10006000+0x448) */ |
| #define SPM_BUS_PROTECT8_MASK_B_LSB (1U << 0) /* 32b */ |
| /* SPM_PLL_CON (0x10006000+0x44C) */ |
| #define SC_MAINPLLOUT_OFF_LSB (1U << 0) /* 1b */ |
| #define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */ |
| #define SC_MAINPLL_OFF_LSB (1U << 4) /* 1b */ |
| #define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */ |
| #define SC_MAINPLL_S_OFF_LSB (1U << 8) /* 1b */ |
| #define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */ |
| #define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */ |
| #define SC_MD32K_CK_OFF_LSB (1U << 17) /* 1b */ |
| #define SC_CKSQ1_OFF_LSB (1U << 18) /* 1b */ |
| #define SC_AXI_MEM_CK_OFF_LSB (1U << 19) /* 1b */ |
| /* CPU_DVFS_REQ (0x10006000+0x450) */ |
| #define CPU_DVFS_REQ_LSB (1U << 0) /* 32b */ |
| /* SPM_DRAM_MCU_SW_CON_0 (0x10006000+0x454) */ |
| #define SW_DDR_PST_REQ_LSB (1U << 0) /* 2b */ |
| #define SW_DDR_PST_ABORT_REQ_LSB (1U << 2) /* 2b */ |
| /* SPM_DRAM_MCU_SW_CON_1 (0x10006000+0x458) */ |
| #define SW_DDR_PST_CH0_LSB (1U << 0) /* 32b */ |
| /* SPM_DRAM_MCU_SW_CON_2 (0x10006000+0x45C) */ |
| #define SW_DDR_PST_CH1_LSB (1U << 0) /* 32b */ |
| /* SPM_DRAM_MCU_SW_CON_3 (0x10006000+0x460) */ |
| #define SW_DDR_RESERVED_CH0_LSB (1U << 0) /* 32b */ |
| /* SPM_DRAM_MCU_SW_CON_4 (0x10006000+0x464) */ |
| #define SW_DDR_RESERVED_CH1_LSB (1U << 0) /* 32b */ |
| /* SPM_DRAM_MCU_STA_0 (0x10006000+0x468) */ |
| #define SC_DDR_PST_ACK_LSB (1U << 0) /* 2b */ |
| #define SC_DDR_PST_ABORT_ACK_LSB (1U << 2) /* 2b */ |
| /* SPM_DRAM_MCU_STA_1 (0x10006000+0x46C) */ |
| #define SC_DDR_CUR_PST_STA_CH0_LSB (1U << 0) /* 32b */ |
| /* SPM_DRAM_MCU_STA_2 (0x10006000+0x470) */ |
| #define SC_DDR_CUR_PST_STA_CH1_LSB (1U << 0) /* 32b */ |
| /* SPM_DRAM_MCU_SW_SEL_0 (0x10006000+0x474) */ |
| #define SW_DDR_PST_REQ_SEL_LSB (1U << 0) /* 2b */ |
| #define SW_DDR_PST_SEL_LSB (1U << 2) /* 2b */ |
| #define SW_DDR_PST_ABORT_REQ_SEL_LSB (1U << 4) /* 2b */ |
| #define SW_DDR_RESERVED_SEL_LSB (1U << 6) /* 2b */ |
| #define SW_DDR_PST_ACK_SEL_LSB (1U << 8) /* 2b */ |
| #define SW_DDR_PST_ABORT_ACK_SEL_LSB (1U << 10) /* 2b */ |
| /* RELAY_DVFS_LEVEL (0x10006000+0x478) */ |
| #define RELAY_DVFS_LEVEL_LSB (1U << 0) /* 32b */ |
| /* DRAMC_DPY_CLK_SW_CON_0 (0x10006000+0x480) */ |
| #define SW_PHYPLL_EN_LSB (1U << 0) /* 2b */ |
| #define SW_DPY_VREF_EN_LSB (1U << 2) /* 2b */ |
| #define SW_DPY_DLL_CK_EN_LSB (1U << 4) /* 2b */ |
| #define SW_DPY_DLL_EN_LSB (1U << 6) /* 2b */ |
| #define SW_DPY_2ND_DLL_EN_LSB (1U << 8) /* 2b */ |
| #define SW_MEM_CK_OFF_LSB (1U << 10) /* 2b */ |
| #define SW_DMSUS_OFF_LSB (1U << 12) /* 2b */ |
| #define SW_DPY_MODE_SW_LSB (1U << 14) /* 2b */ |
| #define SW_EMI_CLK_OFF_LSB (1U << 16) /* 2b */ |
| #define SW_DDRPHY_FB_CK_EN_LSB (1U << 18) /* 2b */ |
| #define SW_DR_GATE_RETRY_EN_LSB (1U << 20) /* 2b */ |
| #define SW_DPHY_PRECAL_UP_LSB (1U << 24) /* 2b */ |
| #define SW_DPY_BCLK_ENABLE_LSB (1U << 26) /* 2b */ |
| #define SW_TX_TRACKING_DIS_LSB (1U << 28) /* 2b */ |
| #define SW_DPHY_RXDLY_TRACKING_EN_LSB (1U << 30) /* 2b */ |
| /* DRAMC_DPY_CLK_SW_CON_1 (0x10006000+0x484) */ |
| #define SW_SHU_RESTORE_LSB (1U << 0) /* 2b */ |
| #define SW_DMYRD_MOD_LSB (1U << 2) /* 2b */ |
| #define SW_DMYRD_INTV_LSB (1U << 4) /* 2b */ |
| #define SW_DMYRD_EN_LSB (1U << 6) /* 2b */ |
| #define SW_DRS_DIS_REQ_LSB (1U << 8) /* 2b */ |
| #define SW_DR_SRAM_LOAD_LSB (1U << 10) /* 2b */ |
| #define SW_DR_SRAM_RESTORE_LSB (1U << 12) /* 2b */ |
| #define SW_DR_SHU_LEVEL_SRAM_LATCH_LSB (1U << 14) /* 2b */ |
| #define SW_TX_TRACK_RETRY_EN_LSB (1U << 16) /* 2b */ |
| #define SW_DPY_MIDPI_EN_LSB (1U << 18) /* 2b */ |
| #define SW_DPY_PI_RESETB_EN_LSB (1U << 20) /* 2b */ |
| #define SW_DPY_MCK8X_EN_LSB (1U << 22) /* 2b */ |
| #define SW_DR_SHU_LEVEL_SRAM_CH0_LSB (1U << 24) /* 4b */ |
| #define SW_DR_SHU_LEVEL_SRAM_CH1_LSB (1U << 28) /* 4b */ |
| /* DRAMC_DPY_CLK_SW_CON_2 (0x10006000+0x488) */ |
| #define SW_DR_SHU_LEVEL_LSB (1U << 0) /* 2b */ |
| #define SW_DR_SHU_EN_LSB (1U << 2) /* 1b */ |
| #define SW_DR_SHORT_QUEUE_LSB (1U << 3) /* 1b */ |
| #define SW_PHYPLL_MODE_SW_LSB (1U << 4) /* 1b */ |
| #define SW_PHYPLL2_MODE_SW_LSB (1U << 5) /* 1b */ |
| #define SW_PHYPLL_SHU_EN_LSB (1U << 6) /* 1b */ |
| #define SW_PHYPLL2_SHU_EN_LSB (1U << 7) /* 1b */ |
| #define SW_DR_RESERVED_0_LSB (1U << 24) /* 2b */ |
| #define SW_DR_RESERVED_1_LSB (1U << 26) /* 2b */ |
| #define SW_DR_RESERVED_2_LSB (1U << 28) /* 2b */ |
| #define SW_DR_RESERVED_3_LSB (1U << 30) /* 2b */ |
| /* DRAMC_DPY_CLK_SW_CON_3 (0x10006000+0x48C) */ |
| #define SC_DR_SHU_EN_ACK_LSB (1U << 0) /* 4b */ |
| #define SC_EMI_CLK_OFF_ACK_LSB (1U << 4) /* 4b */ |
| #define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 8) /* 4b */ |
| #define SC_DRAMC_DFS_STA_LSB (1U << 12) /* 4b */ |
| #define SC_DRS_DIS_ACK_LSB (1U << 16) /* 4b */ |
| #define SC_DR_SRAM_LOAD_ACK_LSB (1U << 20) /* 4b */ |
| #define SC_DR_SRAM_PLL_LOAD_ACK_LSB (1U << 24) /* 4b */ |
| #define SC_DR_SRAM_RESTORE_ACK_LSB (1U << 28) /* 4b */ |
| /* DRAMC_DPY_CLK_SW_SEL_0 (0x10006000+0x490) */ |
| #define SW_PHYPLL_EN_SEL_LSB (1U << 0) /* 2b */ |
| #define SW_DPY_VREF_EN_SEL_LSB (1U << 2) /* 2b */ |
| #define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 4) /* 2b */ |
| #define SW_DPY_DLL_EN_SEL_LSB (1U << 6) /* 2b */ |
| #define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 8) /* 2b */ |
| #define SW_MEM_CK_OFF_SEL_LSB (1U << 10) /* 2b */ |
| #define SW_DMSUS_OFF_SEL_LSB (1U << 12) /* 2b */ |
| #define SW_DPY_MODE_SW_SEL_LSB (1U << 14) /* 2b */ |
| #define SW_EMI_CLK_OFF_SEL_LSB (1U << 16) /* 2b */ |
| #define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 18) /* 2b */ |
| #define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 20) /* 2b */ |
| #define SW_DPHY_PRECAL_UP_SEL_LSB (1U << 24) /* 2b */ |
| #define SW_DPY_BCLK_ENABLE_SEL_LSB (1U << 26) /* 2b */ |
| #define SW_TX_TRACKING_DIS_SEL_LSB (1U << 28) /* 2b */ |
| #define SW_DPHY_RXDLY_TRACKING_EN_SEL_LSB (1U << 30) /* 2b */ |
| /* DRAMC_DPY_CLK_SW_SEL_1 (0x10006000+0x494) */ |
| #define SW_SHU_RESTORE_SEL_LSB (1U << 0) /* 2b */ |
| #define SW_DMYRD_MOD_SEL_LSB (1U << 2) /* 2b */ |
| #define SW_DMYRD_INTV_SEL_LSB (1U << 4) /* 2b */ |
| #define SW_DMYRD_EN_SEL_LSB (1U << 6) /* 2b */ |
| #define SW_DRS_DIS_REQ_SEL_LSB (1U << 8) /* 2b */ |
| #define SW_DR_SRAM_LOAD_SEL_LSB (1U << 10) /* 2b */ |
| #define SW_DR_SRAM_RESTORE_SEL_LSB (1U << 12) /* 2b */ |
| #define SW_DR_SHU_LEVEL_SRAM_LATCH_SEL_LSB (1U << 14) /* 2b */ |
| #define SW_TX_TRACK_RETRY_EN_SEL_LSB (1U << 16) /* 2b */ |
| #define SW_DPY_MIDPI_EN_SEL_LSB (1U << 18) /* 2b */ |
| #define SW_DPY_PI_RESETB_EN_SEL_LSB (1U << 20) /* 2b */ |
| #define SW_DPY_MCK8X_EN_SEL_LSB (1U << 22) /* 2b */ |
| #define SW_DR_SHU_LEVEL_SRAM_SEL_LSB (1U << 24) /* 2b */ |
| /* DRAMC_DPY_CLK_SW_SEL_2 (0x10006000+0x498) */ |
| #define SW_DR_SHU_LEVEL_SEL_LSB (1U << 0) /* 1b */ |
| #define SW_DR_SHU_EN_SEL_LSB (1U << 2) /* 1b */ |
| #define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 3) /* 1b */ |
| #define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 4) /* 1b */ |
| #define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 5) /* 1b */ |
| #define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 6) /* 1b */ |
| #define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 7) /* 1b */ |
| #define SW_DR_RESERVED_0_SEL_LSB (1U << 24) /* 2b */ |
| #define SW_DR_RESERVED_1_SEL_LSB (1U << 26) /* 2b */ |
| #define SW_DR_RESERVED_2_SEL_LSB (1U << 28) /* 2b */ |
| #define SW_DR_RESERVED_3_SEL_LSB (1U << 30) /* 2b */ |
| /* DRAMC_DPY_CLK_SW_SEL_3 (0x10006000+0x49C) */ |
| #define SC_DR_SHU_EN_ACK_SEL_LSB (1U << 0) /* 4b */ |
| #define SC_EMI_CLK_OFF_ACK_SEL_LSB (1U << 4) /* 4b */ |
| #define SC_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 8) /* 4b */ |
| #define SC_DRAMC_DFS_STA_SEL_LSB (1U << 12) /* 4b */ |
| #define SC_DRS_DIS_ACK_SEL_LSB (1U << 16) /* 4b */ |
| #define SC_DR_SRAM_LOAD_ACK_SEL_LSB (1U << 20) /* 4b */ |
| #define SC_DR_SRAM_PLL_LOAD_ACK_SEL_LSB (1U << 24) /* 4b */ |
| #define SC_DR_SRAM_RESTORE_ACK_SEL_LSB (1U << 28) /* 4b */ |
| /* DRAMC_DPY_CLK_SPM_CON (0x10006000+0x4A0) */ |
| #define SC_DMYRD_EN_MOD_SEL_PCM_LSB (1U << 0) /* 1b */ |
| #define SC_DMYRD_INTV_SEL_PCM_LSB (1U << 1) /* 1b */ |
| #define SC_DMYRD_EN_PCM_LSB (1U << 2) /* 1b */ |
| #define SC_DRS_DIS_REQ_PCM_LSB (1U << 3) /* 1b */ |
| #define SC_DR_SHU_LEVEL_SRAM_PCM_LSB (1U << 4) /* 4b */ |
| #define SC_DR_GATE_RETRY_EN_PCM_LSB (1U << 8) /* 1b */ |
| #define SC_DR_SHORT_QUEUE_PCM_LSB (1U << 9) /* 1b */ |
| #define SC_DPY_MIDPI_EN_PCM_LSB (1U << 10) /* 1b */ |
| #define SC_DPY_PI_RESETB_EN_PCM_LSB (1U << 11) /* 1b */ |
| #define SC_DPY_MCK8X_EN_PCM_LSB (1U << 12) /* 1b */ |
| #define SC_DR_RESERVED_0_PCM_LSB (1U << 13) /* 1b */ |
| #define SC_DR_RESERVED_1_PCM_LSB (1U << 14) /* 1b */ |
| #define SC_DR_RESERVED_2_PCM_LSB (1U << 15) /* 1b */ |
| #define SC_DR_RESERVED_3_PCM_LSB (1U << 16) /* 1b */ |
| #define SC_DMDRAMCSHU_ACK_ALL_LSB (1U << 24) /* 1b */ |
| #define SC_EMI_CLK_OFF_ACK_ALL_LSB (1U << 25) /* 1b */ |
| #define SC_DR_SHORT_QUEUE_ACK_ALL_LSB (1U << 26) /* 1b */ |
| #define SC_DRAMC_DFS_STA_ALL_LSB (1U << 27) /* 1b */ |
| #define SC_DRS_DIS_ACK_ALL_LSB (1U << 28) /* 1b */ |
| #define SC_DR_SRAM_LOAD_ACK_ALL_LSB (1U << 29) /* 1b */ |
| #define SC_DR_SRAM_PLL_LOAD_ACK_ALL_LSB (1U << 30) /* 1b */ |
| #define SC_DR_SRAM_RESTORE_ACK_ALL_LSB (1U << 31) /* 1b */ |
| /* SPM_DVFS_LEVEL (0x10006000+0x4A4) */ |
| #define SPM_DVFS_LEVEL_LSB (1U << 0) /* 32b */ |
| /* SPM_CIRQ_CON (0x10006000+0x4A8) */ |
| #define CIRQ_CLK_SEL_LSB (1U << 0) /* 1b */ |
| /* SPM_DVFS_MISC (0x10006000+0x4AC) */ |
| #define MSDC_DVFS_REQUEST_LSB (1U << 0) /* 1b */ |
| #define SPM2EMI_SLP_PROT_EN_LSB (1U << 1) /* 1b */ |
| #define SPM_DVFS_FORCE_ENABLE_LSB (1U << 2) /* 1b */ |
| #define FORCE_DVFS_WAKE_LSB (1U << 3) /* 1b */ |
| #define SPM_DVFSRC_ENABLE_LSB (1U << 4) /* 1b */ |
| #define SPM_DVFS_DONE_LSB (1U << 5) /* 1b */ |
| #define DVFSRC_IRQ_WAKEUP_EVENT_MASK_LSB (1U << 6) /* 1b */ |
| #define SPM2RC_EVENT_ABORT_LSB (1U << 7) /* 1b */ |
| #define EMI_SLP_IDLE_LSB (1U << 14) /* 1b */ |
| #define SDIO_READY_TO_SPM_LSB (1U << 15) /* 1b */ |
| /* SPM_VS1_VS2_RC_CON (0x10006000+0x4B0) */ |
| #define VS1_INIT_LEVEL_LSB (1U << 0) /* 2b */ |
| #define VS1_INIT_LSB (1U << 2) /* 1b */ |
| #define VS1_CURR_LEVEL_LSB (1U << 3) /* 2b */ |
| #define VS1_NEXT_LEVEL_LSB (1U << 5) /* 2b */ |
| #define VS1_VOTE_LEVEL_LSB (1U << 7) /* 2b */ |
| #define VS1_TRIGGER_LSB (1U << 9) /* 1b */ |
| #define VS2_INIT_LEVEL_LSB (1U << 10) /* 3b */ |
| #define VS2_INIT_LSB (1U << 13) /* 1b */ |
| #define VS2_CURR_LEVEL_LSB (1U << 14) /* 3b */ |
| #define VS2_NEXT_LEVEL_LSB (1U << 17) /* 3b */ |
| #define VS2_VOTE_LEVEL_LSB (1U << 20) /* 3b */ |
| #define VS2_TRIGGER_LSB (1U << 23) /* 1b */ |
| #define VS1_FORCE_LSB (1U << 24) /* 1b */ |
| #define VS2_FORCE_LSB (1U << 25) /* 1b */ |
| #define VS1_VOTE_LEVEL_FORCE_LSB (1U << 26) /* 2b */ |
| #define VS2_VOTE_LEVEL_FORCE_LSB (1U << 28) /* 3b */ |
| /* RG_MODULE_SW_CG_0_MASK_REQ_0 (0x10006000+0x4B4) */ |
| #define RG_MODULE_SW_CG_0_MASK_REQ_0_LSB (1U << 0) /* 32b */ |
| /* RG_MODULE_SW_CG_0_MASK_REQ_1 (0x10006000+0x4B8) */ |
| #define RG_MODULE_SW_CG_0_MASK_REQ_1_LSB (1U << 0) /* 32b */ |
| /* RG_MODULE_SW_CG_0_MASK_REQ_2 (0x10006000+0x4BC) */ |
| #define RG_MODULE_SW_CG_0_MASK_REQ_2_LSB (1U << 0) /* 32b */ |
| /* RG_MODULE_SW_CG_1_MASK_REQ_0 (0x10006000+0x4C0) */ |
| #define RG_MODULE_SW_CG_1_MASK_REQ_0_LSB (1U << 0) /* 32b */ |
| /* RG_MODULE_SW_CG_1_MASK_REQ_1 (0x10006000+0x4C4) */ |
| #define RG_MODULE_SW_CG_1_MASK_REQ_1_LSB (1U << 0) /* 32b */ |
| /* RG_MODULE_SW_CG_1_MASK_REQ_2 (0x10006000+0x4C8) */ |
| #define RG_MODULE_SW_CG_1_MASK_REQ_2_LSB (1U << 0) /* 32b */ |
| /* RG_MODULE_SW_CG_2_MASK_REQ_0 (0x10006000+0x4CC) */ |
| #define RG_MODULE_SW_CG_2_MASK_REQ_0_LSB (1U << 0) /* 32b */ |
| /* RG_MODULE_SW_CG_2_MASK_REQ_1 (0x10006000+0x4D0) */ |
| #define RG_MODULE_SW_CG_2_MASK_REQ_1_LSB (1U << 0) /* 32b */ |
| /* RG_MODULE_SW_CG_2_MASK_REQ_2 (0x10006000+0x4D4) */ |
| #define RG_MODULE_SW_CG_2_MASK_REQ_2_LSB (1U << 0) /* 32b */ |
| /* RG_MODULE_SW_CG_3_MASK_REQ_0 (0x10006000+0x4D8) */ |
| #define RG_MODULE_SW_CG_3_MASK_REQ_0_LSB (1U << 0) /* 32b */ |
| /* RG_MODULE_SW_CG_3_MASK_REQ_1 (0x10006000+0x4DC) */ |
| #define RG_MODULE_SW_CG_3_MASK_REQ_1_LSB (1U << 0) /* 32b */ |
| /* RG_MODULE_SW_CG_3_MASK_REQ_2 (0x10006000+0x4E0) */ |
| #define RG_MODULE_SW_CG_3_MASK_REQ_2_LSB (1U << 0) /* 32b */ |
| /* PWR_STATUS_MASK_REQ_0 (0x10006000+0x4E4) */ |
| #define PWR_STATUS_MASK_REQ_0_LSB (1U << 0) /* 32b */ |
| /* PWR_STATUS_MASK_REQ_1 (0x10006000+0x4E8) */ |
| #define PWR_STATUS_MASK_REQ_1_LSB (1U << 0) /* 32b */ |
| /* PWR_STATUS_MASK_REQ_2 (0x10006000+0x4EC) */ |
| #define PWR_STATUS_MASK_REQ_2_LSB (1U << 0) /* 32b */ |
| /* SPM_CG_CHECK_CON (0x10006000+0x4F0) */ |
| #define APMIXEDSYS_BUSY_MASK_REQ_0_LSB (1U << 0) /* 5b */ |
| #define APMIXEDSYS_BUSY_MASK_REQ_1_LSB (1U << 8) /* 5b */ |
| #define APMIXEDSYS_BUSY_MASK_REQ_2_LSB (1U << 16) /* 5b */ |
| #define AUDIOSYS_BUSY_MASK_REQ_0_LSB (1U << 24) /* 1b */ |
| #define AUDIOSYS_BUSY_MASK_REQ_1_LSB (1U << 25) /* 1b */ |
| #define AUDIOSYS_BUSY_MASK_REQ_2_LSB (1U << 26) /* 1b */ |
| #define SSUSB_BUSY_MASK_REQ_0_LSB (1U << 27) /* 1b */ |
| #define SSUSB_BUSY_MASK_REQ_1_LSB (1U << 28) /* 1b */ |
| #define SSUSB_BUSY_MASK_REQ_2_LSB (1U << 29) /* 1b */ |
| /* SPM_SRC_RDY_STA (0x10006000+0x4F4) */ |
| #define SPM_INFRA_INTERNAL_ACK_LSB (1U << 0) /* 1b */ |
| #define SPM_VRF18_INTERNAL_ACK_LSB (1U << 1) /* 1b */ |
| /* SPM_DVS_DFS_LEVEL (0x10006000+0x4F8) */ |
| #define SPM_DFS_LEVEL_LSB (1U << 0) /* 16b */ |
| #define SPM_DVS_LEVEL_LSB (1U << 16) /* 16b */ |
| /* SPM_FORCE_DVFS (0x10006000+0x4FC) */ |
| #define FORCE_DVFS_LEVEL_LSB (1U << 0) /* 32b */ |
| /* SRCLKEN_RC_CFG (0x10006000+0x500) */ |
| #define SRCLKEN_RC_CFG_LSB (1U << 0) /* 32b */ |
| /* RC_CENTRAL_CFG1 (0x10006000+0x504) */ |
| #define RC_CENTRAL_CFG1_LSB (1U << 0) /* 32b */ |
| /* RC_CENTRAL_CFG2 (0x10006000+0x508) */ |
| #define RC_CENTRAL_CFG2_LSB (1U << 0) /* 32b */ |
| /* RC_CMD_ARB_CFG (0x10006000+0x50C) */ |
| #define RC_CMD_ARB_CFG_LSB (1U << 0) /* 32b */ |
| /* RC_PMIC_RCEN_ADDR (0x10006000+0x510) */ |
| #define RC_PMIC_RCEN_ADDR_LSB (1U << 0) /* 16b */ |
| #define RC_PMIC_RCEN_RESERVE_LSB (1U << 16) /* 16b */ |
| /* RC_PMIC_RCEN_SET_CLR_ADDR (0x10006000+0x514) */ |
| #define RC_PMIC_RCEN_SET_ADDR_LSB (1U << 0) /* 16b */ |
| #define RC_PMIC_RCEN_CLR_ADDR_LSB (1U << 16) /* 16b */ |
| /* RC_DCXO_FPM_CFG (0x10006000+0x518) */ |
| #define RC_DCXO_FPM_CFG_LSB (1U << 0) /* 32b */ |
| /* RC_CENTRAL_CFG3 (0x10006000+0x51C) */ |
| #define RC_CENTRAL_CFG3_LSB (1U << 0) /* 32b */ |
| /* RC_M00_SRCLKEN_CFG (0x10006000+0x520) */ |
| #define RC_M00_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| #define RC_SW_SRCLKEN_RC (1U << 3) /* 1b */ |
| #define RC_SW_SRCLKEN_FPM (1U << 4) /* 1b */ |
| /* RC_M01_SRCLKEN_CFG (0x10006000+0x524) */ |
| #define RC_M01_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| /* RC_M02_SRCLKEN_CFG (0x10006000+0x528) */ |
| #define RC_M02_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| /* RC_M03_SRCLKEN_CFG (0x10006000+0x52C) */ |
| #define RC_M03_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| /* RC_M04_SRCLKEN_CFG (0x10006000+0x530) */ |
| #define RC_M04_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| /* RC_M05_SRCLKEN_CFG (0x10006000+0x534) */ |
| #define RC_M05_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| /* RC_M06_SRCLKEN_CFG (0x10006000+0x538) */ |
| #define RC_M06_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| /* RC_M07_SRCLKEN_CFG (0x10006000+0x53C) */ |
| #define RC_M07_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| /* RC_M08_SRCLKEN_CFG (0x10006000+0x540) */ |
| #define RC_M08_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| /* RC_M09_SRCLKEN_CFG (0x10006000+0x544) */ |
| #define RC_M09_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| /* RC_M10_SRCLKEN_CFG (0x10006000+0x548) */ |
| #define RC_M10_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| /* RC_M11_SRCLKEN_CFG (0x10006000+0x54C) */ |
| #define RC_M11_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| /* RC_M12_SRCLKEN_CFG (0x10006000+0x550) */ |
| #define RC_M12_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| /* RC_SRCLKEN_SW_CON_CFG (0x10006000+0x554) */ |
| #define RC_SRCLKEN_SW_CON_CFG_LSB (1U << 0) /* 32b */ |
| /* RC_CENTRAL_CFG4 (0x10006000+0x558) */ |
| #define RC_CENTRAL_CFG4_LSB (1U << 0) /* 32b */ |
| /* RC_PROTOCOL_CHK_CFG (0x10006000+0x560) */ |
| #define RC_PROTOCOL_CHK_CFG_LSB (1U << 0) /* 32b */ |
| /* RC_DEBUG_CFG (0x10006000+0x564) */ |
| #define RC_DEBUG_CFG_LSB (1U << 0) /* 32b */ |
| /* RC_MISC_0 (0x10006000+0x5B4) */ |
| #define SRCCLKENO_LSB (1U << 0) /* 2b */ |
| #define PCM_SRCCLKENO_LSB (1U << 3) /* 2b */ |
| #define RC_VREQ_LSB (1U << 5) /* 1b */ |
| #define RC_SPM_SRCCLKENO_0_ACK_LSB (1U << 6) /* 1b */ |
| /* RC_SPM_CTRL (0x10006000+0x5B8) */ |
| #define SPM_AP_26M_RDY_LSB (1U << 0) /* 1b */ |
| #define KEEP_RC_SPI_ACTIVE_LSB (1U << 1) /* 1b */ |
| #define SPM2RC_DMY_CTRL_LSB (1U << 2) /* 6b */ |
| /* SUBSYS_INTF_CFG (0x10006000+0x5BC) */ |
| #define SRCLKEN_FPM_MASK_B_LSB (1U << 0) /* 13b */ |
| #define SRCLKEN_BBLPM_MASK_B_LSB (1U << 16) /* 13b */ |
| /* PCM_WDT_LATCH_25 (0x10006000+0x5C0) */ |
| #define PCM_WDT_LATCH_25_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_26 (0x10006000+0x5C4) */ |
| #define PCM_WDT_LATCH_26_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_27 (0x10006000+0x5C8) */ |
| #define PCM_WDT_LATCH_27_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_28 (0x10006000+0x5CC) */ |
| #define PCM_WDT_LATCH_28_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_29 (0x10006000+0x5D0) */ |
| #define PCM_WDT_LATCH_29_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_30 (0x10006000+0x5D4) */ |
| #define PCM_WDT_LATCH_30_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_31 (0x10006000+0x5D8) */ |
| #define PCM_WDT_LATCH_31_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_32 (0x10006000+0x5DC) */ |
| #define PCM_WDT_LATCH_32_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_33 (0x10006000+0x5E0) */ |
| #define PCM_WDT_LATCH_33_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_34 (0x10006000+0x5E4) */ |
| #define PCM_WDT_LATCH_34_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_35 (0x10006000+0x5EC) */ |
| #define PCM_WDT_LATCH_35_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_36 (0x10006000+0x5F0) */ |
| #define PCM_WDT_LATCH_36_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_37 (0x10006000+0x5F4) */ |
| #define PCM_WDT_LATCH_37_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_38 (0x10006000+0x5F8) */ |
| #define PCM_WDT_LATCH_38_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_39 (0x10006000+0x5FC) */ |
| #define PCM_WDT_LATCH_39_LSB (1U << 0) /* 32b */ |
| /* SPM_SW_FLAG_0 (0x10006000+0x600) */ |
| #define SPM_SW_FLAG_LSB (1U << 0) /* 32b */ |
| /* SPM_SW_DEBUG_0 (0x10006000+0x604) */ |
| #define SPM_SW_DEBUG_0_LSB (1U << 0) /* 32b */ |
| /* SPM_SW_FLAG_1 (0x10006000+0x608) */ |
| #define SPM_SW_FLAG_1_LSB (1U << 0) /* 32b */ |
| /* SPM_SW_DEBUG_1 (0x10006000+0x60C) */ |
| #define SPM_SW_DEBUG_1_LSB (1U << 0) /* 32b */ |
| /* SPM_SW_RSV_0 (0x10006000+0x610) */ |
| #define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */ |
| /* SPM_SW_RSV_1 (0x10006000+0x614) */ |
| #define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */ |
| /* SPM_SW_RSV_2 (0x10006000+0x618) */ |
| #define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */ |
| /* SPM_SW_RSV_3 (0x10006000+0x61C) */ |
| #define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */ |
| /* SPM_SW_RSV_4 (0x10006000+0x620) */ |
| #define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */ |
| /* SPM_SW_RSV_5 (0x10006000+0x624) */ |
| #define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */ |
| /* SPM_SW_RSV_6 (0x10006000+0x628) */ |
| #define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */ |
| /* SPM_SW_RSV_7 (0x10006000+0x62C) */ |
| #define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */ |
| /* SPM_SW_RSV_8 (0x10006000+0x630) */ |
| #define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */ |
| /* SPM_BK_WAKE_EVENT (0x10006000+0x634) */ |
| #define SPM_BK_WAKE_EVENT_LSB (1U << 0) /* 32b */ |
| /* SPM_BK_VTCXO_DUR (0x10006000+0x638) */ |
| #define SPM_BK_VTCXO_DUR_LSB (1U << 0) /* 32b */ |
| /* SPM_BK_WAKE_MISC (0x10006000+0x63C) */ |
| #define SPM_BK_WAKE_MISC_LSB (1U << 0) /* 32b */ |
| /* SPM_BK_PCM_TIMER (0x10006000+0x640) */ |
| #define SPM_BK_PCM_TIMER_LSB (1U << 0) /* 32b */ |
| /* SPM_RSV_CON_0 (0x10006000+0x650) */ |
| #define SPM_RSV_CON_0_LSB (1U << 0) /* 32b */ |
| /* SPM_RSV_CON_1 (0x10006000+0x654) */ |
| #define SPM_RSV_CON_1_LSB (1U << 0) /* 32b */ |
| /* SPM_RSV_STA_0 (0x10006000+0x658) */ |
| #define SPM_RSV_STA_0_LSB (1U << 0) /* 32b */ |
| /* SPM_RSV_STA_1 (0x10006000+0x65C) */ |
| #define SPM_RSV_STA_1_LSB (1U << 0) /* 32b */ |
| /* SPM_SPARE_CON (0x10006000+0x660) */ |
| #define SPM_SPARE_CON_LSB (1U << 0) /* 32b */ |
| /* SPM_SPARE_CON_SET (0x10006000+0x664) */ |
| #define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */ |
| /* SPM_SPARE_CON_CLR (0x10006000+0x668) */ |
| #define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ |
| /* SPM_CROSS_WAKE_M00_REQ (0x10006000+0x66C) */ |
| #define SPM_CROSS_WAKE_M00_REQ_LSB (1U << 0) /* 5b */ |
| #define SPM_CROSS_WAKE_M00_CHK_LSB (1U << 8) /* 5b */ |
| /* SPM_CROSS_WAKE_M01_REQ (0x10006000+0x670) */ |
| #define SPM_CROSS_WAKE_M01_REQ_LSB (1U << 0) /* 5b */ |
| #define SPM_CROSS_WAKE_M01_CHK_LSB (1U << 8) /* 5b */ |
| /* SPM_CROSS_WAKE_M02_REQ (0x10006000+0x674) */ |
| #define SPM_CROSS_WAKE_M02_REQ_LSB (1U << 0) /* 5b */ |
| #define SPM_CROSS_WAKE_M02_CHK_LSB (1U << 8) /* 5b */ |
| /* SPM_CROSS_WAKE_M03_REQ (0x10006000+0x678) */ |
| #define SPM_CROSS_WAKE_M03_REQ_LSB (1U << 0) /* 5b */ |
| #define SPM_CROSS_WAKE_M03_CHK_LSB (1U << 8) /* 5b */ |
| /* SCP_VCORE_LEVEL (0x10006000+0x67C) */ |
| #define SCP_VCORE_LEVEL_LSB (1U << 0) /* 16b */ |
| /* SC_MM_CK_SEL_CON (0x10006000+0x680) */ |
| #define SC_MM_CK_SEL_LSB (1U << 0) /* 4b */ |
| #define SC_MM_CK_SEL_EN_LSB (1U << 4) /* 1b */ |
| /* SPARE_ACK_MASK (0x10006000+0x684) */ |
| #define SPARE_ACK_MASK_B_LSB (1U << 0) /* 32b */ |
| /* SPM_CROSS_WAKE_M04_REQ (0x10006000+0x688) */ |
| #define SPM_CROSS_WAKE_M04_REQ_LSB (1U << 0) /* 5b */ |
| #define SPM_CROSS_WAKE_M04_CHK_LSB (1U << 8) /* 5b */ |
| /* SPM_DV_CON_0 (0x10006000+0x68C) */ |
| #define SPM_DV_CON_0_LSB (1U << 0) /* 32b */ |
| /* SPM_DV_CON_1 (0x10006000+0x690) */ |
| #define SPM_DV_CON_1_LSB (1U << 0) /* 32b */ |
| /* SPM_DV_STA (0x10006000+0x694) */ |
| #define SPM_DV_STA_LSB (1U << 0) /* 32b */ |
| /* CONN_XOWCN_DEBUG_EN (0x10006000+0x698) */ |
| #define CONN_XOWCN_DEBUG_EN_LSB (1U << 0) /* 1b */ |
| /* SPM_SEMA_M0 (0x10006000+0x69C) */ |
| #define SPM_SEMA_M0_LSB (1U << 0) /* 8b */ |
| /* SPM_SEMA_M1 (0x10006000+0x6A0) */ |
| #define SPM_SEMA_M1_LSB (1U << 0) /* 8b */ |
| /* SPM_SEMA_M2 (0x10006000+0x6A4) */ |
| #define SPM_SEMA_M2_LSB (1U << 0) /* 8b */ |
| /* SPM_SEMA_M3 (0x10006000+0x6A8) */ |
| #define SPM_SEMA_M3_LSB (1U << 0) /* 8b */ |
| /* SPM_SEMA_M4 (0x10006000+0x6AC) */ |
| #define SPM_SEMA_M4_LSB (1U << 0) /* 8b */ |
| /* SPM_SEMA_M5 (0x10006000+0x6B0) */ |
| #define SPM_SEMA_M5_LSB (1U << 0) /* 8b */ |
| /* SPM_SEMA_M6 (0x10006000+0x6B4) */ |
| #define SPM_SEMA_M6_LSB (1U << 0) /* 8b */ |
| /* SPM_SEMA_M7 (0x10006000+0x6B8) */ |
| #define SPM_SEMA_M7_LSB (1U << 0) /* 8b */ |
| /* SPM2ADSP_MAILBOX (0x10006000+0x6BC) */ |
| #define SPM2ADSP_MAILBOX_LSB (1U << 0) /* 32b */ |
| /* ADSP2SPM_MAILBOX (0x10006000+0x6C0) */ |
| #define ADSP2SPM_MAILBOX_LSB (1U << 0) /* 32b */ |
| /* SPM_ADSP_IRQ (0x10006000+0x6C4) */ |
| #define SC_SPM2ADSP_WAKEUP_LSB (1U << 0) /* 1b */ |
| #define SPM_ADSP_IRQ_SC_ADSP2SPM_WAKEUP_LSB (1U << 4) /* 1b */ |
| /* SPM_MD32_IRQ (0x10006000+0x6C8) */ |
| #define SC_SPM2SSPM_WAKEUP_LSB (1U << 0) /* 4b */ |
| #define SPM_MD32_IRQ_SC_SSPM2SPM_WAKEUP_LSB (1U << 4) /* 4b */ |
| /* SPM2PMCU_MAILBOX_0 (0x10006000+0x6CC) */ |
| #define SPM2PMCU_MAILBOX_0_LSB (1U << 0) /* 32b */ |
| /* SPM2PMCU_MAILBOX_1 (0x10006000+0x6D0) */ |
| #define SPM2PMCU_MAILBOX_1_LSB (1U << 0) /* 32b */ |
| /* SPM2PMCU_MAILBOX_2 (0x10006000+0x6D4) */ |
| #define SPM2PMCU_MAILBOX_2_LSB (1U << 0) /* 32b */ |
| /* SPM2PMCU_MAILBOX_3 (0x10006000+0x6D8) */ |
| #define SPM2PMCU_MAILBOX_3_LSB (1U << 0) /* 32b */ |
| /* PMCU2SPM_MAILBOX_0 (0x10006000+0x6DC) */ |
| #define PMCU2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ |
| /* PMCU2SPM_MAILBOX_1 (0x10006000+0x6E0) */ |
| #define PMCU2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ |
| /* PMCU2SPM_MAILBOX_2 (0x10006000+0x6E4) */ |
| #define PMCU2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ |
| /* PMCU2SPM_MAILBOX_3 (0x10006000+0x6E8) */ |
| #define PMCU2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ |
| /* UFS_PSRI_SW (0x10006000+0x6EC) */ |
| #define UFS_PSRI_SW_LSB (1U << 0) /* 1b */ |
| /* UFS_PSRI_SW_SET (0x10006000+0x6F0) */ |
| #define UFS_PSRI_SW_SET_LSB (1U << 0) /* 1b */ |
| /* UFS_PSRI_SW_CLR (0x10006000+0x6F4) */ |
| #define UFS_PSRI_SW_CLR_LSB (1U << 0) /* 1b */ |
| /* SPM_AP_SEMA (0x10006000+0x6F8) */ |
| #define SPM_AP_SEMA_LSB (1U << 0) /* 1b */ |
| /* SPM_SPM_SEMA (0x10006000+0x6FC) */ |
| #define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */ |
| /* SPM_DVFS_CON (0x10006000+0x700) */ |
| #define SPM_DVFS_CON_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CON_STA (0x10006000+0x704) */ |
| #define SPM_DVFS_CON_STA_LSB (1U << 0) /* 32b */ |
| /* SPM_PMIC_SPMI_CON (0x10006000+0x708) */ |
| #define SPM_PMIC_SPMI_CMD_LSB (1U << 0) /* 2b */ |
| #define SPM_PMIC_SPMI_SLAVEID_LSB (1U << 2) /* 4b */ |
| #define SPM_PMIC_SPMI_PMIFID_LSB (1U << 6) /* 1b */ |
| #define SPM_PMIC_SPMI_DBCNT_LSB (1U << 7) /* 1b */ |
| /* SPM_DVFS_CMD0 (0x10006000+0x710) */ |
| #define SPM_DVFS_CMD0_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CMD1 (0x10006000+0x714) */ |
| #define SPM_DVFS_CMD1_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CMD2 (0x10006000+0x718) */ |
| #define SPM_DVFS_CMD2_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CMD3 (0x10006000+0x71C) */ |
| #define SPM_DVFS_CMD3_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CMD4 (0x10006000+0x720) */ |
| #define SPM_DVFS_CMD4_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CMD5 (0x10006000+0x724) */ |
| #define SPM_DVFS_CMD5_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CMD6 (0x10006000+0x728) */ |
| #define SPM_DVFS_CMD6_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CMD7 (0x10006000+0x72C) */ |
| #define SPM_DVFS_CMD7_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CMD8 (0x10006000+0x730) */ |
| #define SPM_DVFS_CMD8_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CMD9 (0x10006000+0x734) */ |
| #define SPM_DVFS_CMD9_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CMD10 (0x10006000+0x738) */ |
| #define SPM_DVFS_CMD10_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CMD11 (0x10006000+0x73C) */ |
| #define SPM_DVFS_CMD11_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CMD12 (0x10006000+0x740) */ |
| #define SPM_DVFS_CMD12_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CMD13 (0x10006000+0x744) */ |
| #define SPM_DVFS_CMD13_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CMD14 (0x10006000+0x748) */ |
| #define SPM_DVFS_CMD14_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CMD15 (0x10006000+0x74C) */ |
| #define SPM_DVFS_CMD15_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CMD16 (0x10006000+0x750) */ |
| #define SPM_DVFS_CMD16_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CMD17 (0x10006000+0x754) */ |
| #define SPM_DVFS_CMD17_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CMD18 (0x10006000+0x758) */ |
| #define SPM_DVFS_CMD18_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CMD19 (0x10006000+0x75C) */ |
| #define SPM_DVFS_CMD19_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CMD20 (0x10006000+0x760) */ |
| #define SPM_DVFS_CMD20_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CMD21 (0x10006000+0x764) */ |
| #define SPM_DVFS_CMD21_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CMD22 (0x10006000+0x768) */ |
| #define SPM_DVFS_CMD22_LSB (1U << 0) /* 32b */ |
| /* SPM_DVFS_CMD23 (0x10006000+0x76C) */ |
| #define SPM_DVFS_CMD23_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_VALUE_L (0x10006000+0x770) */ |
| #define SYS_TIMER_VALUE_L_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_VALUE_H (0x10006000+0x774) */ |
| #define SYS_TIMER_VALUE_H_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_START_L (0x10006000+0x778) */ |
| #define SYS_TIMER_START_L_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_START_H (0x10006000+0x77C) */ |
| #define SYS_TIMER_START_H_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_L_00 (0x10006000+0x780) */ |
| #define SYS_TIMER_LATCH_L_00_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_H_00 (0x10006000+0x784) */ |
| #define SYS_TIMER_LATCH_H_00_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_L_01 (0x10006000+0x788) */ |
| #define SYS_TIMER_LATCH_L_01_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_H_01 (0x10006000+0x78C) */ |
| #define SYS_TIMER_LATCH_H_01_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_L_02 (0x10006000+0x790) */ |
| #define SYS_TIMER_LATCH_L_02_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_H_02 (0x10006000+0x794) */ |
| #define SYS_TIMER_LATCH_H_02_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_L_03 (0x10006000+0x798) */ |
| #define SYS_TIMER_LATCH_L_03_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_H_03 (0x10006000+0x79C) */ |
| #define SYS_TIMER_LATCH_H_03_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_L_04 (0x10006000+0x7A0) */ |
| #define SYS_TIMER_LATCH_L_04_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_H_04 (0x10006000+0x7A4) */ |
| #define SYS_TIMER_LATCH_H_04_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_L_05 (0x10006000+0x7A8) */ |
| #define SYS_TIMER_LATCH_L_05_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_H_05 (0x10006000+0x7AC) */ |
| #define SYS_TIMER_LATCH_H_05_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_L_06 (0x10006000+0x7B0) */ |
| #define SYS_TIMER_LATCH_L_06_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_H_06 (0x10006000+0x7B4) */ |
| #define SYS_TIMER_LATCH_H_06_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_L_07 (0x10006000+0x7B8) */ |
| #define SYS_TIMER_LATCH_L_07_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_H_07 (0x10006000+0x7BC) */ |
| #define SYS_TIMER_LATCH_H_07_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_L_08 (0x10006000+0x7C0) */ |
| #define SYS_TIMER_LATCH_L_08_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_H_08 (0x10006000+0x7C4) */ |
| #define SYS_TIMER_LATCH_H_08_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_L_09 (0x10006000+0x7C8) */ |
| #define SYS_TIMER_LATCH_L_09_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_H_09 (0x10006000+0x7CC) */ |
| #define SYS_TIMER_LATCH_H_09_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_L_10 (0x10006000+0x7D0) */ |
| #define SYS_TIMER_LATCH_L_10_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_H_10 (0x10006000+0x7D4) */ |
| #define SYS_TIMER_LATCH_H_10_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_L_11 (0x10006000+0x7D8) */ |
| #define SYS_TIMER_LATCH_L_11_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_H_11 (0x10006000+0x7DC) */ |
| #define SYS_TIMER_LATCH_H_11_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_L_12 (0x10006000+0x7E0) */ |
| #define SYS_TIMER_LATCH_L_12_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_H_12 (0x10006000+0x7E4) */ |
| #define SYS_TIMER_LATCH_H_12_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_L_13 (0x10006000+0x7E8) */ |
| #define SYS_TIMER_LATCH_L_13_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_H_13 (0x10006000+0x7EC) */ |
| #define SYS_TIMER_LATCH_H_13_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_L_14 (0x10006000+0x7F0) */ |
| #define SYS_TIMER_LATCH_L_14_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_H_14 (0x10006000+0x7F4) */ |
| #define SYS_TIMER_LATCH_H_14_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_L_15 (0x10006000+0x7F8) */ |
| #define SYS_TIMER_LATCH_L_15_LSB (1U << 0) /* 32b */ |
| /* SYS_TIMER_LATCH_H_15 (0x10006000+0x7FC) */ |
| #define SYS_TIMER_LATCH_H_15_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_0 (0x10006000+0x800) */ |
| #define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_1 (0x10006000+0x804) */ |
| #define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_2 (0x10006000+0x808) */ |
| #define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_3 (0x10006000+0x80C) */ |
| #define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_4 (0x10006000+0x810) */ |
| #define PCM_WDT_LATCH_4_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_5 (0x10006000+0x814) */ |
| #define PCM_WDT_LATCH_5_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_6 (0x10006000+0x818) */ |
| #define PCM_WDT_LATCH_6_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_7 (0x10006000+0x81C) */ |
| #define PCM_WDT_LATCH_7_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_8 (0x10006000+0x820) */ |
| #define PCM_WDT_LATCH_8_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_9 (0x10006000+0x824) */ |
| #define PCM_WDT_LATCH_9_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_10 (0x10006000+0x828) */ |
| #define PCM_WDT_LATCH_10_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_11 (0x10006000+0x82C) */ |
| #define PCM_WDT_LATCH_11_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_12 (0x10006000+0x830) */ |
| #define PCM_WDT_LATCH_12_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_13 (0x10006000+0x834) */ |
| #define PCM_WDT_LATCH_13_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_14 (0x10006000+0x838) */ |
| #define PCM_WDT_LATCH_14_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_15 (0x10006000+0x83C) */ |
| #define PCM_WDT_LATCH_15_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_16 (0x10006000+0x840) */ |
| #define PCM_WDT_LATCH_16_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_17 (0x10006000+0x844) */ |
| #define PCM_WDT_LATCH_17_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_18 (0x10006000+0x848) */ |
| #define PCM_WDT_LATCH_18_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_SPARE_0 (0x10006000+0x84C) */ |
| #define PCM_WDT_LATCH_SPARE_0_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_SPARE_1 (0x10006000+0x850) */ |
| #define PCM_WDT_LATCH_SPARE_1_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_SPARE_2 (0x10006000+0x854) */ |
| #define PCM_WDT_LATCH_SPARE_2_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_CONN_0 (0x10006000+0x870) */ |
| #define PCM_WDT_LATCH_CONN_0_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_CONN_1 (0x10006000+0x874) */ |
| #define PCM_WDT_LATCH_CONN_1_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_CONN_2 (0x10006000+0x878) */ |
| #define PCM_WDT_LATCH_CONN_2_LSB (1U << 0) /* 32b */ |
| /* DRAMC_GATING_ERR_LATCH_CH0_0 (0x10006000+0x8A0) */ |
| #define DRAMC_GATING_ERR_LATCH_CH0_0_LSB (1U << 0) /* 32b */ |
| /* DRAMC_GATING_ERR_LATCH_CH0_1 (0x10006000+0x8A4) */ |
| #define DRAMC_GATING_ERR_LATCH_CH0_1_LSB (1U << 0) /* 32b */ |
| /* DRAMC_GATING_ERR_LATCH_CH0_2 (0x10006000+0x8A8) */ |
| #define DRAMC_GATING_ERR_LATCH_CH0_2_LSB (1U << 0) /* 32b */ |
| /* DRAMC_GATING_ERR_LATCH_CH0_3 (0x10006000+0x8AC) */ |
| #define DRAMC_GATING_ERR_LATCH_CH0_3_LSB (1U << 0) /* 32b */ |
| /* DRAMC_GATING_ERR_LATCH_CH0_4 (0x10006000+0x8B0) */ |
| #define DRAMC_GATING_ERR_LATCH_CH0_4_LSB (1U << 0) /* 32b */ |
| /* DRAMC_GATING_ERR_LATCH_CH0_5 (0x10006000+0x8B4) */ |
| #define DRAMC_GATING_ERR_LATCH_CH0_5_LSB (1U << 0) /* 32b */ |
| /* DRAMC_GATING_ERR_LATCH_CH0_6 (0x10006000+0x8B8) */ |
| #define DRAMC_GATING_ERR_LATCH_CH0_6_LSB (1U << 0) /* 32b */ |
| /* DRAMC_GATING_ERR_LATCH_SPARE_0 (0x10006000+0x8F4) */ |
| #define DRAMC_GATING_ERR_LATCH_SPARE_0_LSB (1U << 0) /* 32b */ |
| /* SPM_ACK_CHK_CON_0 (0x10006000+0x900) */ |
| #define SPM_ACK_CHK_SW_EN_0_LSB (1U << 0) /* 1b */ |
| #define SPM_ACK_CHK_CLR_ALL_0_LSB (1U << 1) /* 1b */ |
| #define SPM_ACK_CHK_CLR_TIMER_0_LSB (1U << 2) /* 1b */ |
| #define SPM_ACK_CHK_CLR_IRQ_0_LSB (1U << 3) /* 1b */ |
| #define SPM_ACK_CHK_STA_EN_0_LSB (1U << 4) /* 1b */ |
| #define SPM_ACK_CHK_WAKEUP_EN_0_LSB (1U << 5) /* 1b */ |
| #define SPM_ACK_CHK_WDT_EN_0_LSB (1U << 6) /* 1b */ |
| #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_0_LSB (1U << 7) /* 1b */ |
| #define SPM_ACK_CHK_HW_EN_0_LSB (1U << 8) /* 1b */ |
| #define SPM_ACK_CHK_HW_MODE_0_LSB (1U << 9) /* 3b */ |
| #define SPM_ACK_CHK_FAIL_0_LSB (1U << 15) /* 1b */ |
| /* SPM_ACK_CHK_PC_0 (0x10006000+0x904) */ |
| #define SPM_ACK_CHK_HW_TRIG_PC_VAL_0_LSB (1U << 0) /* 16b */ |
| #define SPM_ACK_CHK_HW_TARG_PC_VAL_0_LSB (1U << 16) /* 16b */ |
| /* SPM_ACK_CHK_SEL_0 (0x10006000+0x908) */ |
| #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_0_LSB (1U << 0) /* 5b */ |
| #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_0_LSB (1U << 5) /* 3b */ |
| #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_0_LSB (1U << 16) /* 5b */ |
| #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_0_LSB (1U << 21) /* 3b */ |
| /* SPM_ACK_CHK_TIMER_0 (0x10006000+0x90C) */ |
| #define SPM_ACK_CHK_TIMER_VAL_0_LSB (1U << 0) /* 16b */ |
| #define SPM_ACK_CHK_TIMER_0_LSB (1U << 16) /* 16b */ |
| /* SPM_ACK_CHK_STA_0 (0x10006000+0x910) */ |
| #define SPM_ACK_CHK_STA_0_LSB (1U << 0) /* 32b */ |
| /* SPM_ACK_CHK_SWINT_0 (0x10006000+0x914) */ |
| #define SPM_ACK_CHK_SWINT_EN_0_LSB (1U << 0) /* 32b */ |
| /* SPM_ACK_CHK_CON_1 (0x10006000+0x920) */ |
| #define SPM_ACK_CHK_SW_EN_1_LSB (1U << 0) /* 1b */ |
| #define SPM_ACK_CHK_CLR_ALL_1_LSB (1U << 1) /* 1b */ |
| #define SPM_ACK_CHK_CLR_TIMER_1_LSB (1U << 2) /* 1b */ |
| #define SPM_ACK_CHK_CLR_IRQ_1_LSB (1U << 3) /* 1b */ |
| #define SPM_ACK_CHK_STA_EN_1_LSB (1U << 4) /* 1b */ |
| #define SPM_ACK_CHK_WAKEUP_EN_1_LSB (1U << 5) /* 1b */ |
| #define SPM_ACK_CHK_WDT_EN_1_LSB (1U << 6) /* 1b */ |
| #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_1_LSB (1U << 7) /* 1b */ |
| #define SPM_ACK_CHK_HW_EN_1_LSB (1U << 8) /* 1b */ |
| #define SPM_ACK_CHK_HW_MODE_1_LSB (1U << 9) /* 3b */ |
| #define SPM_ACK_CHK_FAIL_1_LSB (1U << 15) /* 1b */ |
| /* SPM_ACK_CHK_PC_1 (0x10006000+0x924) */ |
| #define SPM_ACK_CHK_HW_TRIG_PC_VAL_1_LSB (1U << 0) /* 16b */ |
| #define SPM_ACK_CHK_HW_TARG_PC_VAL_1_LSB (1U << 16) /* 16b */ |
| /* SPM_ACK_CHK_SEL_1 (0x10006000+0x928) */ |
| #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_1_LSB (1U << 0) /* 5b */ |
| #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_1_LSB (1U << 5) /* 3b */ |
| #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_1_LSB (1U << 16) /* 5b */ |
| #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_1_LSB (1U << 21) /* 3b */ |
| /* SPM_ACK_CHK_TIMER_1 (0x10006000+0x92C) */ |
| #define SPM_ACK_CHK_TIMER_VAL_1_LSB (1U << 0) /* 16b */ |
| #define SPM_ACK_CHK_TIMER_1_LSB (1U << 16) /* 16b */ |
| /* SPM_ACK_CHK_STA_1 (0x10006000+0x930) */ |
| #define SPM_ACK_CHK_STA_1_LSB (1U << 0) /* 32b */ |
| /* SPM_ACK_CHK_SWINT_1 (0x10006000+0x934) */ |
| #define SPM_ACK_CHK_SWINT_EN_1_LSB (1U << 0) /* 32b */ |
| /* SPM_ACK_CHK_CON_2 (0x10006000+0x940) */ |
| #define SPM_ACK_CHK_SW_EN_2_LSB (1U << 0) /* 1b */ |
| #define SPM_ACK_CHK_CLR_ALL_2_LSB (1U << 1) /* 1b */ |
| #define SPM_ACK_CHK_CLR_TIMER_2_LSB (1U << 2) /* 1b */ |
| #define SPM_ACK_CHK_CLR_IRQ_2_LSB (1U << 3) /* 1b */ |
| #define SPM_ACK_CHK_STA_EN_2_LSB (1U << 4) /* 1b */ |
| #define SPM_ACK_CHK_WAKEUP_EN_2_LSB (1U << 5) /* 1b */ |
| #define SPM_ACK_CHK_WDT_EN_2_LSB (1U << 6) /* 1b */ |
| #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_2_LSB (1U << 7) /* 1b */ |
| #define SPM_ACK_CHK_HW_EN_2_LSB (1U << 8) /* 1b */ |
| #define SPM_ACK_CHK_HW_MODE_2_LSB (1U << 9) /* 3b */ |
| #define SPM_ACK_CHK_FAIL_2_LSB (1U << 15) /* 1b */ |
| /* SPM_ACK_CHK_PC_2 (0x10006000+0x944) */ |
| #define SPM_ACK_CHK_HW_TRIG_PC_VAL_2_LSB (1U << 0) /* 16b */ |
| #define SPM_ACK_CHK_HW_TARG_PC_VAL_2_LSB (1U << 16) /* 16b */ |
| /* SPM_ACK_CHK_SEL_2 (0x10006000+0x948) */ |
| #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_2_LSB (1U << 0) /* 5b */ |
| #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_2_LSB (1U << 5) /* 3b */ |
| #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_2_LSB (1U << 16) /* 5b */ |
| #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_2_LSB (1U << 21) /* 3b */ |
| /* SPM_ACK_CHK_TIMER_2 (0x10006000+0x94C) */ |
| #define SPM_ACK_CHK_TIMER_VAL_2_LSB (1U << 0) /* 16b */ |
| #define SPM_ACK_CHK_TIMER_2_LSB (1U << 16) /* 16b */ |
| /* SPM_ACK_CHK_STA_2 (0x10006000+0x950) */ |
| #define SPM_ACK_CHK_STA_2_LSB (1U << 0) /* 32b */ |
| /* SPM_ACK_CHK_SWINT_2 (0x10006000+0x954) */ |
| #define SPM_ACK_CHK_SWINT_EN_2_LSB (1U << 0) /* 32b */ |
| /* SPM_ACK_CHK_CON_3 (0x10006000+0x960) */ |
| #define SPM_ACK_CHK_SW_EN_3_LSB (1U << 0) /* 1b */ |
| #define SPM_ACK_CHK_CLR_ALL_3_LSB (1U << 1) /* 1b */ |
| #define SPM_ACK_CHK_CLR_TIMER_3_LSB (1U << 2) /* 1b */ |
| #define SPM_ACK_CHK_CLR_IRQ_3_LSB (1U << 3) /* 1b */ |
| #define SPM_ACK_CHK_STA_EN_3_LSB (1U << 4) /* 1b */ |
| #define SPM_ACK_CHK_WAKEUP_EN_3_LSB (1U << 5) /* 1b */ |
| #define SPM_ACK_CHK_WDT_EN_3_LSB (1U << 6) /* 1b */ |
| #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_3_LSB (1U << 7) /* 1b */ |
| #define SPM_ACK_CHK_HW_EN_3_LSB (1U << 8) /* 1b */ |
| #define SPM_ACK_CHK_HW_MODE_3_LSB (1U << 9) /* 3b */ |
| #define SPM_ACK_CHK_FAIL_3_LSB (1U << 15) /* 1b */ |
| /* SPM_ACK_CHK_PC_3 (0x10006000+0x964) */ |
| #define SPM_ACK_CHK_HW_TRIG_PC_VAL_3_LSB (1U << 0) /* 16b */ |
| #define SPM_ACK_CHK_HW_TARG_PC_VAL_3_LSB (1U << 16) /* 16b */ |
| /* SPM_ACK_CHK_SEL_3 (0x10006000+0x968) */ |
| #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_3_LSB (1U << 0) /* 5b */ |
| #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_3_LSB (1U << 5) /* 3b */ |
| #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_3_LSB (1U << 16) /* 5b */ |
| #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_3_LSB (1U << 21) /* 3b */ |
| /* SPM_ACK_CHK_TIMER_3 (0x10006000+0x96C) */ |
| #define SPM_ACK_CHK_TIMER_VAL_3_LSB (1U << 0) /* 16b */ |
| #define SPM_ACK_CHK_TIMER_3_LSB (1U << 16) /* 16b */ |
| /* SPM_ACK_CHK_STA_3 (0x10006000+0x970) */ |
| #define SPM_ACK_CHK_STA_3_LSB (1U << 0) /* 32b */ |
| /* SPM_ACK_CHK_SWINT_3 (0x10006000+0x974) */ |
| #define SPM_ACK_CHK_SWINT_EN_3_LSB (1U << 0) /* 32b */ |
| /* SPM_COUNTER_0 (0x10006000+0x978) */ |
| #define SPM_COUNTER_VAL_0_LSB (1U << 0) /* 14b */ |
| #define SPM_COUNTER_OUT_0_LSB (1U << 14) /* 14b */ |
| #define SPM_COUNTER_EN_0_LSB (1U << 28) /* 1b */ |
| #define SPM_COUNTER_CLR_0_LSB (1U << 29) /* 1b */ |
| #define SPM_COUNTER_TIMEOUT_0_LSB (1U << 30) /* 1b */ |
| #define SPM_COUNTER_WAKEUP_EN_0_LSB (1U << 31) /* 1b */ |
| /* SPM_COUNTER_1 (0x10006000+0x97C) */ |
| #define SPM_COUNTER_VAL_1_LSB (1U << 0) /* 14b */ |
| #define SPM_COUNTER_OUT_1_LSB (1U << 14) /* 14b */ |
| #define SPM_COUNTER_EN_1_LSB (1U << 28) /* 1b */ |
| #define SPM_COUNTER_CLR_1_LSB (1U << 29) /* 1b */ |
| #define SPM_COUNTER_TIMEOUT_1_LSB (1U << 30) /* 1b */ |
| #define SPM_COUNTER_WAKEUP_EN_1_LSB (1U << 31) /* 1b */ |
| /* SPM_COUNTER_2 (0x10006000+0x980) */ |
| #define SPM_COUNTER_VAL_2_LSB (1U << 0) /* 14b */ |
| #define SPM_COUNTER_OUT_2_LSB (1U << 14) /* 14b */ |
| #define SPM_COUNTER_EN_2_LSB (1U << 28) /* 1b */ |
| #define SPM_COUNTER_CLR_2_LSB (1U << 29) /* 1b */ |
| #define SPM_COUNTER_TIMEOUT_2_LSB (1U << 30) /* 1b */ |
| #define SPM_COUNTER_WAKEUP_EN_2_LSB (1U << 31) /* 1b */ |
| /* SYS_TIMER_CON (0x10006000+0x98C) */ |
| #define SYS_TIMER_START_EN_LSB (1U << 0) /* 1b */ |
| #define SYS_TIMER_LATCH_EN_LSB (1U << 1) /* 1b */ |
| #define SYS_TIMER_ID_LSB (1U << 8) /* 8b */ |
| #define SYS_TIMER_VALID_LSB (1U << 31) /* 1b */ |
| /* RC_FSM_STA_0 (0x10006000+0xE00) */ |
| #define RC_FSM_STA_0_LSB (1U << 0) /* 32b */ |
| /* RC_CMD_STA_0 (0x10006000+0xE04) */ |
| #define RC_CMD_STA_0_LSB (1U << 0) /* 32b */ |
| /* RC_CMD_STA_1 (0x10006000+0xE08) */ |
| #define RC_CMD_STA_1_LSB (1U << 0) /* 32b */ |
| /* RC_SPI_STA_0 (0x10006000+0xE0C) */ |
| #define RC_SPI_STA_0_LSB (1U << 0) /* 32b */ |
| /* RC_PI_PO_STA_0 (0x10006000+0xE10) */ |
| #define RC_PI_PO_STA_0_LSB (1U << 0) /* 32b */ |
| /* RC_M00_REQ_STA_0 (0x10006000+0xE14) */ |
| #define RC_M00_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| /* RC_M01_REQ_STA_0 (0x10006000+0xE1C) */ |
| #define RC_M01_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| /* RC_M02_REQ_STA_0 (0x10006000+0xE20) */ |
| #define RC_M02_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| /* RC_M03_REQ_STA_0 (0x10006000+0xE24) */ |
| #define RC_M03_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| /* RC_M04_REQ_STA_0 (0x10006000+0xE28) */ |
| #define RC_M04_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| /* RC_M05_REQ_STA_0 (0x10006000+0xE2C) */ |
| #define RC_M05_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| /* RC_M06_REQ_STA_0 (0x10006000+0xE30) */ |
| #define RC_M06_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| /* RC_M07_REQ_STA_0 (0x10006000+0xE34) */ |
| #define RC_M07_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| /* RC_M08_REQ_STA_0 (0x10006000+0xE38) */ |
| #define RC_M08_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| /* RC_M09_REQ_STA_0 (0x10006000+0xE3C) */ |
| #define RC_M09_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| /* RC_M10_REQ_STA_0 (0x10006000+0xE40) */ |
| #define RC_M10_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| /* RC_M11_REQ_STA_0 (0x10006000+0xE44) */ |
| #define RC_M11_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| /* RC_M12_REQ_STA_0 (0x10006000+0xE48) */ |
| #define RC_M12_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| /* RC_DEBUG_STA_0 (0x10006000+0xE4C) */ |
| #define RC_DEBUG_STA_0_LSB (1U << 0) /* 32b */ |
| /* RC_DEBUG_TRACE_0_LSB (0x10006000+0xE50) */ |
| #define RO_PMRC_TRACE_00_LSB_LSB (1U << 0) /* 32b */ |
| /* RC_DEBUG_TRACE_0_MSB (0x10006000+0xE54) */ |
| #define RO_PMRC_TRACE_00_MSB_LSB (1U << 0) /* 32b */ |
| /* RC_DEBUG_TRACE_1_LSB (0x10006000+0xE5C) */ |
| #define RO_PMRC_TRACE_01_LSB_LSB (1U << 0) /* 32b */ |
| /* RC_DEBUG_TRACE_1_MSB (0x10006000+0xE60) */ |
| #define RO_PMRC_TRACE_01_MSB_LSB (1U << 0) /* 32b */ |
| /* RC_DEBUG_TRACE_2_LSB (0x10006000+0xE64) */ |
| #define RO_PMRC_TRACE_02_LSB_LSB (1U << 0) /* 32b */ |
| /* RC_DEBUG_TRACE_2_MSB (0x10006000+0xE6C) */ |
| #define RO_PMRC_TRACE_02_MSB_LSB (1U << 0) /* 32b */ |
| /* RC_DEBUG_TRACE_3_LSB (0x10006000+0xE70) */ |
| #define RO_PMRC_TRACE_03_LSB_LSB (1U << 0) /* 32b */ |
| /* RC_DEBUG_TRACE_3_MSB (0x10006000+0xE74) */ |
| #define RO_PMRC_TRACE_03_MSB_LSB (1U << 0) /* 32b */ |
| /* RC_DEBUG_TRACE_4_LSB (0x10006000+0xE78) */ |
| #define RO_PMRC_TRACE_04_LSB_LSB (1U << 0) /* 32b */ |
| /* RC_DEBUG_TRACE_4_MSB (0x10006000+0xE7C) */ |
| #define RO_PMRC_TRACE_04_MSB_LSB (1U << 0) /* 32b */ |
| /* RC_DEBUG_TRACE_5_LSB (0x10006000+0xE80) */ |
| #define RO_PMRC_TRACE_05_LSB_LSB (1U << 0) /* 32b */ |
| /* RC_DEBUG_TRACE_5_MSB (0x10006000+0xE84) */ |
| #define RO_PMRC_TRACE_05_MSB_LSB (1U << 0) /* 32b */ |
| /* RC_DEBUG_TRACE_6_LSB (0x10006000+0xE88) */ |
| #define RO_PMRC_TRACE_06_LSB_LSB (1U << 0) /* 32b */ |
| /* RC_DEBUG_TRACE_6_MSB (0x10006000+0xE8C) */ |
| #define RO_PMRC_TRACE_06_MSB_LSB (1U << 0) /* 32b */ |
| /* RC_DEBUG_TRACE_7_LSB (0x10006000+0xE90) */ |
| #define RO_PMRC_TRACE_07_LSB_LSB (1U << 0) /* 32b */ |
| /* RC_DEBUG_TRACE_7_MSB (0x10006000+0xE94) */ |
| #define RO_PMRC_TRACE_07_MSB_LSB (1U << 0) /* 32b */ |
| /* RC_SYS_TIMER_LATCH_0_LSB (0x10006000+0xE98) */ |
| #define RC_SYS_TIMER_LATCH_L_00_LSB (1U << 0) /* 32b */ |
| /* RC_SYS_TIMER_LATCH_0_MSB (0x10006000+0xE9C) */ |
| #define RC_SYS_TIMER_LATCH_H_00_LSB (1U << 0) /* 32b */ |
| /* RC_SYS_TIMER_LATCH_1_LSB (0x10006000+0xEA0) */ |
| #define RC_SYS_TIMER_LATCH_L_01_LSB (1U << 0) /* 32b */ |
| /* RC_SYS_TIMER_LATCH_1_MSB (0x10006000+0xEA4) */ |
| #define RC_SYS_TIMER_LATCH_H_01_LSB (1U << 0) /* 32b */ |
| /* RC_SYS_TIMER_LATCH_2_LSB (0x10006000+0xEA8) */ |
| #define RC_SYS_TIMER_LATCH_L_02_LSB (1U << 0) /* 32b */ |
| /* RC_SYS_TIMER_LATCH_2_MSB (0x10006000+0xEAC) */ |
| #define RC_SYS_TIMER_LATCH_H_02_LSB (1U << 0) /* 32b */ |
| /* RC_SYS_TIMER_LATCH_3_LSB (0x10006000+0xEB0) */ |
| #define RC_SYS_TIMER_LATCH_L_03_LSB (1U << 0) /* 32b */ |
| /* RC_SYS_TIMER_LATCH_3_MSB (0x10006000+0xEB4) */ |
| #define RC_SYS_TIMER_LATCH_H_03_LSB (1U << 0) /* 32b */ |
| /* RC_SYS_TIMER_LATCH_4_LSB (0x10006000+0xEB8) */ |
| #define RC_SYS_TIMER_LATCH_L_04_LSB (1U << 0) /* 32b */ |
| /* RC_SYS_TIMER_LATCH_4_MSB (0x10006000+0xEBC) */ |
| #define RC_SYS_TIMER_LATCH_H_04_LSB (1U << 0) /* 32b */ |
| /* RC_SYS_TIMER_LATCH_5_LSB (0x10006000+0xEC0) */ |
| #define RC_SYS_TIMER_LATCH_L_05_LSB (1U << 0) /* 32b */ |
| /* RC_SYS_TIMER_LATCH_5_MSB (0x10006000+0xEC4) */ |
| #define RC_SYS_TIMER_LATCH_H_05_LSB (1U << 0) /* 32b */ |
| /* RC_SYS_TIMER_LATCH_6_LSB (0x10006000+0xEC8) */ |
| #define RC_SYS_TIMER_LATCH_L_06_LSB (1U << 0) /* 32b */ |
| /* RC_SYS_TIMER_LATCH_6_MSB (0x10006000+0xECC) */ |
| #define RC_SYS_TIMER_LATCH_H_06_LSB (1U << 0) /* 32b */ |
| /* RC_SYS_TIMER_LATCH_7_LSB (0x10006000+0xED0) */ |
| #define RC_SYS_TIMER_LATCH_L_07_LSB (1U << 0) /* 32b */ |
| /* RC_SYS_TIMER_LATCH_7_MSB (0x10006000+0xED4) */ |
| #define RC_SYS_TIMER_LATCH_H_07_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_19 (0x10006000+0xED8) */ |
| #define PCM_WDT_LATCH_19_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_20 (0x10006000+0xEDC) */ |
| #define PCM_WDT_LATCH_20_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_21 (0x10006000+0xEE0) */ |
| #define PCM_WDT_LATCH_21_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_22 (0x10006000+0xEE4) */ |
| #define PCM_WDT_LATCH_22_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_23 (0x10006000+0xEE8) */ |
| #define PCM_WDT_LATCH_23_LSB (1U << 0) /* 32b */ |
| /* PCM_WDT_LATCH_24 (0x10006000+0xEEC) */ |
| #define PCM_WDT_LATCH_24_LSB (1U << 0) /* 32b */ |
| /* PMSR_LAST_DAT (0x10006000+0xF00) */ |
| #define PMSR_LAST_DAT_LSB (1U << 0) /* 32b */ |
| /* PMSR_LAST_CNT (0x10006000+0xF04) */ |
| #define PMSR_LAST_CMD_LSB (1U << 0) /* 30b */ |
| #define PMSR_LAST_REQ_LSB (1U << 30) /* 1b */ |
| /* PMSR_LAST_ACK (0x10006000+0xF08) */ |
| #define PMSR_LAST_ACK_LSB (1U << 0) /* 1b */ |
| /* SPM_PMSR_SEL_CON0 (0x10006000+0xF10) */ |
| #define REG_PMSR_SIG_SEL_0_LSB (1U << 0) /* 8b */ |
| #define REG_PMSR_SIG_SEL_1_LSB (1U << 8) /* 8b */ |
| #define REG_PMSR_SIG_SEL_2_LSB (1U << 16) /* 8b */ |
| #define REG_PMSR_SIG_SEL_3_LSB (1U << 24) /* 8b */ |
| /* SPM_PMSR_SEL_CON1 (0x10006000+0xF14) */ |
| #define REG_PMSR_SIG_SEL_4_LSB (1U << 0) /* 8b */ |
| #define REG_PMSR_SIG_SEL_5_LSB (1U << 8) /* 8b */ |
| #define REG_PMSR_SIG_SEL_6_LSB (1U << 16) /* 8b */ |
| #define REG_PMSR_SIG_SEL_7_LSB (1U << 24) /* 8b */ |
| /* SPM_PMSR_SEL_CON2 (0x10006000+0xF18) */ |
| #define REG_PMSR_SIG_SEL_8_LSB (1U << 0) /* 8b */ |
| #define REG_PMSR_SIG_SEL_9_LSB (1U << 8) /* 8b */ |
| #define REG_PMSR_SIG_SEL_10_LSB (1U << 16) /* 8b */ |
| #define REG_PMSR_SIG_SEL_11_LSB (1U << 24) /* 8b */ |
| /* SPM_PMSR_SEL_CON3 (0x10006000+0xF1C) */ |
| #define REG_PMSR_SIG_SEL_12_LSB (1U << 0) /* 8b */ |
| #define REG_PMSR_SIG_SEL_13_LSB (1U << 8) /* 8b */ |
| #define REG_PMSR_SIG_SEL_14_LSB (1U << 16) /* 8b */ |
| #define REG_PMSR_SIG_SEL_15_LSB (1U << 24) /* 8b */ |
| /* SPM_PMSR_SEL_CON4 (0x10006000+0xF20) */ |
| #define REG_PMSR_SIG_SEL_16_LSB (1U << 0) /* 8b */ |
| #define REG_PMSR_SIG_SEL_17_LSB (1U << 8) /* 8b */ |
| #define REG_PMSR_SIG_SEL_18_LSB (1U << 16) /* 8b */ |
| #define REG_PMSR_SIG_SEL_19_LSB (1U << 24) /* 8b */ |
| /* SPM_PMSR_SEL_CON5 (0x10006000+0xF24) */ |
| #define REG_PMSR_SIG_SEL_20_LSB (1U << 0) /* 8b */ |
| #define REG_PMSR_SIG_SEL_21_LSB (1U << 8) /* 8b */ |
| #define REG_PMSR_SIG_SEL_22_LSB (1U << 16) /* 8b */ |
| #define REG_PMSR_SIG_SEL_23_LSB (1U << 24) /* 8b */ |
| /* SPM_PMSR_SEL_CON6 (0x10006000+0xF28) */ |
| #define REG_PMSR_SIG_SEL_24_LSB (1U << 0) /* 8b */ |
| #define REG_PMSR_SIG_SEL_25_LSB (1U << 8) /* 8b */ |
| #define REG_PMSR_SIG_SEL_26_LSB (1U << 16) /* 8b */ |
| #define REG_PMSR_SIG_SEL_27_LSB (1U << 24) /* 8b */ |
| /* SPM_PMSR_SEL_CON7 (0x10006000+0xF2C) */ |
| #define REG_PMSR_SIG_SEL_28_LSB (1U << 0) /* 8b */ |
| #define REG_PMSR_SIG_SEL_29_LSB (1U << 8) /* 8b */ |
| #define REG_PMSR_SIG_SEL_30_LSB (1U << 16) /* 8b */ |
| #define REG_PMSR_SIG_SEL_31_LSB (1U << 24) /* 8b */ |
| /* SPM_PMSR_SEL_CON8 (0x10006000+0xF30) */ |
| #define REG_PMSR_SIG_SEL_32_LSB (1U << 0) /* 8b */ |
| #define REG_PMSR_SIG_SEL_33_LSB (1U << 8) /* 8b */ |
| #define REG_PMSR_SIG_SEL_34_LSB (1U << 16) /* 8b */ |
| #define REG_PMSR_SIG_SEL_35_LSB (1U << 24) /* 8b */ |
| /* SPM_PMSR_SEL_CON9 (0x10006000+0xF34) */ |
| #define REG_PMSR_SIG_SEL_36_LSB (1U << 0) /* 8b */ |
| #define REG_PMSR_SIG_SEL_37_LSB (1U << 8) /* 8b */ |
| #define REG_PMSR_SIG_SEL_38_LSB (1U << 16) /* 8b */ |
| #define REG_PMSR_SIG_SEL_39_LSB (1U << 24) /* 8b */ |
| /* SPM_PMSR_SEL_CON10 (0x10006000+0xF3C) */ |
| #define REG_PMSR_SIG_SEL_40_LSB (1U << 0) /* 8b */ |
| #define REG_PMSR_SIG_SEL_41_LSB (1U << 8) /* 8b */ |
| #define REG_PMSR_SIG_SEL_42_LSB (1U << 16) /* 8b */ |
| #define REG_PMSR_SIG_SEL_43_LSB (1U << 24) /* 8b */ |
| /* SPM_PMSR_SEL_CON11 (0x10006000+0xF40) */ |
| #define REG_PMSR_SIG_SEL_44_LSB (1U << 0) /* 8b */ |
| #define REG_PMSR_SIG_SEL_45_LSB (1U << 8) /* 8b */ |
| #define REG_PMSR_SIG_SEL_46_LSB (1U << 16) /* 8b */ |
| #define REG_PMSR_SIG_SEL_47_LSB (1U << 24) /* 8b */ |
| /* SPM_PMSR_TIEMR_STA0 (0x10006000+0xFB8) */ |
| #define PMSR_TIMER_SET0_LSB (1U << 0) /* 32b */ |
| /* SPM_PMSR_TIEMR_STA1 (0x10006000+0xFBC) */ |
| #define PMSR_TIMER_SET1_LSB (1U << 0) /* 32b */ |
| /* SPM_PMSR_TIEMR_STA2 (0x10006000+0xFC0) */ |
| #define PMSR_TIMER_SET2_LSB (1U << 0) /* 32b */ |
| /* SPM_PMSR_GENERAL_CON0 (0x10006000+0xFC4) */ |
| #define PMSR_ENABLE_SET0_LSB (1U << 0) /* 1b */ |
| #define PMSR_ENABLE_SET1_LSB (1U << 1) /* 1b */ |
| #define PMSR_ENABLE_SET2_LSB (1U << 2) /* 1b */ |
| #define PMSR_IRQ_CLR_SET0_LSB (1U << 3) /* 1b */ |
| #define PMSR_IRQ_CLR_SET1_LSB (1U << 4) /* 1b */ |
| #define PMSR_IRQ_CLR_SET2_LSB (1U << 5) /* 1b */ |
| #define PMSR_SPEED_MODE_EN_SET0_LSB (1U << 6) /* 1b */ |
| #define PMSR_SPEED_MODE_EN_SET1_LSB (1U << 7) /* 1b */ |
| #define PMSR_SPEED_MODE_EN_SET2_LSB (1U << 8) /* 1b */ |
| #define PMSR_EVENT_CLR_SET0_LSB (1U << 9) /* 1b */ |
| #define PMSR_EVENT_CLR_SET1_LSB (1U << 10) /* 1b */ |
| #define PMSR_EVENT_CLR_SET2_LSB (1U << 11) /* 1b */ |
| #define REG_PMSR_IRQ_MASK_SET0_LSB (1U << 12) /* 1b */ |
| #define REG_PMSR_IRQ_MASK_SET1_LSB (1U << 13) /* 1b */ |
| #define REG_PMSR_IRQ_MASK_SET2_LSB (1U << 14) /* 1b */ |
| #define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET0_LSB (1U << 15) /* 1b */ |
| #define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET1_LSB (1U << 16) /* 1b */ |
| #define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET2_LSB (1U << 17) /* 1b */ |
| #define PMSR_GEN_SW_RST_EN_LSB (1U << 18) /* 1b */ |
| #define PMSR_MODULE_ENABLE_LSB (1U << 19) /* 1b */ |
| #define PMSR_MODE_LSB (1U << 20) /* 2b */ |
| #define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET0_LSB (1U << 29) /* 1b */ |
| #define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET1_LSB (1U << 30) /* 1b */ |
| #define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET2_LSB (1U << 31) /* 1b */ |
| /* SPM_PMSR_GENERAL_CON1 (0x10006000+0xFC8) */ |
| #define PMSR_COUNTER_THRES_LSB (1U << 0) /* 32b */ |
| /* SPM_PMSR_GENERAL_CON2 (0x10006000+0xFCC) */ |
| #define PMSR_DEBUG_IN_0_MASK_B_LSB (1U << 0) /* 32b */ |
| /* SPM_PMSR_GENERAL_CON3 (0x10006000+0xFD0) */ |
| #define PMSR_DEBUG_IN_1_MASK_B_LSB (1U << 0) /* 32b */ |
| /* SPM_PMSR_GENERAL_CON4 (0x10006000+0xFD4) */ |
| #define PMSR_DEBUG_IN_2_MASK_B_LSB (1U << 0) /* 32b */ |
| /* SPM_PMSR_GENERAL_CON5 (0x10006000+0xFD8) */ |
| #define PMSR_DEBUG_IN_3_MASK_B_LSB (1U << 0) /* 32b */ |
| /* SPM_PMSR_SW_RESET (0x10006000+0xFDC) */ |
| #define PMSR_SW_RST_EN_SET0_LSB (1U << 0) /* 1b */ |
| #define PMSR_SW_RST_EN_SET1_LSB (1U << 1) /* 1b */ |
| #define PMSR_SW_RST_EN_SET2_LSB (1U << 2) /* 1b */ |
| /* SPM_PMSR_MON_CON0 (0x10006000+0xFE0) */ |
| #define REG_PMSR_MON_TYPE_0_LSB (1U << 0) /* 2b */ |
| #define REG_PMSR_MON_TYPE_1_LSB (1U << 2) /* 2b */ |
| #define REG_PMSR_MON_TYPE_2_LSB (1U << 4) /* 2b */ |
| #define REG_PMSR_MON_TYPE_3_LSB (1U << 6) /* 2b */ |
| #define REG_PMSR_MON_TYPE_4_LSB (1U << 8) /* 2b */ |
| #define REG_PMSR_MON_TYPE_5_LSB (1U << 10) /* 2b */ |
| #define REG_PMSR_MON_TYPE_6_LSB (1U << 12) /* 2b */ |
| #define REG_PMSR_MON_TYPE_7_LSB (1U << 14) /* 2b */ |
| #define REG_PMSR_MON_TYPE_8_LSB (1U << 16) /* 2b */ |
| #define REG_PMSR_MON_TYPE_9_LSB (1U << 18) /* 2b */ |
| #define REG_PMSR_MON_TYPE_10_LSB (1U << 20) /* 2b */ |
| #define REG_PMSR_MON_TYPE_11_LSB (1U << 22) /* 2b */ |
| #define REG_PMSR_MON_TYPE_12_LSB (1U << 24) /* 2b */ |
| #define REG_PMSR_MON_TYPE_13_LSB (1U << 26) /* 2b */ |
| #define REG_PMSR_MON_TYPE_14_LSB (1U << 28) /* 2b */ |
| #define REG_PMSR_MON_TYPE_15_LSB (1U << 30) /* 2b */ |
| /* SPM_PMSR_MON_CON1 (0x10006000+0xFE4) */ |
| #define REG_PMSR_MON_TYPE_16_LSB (1U << 0) /* 2b */ |
| #define REG_PMSR_MON_TYPE_17_LSB (1U << 2) /* 2b */ |
| #define REG_PMSR_MON_TYPE_18_LSB (1U << 4) /* 2b */ |
| #define REG_PMSR_MON_TYPE_19_LSB (1U << 6) /* 2b */ |
| #define REG_PMSR_MON_TYPE_20_LSB (1U << 8) /* 2b */ |
| #define REG_PMSR_MON_TYPE_21_LSB (1U << 10) /* 2b */ |
| #define REG_PMSR_MON_TYPE_22_LSB (1U << 12) /* 2b */ |
| #define REG_PMSR_MON_TYPE_23_LSB (1U << 14) /* 2b */ |
| #define REG_PMSR_MON_TYPE_24_LSB (1U << 16) /* 2b */ |
| #define REG_PMSR_MON_TYPE_25_LSB (1U << 18) /* 2b */ |
| #define REG_PMSR_MON_TYPE_26_LSB (1U << 20) /* 2b */ |
| #define REG_PMSR_MON_TYPE_27_LSB (1U << 22) /* 2b */ |
| #define REG_PMSR_MON_TYPE_28_LSB (1U << 24) /* 2b */ |
| #define REG_PMSR_MON_TYPE_29_LSB (1U << 26) /* 2b */ |
| #define REG_PMSR_MON_TYPE_30_LSB (1U << 28) /* 2b */ |
| #define REG_PMSR_MON_TYPE_31_LSB (1U << 30) /* 2b */ |
| /* SPM_PMSR_MON_CON2 (0x10006000+0xFE8) */ |
| #define REG_PMSR_MON_TYPE_32_LSB (1U << 0) /* 2b */ |
| #define REG_PMSR_MON_TYPE_33_LSB (1U << 2) /* 2b */ |
| #define REG_PMSR_MON_TYPE_34_LSB (1U << 4) /* 2b */ |
| #define REG_PMSR_MON_TYPE_35_LSB (1U << 6) /* 2b */ |
| #define REG_PMSR_MON_TYPE_36_LSB (1U << 8) /* 2b */ |
| #define REG_PMSR_MON_TYPE_37_LSB (1U << 10) /* 2b */ |
| #define REG_PMSR_MON_TYPE_38_LSB (1U << 12) /* 2b */ |
| #define REG_PMSR_MON_TYPE_39_LSB (1U << 14) /* 2b */ |
| #define REG_PMSR_MON_TYPE_40_LSB (1U << 16) /* 2b */ |
| #define REG_PMSR_MON_TYPE_41_LSB (1U << 18) /* 2b */ |
| #define REG_PMSR_MON_TYPE_42_LSB (1U << 20) /* 2b */ |
| #define REG_PMSR_MON_TYPE_43_LSB (1U << 22) /* 2b */ |
| #define REG_PMSR_MON_TYPE_44_LSB (1U << 24) /* 2b */ |
| #define REG_PMSR_MON_TYPE_45_LSB (1U << 26) /* 2b */ |
| #define REG_PMSR_MON_TYPE_46_LSB (1U << 28) /* 2b */ |
| #define REG_PMSR_MON_TYPE_47_LSB (1U << 30) /* 2b */ |
| /* SPM_PMSR_LEN_CON0 (0x10006000+0xFEC) */ |
| #define REG_PMSR_WINDOW_LEN_SET0_LSB (1U << 0) /* 32b */ |
| /* SPM_PMSR_LEN_CON1 (0x10006000+0xFF0) */ |
| #define REG_PMSR_WINDOW_LEN_SET1_LSB (1U << 0) /* 32b */ |
| /* SPM_PMSR_LEN_CON2 (0x10006000+0xFF4) */ |
| #define REG_PMSR_WINDOW_LEN_SET2_LSB (1U << 0) /* 32b */ |
| |
| #define SPM_PROJECT_CODE 0xb16 |
| #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) |
| #endif /* MT_SPM_REG */ |