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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Masahiro Yamada665e71b2020-03-09 17:39:48 +09002 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-arm82cb2c12017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Masahiro Yamada665e71b2020-03-09 17:39:48 +09007#include <common/bl_common.ld.h>
Antonio Nino Diaz09d40e02018-12-14 00:18:21 +00008#include <lib/xlat_tables/xlat_tables_defs.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +01009
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
Jeenu Viswambharan9f98aa12014-03-11 11:06:45 +000012ENTRY(bl1_entrypoint)
Achin Gupta4f6ad662013-10-25 09:08:21 +010013
14MEMORY {
Juan Castillod7fbf132014-09-16 10:40:35 +010015 ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE
16 RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE
Achin Gupta4f6ad662013-10-25 09:08:21 +010017}
18
19SECTIONS
20{
Sandrine Bailleux4f59d832014-05-22 15:21:35 +010021 . = BL1_RO_BASE;
Antonio Nino Diaza2aedac2017-11-15 11:45:35 +000022 ASSERT(. == ALIGN(PAGE_SIZE),
Sandrine Bailleux4f59d832014-05-22 15:21:35 +010023 "BL1_RO_BASE address is not aligned on a page boundary.")
24
Sandrine Bailleux5d1c1042016-07-08 14:37:40 +010025#if SEPARATE_CODE_AND_RODATA
26 .text . : {
27 __TEXT_START__ = .;
28 *bl1_entrypoint.o(.text*)
Samuel Hollandebd6efa2019-10-20 16:11:25 -050029 *(SORT_BY_ALIGNMENT(.text*))
Sandrine Bailleux5d1c1042016-07-08 14:37:40 +010030 *(.vectors)
Roberto Vargas5629b2b2018-04-11 11:53:31 +010031 . = ALIGN(PAGE_SIZE);
Sandrine Bailleux5d1c1042016-07-08 14:37:40 +010032 __TEXT_END__ = .;
33 } >ROM
34
Roberto Vargasad925092018-05-10 11:01:16 +010035 /* .ARM.extab and .ARM.exidx are only added because Clang need them */
36 .ARM.extab . : {
37 *(.ARM.extab* .gnu.linkonce.armextab.*)
38 } >ROM
39
40 .ARM.exidx . : {
41 *(.ARM.exidx* .gnu.linkonce.armexidx.*)
42 } >ROM
43
Sandrine Bailleux5d1c1042016-07-08 14:37:40 +010044 .rodata . : {
45 __RODATA_START__ = .;
Samuel Hollandebd6efa2019-10-20 16:11:25 -050046 *(SORT_BY_ALIGNMENT(.rodata*))
Sandrine Bailleux5d1c1042016-07-08 14:37:40 +010047
Masahiro Yamada9fb288a2020-03-26 10:51:39 +090048 PARSER_LIB_DESCS
49 CPU_OPS
Sandrine Bailleux5d1c1042016-07-08 14:37:40 +010050
51 /*
52 * No need to pad out the .rodata section to a page boundary. Next is
53 * the .data section, which can mapped in ROM with the same memory
54 * attributes as the .rodata section.
Arve Hjønnevåg41286592020-02-07 14:12:35 -080055 *
56 * Pad out to 16 bytes though as .data section needs to be 16 byte
57 * aligned and lld does not align the LMA to the aligment specified
58 * on the .data section.
Sandrine Bailleux5d1c1042016-07-08 14:37:40 +010059 */
60 __RODATA_END__ = .;
Arve Hjønnevåg41286592020-02-07 14:12:35 -080061 . = ALIGN(16);
Sandrine Bailleux5d1c1042016-07-08 14:37:40 +010062 } >ROM
63#else
Sandrine Bailleux4f59d832014-05-22 15:21:35 +010064 ro . : {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000065 __RO_START__ = .;
Andrew Thoelkedccc5372014-03-18 07:13:52 +000066 *bl1_entrypoint.o(.text*)
Samuel Hollandebd6efa2019-10-20 16:11:25 -050067 *(SORT_BY_ALIGNMENT(.text*))
68 *(SORT_BY_ALIGNMENT(.rodata*))
Soby Mathew9b476842014-08-14 11:33:56 +010069
Masahiro Yamada9fb288a2020-03-26 10:51:39 +090070 PARSER_LIB_DESCS
71 CPU_OPS
Soby Mathew9b476842014-08-14 11:33:56 +010072
Achin Guptab739f222014-01-18 16:50:09 +000073 *(.vectors)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000074 __RO_END__ = .;
Arve Hjønnevåg41286592020-02-07 14:12:35 -080075
76 /*
77 * Pad out to 16 bytes as .data section needs to be 16 byte aligned and
78 * lld does not align the LMA to the aligment specified on the .data
79 * section.
80 */
81 . = ALIGN(16);
Achin Gupta4f6ad662013-10-25 09:08:21 +010082 } >ROM
Sandrine Bailleux5d1c1042016-07-08 14:37:40 +010083#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +010084
Soby Mathew9b476842014-08-14 11:33:56 +010085 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
86 "cpu_ops not defined for this platform.")
87
Douglas Raillard51faada2017-02-24 18:14:15 +000088 . = BL1_RW_BASE;
Antonio Nino Diaza2aedac2017-11-15 11:45:35 +000089 ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE),
Douglas Raillard51faada2017-02-24 18:14:15 +000090 "BL1_RW_BASE address is not aligned on a page boundary.")
91
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000092 /*
93 * The .data section gets copied from ROM to RAM at runtime.
Douglas Raillard51faada2017-02-24 18:14:15 +000094 * Its LMA should be 16-byte aligned to allow efficient copying of 16-bytes
95 * aligned regions in it.
Sandrine Bailleux4f59d832014-05-22 15:21:35 +010096 * Its VMA must be page-aligned as it marks the first read/write page.
Douglas Raillard51faada2017-02-24 18:14:15 +000097 *
98 * It must be placed at a lower address than the stacks if the stack
99 * protector is enabled. Alternatively, the .data.stack_protector_canary
100 * section can be placed independently of the main .data section.
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000101 */
Sandrine Bailleux4f59d832014-05-22 15:21:35 +0100102 .data . : ALIGN(16) {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100103 __DATA_RAM_START__ = .;
Samuel Hollandebd6efa2019-10-20 16:11:25 -0500104 *(SORT_BY_ALIGNMENT(.data*))
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000105 __DATA_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100106 } >RAM AT>ROM
107
Sandrine Bailleux4f59d832014-05-22 15:21:35 +0100108 stacks . (NOLOAD) : {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000109 __STACKS_START__ = .;
110 *(tzfw_normal_stacks)
111 __STACKS_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100112 } >RAM
113
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000114 /*
115 * The .bss section gets initialised to 0 at runtime.
Douglas Raillard308d3592016-12-02 13:51:54 +0000116 * Its base address should be 16-byte aligned for better performance of the
117 * zero-initialization code.
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000118 */
119 .bss : ALIGN(16) {
120 __BSS_START__ = .;
Samuel Hollandebd6efa2019-10-20 16:11:25 -0500121 *(SORT_BY_ALIGNMENT(.bss*))
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000122 *(COMMON)
123 __BSS_END__ = .;
124 } >RAM
Achin Gupta4f6ad662013-10-25 09:08:21 +0100125
Masahiro Yamada665e71b2020-03-09 17:39:48 +0900126 XLAT_TABLE_SECTION >RAM
Jeenu Viswambharan74cbb832014-02-17 17:26:51 +0000127
Soby Mathewab8707e2015-01-08 18:02:44 +0000128#if USE_COHERENT_MEM
Jeenu Viswambharan74cbb832014-02-17 17:26:51 +0000129 /*
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000130 * The base address of the coherent memory section must be page-aligned (4K)
131 * to guarantee that the coherent data are stored on their own pages and
132 * are not mixed with normal data. This is required to set up the correct
133 * memory attributes for the coherent data page tables.
134 */
Antonio Nino Diaza2aedac2017-11-15 11:45:35 +0000135 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000136 __COHERENT_RAM_START__ = .;
137 *(tzfw_coherent_mem)
138 __COHERENT_RAM_END_UNALIGNED__ = .;
139 /*
140 * Memory page(s) mapped to this section will be marked
141 * as device memory. No other unexpected data must creep in.
142 * Ensure the rest of the current memory page is unused.
143 */
Roberto Vargas5629b2b2018-04-11 11:53:31 +0100144 . = ALIGN(PAGE_SIZE);
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000145 __COHERENT_RAM_END__ = .;
146 } >RAM
Soby Mathewab8707e2015-01-08 18:02:44 +0000147#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100148
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000149 __BL1_RAM_START__ = ADDR(.data);
150 __BL1_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100151
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000152 __DATA_ROM_START__ = LOADADDR(.data);
153 __DATA_SIZE__ = SIZEOF(.data);
Sandrine Bailleuxc02fcc42016-06-15 13:53:50 +0100154
Sandrine Bailleuxa37255a2014-05-22 15:28:26 +0100155 /*
156 * The .data section is the last PROGBITS section so its end marks the end
Sandrine Bailleuxc02fcc42016-06-15 13:53:50 +0100157 * of BL1's actual content in Trusted ROM.
Sandrine Bailleuxa37255a2014-05-22 15:28:26 +0100158 */
Sandrine Bailleuxc02fcc42016-06-15 13:53:50 +0100159 __BL1_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__;
160 ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT,
161 "BL1's ROM content has exceeded its limit.")
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000162
163 __BSS_SIZE__ = SIZEOF(.bss);
164
Soby Mathewab8707e2015-01-08 18:02:44 +0000165#if USE_COHERENT_MEM
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000166 __COHERENT_RAM_UNALIGNED_SIZE__ =
167 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
Soby Mathewab8707e2015-01-08 18:02:44 +0000168#endif
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000169
Sandrine Bailleuxa37255a2014-05-22 15:28:26 +0100170 ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.")
Achin Gupta4f6ad662013-10-25 09:08:21 +0100171}