Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 1 | /* |
Heyi Guo | 69ae442 | 2020-05-19 14:01:49 +0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 3 | * |
dp-arm | 82cb2c1 | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | 09d40e0 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 7 | #include <assert.h> |
| 8 | |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 9 | #include <arch.h> |
| 10 | #include <arch_helpers.h> |
Antonio Nino Diaz | 09d40e0 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 11 | #include <common/debug.h> |
| 12 | #include <common/interrupt_props.h> |
| 13 | #include <drivers/arm/gic_common.h> |
| 14 | |
Soby Mathew | e9ec3ce | 2016-02-01 17:59:22 +0000 | [diff] [blame] | 15 | #include "../common/gic_common_private.h" |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 16 | #include "gicv3_private.h" |
| 17 | |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 18 | /****************************************************************************** |
| 19 | * This function marks the core as awake in the re-distributor and |
| 20 | * ensures that the interface is active. |
| 21 | *****************************************************************************/ |
| 22 | void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base) |
| 23 | { |
| 24 | /* |
| 25 | * The WAKER_PS_BIT should be changed to 0 |
| 26 | * only when WAKER_CA_BIT is 1. |
| 27 | */ |
Antonio Nino Diaz | 3fea9c8 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 28 | assert((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U); |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 29 | |
| 30 | /* Mark the connected core as awake */ |
| 31 | gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT); |
| 32 | |
| 33 | /* Wait till the WAKER_CA_BIT changes to 0 */ |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 34 | while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U) { |
| 35 | } |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 36 | } |
| 37 | |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 38 | /****************************************************************************** |
| 39 | * This function marks the core as asleep in the re-distributor and ensures |
| 40 | * that the interface is quiescent. |
| 41 | *****************************************************************************/ |
| 42 | void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base) |
| 43 | { |
| 44 | /* Mark the connected core as asleep */ |
| 45 | gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT); |
| 46 | |
| 47 | /* Wait till the WAKER_CA_BIT changes to 1 */ |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 48 | while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) == 0U) { |
| 49 | } |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 50 | } |
| 51 | |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 52 | /******************************************************************************* |
| 53 | * This function probes the Redistributor frames when the driver is initialised |
| 54 | * and saves their base addresses. These base addresses are used later to |
| 55 | * initialise each Redistributor interface. |
| 56 | ******************************************************************************/ |
| 57 | void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, |
| 58 | unsigned int rdistif_num, |
| 59 | uintptr_t gicr_base, |
| 60 | mpidr_hash_fn mpidr_to_core_pos) |
| 61 | { |
Soby Mathew | 4c0d039 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 62 | u_register_t mpidr; |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 63 | unsigned int proc_num; |
Antonio Nino Diaz | 3fea9c8 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 64 | uint64_t typer_val; |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 65 | uintptr_t rdistif_base = gicr_base; |
| 66 | |
Antonio Nino Diaz | 3fea9c8 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 67 | assert(rdistif_base_addrs != NULL); |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 68 | |
| 69 | /* |
| 70 | * Iterate over the Redistributor frames. Store the base address of each |
| 71 | * frame in the platform provided array. Use the "Processor Number" |
| 72 | * field to index into the array if the platform has not provided a hash |
| 73 | * function to convert an MPIDR (obtained from the "Affinity Value" |
| 74 | * field into a linear index. |
| 75 | */ |
| 76 | do { |
| 77 | typer_val = gicr_read_typer(rdistif_base); |
Antonio Nino Diaz | 3fea9c8 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 78 | if (mpidr_to_core_pos != NULL) { |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 79 | mpidr = mpidr_from_gicr_typer(typer_val); |
| 80 | proc_num = mpidr_to_core_pos(mpidr); |
| 81 | } else { |
| 82 | proc_num = (typer_val >> TYPER_PROC_NUM_SHIFT) & |
| 83 | TYPER_PROC_NUM_MASK; |
| 84 | } |
Soby Mathew | 5dc2c3f | 2019-01-17 14:57:54 +0000 | [diff] [blame] | 85 | |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 86 | if (proc_num < rdistif_num) { |
Soby Mathew | 5dc2c3f | 2019-01-17 14:57:54 +0000 | [diff] [blame] | 87 | rdistif_base_addrs[proc_num] = rdistif_base; |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 88 | } |
Soby Mathew | 5dc2c3f | 2019-01-17 14:57:54 +0000 | [diff] [blame] | 89 | |
Antonio Nino Diaz | 3fea9c8 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 90 | rdistif_base += (1U << GICR_PCPUBASE_SHIFT); |
| 91 | } while ((typer_val & TYPER_LAST_BIT) == 0U); |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 92 | } |
| 93 | |
| 94 | /******************************************************************************* |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 95 | * Helper function to configure the default attributes of (E)SPIs. |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 96 | ******************************************************************************/ |
Daniel Boulby | 87d3aac | 2018-05-01 15:15:34 +0100 | [diff] [blame] | 97 | void gicv3_spis_config_defaults(uintptr_t gicd_base) |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 98 | { |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 99 | unsigned int i, num_ints; |
| 100 | #if GIC_EXT_INTID |
| 101 | unsigned int num_eints; |
| 102 | #endif |
| 103 | unsigned int typer_reg = gicd_read_typer(gicd_base); |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 104 | |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 105 | /* Maximum SPI INTID is 32 * (GICD_TYPER.ITLinesNumber + 1) - 1 */ |
| 106 | num_ints = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5; |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 107 | |
Heyi Guo | 4e42c22 | 2020-05-19 15:41:14 +0800 | [diff] [blame] | 108 | /* |
| 109 | * The GICv3 architecture allows GICD_TYPER.ITLinesNumber to be 31, so |
| 110 | * the maximum possible value for num_ints is 1024. Limit the value to |
| 111 | * MAX_SPI_ID + 1 to avoid getting wrong address in GICD_OFFSET() macro. |
| 112 | */ |
| 113 | if (num_ints > MAX_SPI_ID + 1U) { |
| 114 | num_ints = MAX_SPI_ID + 1U; |
| 115 | } |
Heyi Guo | 705032d | 2021-01-21 10:34:00 +0800 | [diff] [blame] | 116 | INFO("Maximum SPI INTID supported: %u\n", num_ints - 1); |
Heyi Guo | 4e42c22 | 2020-05-19 15:41:14 +0800 | [diff] [blame] | 117 | |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 118 | /* Treat all (E)SPIs as G1NS by default. We do 32 at a time. */ |
| 119 | for (i = MIN_SPI_ID; i < num_ints; i += (1U << IGROUPR_SHIFT)) { |
| 120 | gicd_write_igroupr(gicd_base, i, ~0U); |
| 121 | } |
| 122 | |
| 123 | #if GIC_EXT_INTID |
| 124 | /* Check if extended SPI range is implemented */ |
| 125 | if ((typer_reg & TYPER_ESPI) != 0U) { |
| 126 | /* |
| 127 | * Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095 |
| 128 | */ |
| 129 | num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) & |
Heyi Guo | 69ae442 | 2020-05-19 14:01:49 +0800 | [diff] [blame] | 130 | TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID; |
Heyi Guo | 705032d | 2021-01-21 10:34:00 +0800 | [diff] [blame] | 131 | INFO("Maximum ESPI INTID supported: %u\n", num_eints - 1); |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 132 | |
| 133 | for (i = MIN_ESPI_ID; i < num_eints; |
| 134 | i += (1U << IGROUPR_SHIFT)) { |
| 135 | gicd_write_igroupr(gicd_base, i, ~0U); |
| 136 | } |
| 137 | } else { |
| 138 | num_eints = 0U; |
Heyi Guo | 705032d | 2021-01-21 10:34:00 +0800 | [diff] [blame] | 139 | INFO("ESPI range is not implemented.\n"); |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 140 | } |
| 141 | #endif |
| 142 | |
| 143 | /* Setup the default (E)SPI priorities doing four at a time */ |
| 144 | for (i = MIN_SPI_ID; i < num_ints; i += (1U << IPRIORITYR_SHIFT)) { |
| 145 | gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL); |
| 146 | } |
| 147 | |
| 148 | #if GIC_EXT_INTID |
| 149 | for (i = MIN_ESPI_ID; i < num_eints; |
| 150 | i += (1U << IPRIORITYR_SHIFT)) { |
| 151 | gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL); |
| 152 | } |
| 153 | #endif |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 154 | /* |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 155 | * Treat all (E)SPIs as level triggered by default, write 16 at a time |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 156 | */ |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 157 | for (i = MIN_SPI_ID; i < num_ints; i += (1U << ICFGR_SHIFT)) { |
| 158 | gicd_write_icfgr(gicd_base, i, 0U); |
| 159 | } |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 160 | |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 161 | #if GIC_EXT_INTID |
| 162 | for (i = MIN_ESPI_ID; i < num_eints; i += (1U << ICFGR_SHIFT)) { |
| 163 | gicd_write_icfgr(gicd_base, i, 0U); |
| 164 | } |
| 165 | #endif |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 166 | } |
| 167 | |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 168 | /******************************************************************************* |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 169 | * Helper function to configure properties of secure (E)SPIs |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 170 | ******************************************************************************/ |
Daniel Boulby | 87d3aac | 2018-05-01 15:15:34 +0100 | [diff] [blame] | 171 | unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base, |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 172 | const interrupt_prop_t *interrupt_props, |
| 173 | unsigned int interrupt_props_num) |
| 174 | { |
| 175 | unsigned int i; |
| 176 | const interrupt_prop_t *current_prop; |
| 177 | unsigned long long gic_affinity_val; |
Antonio Nino Diaz | 3fea9c8 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 178 | unsigned int ctlr_enable = 0U; |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 179 | |
| 180 | /* Make sure there's a valid property array */ |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 181 | if (interrupt_props_num > 0U) { |
Antonio Nino Diaz | 3fea9c8 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 182 | assert(interrupt_props != NULL); |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 183 | } |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 184 | |
Antonio Nino Diaz | 3fea9c8 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 185 | for (i = 0U; i < interrupt_props_num; i++) { |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 186 | current_prop = &interrupt_props[i]; |
| 187 | |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 188 | unsigned int intr_num = current_prop->intr_num; |
| 189 | |
| 190 | /* Skip SGI, (E)PPI and LPI interrupts */ |
| 191 | if (!IS_SPI(intr_num)) { |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 192 | continue; |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 193 | } |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 194 | |
| 195 | /* Configure this interrupt as a secure interrupt */ |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 196 | gicd_clr_igroupr(gicd_base, intr_num); |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 197 | |
| 198 | /* Configure this interrupt as G0 or a G1S interrupt */ |
| 199 | assert((current_prop->intr_grp == INTR_GROUP0) || |
| 200 | (current_prop->intr_grp == INTR_GROUP1S)); |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 201 | |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 202 | if (current_prop->intr_grp == INTR_GROUP1S) { |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 203 | gicd_set_igrpmodr(gicd_base, intr_num); |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 204 | ctlr_enable |= CTLR_ENABLE_G1S_BIT; |
| 205 | } else { |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 206 | gicd_clr_igrpmodr(gicd_base, intr_num); |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 207 | ctlr_enable |= CTLR_ENABLE_G0_BIT; |
| 208 | } |
| 209 | |
| 210 | /* Set interrupt configuration */ |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 211 | gicd_set_icfgr(gicd_base, intr_num, current_prop->intr_cfg); |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 212 | |
| 213 | /* Set the priority of this interrupt */ |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 214 | gicd_set_ipriorityr(gicd_base, intr_num, |
| 215 | current_prop->intr_pri); |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 216 | |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 217 | /* Target (E)SPIs to the primary CPU */ |
Antonio Nino Diaz | 3fea9c8 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 218 | gic_affinity_val = |
| 219 | gicd_irouter_val_from_mpidr(read_mpidr(), 0U); |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 220 | gicd_write_irouter(gicd_base, intr_num, |
| 221 | gic_affinity_val); |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 222 | |
| 223 | /* Enable this interrupt */ |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 224 | gicd_set_isenabler(gicd_base, intr_num); |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 225 | } |
| 226 | |
| 227 | return ctlr_enable; |
| 228 | } |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 229 | |
| 230 | /******************************************************************************* |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 231 | * Helper function to configure the default attributes of (E)SPIs |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 232 | ******************************************************************************/ |
Daniel Boulby | 87d3aac | 2018-05-01 15:15:34 +0100 | [diff] [blame] | 233 | void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base) |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 234 | { |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 235 | unsigned int i, ppi_regs_num, regs_num; |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 236 | |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 237 | #if GIC_EXT_INTID |
| 238 | /* Calculate number of PPI registers */ |
| 239 | ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> |
| 240 | TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; |
| 241 | /* All other values except PPInum [0-2] are reserved */ |
| 242 | if (ppi_regs_num > 3U) { |
| 243 | ppi_regs_num = 1U; |
| 244 | } |
| 245 | #else |
| 246 | ppi_regs_num = 1U; |
| 247 | #endif |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 248 | /* |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 249 | * Disable all SGIs (imp. def.)/(E)PPIs before configuring them. |
| 250 | * This is a more scalable approach as it avoids clearing |
| 251 | * the enable bits in the GICD_CTLR. |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 252 | */ |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 253 | for (i = 0U; i < ppi_regs_num; ++i) { |
| 254 | gicr_write_icenabler(gicr_base, i, ~0U); |
| 255 | } |
| 256 | |
| 257 | /* Wait for pending writes to GICR_ICENABLER */ |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 258 | gicr_wait_for_pending_write(gicr_base); |
| 259 | |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 260 | /* 32 interrupt IDs per GICR_IGROUPR register */ |
| 261 | for (i = 0U; i < ppi_regs_num; ++i) { |
| 262 | /* Treat all SGIs/(E)PPIs as G1NS by default */ |
| 263 | gicr_write_igroupr(gicr_base, i, ~0U); |
| 264 | } |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 265 | |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 266 | /* 4 interrupt IDs per GICR_IPRIORITYR register */ |
| 267 | regs_num = ppi_regs_num << 3; |
| 268 | for (i = 0U; i < regs_num; ++i) { |
| 269 | /* Setup the default (E)PPI/SGI priorities doing 4 at a time */ |
| 270 | gicr_write_ipriorityr(gicr_base, i, GICD_IPRIORITYR_DEF_VAL); |
| 271 | } |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 272 | |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 273 | /* 16 interrupt IDs per GICR_ICFGR register */ |
| 274 | regs_num = ppi_regs_num << 1; |
| 275 | for (i = (MIN_PPI_ID >> ICFGR_SHIFT); i < regs_num; ++i) { |
| 276 | /* Configure all (E)PPIs as level triggered by default */ |
| 277 | gicr_write_icfgr(gicr_base, i, 0U); |
| 278 | } |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 279 | } |
| 280 | |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 281 | /******************************************************************************* |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 282 | * Helper function to configure properties of secure G0 and G1S (E)PPIs and SGIs |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 283 | ******************************************************************************/ |
Daniel Boulby | 87d3aac | 2018-05-01 15:15:34 +0100 | [diff] [blame] | 284 | unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base, |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 285 | const interrupt_prop_t *interrupt_props, |
| 286 | unsigned int interrupt_props_num) |
| 287 | { |
| 288 | unsigned int i; |
| 289 | const interrupt_prop_t *current_prop; |
Antonio Nino Diaz | 3fea9c8 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 290 | unsigned int ctlr_enable = 0U; |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 291 | |
| 292 | /* Make sure there's a valid property array */ |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 293 | if (interrupt_props_num > 0U) { |
Antonio Nino Diaz | 3fea9c8 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 294 | assert(interrupt_props != NULL); |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 295 | } |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 296 | |
Antonio Nino Diaz | 3fea9c8 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 297 | for (i = 0U; i < interrupt_props_num; i++) { |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 298 | current_prop = &interrupt_props[i]; |
| 299 | |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 300 | unsigned int intr_num = current_prop->intr_num; |
| 301 | |
| 302 | /* Skip (E)SPI interrupt */ |
| 303 | if (!IS_SGI_PPI(intr_num)) { |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 304 | continue; |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 305 | } |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 306 | |
| 307 | /* Configure this interrupt as a secure interrupt */ |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 308 | gicr_clr_igroupr(gicr_base, intr_num); |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 309 | |
| 310 | /* Configure this interrupt as G0 or a G1S interrupt */ |
| 311 | assert((current_prop->intr_grp == INTR_GROUP0) || |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 312 | (current_prop->intr_grp == INTR_GROUP1S)); |
| 313 | |
Jeenu Viswambharan | 385f1db | 2017-11-07 08:38:23 +0000 | [diff] [blame] | 314 | if (current_prop->intr_grp == INTR_GROUP1S) { |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 315 | gicr_set_igrpmodr(gicr_base, intr_num); |
Jeenu Viswambharan | 385f1db | 2017-11-07 08:38:23 +0000 | [diff] [blame] | 316 | ctlr_enable |= CTLR_ENABLE_G1S_BIT; |
| 317 | } else { |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 318 | gicr_clr_igrpmodr(gicr_base, intr_num); |
Jeenu Viswambharan | 385f1db | 2017-11-07 08:38:23 +0000 | [diff] [blame] | 319 | ctlr_enable |= CTLR_ENABLE_G0_BIT; |
| 320 | } |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 321 | |
| 322 | /* Set the priority of this interrupt */ |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 323 | gicr_set_ipriorityr(gicr_base, intr_num, |
| 324 | current_prop->intr_pri); |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 325 | |
| 326 | /* |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 327 | * Set interrupt configuration for (E)PPIs. |
| 328 | * Configurations for SGIs 0-15 are ignored. |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 329 | */ |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 330 | if (intr_num >= MIN_PPI_ID) { |
| 331 | gicr_set_icfgr(gicr_base, intr_num, |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 332 | current_prop->intr_cfg); |
| 333 | } |
| 334 | |
| 335 | /* Enable this interrupt */ |
Alexei Fedorov | 8f3ad76 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 336 | gicr_set_isenabler(gicr_base, intr_num); |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 337 | } |
Jeenu Viswambharan | 385f1db | 2017-11-07 08:38:23 +0000 | [diff] [blame] | 338 | |
| 339 | return ctlr_enable; |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 340 | } |
Andre Przywara | 79d89e3 | 2020-09-07 14:53:58 +0100 | [diff] [blame] | 341 | |
| 342 | /** |
| 343 | * gicv3_rdistif_get_number_frames() - determine size of GICv3 GICR region |
| 344 | * @gicr_frame: base address of the GICR region to check |
| 345 | * |
| 346 | * This iterates over the GICR_TYPER registers of multiple GICR frames in |
| 347 | * a GICR region, to find the instance which has the LAST bit set. For most |
| 348 | * systems this corresponds to the number of cores handled by a redistributor, |
| 349 | * but there could be disabled cores among them. |
| 350 | * It assumes that each GICR region is fully accessible (till the LAST bit |
| 351 | * marks the end of the region). |
| 352 | * If a platform has multiple GICR regions, this function would need to be |
| 353 | * called multiple times, providing the respective GICR base address each time. |
| 354 | * |
| 355 | * Return: number of valid GICR frames (at least 1, up to PLATFORM_CORE_COUNT) |
| 356 | ******************************************************************************/ |
| 357 | unsigned int gicv3_rdistif_get_number_frames(const uintptr_t gicr_frame) |
| 358 | { |
| 359 | uintptr_t rdistif_base = gicr_frame; |
| 360 | unsigned int count; |
| 361 | |
| 362 | for (count = 1; count < PLATFORM_CORE_COUNT; count++) { |
| 363 | if ((gicr_read_typer(rdistif_base) & TYPER_LAST_BIT) != 0U) { |
| 364 | break; |
| 365 | } |
| 366 | rdistif_base += (1U << GICR_PCPUBASE_SHIFT); |
| 367 | } |
| 368 | |
| 369 | return count; |
| 370 | } |