Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 883d1b5 | 2018-02-23 15:07:54 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 3 | * |
dp-arm | 82cb2c1 | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | 09d40e0 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 7 | #include <lib/xlat_tables/xlat_tables_defs.h> |
Dan Handley | 5f0cdb0 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 8 | #include <platform_def.h> |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 9 | |
| 10 | OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) |
| 11 | OUTPUT_ARCH(PLATFORM_LINKER_ARCH) |
Jeenu Viswambharan | 9f98aa1 | 2014-03-11 11:06:45 +0000 | [diff] [blame] | 12 | ENTRY(tsp_entrypoint) |
| 13 | |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 14 | |
| 15 | MEMORY { |
Sandrine Bailleux | 2467f70 | 2014-05-20 17:22:24 +0100 | [diff] [blame] | 16 | RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 17 | } |
| 18 | |
| 19 | |
| 20 | SECTIONS |
| 21 | { |
| 22 | . = BL32_BASE; |
Antonio Nino Diaz | a2aedac | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 23 | ASSERT(. == ALIGN(PAGE_SIZE), |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 24 | "BL32_BASE address is not aligned on a page boundary.") |
| 25 | |
Sandrine Bailleux | 5d1c104 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 26 | #if SEPARATE_CODE_AND_RODATA |
| 27 | .text . : { |
| 28 | __TEXT_START__ = .; |
| 29 | *tsp_entrypoint.o(.text*) |
| 30 | *(.text*) |
| 31 | *(.vectors) |
Roberto Vargas | 5629b2b | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 32 | . = ALIGN(PAGE_SIZE); |
Sandrine Bailleux | 5d1c104 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 33 | __TEXT_END__ = .; |
| 34 | } >RAM |
| 35 | |
| 36 | .rodata . : { |
| 37 | __RODATA_START__ = .; |
| 38 | *(.rodata*) |
Roberto Vargas | 5629b2b | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 39 | . = ALIGN(PAGE_SIZE); |
Sandrine Bailleux | 5d1c104 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 40 | __RODATA_END__ = .; |
| 41 | } >RAM |
| 42 | #else |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 43 | ro . : { |
| 44 | __RO_START__ = .; |
Andrew Thoelke | dccc537 | 2014-03-18 07:13:52 +0000 | [diff] [blame] | 45 | *tsp_entrypoint.o(.text*) |
| 46 | *(.text*) |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 47 | *(.rodata*) |
| 48 | *(.vectors) |
| 49 | __RO_END_UNALIGNED__ = .; |
| 50 | /* |
| 51 | * Memory page(s) mapped to this section will be marked as |
| 52 | * read-only, executable. No RW data from the next section must |
| 53 | * creep in. Ensure the rest of the current memory page is unused. |
| 54 | */ |
Roberto Vargas | 5629b2b | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 55 | . = ALIGN(PAGE_SIZE); |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 56 | __RO_END__ = .; |
| 57 | } >RAM |
Sandrine Bailleux | 5d1c104 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 58 | #endif |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 59 | |
Achin Gupta | 54dc71e | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 60 | /* |
| 61 | * Define a linker symbol to mark start of the RW memory area for this |
| 62 | * image. |
| 63 | */ |
| 64 | __RW_START__ = . ; |
| 65 | |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 66 | .data . : { |
| 67 | __DATA_START__ = .; |
Andrew Thoelke | dccc537 | 2014-03-18 07:13:52 +0000 | [diff] [blame] | 68 | *(.data*) |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 69 | __DATA_END__ = .; |
| 70 | } >RAM |
| 71 | |
Dan Handley | 5a06bb7 | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 72 | #ifdef TSP_PROGBITS_LIMIT |
| 73 | ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.") |
Sandrine Bailleux | a1b6db6 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 74 | #endif |
| 75 | |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 76 | stacks (NOLOAD) : { |
| 77 | __STACKS_START__ = .; |
| 78 | *(tzfw_normal_stacks) |
| 79 | __STACKS_END__ = .; |
| 80 | } >RAM |
| 81 | |
| 82 | /* |
| 83 | * The .bss section gets initialised to 0 at runtime. |
Douglas Raillard | 308d359 | 2016-12-02 13:51:54 +0000 | [diff] [blame] | 84 | * Its base address should be 16-byte aligned for better performance of the |
| 85 | * zero-initialization code. |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 86 | */ |
| 87 | .bss : ALIGN(16) { |
| 88 | __BSS_START__ = .; |
Andrew Thoelke | dccc537 | 2014-03-18 07:13:52 +0000 | [diff] [blame] | 89 | *(SORT_BY_ALIGNMENT(.bss*)) |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 90 | *(COMMON) |
| 91 | __BSS_END__ = .; |
| 92 | } >RAM |
| 93 | |
| 94 | /* |
| 95 | * The xlat_table section is for full, aligned page tables (4K). |
| 96 | * Removing them from .bss avoids forcing 4K alignment on |
Antonio Nino Diaz | 883d1b5 | 2018-02-23 15:07:54 +0000 | [diff] [blame] | 97 | * the .bss section. The tables are initialized to zero by the translation |
| 98 | * tables library. |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 99 | */ |
| 100 | xlat_table (NOLOAD) : { |
| 101 | *(xlat_table) |
| 102 | } >RAM |
| 103 | |
Soby Mathew | ab8707e | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 104 | #if USE_COHERENT_MEM |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 105 | /* |
| 106 | * The base address of the coherent memory section must be page-aligned (4K) |
| 107 | * to guarantee that the coherent data are stored on their own pages and |
| 108 | * are not mixed with normal data. This is required to set up the correct |
| 109 | * memory attributes for the coherent data page tables. |
| 110 | */ |
Antonio Nino Diaz | a2aedac | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 111 | coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 112 | __COHERENT_RAM_START__ = .; |
| 113 | *(tzfw_coherent_mem) |
| 114 | __COHERENT_RAM_END_UNALIGNED__ = .; |
| 115 | /* |
| 116 | * Memory page(s) mapped to this section will be marked |
| 117 | * as device memory. No other unexpected data must creep in. |
| 118 | * Ensure the rest of the current memory page is unused. |
| 119 | */ |
Roberto Vargas | 5629b2b | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 120 | . = ALIGN(PAGE_SIZE); |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 121 | __COHERENT_RAM_END__ = .; |
| 122 | } >RAM |
Soby Mathew | ab8707e | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 123 | #endif |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 124 | |
Achin Gupta | 54dc71e | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 125 | /* |
| 126 | * Define a linker symbol to mark the end of the RW memory area for this |
| 127 | * image. |
| 128 | */ |
| 129 | __RW_END__ = .; |
Sandrine Bailleux | 53514b2 | 2014-05-20 17:28:25 +0100 | [diff] [blame] | 130 | __BL32_END__ = .; |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 131 | |
| 132 | __BSS_SIZE__ = SIZEOF(.bss); |
Soby Mathew | ab8707e | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 133 | #if USE_COHERENT_MEM |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 134 | __COHERENT_RAM_UNALIGNED_SIZE__ = |
| 135 | __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; |
Soby Mathew | ab8707e | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 136 | #endif |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 137 | |
Juan Castillo | d178637 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 138 | ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.") |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 139 | } |