blob: ed55379504fe99349599439b27cec48f5094003c [file] [log] [blame]
Jens Wiklander419e0d22015-12-07 14:37:10 +01001/*
2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-arm82cb2c12017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Jens Wiklander419e0d22015-12-07 14:37:10 +01005 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <assert_macros.S>
10#include <platform_def.h>
11
12 .globl plat_my_core_pos
13 .globl plat_get_my_entrypoint
14 .globl platform_mem_init
15 .globl plat_qemu_calc_core_pos
16 .globl plat_crash_console_init
17 .globl plat_crash_console_putc
18 .globl plat_secondary_cold_boot_setup
19 .globl plat_get_my_entrypoint
20 .globl plat_is_my_cpu_primary
21
22
23func plat_my_core_pos
24 mrs x0, mpidr_el1
25 b plat_qemu_calc_core_pos
26endfunc plat_my_core_pos
27
28/*
29 * unsigned int plat_qemu_calc_core_pos(u_register_t mpidr);
30 * With this function: CorePos = (ClusterId * 4) + CoreId
31 */
32func plat_qemu_calc_core_pos
33 and x1, x0, #MPIDR_CPU_MASK
34 and x0, x0, #MPIDR_CLUSTER_MASK
35 add x0, x1, x0, LSR #6
36 ret
37endfunc plat_qemu_calc_core_pos
38
39 /* -----------------------------------------------------
40 * unsigned int plat_is_my_cpu_primary (void);
41 *
42 * Find out whether the current cpu is the primary
43 * cpu.
44 * -----------------------------------------------------
45 */
46func plat_is_my_cpu_primary
47 mrs x0, mpidr_el1
48 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
49 cmp x0, #QEMU_PRIMARY_CPU
50 cset w0, eq
51 ret
52endfunc plat_is_my_cpu_primary
53
54 /* -----------------------------------------------------
55 * void plat_secondary_cold_boot_setup (void);
56 *
57 * This function performs any platform specific actions
58 * needed for a secondary cpu after a cold reset e.g
59 * mark the cpu's presence, mechanism to place it in a
60 * holding pen etc.
61 * -----------------------------------------------------
62 */
63func plat_secondary_cold_boot_setup
64 /* Calculate address of our hold entry */
65 bl plat_my_core_pos
Etienne Carriere33dd33f2017-10-24 01:09:52 +020066 lsl x0, x0, #PLAT_QEMU_HOLD_ENTRY_SHIFT
Jens Wiklander419e0d22015-12-07 14:37:10 +010067 mov_imm x2, PLAT_QEMU_HOLD_BASE
68
69 /* Wait until we have a go */
70poll_mailbox:
71 ldr x1, [x2, x0]
72 cbz x1, 1f
73 mov_imm x0, PLAT_QEMU_TRUSTED_MAILBOX_BASE
74 ldr x1, [x0]
75 br x1
761:
77 wfe
78 b poll_mailbox
79endfunc plat_secondary_cold_boot_setup
80
81func plat_get_my_entrypoint
82 /* TODO support warm boot */
83 mov x0, #0
84 ret
85endfunc plat_get_my_entrypoint
86
87func platform_mem_init
88 ret
89endfunc platform_mem_init
90
91 /* ---------------------------------------------
92 * int plat_crash_console_init(void)
93 * Function to initialize the crash console
94 * without a C Runtime to print crash report.
95 * Clobber list : x0, x1, x2
96 * ---------------------------------------------
97 */
98func plat_crash_console_init
99 mov_imm x0, PLAT_QEMU_CRASH_UART_BASE
100 mov_imm x1, PLAT_QEMU_CRASH_UART_CLK_IN_HZ
101 mov_imm x2, PLAT_QEMU_CONSOLE_BAUDRATE
102 b console_core_init
103endfunc plat_crash_console_init
104
105 /* ---------------------------------------------
106 * int plat_crash_console_putc(int c)
107 * Function to print a character on the crash
108 * console without a C Runtime.
109 * Clobber list : x1, x2
110 * ---------------------------------------------
111 */
112func plat_crash_console_putc
113 mov_imm x1, PLAT_QEMU_CRASH_UART_BASE
114 b console_core_putc
115endfunc plat_crash_console_putc
116
117