Isla Mitchell | abbffe9 | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 1 | /* |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 2 | * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. |
Isla Mitchell | abbffe9 | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 9 | #include <neoverse_n1.h> |
Dimitris Papastamos | 08268e2 | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 10 | #include <cpuamu.h> |
Isla Mitchell | abbffe9 | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 11 | #include <cpu_macros.S> |
Dimitris Papastamos | 08268e2 | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 12 | |
Dimitris Papastamos | 040b546 | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 13 | /* -------------------------------------------------- |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 14 | * Errata Workaround for Neoverse N1 Errata |
| 15 | * This applies to revision r0p0 and r1p0 of Neoverse N1. |
Dimitris Papastamos | 040b546 | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 16 | * Inputs: |
| 17 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 18 | * Shall clobber: x0-x17 |
| 19 | * -------------------------------------------------- |
| 20 | */ |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 21 | func errata_n1_1043202_wa |
Dimitris Papastamos | 040b546 | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 22 | /* Compare x0 against revision r1p0 */ |
| 23 | mov x17, x30 |
| 24 | bl check_errata_1043202 |
| 25 | cbz x0, 1f |
| 26 | |
| 27 | /* Apply instruction patching sequence */ |
| 28 | ldr x0, =0x0 |
| 29 | msr CPUPSELR_EL3, x0 |
| 30 | ldr x0, =0xF3BF8F2F |
| 31 | msr CPUPOR_EL3, x0 |
| 32 | ldr x0, =0xFFFFFFFF |
| 33 | msr CPUPMR_EL3, x0 |
| 34 | ldr x0, =0x800200071 |
| 35 | msr CPUPCR_EL3, x0 |
| 36 | isb |
| 37 | 1: |
| 38 | ret x17 |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 39 | endfunc errata_n1_1043202_wa |
Dimitris Papastamos | 040b546 | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 40 | |
| 41 | func check_errata_1043202 |
| 42 | /* Applies to r0p0 and r1p0 */ |
| 43 | mov x1, #0x10 |
| 44 | b cpu_rev_var_ls |
| 45 | endfunc check_errata_1043202 |
| 46 | |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 47 | func neoverse_n1_reset_func |
Dimitris Papastamos | 040b546 | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 48 | mov x19, x30 |
John Tsichritzis | 8074448 | 2019-03-04 16:41:26 +0000 | [diff] [blame] | 49 | |
| 50 | /* Disables speculative loads */ |
| 51 | msr SSBS, xzr |
| 52 | |
Louis Mayencourt | 632ab3e | 2019-04-18 14:34:11 +0100 | [diff] [blame^] | 53 | /* Forces all cacheable atomic instructions to be near */ |
| 54 | mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 |
| 55 | orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 |
| 56 | msr NEOVERSE_N1_CPUACTLR2_EL1, x0 |
| 57 | isb |
| 58 | |
Dimitris Papastamos | 040b546 | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 59 | bl cpu_get_rev_var |
| 60 | mov x18, x0 |
| 61 | |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 62 | #if ERRATA_N1_1043202 |
Dimitris Papastamos | 040b546 | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 63 | mov x0, x18 |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 64 | bl errata_n1_1043202_wa |
Dimitris Papastamos | 040b546 | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 65 | #endif |
| 66 | |
Dimitris Papastamos | 08268e2 | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 67 | #if ENABLE_AMU |
| 68 | /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ |
| 69 | mrs x0, actlr_el3 |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 70 | orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT |
Dimitris Papastamos | 08268e2 | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 71 | msr actlr_el3, x0 |
| 72 | isb |
| 73 | |
| 74 | /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ |
| 75 | mrs x0, actlr_el2 |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 76 | orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT |
Dimitris Papastamos | 08268e2 | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 77 | msr actlr_el2, x0 |
| 78 | isb |
| 79 | |
| 80 | /* Enable group0 counters */ |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 81 | mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK |
Dimitris Papastamos | 08268e2 | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 82 | msr CPUAMCNTENSET_EL0, x0 |
| 83 | isb |
| 84 | #endif |
Dimitris Papastamos | 040b546 | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 85 | ret x19 |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 86 | endfunc neoverse_n1_reset_func |
Isla Mitchell | abbffe9 | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 87 | |
| 88 | /* --------------------------------------------- |
| 89 | * HW will do the cache maintenance while powering down |
| 90 | * --------------------------------------------- |
| 91 | */ |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 92 | func neoverse_n1_core_pwr_dwn |
Isla Mitchell | abbffe9 | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 93 | /* --------------------------------------------- |
| 94 | * Enable CPU power down bit in power control register |
| 95 | * --------------------------------------------- |
| 96 | */ |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 97 | mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 |
| 98 | orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK |
| 99 | msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 |
Isla Mitchell | abbffe9 | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 100 | isb |
| 101 | ret |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 102 | endfunc neoverse_n1_core_pwr_dwn |
Isla Mitchell | abbffe9 | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 103 | |
Dimitris Papastamos | 040b546 | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 104 | #if REPORT_ERRATA |
| 105 | /* |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 106 | * Errata printing function for Neoverse N1. Must follow AAPCS. |
Dimitris Papastamos | 040b546 | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 107 | */ |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 108 | func neoverse_n1_errata_report |
Dimitris Papastamos | 040b546 | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 109 | stp x8, x30, [sp, #-16]! |
| 110 | |
| 111 | bl cpu_get_rev_var |
| 112 | mov x8, x0 |
| 113 | |
| 114 | /* |
| 115 | * Report all errata. The revision-variant information is passed to |
| 116 | * checking functions of each errata. |
| 117 | */ |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 118 | report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 |
Dimitris Papastamos | 040b546 | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 119 | |
| 120 | ldp x8, x30, [sp], #16 |
| 121 | ret |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 122 | endfunc neoverse_n1_errata_report |
Dimitris Papastamos | 040b546 | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 123 | #endif |
| 124 | |
Isla Mitchell | abbffe9 | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 125 | /* --------------------------------------------- |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 126 | * This function provides neoverse_n1 specific |
Isla Mitchell | abbffe9 | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 127 | * register information for crash reporting. |
| 128 | * It needs to return with x6 pointing to |
| 129 | * a list of register names in ascii and |
| 130 | * x8 - x15 having values of registers to be |
| 131 | * reported. |
| 132 | * --------------------------------------------- |
| 133 | */ |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 134 | .section .rodata.neoverse_n1_regs, "aS" |
| 135 | neoverse_n1_regs: /* The ascii list of register names to be reported */ |
Isla Mitchell | abbffe9 | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 136 | .asciz "cpuectlr_el1", "" |
| 137 | |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 138 | func neoverse_n1_cpu_reg_dump |
| 139 | adr x6, neoverse_n1_regs |
| 140 | mrs x8, NEOVERSE_N1_CPUECTLR_EL1 |
Isla Mitchell | abbffe9 | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 141 | ret |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 142 | endfunc neoverse_n1_cpu_reg_dump |
Isla Mitchell | abbffe9 | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 143 | |
John Tsichritzis | da6d75a | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 144 | declare_cpu_ops neoverse_n1, NEOVERSE_N1_MIDR, \ |
| 145 | neoverse_n1_reset_func, \ |
| 146 | neoverse_n1_core_pwr_dwn |