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Soby Mathewc11ba852016-05-05 14:32:05 +01001/*
Douglas Raillard32f0d3c2017-01-26 15:54:44 +00002 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
Soby Mathewc11ba852016-05-05 14:32:05 +01003 *
dp-arm82cb2c12017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewc11ba852016-05-05 14:32:05 +01005 */
6
7#include <arch.h>
8#include <arch_helpers.h>
9#include <assert.h>
10#include <bl_common.h>
11#include <context.h>
12#include <context_mgmt.h>
13#include <debug.h>
14#include <platform.h>
15#include <platform_def.h>
16#include <platform_sp_min.h>
17#include <psci.h>
18#include <runtime_svc.h>
19#include <smcc_helpers.h>
20#include <stddef.h>
21#include <stdint.h>
22#include <string.h>
23#include <types.h>
Douglas Raillard32f0d3c2017-01-26 15:54:44 +000024#include <utils.h>
Soby Mathewc11ba852016-05-05 14:32:05 +010025#include "sp_min_private.h"
26
27/* Pointers to per-core cpu contexts */
28static void *sp_min_cpu_ctx_ptr[PLATFORM_CORE_COUNT];
29
30/* SP_MIN only stores the non secure smc context */
31static smc_ctx_t sp_min_smc_context[PLATFORM_CORE_COUNT];
32
33/******************************************************************************
34 * Define the smcc helper library API's
35 *****************************************************************************/
36void *smc_get_ctx(int security_state)
37{
38 assert(security_state == NON_SECURE);
39 return &sp_min_smc_context[plat_my_core_pos()];
40}
41
42void smc_set_next_ctx(int security_state)
43{
44 assert(security_state == NON_SECURE);
45 /* SP_MIN stores only non secure smc context. Nothing to do here */
46}
47
48void *smc_get_next_ctx(void)
49{
50 return &sp_min_smc_context[plat_my_core_pos()];
51}
52
53/*******************************************************************************
54 * This function returns a pointer to the most recent 'cpu_context' structure
55 * for the calling CPU that was set as the context for the specified security
56 * state. NULL is returned if no such structure has been specified.
57 ******************************************************************************/
58void *cm_get_context(uint32_t security_state)
59{
60 assert(security_state == NON_SECURE);
61 return sp_min_cpu_ctx_ptr[plat_my_core_pos()];
62}
63
64/*******************************************************************************
65 * This function sets the pointer to the current 'cpu_context' structure for the
66 * specified security state for the calling CPU
67 ******************************************************************************/
68void cm_set_context(void *context, uint32_t security_state)
69{
70 assert(security_state == NON_SECURE);
71 sp_min_cpu_ctx_ptr[plat_my_core_pos()] = context;
72}
73
74/*******************************************************************************
75 * This function returns a pointer to the most recent 'cpu_context' structure
76 * for the CPU identified by `cpu_idx` that was set as the context for the
77 * specified security state. NULL is returned if no such structure has been
78 * specified.
79 ******************************************************************************/
80void *cm_get_context_by_index(unsigned int cpu_idx,
81 unsigned int security_state)
82{
83 assert(security_state == NON_SECURE);
84 return sp_min_cpu_ctx_ptr[cpu_idx];
85}
86
87/*******************************************************************************
88 * This function sets the pointer to the current 'cpu_context' structure for the
89 * specified security state for the CPU identified by CPU index.
90 ******************************************************************************/
91void cm_set_context_by_index(unsigned int cpu_idx, void *context,
92 unsigned int security_state)
93{
94 assert(security_state == NON_SECURE);
95 sp_min_cpu_ctx_ptr[cpu_idx] = context;
96}
97
98static void copy_cpu_ctx_to_smc_stx(const regs_t *cpu_reg_ctx,
99 smc_ctx_t *next_smc_ctx)
100{
101 next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0);
102 next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR);
103 next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR);
104}
105
106/*******************************************************************************
107 * This function invokes the PSCI library interface to initialize the
108 * non secure cpu context and copies the relevant cpu context register values
109 * to smc context. These registers will get programmed during `smc_exit`.
110 ******************************************************************************/
111static void sp_min_prepare_next_image_entry(void)
112{
113 entry_point_info_t *next_image_info;
114
115 /* Program system registers to proceed to non-secure */
116 next_image_info = sp_min_plat_get_bl33_ep_info();
117 assert(next_image_info);
118 assert(NON_SECURE == GET_SECURITY_STATE(next_image_info->h.attr));
119
120 INFO("SP_MIN: Preparing exit to normal world\n");
121
122 psci_prepare_next_non_secure_ctx(next_image_info);
123 smc_set_next_ctx(NON_SECURE);
124
125 /* Copy r0, lr and spsr from cpu context to SMC context */
126 copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)),
127 smc_get_next_ctx());
128}
129
130/******************************************************************************
Soby Mathew58e946a2016-09-19 17:21:15 +0100131 * Implement the ARM Standard Service function to get arguments for a
132 * particular service.
133 *****************************************************************************/
134uintptr_t get_arm_std_svc_args(unsigned int svc_mask)
135{
136 /* Setup the arguments for PSCI Library */
137 DEFINE_STATIC_PSCI_LIB_ARGS_V1(psci_args, sp_min_warm_entrypoint);
138
139 /* PSCI is the only ARM Standard Service implemented */
140 assert(svc_mask == PSCI_FID_MASK);
141
142 return (uintptr_t)&psci_args;
143}
144
145/******************************************************************************
Soby Mathewc11ba852016-05-05 14:32:05 +0100146 * The SP_MIN main function. Do the platform and PSCI Library setup. Also
147 * initialize the runtime service framework.
148 *****************************************************************************/
149void sp_min_main(void)
150{
Soby Mathewf426fc02016-09-13 14:19:08 +0100151 NOTICE("SP_MIN: %s\n", version_string);
152 NOTICE("SP_MIN: %s\n", build_message);
153
154 /* Perform the SP_MIN platform setup */
Soby Mathewc11ba852016-05-05 14:32:05 +0100155 sp_min_platform_setup();
156
Soby Mathew58e946a2016-09-19 17:21:15 +0100157 /* Initialize the runtime services e.g. psci */
Soby Mathewc11ba852016-05-05 14:32:05 +0100158 INFO("SP_MIN: Initializing runtime services\n");
159 runtime_svc_init();
160
161 /*
162 * We are ready to enter the next EL. Prepare entry into the image
163 * corresponding to the desired security state after the next ERET.
164 */
165 sp_min_prepare_next_image_entry();
166}
167
168/******************************************************************************
169 * This function is invoked during warm boot. Invoke the PSCI library
170 * warm boot entry point which takes care of Architectural and platform setup/
171 * restore. Copy the relevant cpu_context register values to smc context which
172 * will get programmed during `smc_exit`.
173 *****************************************************************************/
174void sp_min_warm_boot(void)
175{
176 smc_ctx_t *next_smc_ctx;
177
178 psci_warmboot_entrypoint();
179
180 smc_set_next_ctx(NON_SECURE);
181
182 next_smc_ctx = smc_get_next_ctx();
Douglas Raillard32f0d3c2017-01-26 15:54:44 +0000183 zeromem(next_smc_ctx, sizeof(smc_ctx_t));
Soby Mathewc11ba852016-05-05 14:32:05 +0100184
185 copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)),
186 next_smc_ctx);
187}