Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 1 | /* |
Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 2 | * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 3 | * |
dp-arm | 82cb2c1 | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __CONTEXT_H__ |
| 8 | #define __CONTEXT_H__ |
| 9 | |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 10 | /******************************************************************************* |
Achin Gupta | 07f4e07 | 2014-02-02 12:02:23 +0000 | [diff] [blame] | 11 | * Constants that allow assembler code to access members of and the 'gp_regs' |
| 12 | * structure at their correct offsets. |
| 13 | ******************************************************************************/ |
Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 14 | #define CTX_GPREGS_OFFSET U(0x0) |
| 15 | #define CTX_GPREG_X0 U(0x0) |
| 16 | #define CTX_GPREG_X1 U(0x8) |
| 17 | #define CTX_GPREG_X2 U(0x10) |
| 18 | #define CTX_GPREG_X3 U(0x18) |
| 19 | #define CTX_GPREG_X4 U(0x20) |
| 20 | #define CTX_GPREG_X5 U(0x28) |
| 21 | #define CTX_GPREG_X6 U(0x30) |
| 22 | #define CTX_GPREG_X7 U(0x38) |
| 23 | #define CTX_GPREG_X8 U(0x40) |
| 24 | #define CTX_GPREG_X9 U(0x48) |
| 25 | #define CTX_GPREG_X10 U(0x50) |
| 26 | #define CTX_GPREG_X11 U(0x58) |
| 27 | #define CTX_GPREG_X12 U(0x60) |
| 28 | #define CTX_GPREG_X13 U(0x68) |
| 29 | #define CTX_GPREG_X14 U(0x70) |
| 30 | #define CTX_GPREG_X15 U(0x78) |
| 31 | #define CTX_GPREG_X16 U(0x80) |
| 32 | #define CTX_GPREG_X17 U(0x88) |
| 33 | #define CTX_GPREG_X18 U(0x90) |
| 34 | #define CTX_GPREG_X19 U(0x98) |
| 35 | #define CTX_GPREG_X20 U(0xa0) |
| 36 | #define CTX_GPREG_X21 U(0xa8) |
| 37 | #define CTX_GPREG_X22 U(0xb0) |
| 38 | #define CTX_GPREG_X23 U(0xb8) |
| 39 | #define CTX_GPREG_X24 U(0xc0) |
| 40 | #define CTX_GPREG_X25 U(0xc8) |
| 41 | #define CTX_GPREG_X26 U(0xd0) |
| 42 | #define CTX_GPREG_X27 U(0xd8) |
| 43 | #define CTX_GPREG_X28 U(0xe0) |
| 44 | #define CTX_GPREG_X29 U(0xe8) |
| 45 | #define CTX_GPREG_LR U(0xf0) |
| 46 | #define CTX_GPREG_SP_EL0 U(0xf8) |
| 47 | #define CTX_GPREGS_END U(0x100) |
Achin Gupta | 07f4e07 | 2014-02-02 12:02:23 +0000 | [diff] [blame] | 48 | |
| 49 | /******************************************************************************* |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 50 | * Constants that allow assembler code to access members of and the 'el3_state' |
| 51 | * structure at their correct offsets. Note that some of the registers are only |
| 52 | * 32-bits wide but are stored as 64-bit values for convenience |
| 53 | ******************************************************************************/ |
Achin Gupta | 07f4e07 | 2014-02-02 12:02:23 +0000 | [diff] [blame] | 54 | #define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) |
Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 55 | #define CTX_SCR_EL3 U(0x0) |
| 56 | #define CTX_RUNTIME_SP U(0x8) |
| 57 | #define CTX_SPSR_EL3 U(0x10) |
| 58 | #define CTX_ELR_EL3 U(0x18) |
| 59 | #define CTX_EL3STATE_END U(0x20) |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 60 | |
| 61 | /******************************************************************************* |
| 62 | * Constants that allow assembler code to access members of and the |
| 63 | * 'el1_sys_regs' structure at their correct offsets. Note that some of the |
| 64 | * registers are only 32-bits wide but are stored as 64-bit values for |
| 65 | * convenience |
| 66 | ******************************************************************************/ |
| 67 | #define CTX_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) |
Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 68 | #define CTX_SPSR_EL1 U(0x0) |
| 69 | #define CTX_ELR_EL1 U(0x8) |
| 70 | #define CTX_SCTLR_EL1 U(0x10) |
| 71 | #define CTX_ACTLR_EL1 U(0x18) |
| 72 | #define CTX_CPACR_EL1 U(0x20) |
| 73 | #define CTX_CSSELR_EL1 U(0x28) |
| 74 | #define CTX_SP_EL1 U(0x30) |
| 75 | #define CTX_ESR_EL1 U(0x38) |
| 76 | #define CTX_TTBR0_EL1 U(0x40) |
| 77 | #define CTX_TTBR1_EL1 U(0x48) |
| 78 | #define CTX_MAIR_EL1 U(0x50) |
| 79 | #define CTX_AMAIR_EL1 U(0x58) |
| 80 | #define CTX_TCR_EL1 U(0x60) |
| 81 | #define CTX_TPIDR_EL1 U(0x68) |
| 82 | #define CTX_TPIDR_EL0 U(0x70) |
| 83 | #define CTX_TPIDRRO_EL0 U(0x78) |
| 84 | #define CTX_PAR_EL1 U(0x80) |
| 85 | #define CTX_FAR_EL1 U(0x88) |
| 86 | #define CTX_AFSR0_EL1 U(0x90) |
| 87 | #define CTX_AFSR1_EL1 U(0x98) |
| 88 | #define CTX_CONTEXTIDR_EL1 U(0xa0) |
| 89 | #define CTX_VBAR_EL1 U(0xa8) |
David Cunado | 3e61b2b | 2017-10-02 17:41:39 +0100 | [diff] [blame] | 90 | #define CTX_PMCR_EL0 U(0xb0) |
Soby Mathew | 8cd16e6 | 2016-05-17 14:01:32 +0100 | [diff] [blame] | 91 | |
| 92 | /* |
| 93 | * If the platform is AArch64-only, there is no need to save and restore these |
| 94 | * AArch32 registers. |
| 95 | */ |
| 96 | #if CTX_INCLUDE_AARCH32_REGS |
David Cunado | 3e61b2b | 2017-10-02 17:41:39 +0100 | [diff] [blame] | 97 | #define CTX_SPSR_ABT U(0xc0) /* Align to the next 16 byte boundary */ |
| 98 | #define CTX_SPSR_UND U(0xc8) |
| 99 | #define CTX_SPSR_IRQ U(0xd0) |
| 100 | #define CTX_SPSR_FIQ U(0xd8) |
| 101 | #define CTX_DACR32_EL2 U(0xe0) |
| 102 | #define CTX_IFSR32_EL2 U(0xe8) |
David Cunado | 91089f3 | 2017-10-20 11:30:57 +0100 | [diff] [blame^] | 103 | #define CTX_TIMER_SYSREGS_OFF U(0xf0) /* Align to the next 16 byte boundary */ |
Soby Mathew | 8cd16e6 | 2016-05-17 14:01:32 +0100 | [diff] [blame] | 104 | #else |
David Cunado | 3e61b2b | 2017-10-02 17:41:39 +0100 | [diff] [blame] | 105 | #define CTX_TIMER_SYSREGS_OFF U(0xc0) /* Align to the next 16 byte boundary */ |
Soby Mathew | 8cd16e6 | 2016-05-17 14:01:32 +0100 | [diff] [blame] | 106 | #endif /* __CTX_INCLUDE_AARCH32_REGS__ */ |
| 107 | |
Jeenu Viswambharan | 2da8d8b | 2014-05-12 15:28:47 +0100 | [diff] [blame] | 108 | /* |
| 109 | * If the timer registers aren't saved and restored, we don't have to reserve |
| 110 | * space for them in the context |
| 111 | */ |
| 112 | #if NS_TIMER_SWITCH |
Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 113 | #define CTX_CNTP_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x0)) |
| 114 | #define CTX_CNTP_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x8)) |
| 115 | #define CTX_CNTV_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x10)) |
| 116 | #define CTX_CNTV_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x18)) |
| 117 | #define CTX_CNTKCTL_EL1 (CTX_TIMER_SYSREGS_OFF + U(0x20)) |
| 118 | #define CTX_SYSREGS_END (CTX_TIMER_SYSREGS_OFF + U(0x30)) /* Align to the next 16 byte boundary */ |
Jeenu Viswambharan | 2da8d8b | 2014-05-12 15:28:47 +0100 | [diff] [blame] | 119 | #else |
Soby Mathew | 8cd16e6 | 2016-05-17 14:01:32 +0100 | [diff] [blame] | 120 | #define CTX_SYSREGS_END CTX_TIMER_SYSREGS_OFF |
| 121 | #endif /* __NS_TIMER_SWITCH__ */ |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 122 | |
| 123 | /******************************************************************************* |
| 124 | * Constants that allow assembler code to access members of and the 'fp_regs' |
| 125 | * structure at their correct offsets. |
| 126 | ******************************************************************************/ |
Juan Castillo | 0f21c54 | 2014-06-25 17:26:36 +0100 | [diff] [blame] | 127 | #if CTX_INCLUDE_FPREGS |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 128 | #define CTX_FPREGS_OFFSET (CTX_SYSREGS_OFFSET + CTX_SYSREGS_END) |
Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 129 | #define CTX_FP_Q0 U(0x0) |
| 130 | #define CTX_FP_Q1 U(0x10) |
| 131 | #define CTX_FP_Q2 U(0x20) |
| 132 | #define CTX_FP_Q3 U(0x30) |
| 133 | #define CTX_FP_Q4 U(0x40) |
| 134 | #define CTX_FP_Q5 U(0x50) |
| 135 | #define CTX_FP_Q6 U(0x60) |
| 136 | #define CTX_FP_Q7 U(0x70) |
| 137 | #define CTX_FP_Q8 U(0x80) |
| 138 | #define CTX_FP_Q9 U(0x90) |
| 139 | #define CTX_FP_Q10 U(0xa0) |
| 140 | #define CTX_FP_Q11 U(0xb0) |
| 141 | #define CTX_FP_Q12 U(0xc0) |
| 142 | #define CTX_FP_Q13 U(0xd0) |
| 143 | #define CTX_FP_Q14 U(0xe0) |
| 144 | #define CTX_FP_Q15 U(0xf0) |
| 145 | #define CTX_FP_Q16 U(0x100) |
| 146 | #define CTX_FP_Q17 U(0x110) |
| 147 | #define CTX_FP_Q18 U(0x120) |
| 148 | #define CTX_FP_Q19 U(0x130) |
| 149 | #define CTX_FP_Q20 U(0x140) |
| 150 | #define CTX_FP_Q21 U(0x150) |
| 151 | #define CTX_FP_Q22 U(0x160) |
| 152 | #define CTX_FP_Q23 U(0x170) |
| 153 | #define CTX_FP_Q24 U(0x180) |
| 154 | #define CTX_FP_Q25 U(0x190) |
| 155 | #define CTX_FP_Q26 U(0x1a0) |
| 156 | #define CTX_FP_Q27 U(0x1b0) |
| 157 | #define CTX_FP_Q28 U(0x1c0) |
| 158 | #define CTX_FP_Q29 U(0x1d0) |
| 159 | #define CTX_FP_Q30 U(0x1e0) |
| 160 | #define CTX_FP_Q31 U(0x1f0) |
| 161 | #define CTX_FP_FPSR U(0x200) |
| 162 | #define CTX_FP_FPCR U(0x208) |
David Cunado | 91089f3 | 2017-10-20 11:30:57 +0100 | [diff] [blame^] | 163 | #if CTX_INCLUDE_AARCH32_REGS |
| 164 | #define CTX_FP_FPEXC32_EL2 U(0x210) |
| 165 | #define CTX_FPREGS_END U(0x220) /* Align to the next 16 byte boundary */ |
| 166 | #else |
| 167 | #define CTX_FPREGS_END U(0x210) /* Align to the next 16 byte boundary */ |
| 168 | #endif |
Juan Castillo | 0f21c54 | 2014-06-25 17:26:36 +0100 | [diff] [blame] | 169 | #endif |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 170 | |
| 171 | #ifndef __ASSEMBLY__ |
| 172 | |
Dan Handley | 97043ac | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 173 | #include <cassert.h> |
Andrew Thoelke | aaba4f2 | 2014-06-02 10:00:25 +0100 | [diff] [blame] | 174 | #include <platform_def.h> /* for CACHE_WRITEBACK_GRANULE */ |
Dan Handley | 97043ac | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 175 | #include <stdint.h> |
| 176 | |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 177 | /* |
| 178 | * Common constants to help define the 'cpu_context' structure and its |
| 179 | * members below. |
| 180 | */ |
Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 181 | #define DWORD_SHIFT U(3) |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 182 | #define DEFINE_REG_STRUCT(name, num_regs) \ |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 183 | typedef struct name { \ |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 184 | uint64_t _regs[num_regs]; \ |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 185 | } __aligned(16) name##_t |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 186 | |
| 187 | /* Constants to determine the size of individual context structures */ |
Achin Gupta | 07f4e07 | 2014-02-02 12:02:23 +0000 | [diff] [blame] | 188 | #define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT) |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 189 | #define CTX_SYSREG_ALL (CTX_SYSREGS_END >> DWORD_SHIFT) |
Juan Castillo | 0f21c54 | 2014-06-25 17:26:36 +0100 | [diff] [blame] | 190 | #if CTX_INCLUDE_FPREGS |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 191 | #define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT) |
Juan Castillo | 0f21c54 | 2014-06-25 17:26:36 +0100 | [diff] [blame] | 192 | #endif |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 193 | #define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT) |
| 194 | |
| 195 | /* |
Soby Mathew | c3260f9 | 2014-04-30 15:36:37 +0100 | [diff] [blame] | 196 | * AArch64 general purpose register context structure. Usually x0-x18, |
| 197 | * lr are saved as the compiler is expected to preserve the remaining |
Achin Gupta | 07f4e07 | 2014-02-02 12:02:23 +0000 | [diff] [blame] | 198 | * callee saved registers if used by the C runtime and the assembler |
Soby Mathew | c3260f9 | 2014-04-30 15:36:37 +0100 | [diff] [blame] | 199 | * does not touch the remaining. But in case of world switch during |
| 200 | * exception handling, we need to save the callee registers too. |
Achin Gupta | 07f4e07 | 2014-02-02 12:02:23 +0000 | [diff] [blame] | 201 | */ |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 202 | DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL); |
Achin Gupta | 07f4e07 | 2014-02-02 12:02:23 +0000 | [diff] [blame] | 203 | |
| 204 | /* |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 205 | * AArch64 EL1 system register context structure for preserving the |
| 206 | * architectural state during switches from one security state to |
| 207 | * another in EL1. |
| 208 | */ |
| 209 | DEFINE_REG_STRUCT(el1_sys_regs, CTX_SYSREG_ALL); |
| 210 | |
| 211 | /* |
| 212 | * AArch64 floating point register context structure for preserving |
| 213 | * the floating point state during switches from one security state to |
| 214 | * another. |
| 215 | */ |
Juan Castillo | 0f21c54 | 2014-06-25 17:26:36 +0100 | [diff] [blame] | 216 | #if CTX_INCLUDE_FPREGS |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 217 | DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL); |
Juan Castillo | 0f21c54 | 2014-06-25 17:26:36 +0100 | [diff] [blame] | 218 | #endif |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 219 | |
| 220 | /* |
| 221 | * Miscellaneous registers used by EL3 firmware to maintain its state |
| 222 | * across exception entries and exits |
| 223 | */ |
| 224 | DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL); |
| 225 | |
| 226 | /* |
| 227 | * Macros to access members of any of the above structures using their |
| 228 | * offsets |
| 229 | */ |
| 230 | #define read_ctx_reg(ctx, offset) ((ctx)->_regs[offset >> DWORD_SHIFT]) |
| 231 | #define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[offset >> DWORD_SHIFT]) \ |
| 232 | = val) |
| 233 | |
| 234 | /* |
| 235 | * Top-level context structure which is used by EL3 firmware to |
| 236 | * preserve the state of a core at EL1 in one of the two security |
| 237 | * states and save enough EL3 meta data to be able to return to that |
| 238 | * EL and security state. The context management library will be used |
| 239 | * to ensure that SP_EL3 always points to an instance of this |
| 240 | * structure at exception entry and exit. Each instance will |
| 241 | * correspond to either the secure or the non-secure state. |
| 242 | */ |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 243 | typedef struct cpu_context { |
| 244 | gp_regs_t gpregs_ctx; |
| 245 | el3_state_t el3state_ctx; |
| 246 | el1_sys_regs_t sysregs_ctx; |
Juan Castillo | 0f21c54 | 2014-06-25 17:26:36 +0100 | [diff] [blame] | 247 | #if CTX_INCLUDE_FPREGS |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 248 | fp_regs_t fpregs_ctx; |
Juan Castillo | 0f21c54 | 2014-06-25 17:26:36 +0100 | [diff] [blame] | 249 | #endif |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 250 | } cpu_context_t; |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 251 | |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 252 | /* Macros to access members of the 'cpu_context_t' structure */ |
| 253 | #define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx) |
Juan Castillo | 0f21c54 | 2014-06-25 17:26:36 +0100 | [diff] [blame] | 254 | #if CTX_INCLUDE_FPREGS |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 255 | #define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx) |
Juan Castillo | 0f21c54 | 2014-06-25 17:26:36 +0100 | [diff] [blame] | 256 | #endif |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 257 | #define get_sysregs_ctx(h) (&((cpu_context_t *) h)->sysregs_ctx) |
| 258 | #define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx) |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 259 | |
| 260 | /* |
| 261 | * Compile time assertions related to the 'cpu_context' structure to |
| 262 | * ensure that the assembler and the compiler view of the offsets of |
| 263 | * the structure members is the same. |
| 264 | */ |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 265 | CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \ |
Achin Gupta | 07f4e07 | 2014-02-02 12:02:23 +0000 | [diff] [blame] | 266 | assert_core_context_gp_offset_mismatch); |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 267 | CASSERT(CTX_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, sysregs_ctx), \ |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 268 | assert_core_context_sys_offset_mismatch); |
Juan Castillo | 0f21c54 | 2014-06-25 17:26:36 +0100 | [diff] [blame] | 269 | #if CTX_INCLUDE_FPREGS |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 270 | CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), \ |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 271 | assert_core_context_fp_offset_mismatch); |
Juan Castillo | 0f21c54 | 2014-06-25 17:26:36 +0100 | [diff] [blame] | 272 | #endif |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 273 | CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), \ |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 274 | assert_core_context_el3state_offset_mismatch); |
| 275 | |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 276 | /* |
| 277 | * Helper macro to set the general purpose registers that correspond to |
| 278 | * parameters in an aapcs_64 call i.e. x0-x7 |
| 279 | */ |
| 280 | #define set_aapcs_args0(ctx, x0) do { \ |
| 281 | write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \ |
Soby Mathew | da554d7 | 2016-05-03 17:11:42 +0100 | [diff] [blame] | 282 | } while (0) |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 283 | #define set_aapcs_args1(ctx, x0, x1) do { \ |
| 284 | write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \ |
| 285 | set_aapcs_args0(ctx, x0); \ |
Soby Mathew | da554d7 | 2016-05-03 17:11:42 +0100 | [diff] [blame] | 286 | } while (0) |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 287 | #define set_aapcs_args2(ctx, x0, x1, x2) do { \ |
| 288 | write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \ |
| 289 | set_aapcs_args1(ctx, x0, x1); \ |
Soby Mathew | da554d7 | 2016-05-03 17:11:42 +0100 | [diff] [blame] | 290 | } while (0) |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 291 | #define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \ |
| 292 | write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \ |
| 293 | set_aapcs_args2(ctx, x0, x1, x2); \ |
Soby Mathew | da554d7 | 2016-05-03 17:11:42 +0100 | [diff] [blame] | 294 | } while (0) |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 295 | #define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \ |
| 296 | write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \ |
| 297 | set_aapcs_args3(ctx, x0, x1, x2, x3); \ |
Soby Mathew | da554d7 | 2016-05-03 17:11:42 +0100 | [diff] [blame] | 298 | } while (0) |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 299 | #define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \ |
| 300 | write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \ |
| 301 | set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \ |
Soby Mathew | da554d7 | 2016-05-03 17:11:42 +0100 | [diff] [blame] | 302 | } while (0) |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 303 | #define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \ |
| 304 | write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \ |
| 305 | set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \ |
Soby Mathew | da554d7 | 2016-05-03 17:11:42 +0100 | [diff] [blame] | 306 | } while (0) |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 307 | #define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \ |
| 308 | write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \ |
| 309 | set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \ |
Soby Mathew | da554d7 | 2016-05-03 17:11:42 +0100 | [diff] [blame] | 310 | } while (0) |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 311 | |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 312 | /******************************************************************************* |
| 313 | * Function prototypes |
| 314 | ******************************************************************************/ |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 315 | void el1_sysregs_context_save(el1_sys_regs_t *regs); |
dp-arm | d832aee | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 316 | void el1_sysregs_context_save_post_ops(void); |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 317 | void el1_sysregs_context_restore(el1_sys_regs_t *regs); |
Juan Castillo | 0f21c54 | 2014-06-25 17:26:36 +0100 | [diff] [blame] | 318 | #if CTX_INCLUDE_FPREGS |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 319 | void fpregs_context_save(fp_regs_t *regs); |
| 320 | void fpregs_context_restore(fp_regs_t *regs); |
Juan Castillo | 0f21c54 | 2014-06-25 17:26:36 +0100 | [diff] [blame] | 321 | #endif |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 322 | |
Soby Mathew | a43d431 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 323 | |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 324 | #undef CTX_SYSREG_ALL |
Juan Castillo | 0f21c54 | 2014-06-25 17:26:36 +0100 | [diff] [blame] | 325 | #if CTX_INCLUDE_FPREGS |
| 326 | #undef CTX_FPREG_ALL |
| 327 | #endif |
Achin Gupta | 07f4e07 | 2014-02-02 12:02:23 +0000 | [diff] [blame] | 328 | #undef CTX_GPREG_ALL |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 329 | #undef CTX_EL3STATE_ALL |
| 330 | |
| 331 | #endif /* __ASSEMBLY__ */ |
| 332 | |
| 333 | #endif /* __CONTEXT_H__ */ |