Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 1 | /* |
Alexei Fedorov | b29c350 | 2020-07-29 15:16:36 +0100 | [diff] [blame] | 2 | * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | 8e570b7 | 2020-07-05 13:12:28 -0700 | [diff] [blame] | 3 | * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | /* |
Andre Przywara | b4ad365 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 9 | * Driver for GIC-500 and GIC-600 specific features. This driver only |
| 10 | * overrides APIs that are different to those generic ones in GICv3 |
| 11 | * driver. |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 12 | * |
Alexei Fedorov | 7a7fbb1 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 13 | * GIC-600 supports independently power-gating redistributor interface. |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 16 | #include <assert.h> |
Antonio Nino Diaz | 09d40e0 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 17 | |
| 18 | #include <arch_helpers.h> |
| 19 | #include <drivers/arm/gicv3.h> |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 20 | |
| 21 | #include "gicv3_private.h" |
| 22 | |
Alexei Fedorov | 7a7fbb1 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 23 | /* GIC-600 specific register offsets */ |
Alexei Fedorov | b29c350 | 2020-07-29 15:16:36 +0100 | [diff] [blame] | 24 | #define GICR_PWRR 0x24U |
| 25 | #define IIDR_MODEL_ARM_GIC_600 U(0x0200043b) |
| 26 | #define IIDR_MODEL_ARM_GIC_600AE U(0x0300043b) |
| 27 | #define IIDR_MODEL_ARM_GIC_CLAYTON U(0x0400043b) |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 28 | |
| 29 | /* GICR_PWRR fields */ |
Varun Wadekar | 8e570b7 | 2020-07-05 13:12:28 -0700 | [diff] [blame] | 30 | #define PWRR_RDPD_SHIFT 0 |
| 31 | #define PWRR_RDAG_SHIFT 1 |
| 32 | #define PWRR_RDGPD_SHIFT 2 |
| 33 | #define PWRR_RDGPO_SHIFT 3 |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 34 | |
Alexei Fedorov | b29c350 | 2020-07-29 15:16:36 +0100 | [diff] [blame] | 35 | #define PWRR_RDPD (1U << PWRR_RDPD_SHIFT) |
| 36 | #define PWRR_RDAG (1U << PWRR_RDAG_SHIFT) |
| 37 | #define PWRR_RDGPD (1U << PWRR_RDGPD_SHIFT) |
| 38 | #define PWRR_RDGPO (1U << PWRR_RDGPO_SHIFT) |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 39 | |
Alexei Fedorov | 7a7fbb1 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 40 | /* |
| 41 | * Values to write to GICR_PWRR register to power redistributor |
| 42 | * for operating through the core (GICR_PWRR.RDAG = 0) |
| 43 | */ |
Alexei Fedorov | b29c350 | 2020-07-29 15:16:36 +0100 | [diff] [blame] | 44 | #define PWRR_ON (0U << PWRR_RDPD_SHIFT) |
| 45 | #define PWRR_OFF (1U << PWRR_RDPD_SHIFT) |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 46 | |
Andre Przywara | b4ad365 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 47 | #if GICV3_SUPPORT_GIC600 |
| 48 | |
Andre Przywara | e270e67 | 2020-06-26 10:30:33 +0100 | [diff] [blame] | 49 | /* GIC-600/Clayton specific accessor functions */ |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 50 | static void gicr_write_pwrr(uintptr_t base, unsigned int val) |
| 51 | { |
Douglas Raillard | b50bdce | 2017-08-03 15:59:49 +0100 | [diff] [blame] | 52 | mmio_write_32(base + GICR_PWRR, val); |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 53 | } |
| 54 | |
| 55 | static uint32_t gicr_read_pwrr(uintptr_t base) |
| 56 | { |
Douglas Raillard | b50bdce | 2017-08-03 15:59:49 +0100 | [diff] [blame] | 57 | return mmio_read_32(base + GICR_PWRR); |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 58 | } |
| 59 | |
Alexei Fedorov | 7a7fbb1 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 60 | static void gicr_wait_group_not_in_transit(uintptr_t base) |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 61 | { |
Alexei Fedorov | b29c350 | 2020-07-29 15:16:36 +0100 | [diff] [blame] | 62 | uint32_t pwrr; |
| 63 | |
| 64 | do { |
| 65 | pwrr = gicr_read_pwrr(base); |
| 66 | |
Alexei Fedorov | 7a7fbb1 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 67 | /* Check group not transitioning: RDGPD == RDGPO */ |
Alexei Fedorov | b29c350 | 2020-07-29 15:16:36 +0100 | [diff] [blame] | 68 | } while (((pwrr & PWRR_RDGPD) >> PWRR_RDGPD_SHIFT) != |
| 69 | ((pwrr & PWRR_RDGPO) >> PWRR_RDGPO_SHIFT)); |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 70 | } |
| 71 | |
| 72 | static void gic600_pwr_on(uintptr_t base) |
| 73 | { |
Alexei Fedorov | 7a7fbb1 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 74 | do { /* Wait until group not transitioning */ |
| 75 | gicr_wait_group_not_in_transit(base); |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 76 | |
Alexei Fedorov | 7a7fbb1 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 77 | /* Power on redistributor */ |
| 78 | gicr_write_pwrr(base, PWRR_ON); |
| 79 | |
| 80 | /* |
| 81 | * Wait until the power on state is reflected. |
| 82 | * If RDPD == 0 then powered on. |
| 83 | */ |
| 84 | } while ((gicr_read_pwrr(base) & PWRR_RDPD) != PWRR_ON); |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 85 | } |
| 86 | |
| 87 | static void gic600_pwr_off(uintptr_t base) |
| 88 | { |
Alexei Fedorov | 7a7fbb1 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 89 | /* Wait until group not transitioning */ |
| 90 | gicr_wait_group_not_in_transit(base); |
| 91 | |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 92 | /* Power off redistributor */ |
| 93 | gicr_write_pwrr(base, PWRR_OFF); |
| 94 | |
| 95 | /* |
| 96 | * If this is the last man, turning this redistributor frame off will |
Alexei Fedorov | 7a7fbb1 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 97 | * result in the group itself being powered off and RDGPD = 1. |
| 98 | * In that case, wait as long as it's in transition, or has aborted |
| 99 | * the transition altogether for any reason. |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 100 | */ |
Alexei Fedorov | b29c350 | 2020-07-29 15:16:36 +0100 | [diff] [blame] | 101 | if ((gicr_read_pwrr(base) & PWRR_RDGPD) != 0U) { |
Alexei Fedorov | 7a7fbb1 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 102 | /* Wait until group not transitioning */ |
| 103 | gicr_wait_group_not_in_transit(base); |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 104 | } |
| 105 | } |
| 106 | |
Andre Przywara | b4ad365 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 107 | static uintptr_t get_gicr_base(unsigned int proc_num) |
| 108 | { |
| 109 | uintptr_t gicr_base; |
| 110 | |
Alexei Fedorov | b29c350 | 2020-07-29 15:16:36 +0100 | [diff] [blame] | 111 | assert(gicv3_driver_data != NULL); |
Andre Przywara | b4ad365 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 112 | assert(proc_num < gicv3_driver_data->rdistif_num); |
Alexei Fedorov | b29c350 | 2020-07-29 15:16:36 +0100 | [diff] [blame] | 113 | assert(gicv3_driver_data->rdistif_base_addrs != NULL); |
Andre Przywara | b4ad365 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 114 | |
| 115 | gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; |
Alexei Fedorov | b29c350 | 2020-07-29 15:16:36 +0100 | [diff] [blame] | 116 | assert(gicr_base != 0UL); |
Andre Przywara | b4ad365 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 117 | |
| 118 | return gicr_base; |
| 119 | } |
| 120 | |
Andre Przywara | e270e67 | 2020-06-26 10:30:33 +0100 | [diff] [blame] | 121 | static bool gicv3_redists_need_power_mgmt(uintptr_t gicr_base) |
Andre Przywara | b4ad365 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 122 | { |
| 123 | uint32_t reg = mmio_read_32(gicr_base + GICR_IIDR); |
| 124 | |
Andre Przywara | e270e67 | 2020-06-26 10:30:33 +0100 | [diff] [blame] | 125 | /* |
| 126 | * The Arm GIC-600 and GIC-Clayton models have their redistributors |
| 127 | * powered down at reset. |
| 128 | */ |
Varun Wadekar | 8e570b7 | 2020-07-05 13:12:28 -0700 | [diff] [blame] | 129 | return (((reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_600) || |
Andre Przywara | e270e67 | 2020-06-26 10:30:33 +0100 | [diff] [blame] | 130 | ((reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_600AE) || |
| 131 | ((reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_CLAYTON)); |
Andre Przywara | b4ad365 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 132 | } |
| 133 | |
Alexei Fedorov | b29c350 | 2020-07-29 15:16:36 +0100 | [diff] [blame] | 134 | #endif /* GICV3_SUPPORT_GIC600 */ |
Andre Przywara | b4ad365 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 135 | |
Soby Mathew | ebf1ca1 | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 136 | void gicv3_distif_pre_save(unsigned int proc_num) |
| 137 | { |
| 138 | arm_gicv3_distif_pre_save(proc_num); |
| 139 | } |
| 140 | |
| 141 | void gicv3_distif_post_restore(unsigned int proc_num) |
| 142 | { |
| 143 | arm_gicv3_distif_post_restore(proc_num); |
| 144 | } |
| 145 | |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 146 | /* |
Andre Przywara | b4ad365 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 147 | * Power off GIC-600 redistributor (if configured and detected) |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 148 | */ |
| 149 | void gicv3_rdistif_off(unsigned int proc_num) |
| 150 | { |
Andre Przywara | b4ad365 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 151 | #if GICV3_SUPPORT_GIC600 |
| 152 | uintptr_t gicr_base = get_gicr_base(proc_num); |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 153 | |
| 154 | /* Attempt to power redistributor off */ |
Andre Przywara | e270e67 | 2020-06-26 10:30:33 +0100 | [diff] [blame] | 155 | if (gicv3_redists_need_power_mgmt(gicr_base)) { |
Andre Przywara | b4ad365 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 156 | gic600_pwr_off(gicr_base); |
| 157 | } |
| 158 | #endif |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 159 | } |
| 160 | |
| 161 | /* |
Andre Przywara | b4ad365 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 162 | * Power on GIC-600 redistributor (if configured and detected) |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 163 | */ |
| 164 | void gicv3_rdistif_on(unsigned int proc_num) |
| 165 | { |
Andre Przywara | b4ad365 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 166 | #if GICV3_SUPPORT_GIC600 |
| 167 | uintptr_t gicr_base = get_gicr_base(proc_num); |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 168 | |
| 169 | /* Power redistributor on */ |
Andre Przywara | e270e67 | 2020-06-26 10:30:33 +0100 | [diff] [blame] | 170 | if (gicv3_redists_need_power_mgmt(gicr_base)) { |
Andre Przywara | b4ad365 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 171 | gic600_pwr_on(gicr_base); |
| 172 | } |
| 173 | #endif |
Jeenu Viswambharan | e1c59ab | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 174 | } |