Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
David Wang | 4518dd9 | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch_helpers.h> |
| 32 | #include <arm_def.h> |
Yatharth Kochar | a8aa7fe | 2016-09-13 17:07:57 +0100 | [diff] [blame^] | 33 | #include <assert.h> |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 34 | #include <bl_common.h> |
| 35 | #include <console.h> |
Yatharth Kochar | a8aa7fe | 2016-09-13 17:07:57 +0100 | [diff] [blame^] | 36 | #include <debug.h> |
| 37 | #include <desc_image_load.h> |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 38 | #include <plat_arm.h> |
Yatharth Kochar | a8aa7fe | 2016-09-13 17:07:57 +0100 | [diff] [blame^] | 39 | #include <platform_def.h> |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 40 | #include <string.h> |
| 41 | |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 42 | #if USE_COHERENT_MEM |
| 43 | /* |
| 44 | * The next 2 constants identify the extents of the coherent memory region. |
| 45 | * These addresses are used by the MMU setup code and therefore they must be |
| 46 | * page-aligned. It is the responsibility of the linker script to ensure that |
| 47 | * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to |
| 48 | * page-aligned addresses. |
| 49 | */ |
| 50 | #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) |
| 51 | #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) |
| 52 | #endif |
| 53 | |
| 54 | /* Data structure which holds the extents of the trusted SRAM for BL2 */ |
| 55 | static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); |
| 56 | |
Yatharth Kochar | a8aa7fe | 2016-09-13 17:07:57 +0100 | [diff] [blame^] | 57 | /* Weak definitions may be overridden in specific ARM standard platform */ |
| 58 | #pragma weak bl2_early_platform_setup |
| 59 | #pragma weak bl2_platform_setup |
| 60 | #pragma weak bl2_plat_arch_setup |
| 61 | #pragma weak bl2_plat_sec_mem_layout |
| 62 | |
| 63 | #if LOAD_IMAGE_V2 |
| 64 | |
| 65 | #pragma weak bl2_plat_handle_post_image_load |
| 66 | |
| 67 | #else /* LOAD_IMAGE_V2 */ |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 68 | |
| 69 | /******************************************************************************* |
| 70 | * This structure represents the superset of information that is passed to |
Juan Castillo | d178637 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 71 | * BL31, e.g. while passing control to it from BL2, bl31_params |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 72 | * and other platform specific params |
| 73 | ******************************************************************************/ |
| 74 | typedef struct bl2_to_bl31_params_mem { |
| 75 | bl31_params_t bl31_params; |
| 76 | image_info_t bl31_image_info; |
| 77 | image_info_t bl32_image_info; |
| 78 | image_info_t bl33_image_info; |
| 79 | entry_point_info_t bl33_ep_info; |
| 80 | entry_point_info_t bl32_ep_info; |
| 81 | entry_point_info_t bl31_ep_info; |
| 82 | } bl2_to_bl31_params_mem_t; |
| 83 | |
| 84 | |
| 85 | static bl2_to_bl31_params_mem_t bl31_params_mem; |
| 86 | |
| 87 | |
| 88 | /* Weak definitions may be overridden in specific ARM standard platform */ |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 89 | #pragma weak bl2_plat_get_bl31_params |
| 90 | #pragma weak bl2_plat_get_bl31_ep_info |
| 91 | #pragma weak bl2_plat_flush_bl31_params |
| 92 | #pragma weak bl2_plat_set_bl31_ep_info |
Juan Castillo | f59821d | 2015-12-10 15:49:17 +0000 | [diff] [blame] | 93 | #pragma weak bl2_plat_get_scp_bl2_meminfo |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 94 | #pragma weak bl2_plat_get_bl32_meminfo |
| 95 | #pragma weak bl2_plat_set_bl32_ep_info |
| 96 | #pragma weak bl2_plat_get_bl33_meminfo |
| 97 | #pragma weak bl2_plat_set_bl33_ep_info |
| 98 | |
David Wang | 4518dd9 | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 99 | #if ARM_BL31_IN_DRAM |
| 100 | meminfo_t *bl2_plat_sec_mem_layout(void) |
| 101 | { |
| 102 | static meminfo_t bl2_dram_layout |
| 103 | __aligned(CACHE_WRITEBACK_GRANULE) = { |
| 104 | .total_base = BL31_BASE, |
| 105 | .total_size = (ARM_AP_TZC_DRAM1_BASE + |
| 106 | ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE, |
| 107 | .free_base = BL31_BASE, |
| 108 | .free_size = (ARM_AP_TZC_DRAM1_BASE + |
| 109 | ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE |
| 110 | }; |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 111 | |
David Wang | 4518dd9 | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 112 | return &bl2_dram_layout; |
| 113 | } |
| 114 | #else |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 115 | meminfo_t *bl2_plat_sec_mem_layout(void) |
| 116 | { |
| 117 | return &bl2_tzram_layout; |
| 118 | } |
Yatharth Kochar | a8aa7fe | 2016-09-13 17:07:57 +0100 | [diff] [blame^] | 119 | #endif /* ARM_BL31_IN_DRAM */ |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 120 | |
| 121 | /******************************************************************************* |
| 122 | * This function assigns a pointer to the memory that the platform has kept |
| 123 | * aside to pass platform specific and trusted firmware related information |
| 124 | * to BL31. This memory is allocated by allocating memory to |
| 125 | * bl2_to_bl31_params_mem_t structure which is a superset of all the |
| 126 | * structure whose information is passed to BL31 |
| 127 | * NOTE: This function should be called only once and should be done |
| 128 | * before generating params to BL31 |
| 129 | ******************************************************************************/ |
| 130 | bl31_params_t *bl2_plat_get_bl31_params(void) |
| 131 | { |
| 132 | bl31_params_t *bl2_to_bl31_params; |
| 133 | |
| 134 | /* |
| 135 | * Initialise the memory for all the arguments that needs to |
Juan Castillo | d178637 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 136 | * be passed to BL31 |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 137 | */ |
| 138 | memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t)); |
| 139 | |
| 140 | /* Assign memory for TF related information */ |
| 141 | bl2_to_bl31_params = &bl31_params_mem.bl31_params; |
| 142 | SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); |
| 143 | |
Juan Castillo | d178637 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 144 | /* Fill BL31 related information */ |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 145 | bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; |
| 146 | SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, |
| 147 | VERSION_1, 0); |
| 148 | |
Juan Castillo | d178637 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 149 | /* Fill BL32 related information if it exists */ |
Antonio Nino Diaz | 81d139d | 2016-04-05 11:38:49 +0100 | [diff] [blame] | 150 | #ifdef BL32_BASE |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 151 | bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; |
| 152 | SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, |
| 153 | VERSION_1, 0); |
| 154 | bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; |
| 155 | SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, |
| 156 | VERSION_1, 0); |
Antonio Nino Diaz | 81d139d | 2016-04-05 11:38:49 +0100 | [diff] [blame] | 157 | #endif /* BL32_BASE */ |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 158 | |
Juan Castillo | d178637 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 159 | /* Fill BL33 related information */ |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 160 | bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; |
| 161 | SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, |
| 162 | PARAM_EP, VERSION_1, 0); |
| 163 | |
Juan Castillo | d178637 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 164 | /* BL33 expects to receive the primary CPU MPID (through x0) */ |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 165 | bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); |
| 166 | |
| 167 | bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; |
| 168 | SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, |
| 169 | VERSION_1, 0); |
| 170 | |
| 171 | return bl2_to_bl31_params; |
| 172 | } |
| 173 | |
| 174 | /* Flush the TF params and the TF plat params */ |
| 175 | void bl2_plat_flush_bl31_params(void) |
| 176 | { |
| 177 | flush_dcache_range((unsigned long)&bl31_params_mem, |
| 178 | sizeof(bl2_to_bl31_params_mem_t)); |
| 179 | } |
| 180 | |
| 181 | /******************************************************************************* |
| 182 | * This function returns a pointer to the shared memory that the platform |
| 183 | * has kept to point to entry point information of BL31 to BL2 |
| 184 | ******************************************************************************/ |
| 185 | struct entry_point_info *bl2_plat_get_bl31_ep_info(void) |
| 186 | { |
| 187 | #if DEBUG |
| 188 | bl31_params_mem.bl31_ep_info.args.arg1 = ARM_BL31_PLAT_PARAM_VAL; |
| 189 | #endif |
| 190 | |
| 191 | return &bl31_params_mem.bl31_ep_info; |
| 192 | } |
Yatharth Kochar | a8aa7fe | 2016-09-13 17:07:57 +0100 | [diff] [blame^] | 193 | #endif /* LOAD_IMAGE_V2 */ |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 194 | |
| 195 | /******************************************************************************* |
| 196 | * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 |
| 197 | * in x0. This memory layout is sitting at the base of the free trusted SRAM. |
| 198 | * Copy it to a safe location before its reclaimed by later BL2 functionality. |
| 199 | ******************************************************************************/ |
| 200 | void arm_bl2_early_platform_setup(meminfo_t *mem_layout) |
| 201 | { |
| 202 | /* Initialize the console to provide early debug support */ |
| 203 | console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, |
| 204 | ARM_CONSOLE_BAUDRATE); |
| 205 | |
| 206 | /* Setup the BL2 memory layout */ |
| 207 | bl2_tzram_layout = *mem_layout; |
| 208 | |
| 209 | /* Initialise the IO layer and register platform IO devices */ |
| 210 | plat_arm_io_setup(); |
| 211 | } |
| 212 | |
| 213 | void bl2_early_platform_setup(meminfo_t *mem_layout) |
| 214 | { |
| 215 | arm_bl2_early_platform_setup(mem_layout); |
| 216 | } |
| 217 | |
| 218 | /* |
| 219 | * Perform ARM standard platform setup. |
| 220 | */ |
| 221 | void arm_bl2_platform_setup(void) |
| 222 | { |
| 223 | /* Initialize the secure environment */ |
| 224 | plat_arm_security_setup(); |
| 225 | } |
| 226 | |
| 227 | void bl2_platform_setup(void) |
| 228 | { |
| 229 | arm_bl2_platform_setup(); |
| 230 | } |
| 231 | |
| 232 | /******************************************************************************* |
| 233 | * Perform the very early platform specific architectural setup here. At the |
| 234 | * moment this is only initializes the mmu in a quick and dirty way. |
| 235 | ******************************************************************************/ |
| 236 | void arm_bl2_plat_arch_setup(void) |
| 237 | { |
Sandrine Bailleux | b5fa656 | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 238 | arm_setup_page_tables(bl2_tzram_layout.total_base, |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 239 | bl2_tzram_layout.total_size, |
Sandrine Bailleux | 0af559a | 2016-07-08 14:38:16 +0100 | [diff] [blame] | 240 | BL_CODE_BASE, |
| 241 | BL_CODE_LIMIT, |
| 242 | BL_RO_DATA_BASE, |
| 243 | BL_RO_DATA_LIMIT |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 244 | #if USE_COHERENT_MEM |
| 245 | , BL2_COHERENT_RAM_BASE, |
| 246 | BL2_COHERENT_RAM_LIMIT |
| 247 | #endif |
| 248 | ); |
Sandrine Bailleux | b5fa656 | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 249 | enable_mmu_el1(0); |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 250 | } |
| 251 | |
| 252 | void bl2_plat_arch_setup(void) |
| 253 | { |
| 254 | arm_bl2_plat_arch_setup(); |
| 255 | } |
| 256 | |
Yatharth Kochar | a8aa7fe | 2016-09-13 17:07:57 +0100 | [diff] [blame^] | 257 | #if LOAD_IMAGE_V2 |
| 258 | /******************************************************************************* |
| 259 | * This function can be used by the platforms to update/use image |
| 260 | * information for given `image_id`. |
| 261 | ******************************************************************************/ |
| 262 | int bl2_plat_handle_post_image_load(unsigned int image_id) |
| 263 | { |
| 264 | int err = 0; |
| 265 | bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); |
| 266 | assert(bl_mem_params); |
| 267 | |
| 268 | switch (image_id) { |
| 269 | case BL32_IMAGE_ID: |
| 270 | bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); |
| 271 | break; |
| 272 | |
| 273 | case BL33_IMAGE_ID: |
| 274 | /* BL33 expects to receive the primary CPU MPID (through r0) */ |
| 275 | bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); |
| 276 | bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); |
| 277 | break; |
| 278 | |
| 279 | #ifdef SCP_BL2_BASE |
| 280 | case SCP_BL2_IMAGE_ID: |
| 281 | /* The subsequent handling of SCP_BL2 is platform specific */ |
| 282 | err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); |
| 283 | if (err) { |
| 284 | WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); |
| 285 | } |
| 286 | break; |
| 287 | #endif |
| 288 | } |
| 289 | |
| 290 | return err; |
| 291 | } |
| 292 | |
| 293 | #else /* LOAD_IMAGE_V2 */ |
| 294 | |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 295 | /******************************************************************************* |
Juan Castillo | f59821d | 2015-12-10 15:49:17 +0000 | [diff] [blame] | 296 | * Populate the extents of memory available for loading SCP_BL2 (if used), |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 297 | * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2. |
| 298 | ******************************************************************************/ |
Juan Castillo | f59821d | 2015-12-10 15:49:17 +0000 | [diff] [blame] | 299 | void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 300 | { |
Juan Castillo | f59821d | 2015-12-10 15:49:17 +0000 | [diff] [blame] | 301 | *scp_bl2_meminfo = bl2_tzram_layout; |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 302 | } |
| 303 | |
| 304 | /******************************************************************************* |
Juan Castillo | d178637 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 305 | * Before calling this function BL31 is loaded in memory and its entrypoint |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 306 | * is set by load_image. This is a placeholder for the platform to change |
Juan Castillo | d178637 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 307 | * the entrypoint of BL31 and set SPSR and security state. |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 308 | * On ARM standard platforms we only set the security state of the entrypoint |
| 309 | ******************************************************************************/ |
| 310 | void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, |
| 311 | entry_point_info_t *bl31_ep_info) |
| 312 | { |
| 313 | SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); |
| 314 | bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, |
| 315 | DISABLE_ALL_EXCEPTIONS); |
| 316 | } |
| 317 | |
| 318 | |
| 319 | /******************************************************************************* |
Juan Castillo | d178637 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 320 | * Before calling this function BL32 is loaded in memory and its entrypoint |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 321 | * is set by load_image. This is a placeholder for the platform to change |
Juan Castillo | d178637 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 322 | * the entrypoint of BL32 and set SPSR and security state. |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 323 | * On ARM standard platforms we only set the security state of the entrypoint |
| 324 | ******************************************************************************/ |
Antonio Nino Diaz | 81d139d | 2016-04-05 11:38:49 +0100 | [diff] [blame] | 325 | #ifdef BL32_BASE |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 326 | void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, |
| 327 | entry_point_info_t *bl32_ep_info) |
| 328 | { |
| 329 | SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); |
| 330 | bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry(); |
| 331 | } |
| 332 | |
| 333 | /******************************************************************************* |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 334 | * Populate the extents of memory available for loading BL32 |
| 335 | ******************************************************************************/ |
| 336 | void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) |
| 337 | { |
| 338 | /* |
| 339 | * Populate the extents of memory available for loading BL32. |
| 340 | */ |
| 341 | bl32_meminfo->total_base = BL32_BASE; |
| 342 | bl32_meminfo->free_base = BL32_BASE; |
| 343 | bl32_meminfo->total_size = |
| 344 | (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; |
| 345 | bl32_meminfo->free_size = |
| 346 | (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; |
| 347 | } |
Antonio Nino Diaz | 81d139d | 2016-04-05 11:38:49 +0100 | [diff] [blame] | 348 | #endif /* BL32_BASE */ |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 349 | |
Antonio Nino Diaz | 81d139d | 2016-04-05 11:38:49 +0100 | [diff] [blame] | 350 | /******************************************************************************* |
| 351 | * Before calling this function BL33 is loaded in memory and its entrypoint |
| 352 | * is set by load_image. This is a placeholder for the platform to change |
| 353 | * the entrypoint of BL33 and set SPSR and security state. |
| 354 | * On ARM standard platforms we only set the security state of the entrypoint |
| 355 | ******************************************************************************/ |
| 356 | void bl2_plat_set_bl33_ep_info(image_info_t *image, |
| 357 | entry_point_info_t *bl33_ep_info) |
| 358 | { |
| 359 | SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); |
| 360 | bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry(); |
| 361 | } |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 362 | |
| 363 | /******************************************************************************* |
| 364 | * Populate the extents of memory available for loading BL33 |
| 365 | ******************************************************************************/ |
| 366 | void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) |
| 367 | { |
| 368 | bl33_meminfo->total_base = ARM_NS_DRAM1_BASE; |
| 369 | bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE; |
| 370 | bl33_meminfo->free_base = ARM_NS_DRAM1_BASE; |
| 371 | bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE; |
| 372 | } |
Yatharth Kochar | a8aa7fe | 2016-09-13 17:07:57 +0100 | [diff] [blame^] | 373 | |
| 374 | #endif /* LOAD_IMAGE_V2 */ |