Konstantin Porotchkin | 1e66bac | 2018-10-08 16:53:09 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2016 Marvell International Ltd. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * https://spdx.org/licenses |
| 6 | */ |
| 7 | |
Antonio Nino Diaz | c3cf06f | 2018-11-08 10:20:19 +0000 | [diff] [blame^] | 8 | #ifndef PLATFORM_DEF_H |
| 9 | #define PLATFORM_DEF_H |
Konstantin Porotchkin | 1e66bac | 2018-10-08 16:53:09 +0300 | [diff] [blame] | 10 | |
| 11 | #include <board_marvell_def.h> |
| 12 | #include <mvebu_def.h> |
| 13 | #ifndef __ASSEMBLY__ |
| 14 | #include <stdio.h> |
| 15 | #endif /* __ASSEMBLY__ */ |
| 16 | |
| 17 | /* |
| 18 | * Most platform porting definitions provided by included headers |
| 19 | */ |
| 20 | |
| 21 | /* |
| 22 | * DRAM Memory layout: |
| 23 | * +-----------------------+ |
| 24 | * : : |
| 25 | * : Linux : |
| 26 | * 0x04X00000-->+-----------------------+ |
| 27 | * | BL3-3(u-boot) |>>}>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> |
| 28 | * |-----------------------| } | |
| 29 | * | BL3-[0,1, 2] | }---------------------------------> | |
| 30 | * |-----------------------| } || | |
| 31 | * | BL2 | }->FIP (loaded by || | |
| 32 | * |-----------------------| } BootROM to DRAM) || | |
| 33 | * | FIP_TOC | } || | |
| 34 | * 0x04120000-->|-----------------------| || | |
| 35 | * | BL1 (RO) | || | |
| 36 | * 0x04100000-->+-----------------------+ || | |
| 37 | * : : || | |
| 38 | * : Trusted SRAM section : \/ | |
| 39 | * 0x04040000-->+-----------------------+ Replaced by BL2 +----------------+ | |
| 40 | * | BL1 (RW) | <<<<<<<<<<<<<<<< | BL3-1 NOBITS | | |
| 41 | * 0x04037000-->|-----------------------| <<<<<<<<<<<<<<<< |----------------| | |
| 42 | * | | <<<<<<<<<<<<<<<< | BL3-1 PROGBITS | | |
| 43 | * 0x04023000-->|-----------------------| +----------------+ | |
| 44 | * | BL2 | | |
| 45 | * |-----------------------| | |
| 46 | * | | | |
| 47 | * 0x04001000-->|-----------------------| | |
| 48 | * | Shared | | |
| 49 | * 0x04000000-->+-----------------------+ | |
| 50 | * : : | |
| 51 | * : Linux : | |
| 52 | * : : | |
| 53 | * |-----------------------| | |
| 54 | * | | U-Boot(BL3-3) Loaded by BL2 | |
| 55 | * | U-Boot | <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 56 | * 0x00000000-->+-----------------------+ |
| 57 | * |
| 58 | * Trusted SRAM section 0x4000000..0x4200000: |
| 59 | * ---------------------------------------- |
| 60 | * SRAM_BASE = 0x4001000 |
| 61 | * BL2_BASE = 0x4006000 |
| 62 | * BL2_LIMIT = BL31_BASE |
| 63 | * BL31_BASE = 0x4023000 = (64MB + 256KB - 0x1D000) |
| 64 | * BL31_PROGBITS_LIMIT = BL1_RW_BASE |
| 65 | * BL1_RW_BASE = 0x4037000 = (64MB + 256KB - 0x9000) |
| 66 | * BL1_RW_LIMIT = BL31_LIMIT = 0x4040000 |
| 67 | * |
| 68 | * |
| 69 | * PLAT_MARVELL_FIP_BASE = 0x4120000 |
| 70 | */ |
| 71 | |
| 72 | #define PLAT_MARVELL_ATF_BASE 0x4000000 |
| 73 | #define PLAT_MARVELL_ATF_LOAD_ADDR \ |
| 74 | (PLAT_MARVELL_ATF_BASE + 0x100000) |
| 75 | |
| 76 | #define PLAT_MARVELL_FIP_BASE \ |
| 77 | (PLAT_MARVELL_ATF_LOAD_ADDR + 0x20000) |
| 78 | #define PLAT_MARVELL_FIP_MAX_SIZE 0x4000000 |
| 79 | |
| 80 | #define PLAT_MARVELL_CLUSTER_CORE_COUNT 2 |
| 81 | /* DRAM[2MB..66MB] is used as Trusted ROM */ |
| 82 | #define PLAT_MARVELL_TRUSTED_ROM_BASE PLAT_MARVELL_ATF_LOAD_ADDR |
| 83 | /* 64 MB TODO: reduce this to minimum needed according to fip image size*/ |
| 84 | #define PLAT_MARVELL_TRUSTED_ROM_SIZE 0x04000000 |
| 85 | /* Reserve 16M for SCP (Secure PayLoad) Trusted DRAM */ |
| 86 | #define PLAT_MARVELL_TRUSTED_DRAM_BASE 0x04400000 |
| 87 | #define PLAT_MARVELL_TRUSTED_DRAM_SIZE 0x01000000 /* 16 MB */ |
| 88 | |
| 89 | /* |
| 90 | * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size |
| 91 | * plus a little space for growth. |
| 92 | */ |
| 93 | #define PLAT_MARVELL_MAX_BL1_RW_SIZE 0xA000 |
| 94 | |
| 95 | /* |
| 96 | * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a |
| 97 | * little space for growth. |
| 98 | */ |
| 99 | #define PLAT_MARVELL_MAX_BL2_SIZE 0xF000 |
| 100 | |
| 101 | /* |
| 102 | * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a |
| 103 | * little space for growth. |
| 104 | */ |
| 105 | #define PLAT_MARVEL_MAX_BL31_SIZE 0x5D000 |
| 106 | |
| 107 | #define PLAT_MARVELL_CPU_ENTRY_ADDR BL1_RO_BASE |
| 108 | |
| 109 | /* GIC related definitions */ |
| 110 | #define PLAT_MARVELL_GICD_BASE (MVEBU_REGS_BASE + MVEBU_GICD_BASE) |
| 111 | #define PLAT_MARVELL_GICR_BASE (MVEBU_REGS_BASE + MVEBU_GICR_BASE) |
| 112 | #define PLAT_MARVELL_GICC_BASE (MVEBU_REGS_BASE + MVEBU_GICC_BASE) |
| 113 | |
| 114 | #define PLAT_MARVELL_G0_IRQ_PROPS(grp) \ |
| 115 | INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 116 | GIC_INTR_CFG_LEVEL), \ |
| 117 | INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 118 | GIC_INTR_CFG_LEVEL) |
| 119 | |
| 120 | #define PLAT_MARVELL_G1S_IRQ_PROPS(grp) \ |
| 121 | INTR_PROP_DESC(MARVELL_IRQ_SEC_PHY_TIMER, \ |
| 122 | GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ |
| 123 | INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 124 | GIC_INTR_CFG_LEVEL), \ |
| 125 | INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 126 | GIC_INTR_CFG_LEVEL), \ |
| 127 | INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 128 | GIC_INTR_CFG_LEVEL), \ |
| 129 | INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 130 | GIC_INTR_CFG_LEVEL), \ |
| 131 | INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 132 | GIC_INTR_CFG_LEVEL), \ |
| 133 | INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 134 | GIC_INTR_CFG_LEVEL) |
| 135 | |
| 136 | |
| 137 | #define PLAT_MARVELL_SHARED_RAM_CACHED 1 |
| 138 | |
| 139 | /* CCI related constants */ |
| 140 | #define PLAT_MARVELL_CCI_BASE (MVEBU_REGS_BASE + MVEBU_CCI_BASE) |
| 141 | #define PLAT_MARVELL_CCI_CLUSTER0_SL_IFACE_IX 3 |
| 142 | #define PLAT_MARVELL_CCI_CLUSTER1_SL_IFACE_IX 4 |
| 143 | |
| 144 | /* |
| 145 | * Load address of BL3-3 for this platform port |
| 146 | */ |
| 147 | #define PLAT_MARVELL_NS_IMAGE_OFFSET 0x0 |
| 148 | |
| 149 | /* System Reference Clock*/ |
| 150 | #define PLAT_REF_CLK_IN_HZ COUNTER_FREQUENCY |
| 151 | |
| 152 | /* |
| 153 | * PL011 related constants |
| 154 | */ |
| 155 | #define PLAT_MARVELL_BOOT_UART_BASE (MVEBU_REGS_BASE + 0x12000) |
| 156 | #define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 25804800 |
| 157 | |
| 158 | #define PLAT_MARVELL_CRASH_UART_BASE PLAT_MARVELL_BOOT_UART_BASE |
| 159 | #define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ |
| 160 | |
| 161 | #define PLAT_MARVELL_BL31_RUN_UART_BASE PLAT_MARVELL_BOOT_UART_BASE |
| 162 | #define PLAT_MARVELL_BL31_RUN_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ |
| 163 | |
| 164 | /* Required platform porting definitions */ |
| 165 | #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 |
| 166 | |
| 167 | /* System timer related constants */ |
| 168 | #define PLAT_MARVELL_NSTIMER_FRAME_ID 1 |
| 169 | |
| 170 | /* Mailbox base address */ |
| 171 | #define PLAT_MARVELL_MAILBOX_BASE \ |
| 172 | (MARVELL_TRUSTED_SRAM_BASE + 0x400) |
| 173 | #define PLAT_MARVELL_MAILBOX_SIZE 0x100 |
| 174 | #define PLAT_MARVELL_MAILBOX_MAGIC_NUM 0x6D72766C /* mrvl */ |
| 175 | |
| 176 | /* DRAM CS memory map registers related constants */ |
| 177 | #define MVEBU_CS_MMAP_LOW(cs_num) \ |
| 178 | (MVEBU_CS_MMAP_REG_BASE + (cs_num) * 0x8) |
| 179 | #define MVEBU_CS_MMAP_ENABLE 0x1 |
| 180 | #define MVEBU_CS_MMAP_AREA_LEN_OFFS 16 |
| 181 | #define MVEBU_CS_MMAP_AREA_LEN_MASK \ |
| 182 | (0x1f << MVEBU_CS_MMAP_AREA_LEN_OFFS) |
| 183 | #define MVEBU_CS_MMAP_START_ADDR_LOW_OFFS 23 |
| 184 | #define MVEBU_CS_MMAP_START_ADDR_LOW_MASK \ |
| 185 | (0x1ff << MVEBU_CS_MMAP_START_ADDR_LOW_OFFS) |
| 186 | |
| 187 | #define MVEBU_CS_MMAP_HIGH(cs_num) \ |
| 188 | (MVEBU_CS_MMAP_REG_BASE + 0x4 + (cs_num) * 0x8) |
| 189 | |
| 190 | /* DRAM max CS number */ |
| 191 | #define MVEBU_MAX_CS_MMAP_NUM (2) |
| 192 | |
| 193 | /* CPU decoder window related constants */ |
| 194 | #define CPU_DEC_WIN_CTRL_REG(win_num) \ |
| 195 | (MVEBU_CPU_DEC_WIN_REG_BASE + (win_num) * 0x10) |
| 196 | #define CPU_DEC_CR_WIN_ENABLE 0x1 |
| 197 | #define CPU_DEC_CR_WIN_TARGET_OFFS 4 |
| 198 | #define CPU_DEC_CR_WIN_TARGET_MASK \ |
| 199 | (0xf << CPU_DEC_CR_WIN_TARGET_OFFS) |
| 200 | |
| 201 | #define CPU_DEC_WIN_SIZE_REG(win_num) \ |
| 202 | (MVEBU_CPU_DEC_WIN_REG_BASE + 0x4 + (win_num) * 0x10) |
| 203 | #define CPU_DEC_CR_WIN_SIZE_OFFS 0 |
| 204 | #define CPU_DEC_CR_WIN_SIZE_MASK \ |
| 205 | (0xffff << CPU_DEC_CR_WIN_SIZE_OFFS) |
| 206 | #define CPU_DEC_CR_WIN_SIZE_ALIGNMENT 0x10000 |
| 207 | |
| 208 | #define CPU_DEC_WIN_BASE_REG(win_num) \ |
| 209 | (MVEBU_CPU_DEC_WIN_REG_BASE + 0x8 + (win_num) * 0x10) |
| 210 | #define CPU_DEC_BR_BASE_OFFS 0 |
| 211 | #define CPU_DEC_BR_BASE_MASK \ |
| 212 | (0xffff << CPU_DEC_BR_BASE_OFFS) |
| 213 | |
| 214 | #define CPU_DEC_REMAP_LOW_REG(win_num) \ |
| 215 | (MVEBU_CPU_DEC_WIN_REG_BASE + 0xC + (win_num) * 0x10) |
| 216 | #define CPU_DEC_RLR_REMAP_LOW_OFFS 0 |
| 217 | #define CPU_DEC_RLR_REMAP_LOW_MASK \ |
| 218 | (0xffff << CPU_DEC_BR_BASE_OFFS) |
| 219 | |
| 220 | /* Securities */ |
| 221 | #define IRQ_SEC_OS_TICK_INT MARVELL_IRQ_SEC_PHY_TIMER |
| 222 | |
| 223 | #define TRUSTED_DRAM_BASE PLAT_MARVELL_TRUSTED_DRAM_BASE |
| 224 | #define TRUSTED_DRAM_SIZE PLAT_MARVELL_TRUSTED_DRAM_SIZE |
| 225 | |
| 226 | #ifdef BL32 |
| 227 | #define BL32_BASE TRUSTED_DRAM_BASE |
| 228 | #define BL32_LIMIT TRUSTED_DRAM_SIZE |
| 229 | #endif |
| 230 | |
Antonio Nino Diaz | c3cf06f | 2018-11-08 10:20:19 +0000 | [diff] [blame^] | 231 | #endif /* PLATFORM_DEF_H */ |