Soby Mathew | 464ce2b | 2015-10-07 09:45:27 +0100 | [diff] [blame] | 1 | /* |
Soby Mathew | 311b177 | 2017-02-14 10:11:52 +0000 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Soby Mathew | 464ce2b | 2015-10-07 09:45:27 +0100 | [diff] [blame] | 3 | * |
dp-arm | 82cb2c1 | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Soby Mathew | 464ce2b | 2015-10-07 09:45:27 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <arch_helpers.h> |
| 9 | #include <assert.h> |
| 10 | #include <debug.h> |
| 11 | #include <gic_common.h> |
| 12 | #include <gicv2.h> |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame^] | 13 | #include <interrupt_props.h> |
Jeenu Viswambharan | 74dce7f | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 14 | #include <spinlock.h> |
Soby Mathew | e9ec3ce | 2016-02-01 17:59:22 +0000 | [diff] [blame] | 15 | #include "../common/gic_common_private.h" |
Soby Mathew | 464ce2b | 2015-10-07 09:45:27 +0100 | [diff] [blame] | 16 | #include "gicv2_private.h" |
| 17 | |
| 18 | static const gicv2_driver_data_t *driver_data; |
| 19 | |
Jeenu Viswambharan | 74dce7f | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 20 | /* |
| 21 | * Spinlock to guard registers needing read-modify-write. APIs protected by this |
| 22 | * spinlock are used either at boot time (when only a single CPU is active), or |
| 23 | * when the system is fully coherent. |
| 24 | */ |
| 25 | spinlock_t gic_lock; |
| 26 | |
Soby Mathew | 464ce2b | 2015-10-07 09:45:27 +0100 | [diff] [blame] | 27 | /******************************************************************************* |
| 28 | * Enable secure interrupts and use FIQs to route them. Disable legacy bypass |
| 29 | * and set the priority mask register to allow all interrupts to trickle in. |
| 30 | ******************************************************************************/ |
| 31 | void gicv2_cpuif_enable(void) |
| 32 | { |
| 33 | unsigned int val; |
| 34 | |
| 35 | assert(driver_data); |
| 36 | assert(driver_data->gicc_base); |
| 37 | |
| 38 | /* |
| 39 | * Enable the Group 0 interrupts, FIQEn and disable Group 0/1 |
| 40 | * bypass. |
| 41 | */ |
| 42 | val = CTLR_ENABLE_G0_BIT | FIQ_EN_BIT | FIQ_BYP_DIS_GRP0; |
| 43 | val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; |
| 44 | |
| 45 | /* Program the idle priority in the PMR */ |
| 46 | gicc_write_pmr(driver_data->gicc_base, GIC_PRI_MASK); |
| 47 | gicc_write_ctlr(driver_data->gicc_base, val); |
| 48 | } |
| 49 | |
| 50 | /******************************************************************************* |
| 51 | * Place the cpu interface in a state where it can never make a cpu exit wfi as |
| 52 | * as result of an asserted interrupt. This is critical for powering down a cpu |
| 53 | ******************************************************************************/ |
| 54 | void gicv2_cpuif_disable(void) |
| 55 | { |
| 56 | unsigned int val; |
| 57 | |
| 58 | assert(driver_data); |
| 59 | assert(driver_data->gicc_base); |
| 60 | |
| 61 | /* Disable secure, non-secure interrupts and disable their bypass */ |
| 62 | val = gicc_read_ctlr(driver_data->gicc_base); |
| 63 | val &= ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT); |
| 64 | val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; |
| 65 | val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; |
| 66 | gicc_write_ctlr(driver_data->gicc_base, val); |
| 67 | } |
| 68 | |
| 69 | /******************************************************************************* |
| 70 | * Per cpu gic distributor setup which will be done by all cpus after a cold |
| 71 | * boot/hotplug. This marks out the secure SPIs and PPIs & enables them. |
| 72 | ******************************************************************************/ |
| 73 | void gicv2_pcpu_distif_init(void) |
| 74 | { |
| 75 | assert(driver_data); |
| 76 | assert(driver_data->gicd_base); |
Soby Mathew | 464ce2b | 2015-10-07 09:45:27 +0100 | [diff] [blame] | 77 | |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame^] | 78 | #if !ERROR_DEPRECATED |
| 79 | if (driver_data->interrupt_props != NULL) { |
| 80 | #endif |
| 81 | gicv2_secure_ppi_sgi_setup_props(driver_data->gicd_base, |
| 82 | driver_data->interrupt_props, |
| 83 | driver_data->interrupt_props_num); |
| 84 | #if !ERROR_DEPRECATED |
| 85 | } else { |
| 86 | assert(driver_data->g0_interrupt_array); |
| 87 | gicv2_secure_ppi_sgi_setup(driver_data->gicd_base, |
| 88 | driver_data->g0_interrupt_num, |
| 89 | driver_data->g0_interrupt_array); |
| 90 | } |
| 91 | #endif |
Soby Mathew | 464ce2b | 2015-10-07 09:45:27 +0100 | [diff] [blame] | 92 | } |
| 93 | |
| 94 | /******************************************************************************* |
| 95 | * Global gic distributor init which will be done by the primary cpu after a |
| 96 | * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It |
| 97 | * then enables the secure GIC distributor interface. |
| 98 | ******************************************************************************/ |
| 99 | void gicv2_distif_init(void) |
| 100 | { |
| 101 | unsigned int ctlr; |
| 102 | |
| 103 | assert(driver_data); |
| 104 | assert(driver_data->gicd_base); |
Soby Mathew | 464ce2b | 2015-10-07 09:45:27 +0100 | [diff] [blame] | 105 | |
| 106 | /* Disable the distributor before going further */ |
| 107 | ctlr = gicd_read_ctlr(driver_data->gicd_base); |
| 108 | gicd_write_ctlr(driver_data->gicd_base, |
| 109 | ctlr & ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT)); |
| 110 | |
| 111 | /* Set the default attribute of all SPIs */ |
| 112 | gicv2_spis_configure_defaults(driver_data->gicd_base); |
| 113 | |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame^] | 114 | #if !ERROR_DEPRECATED |
| 115 | if (driver_data->interrupt_props != NULL) { |
| 116 | #endif |
| 117 | gicv2_secure_spis_configure_props(driver_data->gicd_base, |
| 118 | driver_data->interrupt_props, |
| 119 | driver_data->interrupt_props_num); |
| 120 | #if !ERROR_DEPRECATED |
| 121 | } else { |
| 122 | assert(driver_data->g0_interrupt_array); |
| 123 | |
| 124 | /* Configure the G0 SPIs */ |
| 125 | gicv2_secure_spis_configure(driver_data->gicd_base, |
| 126 | driver_data->g0_interrupt_num, |
| 127 | driver_data->g0_interrupt_array); |
| 128 | } |
| 129 | #endif |
Soby Mathew | 464ce2b | 2015-10-07 09:45:27 +0100 | [diff] [blame] | 130 | |
| 131 | /* Re-enable the secure SPIs now that they have been configured */ |
| 132 | gicd_write_ctlr(driver_data->gicd_base, ctlr | CTLR_ENABLE_G0_BIT); |
| 133 | } |
| 134 | |
| 135 | /******************************************************************************* |
| 136 | * Initialize the ARM GICv2 driver with the provided platform inputs |
| 137 | ******************************************************************************/ |
| 138 | void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data) |
| 139 | { |
| 140 | unsigned int gic_version; |
| 141 | assert(plat_driver_data); |
| 142 | assert(plat_driver_data->gicd_base); |
| 143 | assert(plat_driver_data->gicc_base); |
| 144 | |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame^] | 145 | #if !ERROR_DEPRECATED |
| 146 | if (plat_driver_data->interrupt_props == NULL) { |
| 147 | /* Interrupt properties array size must be 0 */ |
| 148 | assert(plat_driver_data->interrupt_props_num == 0); |
Soby Mathew | 464ce2b | 2015-10-07 09:45:27 +0100 | [diff] [blame] | 149 | |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame^] | 150 | /* The platform should provide a list of secure interrupts */ |
| 151 | assert(plat_driver_data->g0_interrupt_array); |
| 152 | |
| 153 | /* |
| 154 | * If there are no interrupts of a particular type, then the |
| 155 | * number of interrupts of that type should be 0 and vice-versa. |
| 156 | */ |
| 157 | assert(plat_driver_data->g0_interrupt_array ? |
| 158 | plat_driver_data->g0_interrupt_num : |
| 159 | plat_driver_data->g0_interrupt_num == 0); |
| 160 | } |
| 161 | #else |
| 162 | assert(plat_driver_data->interrupt_props != NULL); |
| 163 | assert(plat_driver_data->interrupt_props_num > 0); |
| 164 | #endif |
Soby Mathew | 464ce2b | 2015-10-07 09:45:27 +0100 | [diff] [blame] | 165 | |
| 166 | /* Ensure that this is a GICv2 system */ |
| 167 | gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); |
| 168 | gic_version = (gic_version >> PIDR2_ARCH_REV_SHIFT) |
| 169 | & PIDR2_ARCH_REV_MASK; |
| 170 | assert(gic_version == ARCH_REV_GICV2); |
| 171 | |
| 172 | driver_data = plat_driver_data; |
| 173 | |
Soby Mathew | 311b177 | 2017-02-14 10:11:52 +0000 | [diff] [blame] | 174 | /* |
| 175 | * The GIC driver data is initialized by the primary CPU with caches |
| 176 | * enabled. When the secondary CPU boots up, it initializes the |
| 177 | * GICC/GICR interface with the caches disabled. Hence flush the |
| 178 | * driver_data to ensure coherency. This is not required if the |
| 179 | * platform has HW_ASSISTED_COHERENCY enabled. |
| 180 | */ |
| 181 | #if !HW_ASSISTED_COHERENCY |
| 182 | flush_dcache_range((uintptr_t) &driver_data, sizeof(driver_data)); |
| 183 | flush_dcache_range((uintptr_t) driver_data, sizeof(*driver_data)); |
| 184 | #endif |
Soby Mathew | 464ce2b | 2015-10-07 09:45:27 +0100 | [diff] [blame] | 185 | INFO("ARM GICv2 driver initialized\n"); |
| 186 | } |
| 187 | |
| 188 | /****************************************************************************** |
| 189 | * This function returns whether FIQ is enabled in the GIC CPU interface. |
| 190 | *****************************************************************************/ |
| 191 | unsigned int gicv2_is_fiq_enabled(void) |
| 192 | { |
| 193 | unsigned int gicc_ctlr; |
| 194 | |
| 195 | assert(driver_data); |
| 196 | assert(driver_data->gicc_base); |
| 197 | |
| 198 | gicc_ctlr = gicc_read_ctlr(driver_data->gicc_base); |
| 199 | return (gicc_ctlr >> FIQ_EN_SHIFT) & 0x1; |
| 200 | } |
| 201 | |
| 202 | /******************************************************************************* |
| 203 | * This function returns the type of the highest priority pending interrupt at |
| 204 | * the GIC cpu interface. The return values can be one of the following : |
| 205 | * PENDING_G1_INTID : The interrupt type is non secure Group 1. |
| 206 | * 0 - 1019 : The interrupt type is secure Group 0. |
| 207 | * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with |
| 208 | * sufficient priority to be signaled |
| 209 | ******************************************************************************/ |
| 210 | unsigned int gicv2_get_pending_interrupt_type(void) |
| 211 | { |
| 212 | assert(driver_data); |
| 213 | assert(driver_data->gicc_base); |
| 214 | |
| 215 | return gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK; |
| 216 | } |
| 217 | |
| 218 | /******************************************************************************* |
| 219 | * This function returns the id of the highest priority pending interrupt at |
| 220 | * the GIC cpu interface. GIC_SPURIOUS_INTERRUPT is returned when there is no |
| 221 | * interrupt pending. |
| 222 | ******************************************************************************/ |
| 223 | unsigned int gicv2_get_pending_interrupt_id(void) |
| 224 | { |
| 225 | unsigned int id; |
| 226 | |
| 227 | assert(driver_data); |
| 228 | assert(driver_data->gicc_base); |
| 229 | |
| 230 | id = gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK; |
| 231 | |
| 232 | /* |
| 233 | * Find out which non-secure interrupt it is under the assumption that |
| 234 | * the GICC_CTLR.AckCtl bit is 0. |
| 235 | */ |
| 236 | if (id == PENDING_G1_INTID) |
| 237 | id = gicc_read_ahppir(driver_data->gicc_base) & INT_ID_MASK; |
| 238 | |
| 239 | return id; |
| 240 | } |
| 241 | |
| 242 | /******************************************************************************* |
| 243 | * This functions reads the GIC cpu interface Interrupt Acknowledge register |
| 244 | * to start handling the pending secure 0 interrupt. It returns the |
| 245 | * contents of the IAR. |
| 246 | ******************************************************************************/ |
| 247 | unsigned int gicv2_acknowledge_interrupt(void) |
| 248 | { |
| 249 | assert(driver_data); |
| 250 | assert(driver_data->gicc_base); |
| 251 | |
| 252 | return gicc_read_IAR(driver_data->gicc_base); |
| 253 | } |
| 254 | |
| 255 | /******************************************************************************* |
| 256 | * This functions writes the GIC cpu interface End Of Interrupt register with |
| 257 | * the passed value to finish handling the active secure group 0 interrupt. |
| 258 | ******************************************************************************/ |
| 259 | void gicv2_end_of_interrupt(unsigned int id) |
| 260 | { |
| 261 | assert(driver_data); |
| 262 | assert(driver_data->gicc_base); |
| 263 | |
| 264 | gicc_write_EOIR(driver_data->gicc_base, id); |
| 265 | } |
| 266 | |
| 267 | /******************************************************************************* |
| 268 | * This function returns the type of the interrupt id depending upon the group |
| 269 | * this interrupt has been configured under by the interrupt controller i.e. |
| 270 | * group0 secure or group1 non secure. It returns zero for Group 0 secure and |
| 271 | * one for Group 1 non secure interrupt. |
| 272 | ******************************************************************************/ |
| 273 | unsigned int gicv2_get_interrupt_group(unsigned int id) |
| 274 | { |
| 275 | assert(driver_data); |
| 276 | assert(driver_data->gicd_base); |
| 277 | |
| 278 | return gicd_get_igroupr(driver_data->gicd_base, id); |
| 279 | } |
Jeenu Viswambharan | eb68ea9 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 280 | |
| 281 | /******************************************************************************* |
| 282 | * This function returns the priority of the interrupt the processor is |
| 283 | * currently servicing. |
| 284 | ******************************************************************************/ |
| 285 | unsigned int gicv2_get_running_priority(void) |
| 286 | { |
| 287 | assert(driver_data); |
| 288 | assert(driver_data->gicc_base); |
| 289 | |
| 290 | return gicc_read_rpr(driver_data->gicc_base); |
| 291 | } |
Jeenu Viswambharan | fa9db42 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 292 | |
| 293 | /******************************************************************************* |
| 294 | * This function sets the GICv2 target mask pattern for the current PE. The PE |
| 295 | * target mask is used to translate linear PE index (returned by platform core |
| 296 | * position) to a bit mask used when targeting interrupts to a PE, viz. when |
| 297 | * raising SGIs and routing SPIs. |
| 298 | ******************************************************************************/ |
| 299 | void gicv2_set_pe_target_mask(unsigned int proc_num) |
| 300 | { |
| 301 | assert(driver_data); |
| 302 | assert(driver_data->gicd_base); |
| 303 | assert(driver_data->target_masks); |
| 304 | assert(proc_num < GICV2_MAX_TARGET_PE); |
| 305 | assert(proc_num < driver_data->target_masks_num); |
| 306 | |
| 307 | /* Return if the target mask is already populated */ |
| 308 | if (driver_data->target_masks[proc_num]) |
| 309 | return; |
| 310 | |
| 311 | /* Read target register corresponding to this CPU */ |
| 312 | driver_data->target_masks[proc_num] = |
| 313 | gicv2_get_cpuif_id(driver_data->gicd_base); |
| 314 | } |
Jeenu Viswambharan | cbd3f37 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 315 | |
| 316 | /******************************************************************************* |
| 317 | * This function returns the active status of the interrupt (either because the |
| 318 | * state is active, or active and pending). |
| 319 | ******************************************************************************/ |
| 320 | unsigned int gicv2_get_interrupt_active(unsigned int id) |
| 321 | { |
| 322 | assert(driver_data); |
| 323 | assert(driver_data->gicd_base); |
| 324 | assert(id <= MAX_SPI_ID); |
| 325 | |
| 326 | return gicd_get_isactiver(driver_data->gicd_base, id); |
| 327 | } |
Jeenu Viswambharan | 979225f | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 328 | |
| 329 | /******************************************************************************* |
| 330 | * This function enables the interrupt identified by id. |
| 331 | ******************************************************************************/ |
| 332 | void gicv2_enable_interrupt(unsigned int id) |
| 333 | { |
| 334 | assert(driver_data); |
| 335 | assert(driver_data->gicd_base); |
| 336 | assert(id <= MAX_SPI_ID); |
| 337 | |
| 338 | /* |
| 339 | * Ensure that any shared variable updates depending on out of band |
| 340 | * interrupt trigger are observed before enabling interrupt. |
| 341 | */ |
| 342 | dsbishst(); |
| 343 | gicd_set_isenabler(driver_data->gicd_base, id); |
| 344 | } |
| 345 | |
| 346 | /******************************************************************************* |
| 347 | * This function disables the interrupt identified by id. |
| 348 | ******************************************************************************/ |
| 349 | void gicv2_disable_interrupt(unsigned int id) |
| 350 | { |
| 351 | assert(driver_data); |
| 352 | assert(driver_data->gicd_base); |
| 353 | assert(id <= MAX_SPI_ID); |
| 354 | |
| 355 | /* |
| 356 | * Disable interrupt, and ensure that any shared variable updates |
| 357 | * depending on out of band interrupt trigger are observed afterwards. |
| 358 | */ |
| 359 | gicd_set_icenabler(driver_data->gicd_base, id); |
| 360 | dsbishst(); |
| 361 | } |
Jeenu Viswambharan | f3a8660 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 362 | |
| 363 | /******************************************************************************* |
| 364 | * This function sets the interrupt priority as supplied for the given interrupt |
| 365 | * id. |
| 366 | ******************************************************************************/ |
| 367 | void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority) |
| 368 | { |
| 369 | assert(driver_data); |
| 370 | assert(driver_data->gicd_base); |
| 371 | assert(id <= MAX_SPI_ID); |
| 372 | |
| 373 | gicd_set_ipriorityr(driver_data->gicd_base, id, priority); |
| 374 | } |
Jeenu Viswambharan | 74dce7f | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 375 | |
| 376 | /******************************************************************************* |
| 377 | * This function assigns group for the interrupt identified by id. The group can |
| 378 | * be any of GICV2_INTR_GROUP* |
| 379 | ******************************************************************************/ |
| 380 | void gicv2_set_interrupt_type(unsigned int id, unsigned int type) |
| 381 | { |
| 382 | assert(driver_data); |
| 383 | assert(driver_data->gicd_base); |
| 384 | assert(id <= MAX_SPI_ID); |
| 385 | |
| 386 | /* Serialize read-modify-write to Distributor registers */ |
| 387 | spin_lock(&gic_lock); |
| 388 | switch (type) { |
| 389 | case GICV2_INTR_GROUP1: |
| 390 | gicd_set_igroupr(driver_data->gicd_base, id); |
| 391 | break; |
| 392 | case GICV2_INTR_GROUP0: |
| 393 | gicd_clr_igroupr(driver_data->gicd_base, id); |
| 394 | break; |
| 395 | default: |
| 396 | assert(0); |
| 397 | } |
| 398 | spin_unlock(&gic_lock); |
| 399 | } |
Jeenu Viswambharan | 8db978b | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 400 | |
| 401 | /******************************************************************************* |
| 402 | * This function raises the specified SGI to requested targets. |
| 403 | * |
| 404 | * The proc_num parameter must be the linear index of the target PE in the |
| 405 | * system. |
| 406 | ******************************************************************************/ |
| 407 | void gicv2_raise_sgi(int sgi_num, int proc_num) |
| 408 | { |
| 409 | unsigned int sgir_val, target; |
| 410 | |
| 411 | assert(driver_data); |
| 412 | assert(proc_num < GICV2_MAX_TARGET_PE); |
| 413 | assert(driver_data->gicd_base); |
| 414 | |
| 415 | /* |
| 416 | * Target masks array must have been supplied, and the core position |
| 417 | * should be valid. |
| 418 | */ |
| 419 | assert(driver_data->target_masks); |
| 420 | assert(proc_num < driver_data->target_masks_num); |
| 421 | |
| 422 | /* Don't raise SGI if the mask hasn't been populated */ |
| 423 | target = driver_data->target_masks[proc_num]; |
| 424 | assert(target != 0); |
| 425 | |
| 426 | sgir_val = GICV2_SGIR_VALUE(SGIR_TGT_SPECIFIC, target, sgi_num); |
| 427 | |
| 428 | /* |
| 429 | * Ensure that any shared variable updates depending on out of band |
| 430 | * interrupt trigger are observed before raising SGI. |
| 431 | */ |
| 432 | dsbishst(); |
| 433 | gicd_write_sgir(driver_data->gicd_base, sgir_val); |
| 434 | } |
Jeenu Viswambharan | fc529fe | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 435 | |
| 436 | /******************************************************************************* |
| 437 | * This function sets the interrupt routing for the given SPI interrupt id. |
| 438 | * The interrupt routing is specified in routing mode. The proc_num parameter is |
| 439 | * linear index of the PE to target SPI. When proc_num < 0, the SPI may target |
| 440 | * all PEs. |
| 441 | ******************************************************************************/ |
| 442 | void gicv2_set_spi_routing(unsigned int id, int proc_num) |
| 443 | { |
| 444 | int target; |
| 445 | |
| 446 | assert(driver_data); |
| 447 | assert(driver_data->gicd_base); |
| 448 | |
| 449 | assert(id >= MIN_SPI_ID && id <= MAX_SPI_ID); |
| 450 | |
| 451 | /* |
| 452 | * Target masks array must have been supplied, and the core position |
| 453 | * should be valid. |
| 454 | */ |
| 455 | assert(driver_data->target_masks); |
| 456 | assert(proc_num < GICV2_MAX_TARGET_PE); |
| 457 | assert(proc_num < driver_data->target_masks_num); |
| 458 | |
| 459 | if (proc_num < 0) { |
| 460 | /* Target all PEs */ |
| 461 | target = GIC_TARGET_CPU_MASK; |
| 462 | } else { |
| 463 | /* Don't route interrupt if the mask hasn't been populated */ |
| 464 | target = driver_data->target_masks[proc_num]; |
| 465 | assert(target != 0); |
| 466 | } |
| 467 | |
| 468 | gicd_set_itargetsr(driver_data->gicd_base, id, target); |
| 469 | } |
Jeenu Viswambharan | a2816a1 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 470 | |
| 471 | /******************************************************************************* |
| 472 | * This function clears the pending status of an interrupt identified by id. |
| 473 | ******************************************************************************/ |
| 474 | void gicv2_clear_interrupt_pending(unsigned int id) |
| 475 | { |
| 476 | assert(driver_data); |
| 477 | assert(driver_data->gicd_base); |
| 478 | |
| 479 | /* SGIs can't be cleared pending */ |
| 480 | assert(id >= MIN_PPI_ID); |
| 481 | |
| 482 | /* |
| 483 | * Clear pending interrupt, and ensure that any shared variable updates |
| 484 | * depending on out of band interrupt trigger are observed afterwards. |
| 485 | */ |
| 486 | gicd_set_icpendr(driver_data->gicd_base, id); |
| 487 | dsbishst(); |
| 488 | } |
| 489 | |
| 490 | /******************************************************************************* |
| 491 | * This function sets the pending status of an interrupt identified by id. |
| 492 | ******************************************************************************/ |
| 493 | void gicv2_set_interrupt_pending(unsigned int id) |
| 494 | { |
| 495 | assert(driver_data); |
| 496 | assert(driver_data->gicd_base); |
| 497 | |
| 498 | /* SGIs can't be cleared pending */ |
| 499 | assert(id >= MIN_PPI_ID); |
| 500 | |
| 501 | /* |
| 502 | * Ensure that any shared variable updates depending on out of band |
| 503 | * interrupt trigger are observed before setting interrupt pending. |
| 504 | */ |
| 505 | dsbishst(); |
| 506 | gicd_set_ispendr(driver_data->gicd_base, id); |
| 507 | } |
Jeenu Viswambharan | d55a445 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 508 | |
| 509 | /******************************************************************************* |
| 510 | * This function sets the PMR register with the supplied value. Returns the |
| 511 | * original PMR. |
| 512 | ******************************************************************************/ |
| 513 | unsigned int gicv2_set_pmr(unsigned int mask) |
| 514 | { |
| 515 | unsigned int old_mask; |
| 516 | |
| 517 | assert(driver_data); |
| 518 | assert(driver_data->gicc_base); |
| 519 | |
| 520 | old_mask = gicc_read_pmr(driver_data->gicc_base); |
| 521 | |
| 522 | /* |
| 523 | * Order memory updates w.r.t. PMR write, and ensure they're visible |
| 524 | * before potential out of band interrupt trigger because of PMR update. |
| 525 | */ |
| 526 | dmbishst(); |
| 527 | gicc_write_pmr(driver_data->gicc_base, mask); |
| 528 | dsbishst(); |
| 529 | |
| 530 | return old_mask; |
| 531 | } |