Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
Jimmy Brisson | 831b0e9 | 2020-08-05 13:44:05 -0500 | [diff] [blame] | 2 | * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | e44f86e | 2018-05-17 10:10:25 -0700 | [diff] [blame] | 3 | * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 4 | * |
dp-arm | 82cb2c1 | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 5 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 6 | */ |
| 7 | |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 8 | #include <assert.h> |
Antonio Nino Diaz | 09d40e0 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 10 | #include <platform_def.h> |
Antonio Nino Diaz | 09d40e0 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 11 | |
| 12 | #include <arch_helpers.h> |
| 13 | #include <common/bl_common.h> |
| 14 | #include <common/debug.h> |
| 15 | #include <context.h> |
| 16 | #include <drivers/console.h> |
| 17 | #include <lib/el3_runtime/context_mgmt.h> |
| 18 | #include <lib/mmio.h> |
| 19 | #include <lib/psci/psci.h> |
| 20 | #include <plat/common/platform.h> |
| 21 | |
| 22 | #include <memctrl.h> |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 23 | #include <pmc.h> |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 24 | #include <tegra_def.h> |
Harvey Hsieh | 322e7c3 | 2017-04-10 16:20:32 +0800 | [diff] [blame] | 25 | #include <tegra_platform.h> |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 26 | #include <tegra_private.h> |
| 27 | |
| 28 | extern uint64_t tegra_bl31_phys_base; |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 29 | extern uint64_t tegra_sec_entry_point; |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 30 | |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 31 | /******************************************************************************* |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 32 | * This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND` |
| 33 | * call to get the `power_state` parameter. This allows the platform to encode |
| 34 | * the appropriate State-ID field within the `power_state` parameter which can |
| 35 | * be utilized in `pwr_domain_suspend()` to suspend to system affinity level. |
| 36 | ******************************************************************************/ |
David Pu | 57e92da | 2019-08-08 14:20:03 -0700 | [diff] [blame] | 37 | static void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state) |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 38 | { |
Varun Wadekar | a7cd095 | 2016-06-07 12:00:06 -0700 | [diff] [blame] | 39 | /* all affinities use system suspend state id */ |
Anthony Zhou | b36aea5 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 40 | for (uint32_t i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) { |
Varun Wadekar | a7cd095 | 2016-06-07 12:00:06 -0700 | [diff] [blame] | 41 | req_state->pwr_domain_state[i] = PSTATE_ID_SOC_POWERDN; |
Anthony Zhou | b36aea5 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 42 | } |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 43 | } |
| 44 | |
| 45 | /******************************************************************************* |
| 46 | * Handler called when an affinity instance is about to enter standby. |
| 47 | ******************************************************************************/ |
David Pu | 57e92da | 2019-08-08 14:20:03 -0700 | [diff] [blame] | 48 | static void tegra_cpu_standby(plat_local_state_t cpu_state) |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 49 | { |
Vignesh Radhakrishnan | 07faf4d | 2018-04-20 14:31:41 -0700 | [diff] [blame] | 50 | u_register_t saved_scr_el3; |
| 51 | |
Anthony Zhou | b36aea5 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 52 | (void)cpu_state; |
| 53 | |
Varun Wadekar | 0887026 | 2017-12-27 18:10:12 -0800 | [diff] [blame] | 54 | /* Tegra SoC specific handler */ |
| 55 | if (tegra_soc_cpu_standby(cpu_state) != PSCI_E_SUCCESS) |
| 56 | ERROR("%s failed\n", __func__); |
| 57 | |
Vignesh Radhakrishnan | 07faf4d | 2018-04-20 14:31:41 -0700 | [diff] [blame] | 58 | saved_scr_el3 = read_scr_el3(); |
| 59 | |
| 60 | /* |
| 61 | * As per ARM ARM D1.17.2, any physical IRQ interrupt received by the |
| 62 | * PE will be treated as a wake-up event, if SCR_EL3.IRQ is set to '1', |
| 63 | * irrespective of the value of the PSTATE.I bit value. |
| 64 | */ |
| 65 | write_scr_el3(saved_scr_el3 | SCR_IRQ_BIT); |
| 66 | |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 67 | /* |
| 68 | * Enter standby state |
Vignesh Radhakrishnan | 07faf4d | 2018-04-20 14:31:41 -0700 | [diff] [blame] | 69 | * |
| 70 | * dsb & isb is good practice before using wfi to enter low power states |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 71 | */ |
| 72 | dsb(); |
Vignesh Radhakrishnan | 07faf4d | 2018-04-20 14:31:41 -0700 | [diff] [blame] | 73 | isb(); |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 74 | wfi(); |
Vignesh Radhakrishnan | 07faf4d | 2018-04-20 14:31:41 -0700 | [diff] [blame] | 75 | |
| 76 | /* |
| 77 | * Restore saved scr_el3 that has IRQ bit cleared as we don't want EL3 |
| 78 | * handling any further interrupts |
| 79 | */ |
| 80 | write_scr_el3(saved_scr_el3); |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 81 | } |
| 82 | |
| 83 | /******************************************************************************* |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 84 | * Handler called when an affinity instance is about to be turned on. The |
| 85 | * level and mpidr determine the affinity instance. |
| 86 | ******************************************************************************/ |
David Pu | 57e92da | 2019-08-08 14:20:03 -0700 | [diff] [blame] | 87 | static int32_t tegra_pwr_domain_on(u_register_t mpidr) |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 88 | { |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 89 | return tegra_soc_pwr_domain_on(mpidr); |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 90 | } |
| 91 | |
| 92 | /******************************************************************************* |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 93 | * Handler called when a power domain is about to be turned off. The |
| 94 | * target_state encodes the power state that each level should transition to. |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 95 | ******************************************************************************/ |
David Pu | 57e92da | 2019-08-08 14:20:03 -0700 | [diff] [blame] | 96 | static void tegra_pwr_domain_off(const psci_power_state_t *target_state) |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 97 | { |
Anthony Zhou | b36aea5 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 98 | (void)tegra_soc_pwr_domain_off(target_state); |
anzhou | c23f5e1 | 2020-08-05 22:34:13 +0800 | [diff] [blame] | 99 | |
| 100 | /* disable GICC */ |
| 101 | tegra_gic_cpuif_deactivate(); |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 102 | } |
| 103 | |
| 104 | /******************************************************************************* |
Varun Wadekar | 26c0d9b | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 105 | * Handler called when a power domain is about to be suspended. The |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 106 | * target_state encodes the power state that each level should transition to. |
Varun Wadekar | cb95a19 | 2017-07-05 17:44:12 -0700 | [diff] [blame] | 107 | * This handler is called with SMP and data cache enabled, when |
| 108 | * HW_ASSISTED_COHERENCY = 0 |
| 109 | ******************************************************************************/ |
| 110 | void tegra_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state) |
| 111 | { |
| 112 | tegra_soc_pwr_domain_suspend_pwrdown_early(target_state); |
| 113 | } |
| 114 | |
| 115 | /******************************************************************************* |
| 116 | * Handler called when a power domain is about to be suspended. The |
| 117 | * target_state encodes the power state that each level should transition to. |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 118 | ******************************************************************************/ |
David Pu | 57e92da | 2019-08-08 14:20:03 -0700 | [diff] [blame] | 119 | static void tegra_pwr_domain_suspend(const psci_power_state_t *target_state) |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 120 | { |
Anthony Zhou | b36aea5 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 121 | (void)tegra_soc_pwr_domain_suspend(target_state); |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 122 | |
| 123 | /* disable GICC */ |
| 124 | tegra_gic_cpuif_deactivate(); |
| 125 | } |
| 126 | |
| 127 | /******************************************************************************* |
Varun Wadekar | 26c0d9b | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 128 | * Handler called at the end of the power domain suspend sequence. The |
| 129 | * target_state encodes the power state that each level should transition to. |
| 130 | ******************************************************************************/ |
David Pu | 57e92da | 2019-08-08 14:20:03 -0700 | [diff] [blame] | 131 | static __dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t |
Varun Wadekar | 26c0d9b | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 132 | *target_state) |
| 133 | { |
| 134 | /* call the chip's power down handler */ |
Anthony Zhou | b36aea5 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 135 | (void)tegra_soc_pwr_domain_power_down_wfi(target_state); |
Varun Wadekar | 26c0d9b | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 136 | |
Varun Wadekar | 0ce729b | 2019-12-11 13:22:21 -0800 | [diff] [blame] | 137 | /* Disable console if we are entering deep sleep. */ |
| 138 | if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == |
| 139 | PSTATE_ID_SOC_POWERDN) { |
| 140 | INFO("%s: complete. Entering System Suspend...\n", __func__); |
Jimmy Brisson | 831b0e9 | 2020-08-05 13:44:05 -0500 | [diff] [blame] | 141 | console_flush(); |
Varun Wadekar | 0ce729b | 2019-12-11 13:22:21 -0800 | [diff] [blame] | 142 | console_switch_state(0); |
| 143 | } |
| 144 | |
Vignesh Radhakrishnan | cf489bf | 2017-05-25 10:31:42 -0700 | [diff] [blame] | 145 | wfi(); |
Varun Wadekar | 26c0d9b | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 146 | panic(); |
| 147 | } |
| 148 | |
| 149 | /******************************************************************************* |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 150 | * Handler called when a power domain has just been powered on after |
| 151 | * being turned off earlier. The target_state encodes the low power state that |
| 152 | * each level has woken up from. |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 153 | ******************************************************************************/ |
David Pu | 57e92da | 2019-08-08 14:20:03 -0700 | [diff] [blame] | 154 | static void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state) |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 155 | { |
Anthony Zhou | b36aea5 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 156 | const plat_params_from_bl2_t *plat_params; |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 157 | |
| 158 | /* |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 159 | * Check if we are exiting from deep sleep. |
| 160 | */ |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 161 | if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == |
| 162 | PSTATE_ID_SOC_POWERDN) { |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 163 | |
Varun Wadekar | 2a3dd38 | 2020-03-21 18:49:33 -0700 | [diff] [blame] | 164 | /* |
| 165 | * On entering System Suspend state, the GIC loses power |
| 166 | * completely. Initialize the GIC global distributor and |
| 167 | * GIC cpu interfaces. |
| 168 | */ |
| 169 | tegra_gic_init(); |
| 170 | |
Ambroise Vincent | 544c092 | 2019-05-29 14:04:16 +0100 | [diff] [blame] | 171 | /* Restart console output. */ |
| 172 | console_switch_state(CONSOLE_FLAG_RUNTIME); |
Varun Wadekar | 5b5928e | 2016-08-01 22:16:21 -0700 | [diff] [blame] | 173 | |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 174 | /* |
Varun Wadekar | 102e408 | 2016-03-03 13:28:10 -0800 | [diff] [blame] | 175 | * Restore Memory Controller settings as it loses state |
| 176 | * during system suspend. |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 177 | */ |
Varun Wadekar | 102e408 | 2016-03-03 13:28:10 -0800 | [diff] [blame] | 178 | tegra_memctrl_restore_settings(); |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 179 | |
| 180 | /* |
| 181 | * Security configuration to allow DRAM/device access. |
| 182 | */ |
| 183 | plat_params = bl31_get_plat_params(); |
Varun Wadekar | e0d4158 | 2015-10-06 12:49:31 +0530 | [diff] [blame] | 184 | tegra_memctrl_tzdram_setup(plat_params->tzdram_base, |
Anthony Zhou | b36aea5 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 185 | (uint32_t)plat_params->tzdram_size); |
Varun Wadekar | 207680c | 2016-06-01 19:34:37 -0700 | [diff] [blame] | 186 | |
Varun Wadekar | 2a3dd38 | 2020-03-21 18:49:33 -0700 | [diff] [blame] | 187 | } else { |
| 188 | /* |
| 189 | * Initialize the GIC cpu and distributor interfaces |
| 190 | */ |
| 191 | tegra_gic_pcpu_init(); |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 192 | } |
| 193 | |
| 194 | /* |
| 195 | * Reset hardware settings. |
| 196 | */ |
Anthony Zhou | b36aea5 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 197 | (void)tegra_soc_pwr_domain_on_finish(target_state); |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 198 | } |
| 199 | |
| 200 | /******************************************************************************* |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 201 | * Handler called when a power domain has just been powered on after |
| 202 | * having been suspended earlier. The target_state encodes the low power state |
| 203 | * that each level has woken up from. |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 204 | ******************************************************************************/ |
David Pu | 57e92da | 2019-08-08 14:20:03 -0700 | [diff] [blame] | 205 | static void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state) |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 206 | { |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 207 | tegra_pwr_domain_on_finish(target_state); |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 208 | } |
| 209 | |
| 210 | /******************************************************************************* |
| 211 | * Handler called when the system wants to be powered off |
| 212 | ******************************************************************************/ |
David Pu | 57e92da | 2019-08-08 14:20:03 -0700 | [diff] [blame] | 213 | static __dead2 void tegra_system_off(void) |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 214 | { |
Varun Wadekar | 31a4957 | 2016-01-07 14:04:21 -0800 | [diff] [blame] | 215 | INFO("Powering down system...\n"); |
| 216 | |
| 217 | tegra_soc_prepare_system_off(); |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 218 | } |
| 219 | |
| 220 | /******************************************************************************* |
| 221 | * Handler called when the system wants to be restarted. |
| 222 | ******************************************************************************/ |
David Pu | 57e92da | 2019-08-08 14:20:03 -0700 | [diff] [blame] | 223 | static __dead2 void tegra_system_reset(void) |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 224 | { |
Varun Wadekar | 31a4957 | 2016-01-07 14:04:21 -0800 | [diff] [blame] | 225 | INFO("Restarting system...\n"); |
| 226 | |
Varun Wadekar | 3b40f99 | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 227 | /* per-SoC system reset handler */ |
Anthony Zhou | b36aea5 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 228 | (void)tegra_soc_prepare_system_reset(); |
Varun Wadekar | 3b40f99 | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 229 | |
Varun Wadekar | 57c539f | 2018-05-17 11:10:13 -0700 | [diff] [blame] | 230 | /* wait for the system to reset */ |
| 231 | for (;;) { |
| 232 | ; |
| 233 | } |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 234 | } |
| 235 | |
| 236 | /******************************************************************************* |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 237 | * Handler called to check the validity of the power state parameter. |
| 238 | ******************************************************************************/ |
David Pu | 57e92da | 2019-08-08 14:20:03 -0700 | [diff] [blame] | 239 | static int32_t tegra_validate_power_state(uint32_t power_state, |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 240 | psci_power_state_t *req_state) |
| 241 | { |
Anthony Zhou | 4c99400 | 2017-07-07 14:29:51 +0800 | [diff] [blame] | 242 | assert(req_state != NULL); |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 243 | |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 244 | return tegra_soc_validate_power_state(power_state, req_state); |
| 245 | } |
| 246 | |
| 247 | /******************************************************************************* |
| 248 | * Platform handler called to check the validity of the non secure entrypoint. |
| 249 | ******************************************************************************/ |
David Pu | 57e92da | 2019-08-08 14:20:03 -0700 | [diff] [blame] | 250 | static int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint) |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 251 | { |
Anthony Zhou | b36aea5 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 252 | int32_t ret = PSCI_E_INVALID_ADDRESS; |
| 253 | |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 254 | /* |
| 255 | * Check if the non secure entrypoint lies within the non |
| 256 | * secure DRAM. |
| 257 | */ |
Anthony Zhou | b36aea5 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 258 | if ((entrypoint >= TEGRA_DRAM_BASE) && (entrypoint <= TEGRA_DRAM_END)) { |
| 259 | ret = PSCI_E_SUCCESS; |
| 260 | } |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 261 | |
Anthony Zhou | b36aea5 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 262 | return ret; |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 263 | } |
| 264 | |
| 265 | /******************************************************************************* |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 266 | * Export the platform handlers to enable psci to invoke them |
| 267 | ******************************************************************************/ |
Varun Wadekar | 5d52aea | 2018-06-26 16:07:50 -0700 | [diff] [blame] | 268 | static plat_psci_ops_t tegra_plat_psci_ops = { |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 269 | .cpu_standby = tegra_cpu_standby, |
| 270 | .pwr_domain_on = tegra_pwr_domain_on, |
| 271 | .pwr_domain_off = tegra_pwr_domain_off, |
Varun Wadekar | cb95a19 | 2017-07-05 17:44:12 -0700 | [diff] [blame] | 272 | .pwr_domain_suspend_pwrdown_early = tegra_pwr_domain_suspend_pwrdown_early, |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 273 | .pwr_domain_suspend = tegra_pwr_domain_suspend, |
| 274 | .pwr_domain_on_finish = tegra_pwr_domain_on_finish, |
| 275 | .pwr_domain_suspend_finish = tegra_pwr_domain_suspend_finish, |
Varun Wadekar | 26c0d9b | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 276 | .pwr_domain_pwr_down_wfi = tegra_pwr_domain_power_down_wfi, |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 277 | .system_off = tegra_system_off, |
| 278 | .system_reset = tegra_system_reset, |
| 279 | .validate_power_state = tegra_validate_power_state, |
| 280 | .validate_ns_entrypoint = tegra_validate_ns_entrypoint, |
| 281 | .get_sys_suspend_power_state = tegra_get_sys_suspend_power_state, |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 282 | }; |
| 283 | |
| 284 | /******************************************************************************* |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 285 | * Export the platform specific power ops and initialize Power Controller |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 286 | ******************************************************************************/ |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 287 | int plat_setup_psci_ops(uintptr_t sec_entrypoint, |
| 288 | const plat_psci_ops_t **psci_ops) |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 289 | { |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 290 | psci_power_state_t target_state = { { PSCI_LOCAL_STATE_RUN } }; |
| 291 | |
| 292 | /* |
| 293 | * Flush entrypoint variable to PoC since it will be |
| 294 | * accessed after a reset with the caches turned off. |
| 295 | */ |
| 296 | tegra_sec_entry_point = sec_entrypoint; |
| 297 | flush_dcache_range((uint64_t)&tegra_sec_entry_point, sizeof(uint64_t)); |
| 298 | |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 299 | /* |
| 300 | * Reset hardware settings. |
| 301 | */ |
Anthony Zhou | b36aea5 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 302 | (void)tegra_soc_pwr_domain_on_finish(&target_state); |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 303 | |
| 304 | /* |
Varun Wadekar | 5d52aea | 2018-06-26 16:07:50 -0700 | [diff] [blame] | 305 | * Disable System Suspend if the platform does not |
| 306 | * support it |
| 307 | */ |
| 308 | if (!plat_supports_system_suspend()) { |
| 309 | tegra_plat_psci_ops.get_sys_suspend_power_state = NULL; |
| 310 | } |
| 311 | |
| 312 | /* |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 313 | * Initialize PSCI ops struct |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 314 | */ |
Varun Wadekar | 71cb26e | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 315 | *psci_ops = &tegra_plat_psci_ops; |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 316 | |
| 317 | return 0; |
| 318 | } |
Varun Wadekar | 2693f1d | 2016-05-05 14:13:30 -0700 | [diff] [blame] | 319 | |
| 320 | /******************************************************************************* |
| 321 | * Platform handler to calculate the proper target power level at the |
| 322 | * specified affinity level |
| 323 | ******************************************************************************/ |
| 324 | plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, |
| 325 | const plat_local_state_t *states, |
| 326 | unsigned int ncpu) |
| 327 | { |
Varun Wadekar | a7cd095 | 2016-06-07 12:00:06 -0700 | [diff] [blame] | 328 | return tegra_soc_get_target_pwr_state(lvl, states, ncpu); |
Varun Wadekar | 2693f1d | 2016-05-05 14:13:30 -0700 | [diff] [blame] | 329 | } |