Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 31 | #include <arm_config.h> |
| 32 | #include <arm_def.h> |
Vikram Kanigiri | 4991ecd | 2015-02-26 15:25:58 +0000 | [diff] [blame] | 33 | #include <cci.h> |
Dan Handley | 35e98e5 | 2014-04-09 13:13:04 +0100 | [diff] [blame] | 34 | #include <debug.h> |
Achin Gupta | 27573c5 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 35 | #include <gicv2.h> |
Dan Handley | 97043ac | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 36 | #include <mmio.h> |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 37 | #include <plat_arm.h> |
| 38 | #include <v2m_def.h> |
Dan Handley | 5f0cdb0 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 39 | #include "../fvp_def.h" |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 40 | |
Achin Gupta | 27573c5 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 41 | #if (FVP_USE_GIC_DRIVER == FVP_GICV2) |
| 42 | extern gicv2_driver_data_t arm_gic_data; |
| 43 | #endif |
| 44 | |
| 45 | /* Defines for GIC Driver build time selection */ |
| 46 | #define FVP_GICV2 1 |
| 47 | #define FVP_GICV3 2 |
| 48 | #define FVP_GICV3_LEGACY 3 |
| 49 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 50 | /******************************************************************************* |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 51 | * arm_config holds the characteristics of the differences between the three FVP |
| 52 | * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot |
| 53 | * at each boot stage by the primary before enabling the MMU (to allow cci |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 54 | * configuration) & used thereafter. Each BL will have its own copy to allow |
| 55 | * independent operation. |
| 56 | ******************************************************************************/ |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 57 | arm_config_t arm_config; |
Soby Mathew | d0ecd97 | 2014-09-03 17:48:44 +0100 | [diff] [blame] | 58 | |
| 59 | #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ |
| 60 | DEVICE0_SIZE, \ |
| 61 | MT_DEVICE | MT_RW | MT_SECURE) |
| 62 | |
| 63 | #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ |
| 64 | DEVICE1_SIZE, \ |
| 65 | MT_DEVICE | MT_RW | MT_SECURE) |
| 66 | |
Juan Castillo | 95cfd4a | 2015-04-14 12:49:03 +0100 | [diff] [blame] | 67 | #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ |
| 68 | DEVICE2_SIZE, \ |
| 69 | MT_DEVICE | MT_RO | MT_SECURE) |
| 70 | |
| 71 | |
Jon Medhurst | 38aa76a | 2014-02-26 16:27:53 +0000 | [diff] [blame] | 72 | /* |
Soby Mathew | d0ecd97 | 2014-09-03 17:48:44 +0100 | [diff] [blame] | 73 | * Table of regions for various BL stages to map using the MMU. |
Sandrine Bailleux | b793e43 | 2014-05-09 11:35:36 +0100 | [diff] [blame] | 74 | * This doesn't include TZRAM as the 'mem_layout' argument passed to |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 75 | * arm_configure_mmu_elx() will give the available subset of that, |
Jon Medhurst | 38aa76a | 2014-02-26 16:27:53 +0000 | [diff] [blame] | 76 | */ |
Soby Mathew | d0ecd97 | 2014-09-03 17:48:44 +0100 | [diff] [blame] | 77 | #if IMAGE_BL1 |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 78 | const mmap_region_t plat_arm_mmap[] = { |
| 79 | ARM_MAP_SHARED_RAM, |
Juan Castillo | 7b4c140 | 2015-10-06 14:01:35 +0100 | [diff] [blame] | 80 | V2M_MAP_FLASH0_RW, |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 81 | V2M_MAP_IOFPGA, |
Soby Mathew | d0ecd97 | 2014-09-03 17:48:44 +0100 | [diff] [blame] | 82 | MAP_DEVICE0, |
| 83 | MAP_DEVICE1, |
Juan Castillo | 95cfd4a | 2015-04-14 12:49:03 +0100 | [diff] [blame] | 84 | MAP_DEVICE2, |
Yatharth Kochar | 436223d | 2015-10-11 14:14:55 +0100 | [diff] [blame] | 85 | #if TRUSTED_BOARD_BOOT |
| 86 | ARM_MAP_NS_DRAM1, |
| 87 | #endif |
Jon Medhurst | 38aa76a | 2014-02-26 16:27:53 +0000 | [diff] [blame] | 88 | {0} |
| 89 | }; |
Soby Mathew | d0ecd97 | 2014-09-03 17:48:44 +0100 | [diff] [blame] | 90 | #endif |
| 91 | #if IMAGE_BL2 |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 92 | const mmap_region_t plat_arm_mmap[] = { |
| 93 | ARM_MAP_SHARED_RAM, |
Juan Castillo | 7b4c140 | 2015-10-06 14:01:35 +0100 | [diff] [blame] | 94 | V2M_MAP_FLASH0_RW, |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 95 | V2M_MAP_IOFPGA, |
Soby Mathew | d0ecd97 | 2014-09-03 17:48:44 +0100 | [diff] [blame] | 96 | MAP_DEVICE0, |
| 97 | MAP_DEVICE1, |
Juan Castillo | 95cfd4a | 2015-04-14 12:49:03 +0100 | [diff] [blame] | 98 | MAP_DEVICE2, |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 99 | ARM_MAP_NS_DRAM1, |
| 100 | ARM_MAP_TSP_SEC_MEM, |
Soby Mathew | d0ecd97 | 2014-09-03 17:48:44 +0100 | [diff] [blame] | 101 | {0} |
| 102 | }; |
| 103 | #endif |
Yatharth Kochar | dcda29f | 2015-10-14 15:28:11 +0100 | [diff] [blame^] | 104 | #if IMAGE_BL2U |
| 105 | const mmap_region_t plat_arm_mmap[] = { |
| 106 | MAP_DEVICE0, |
| 107 | V2M_MAP_IOFPGA, |
| 108 | {0} |
| 109 | }; |
| 110 | #endif |
Soby Mathew | d0ecd97 | 2014-09-03 17:48:44 +0100 | [diff] [blame] | 111 | #if IMAGE_BL31 |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 112 | const mmap_region_t plat_arm_mmap[] = { |
| 113 | ARM_MAP_SHARED_RAM, |
| 114 | V2M_MAP_IOFPGA, |
Soby Mathew | d0ecd97 | 2014-09-03 17:48:44 +0100 | [diff] [blame] | 115 | MAP_DEVICE0, |
| 116 | MAP_DEVICE1, |
| 117 | {0} |
| 118 | }; |
| 119 | #endif |
| 120 | #if IMAGE_BL32 |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 121 | const mmap_region_t plat_arm_mmap[] = { |
| 122 | V2M_MAP_IOFPGA, |
Soby Mathew | d0ecd97 | 2014-09-03 17:48:44 +0100 | [diff] [blame] | 123 | MAP_DEVICE0, |
| 124 | MAP_DEVICE1, |
| 125 | {0} |
| 126 | }; |
| 127 | #endif |
Jon Medhurst | 38aa76a | 2014-02-26 16:27:53 +0000 | [diff] [blame] | 128 | |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 129 | ARM_CASSERT_MMAP |
Soby Mathew | ce41250 | 2015-01-22 11:22:22 +0000 | [diff] [blame] | 130 | |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 131 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 132 | /******************************************************************************* |
| 133 | * A single boot loader stack is expected to work on both the Foundation FVP |
| 134 | * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The |
| 135 | * SYS_ID register provides a mechanism for detecting the differences between |
| 136 | * these platforms. This information is stored in a per-BL array to allow the |
| 137 | * code to take the correct path.Per BL platform configuration. |
| 138 | ******************************************************************************/ |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 139 | void fvp_config_setup(void) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 140 | { |
Soby Mathew | add4035 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 141 | unsigned int rev, hbi, bld, arch, sys_id; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 142 | |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 143 | sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); |
| 144 | rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; |
| 145 | hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; |
| 146 | bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; |
| 147 | arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 148 | |
Andrew Thoelke | 90e3147 | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 149 | if (arch != ARCH_MODEL) { |
| 150 | ERROR("This firmware is for FVP models\n"); |
James Morrissey | 40a6f64 | 2014-02-10 14:24:36 +0000 | [diff] [blame] | 151 | panic(); |
Andrew Thoelke | 90e3147 | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 152 | } |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 153 | |
| 154 | /* |
| 155 | * The build field in the SYS_ID tells which variant of the GIC |
| 156 | * memory is implemented by the model. |
| 157 | */ |
| 158 | switch (bld) { |
| 159 | case BLD_GIC_VE_MMAP: |
Achin Gupta | 27573c5 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 160 | #if IMAGE_BL31 || IMAGE_BL32 |
| 161 | #if FVP_USE_GIC_DRIVER == FVP_GICV2 |
| 162 | /* |
| 163 | * If the FVP implements the VE compatible memory map, then the |
| 164 | * GICv2 driver must be included in the build. Update the platform |
| 165 | * data with the correct GICv2 base addresses before it is used |
| 166 | * to initialise the driver. |
| 167 | * |
| 168 | * This update of platform data is temporary and will be removed |
| 169 | * once VE memory map for FVP is no longer supported by Trusted |
| 170 | * Firmware. |
| 171 | */ |
| 172 | arm_gic_data.gicd_base = VE_GICD_BASE; |
| 173 | arm_gic_data.gicc_base = VE_GICC_BASE; |
| 174 | |
| 175 | #else |
| 176 | ERROR("Only GICv2 driver supported for VE memory map\n"); |
| 177 | panic(); |
| 178 | #endif /* __FVP_USE_GIC_DRIVER == FVP_GICV2__ */ |
| 179 | #endif /* __IMAGE_BL31 || IMAGE_BL32__ */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 180 | break; |
| 181 | case BLD_GIC_A53A57_MMAP: |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 182 | break; |
| 183 | default: |
Andrew Thoelke | 90e3147 | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 184 | ERROR("Unsupported board build %x\n", bld); |
| 185 | panic(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 186 | } |
| 187 | |
| 188 | /* |
| 189 | * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 |
| 190 | * for the Foundation FVP. |
| 191 | */ |
| 192 | switch (hbi) { |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 193 | case HBI_FOUNDATION_FVP: |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 194 | arm_config.flags = 0; |
Andrew Thoelke | 90e3147 | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 195 | |
| 196 | /* |
| 197 | * Check for supported revisions of Foundation FVP |
| 198 | * Allow future revisions to run but emit warning diagnostic |
| 199 | */ |
| 200 | switch (rev) { |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 201 | case REV_FOUNDATION_FVP_V2_0: |
| 202 | case REV_FOUNDATION_FVP_V2_1: |
| 203 | case REV_FOUNDATION_FVP_v9_1: |
Andrew Thoelke | 90e3147 | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 204 | break; |
| 205 | default: |
| 206 | WARN("Unrecognized Foundation FVP revision %x\n", rev); |
| 207 | break; |
| 208 | } |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 209 | break; |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 210 | case HBI_BASE_FVP: |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 211 | arm_config.flags |= ARM_CONFIG_BASE_MMAP | |
| 212 | ARM_CONFIG_HAS_CCI | ARM_CONFIG_HAS_TZC; |
Andrew Thoelke | 90e3147 | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 213 | |
| 214 | /* |
| 215 | * Check for supported revisions |
| 216 | * Allow future revisions to run but emit warning diagnostic |
| 217 | */ |
| 218 | switch (rev) { |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 219 | case REV_BASE_FVP_V0: |
Andrew Thoelke | 90e3147 | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 220 | break; |
| 221 | default: |
| 222 | WARN("Unrecognized Base FVP revision %x\n", rev); |
| 223 | break; |
| 224 | } |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 225 | break; |
| 226 | default: |
Andrew Thoelke | 90e3147 | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 227 | ERROR("Unsupported board HBI number 0x%x\n", hbi); |
| 228 | panic(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 229 | } |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 230 | } |
| 231 | |
Vikram Kanigiri | 4991ecd | 2015-02-26 15:25:58 +0000 | [diff] [blame] | 232 | |
Dan Handley | cae3ef9 | 2014-08-04 16:11:15 +0100 | [diff] [blame] | 233 | void fvp_cci_init(void) |
Vikram Kanigiri | dbad1ba | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 234 | { |
Vikram Kanigiri | dbad1ba | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 235 | /* |
Dan Handley | cae3ef9 | 2014-08-04 16:11:15 +0100 | [diff] [blame] | 236 | * Initialize CCI-400 driver |
| 237 | */ |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 238 | if (arm_config.flags & ARM_CONFIG_HAS_CCI) |
| 239 | arm_cci_init(); |
Dan Handley | cae3ef9 | 2014-08-04 16:11:15 +0100 | [diff] [blame] | 240 | } |
| 241 | |
| 242 | void fvp_cci_enable(void) |
| 243 | { |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 244 | if (arm_config.flags & ARM_CONFIG_HAS_CCI) |
Vikram Kanigiri | 4991ecd | 2015-02-26 15:25:58 +0000 | [diff] [blame] | 245 | cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); |
| 246 | } |
| 247 | |
| 248 | void fvp_cci_disable(void) |
| 249 | { |
Dan Handley | 60eea55 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 250 | if (arm_config.flags & ARM_CONFIG_HAS_CCI) |
Vikram Kanigiri | 4991ecd | 2015-02-26 15:25:58 +0000 | [diff] [blame] | 251 | cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); |
Vikram Kanigiri | dbad1ba | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 252 | } |