Soby Mathew | 5882c57 | 2018-02-09 10:40:49 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | motherboard { |
| 8 | arm,v2m-memory-map = "rs1"; |
| 9 | compatible = "arm,vexpress,v2m-p1", "simple-bus"; |
| 10 | #address-cells = <2>; /* SMB chipselect number and offset */ |
| 11 | #size-cells = <1>; |
| 12 | #interrupt-cells = <1>; |
| 13 | ranges; |
| 14 | |
| 15 | flash@0,00000000 { |
| 16 | compatible = "arm,vexpress-flash", "cfi-flash"; |
| 17 | reg = <0 0x00000000 0x04000000>, |
| 18 | <4 0x00000000 0x04000000>; |
| 19 | bank-width = <4>; |
| 20 | }; |
| 21 | |
| 22 | vram@2,00000000 { |
| 23 | compatible = "arm,vexpress-vram"; |
| 24 | reg = <2 0x00000000 0x00800000>; |
| 25 | }; |
| 26 | |
| 27 | ethernet@2,02000000 { |
| 28 | compatible = "smsc,lan91c111"; |
| 29 | reg = <2 0x02000000 0x10000>; |
| 30 | interrupts = <15>; |
| 31 | }; |
| 32 | |
| 33 | v2m_clk24mhz: clk24mhz { |
| 34 | compatible = "fixed-clock"; |
| 35 | #clock-cells = <0>; |
| 36 | clock-frequency = <24000000>; |
| 37 | clock-output-names = "v2m:clk24mhz"; |
| 38 | }; |
| 39 | |
| 40 | v2m_refclk1mhz: refclk1mhz { |
| 41 | compatible = "fixed-clock"; |
| 42 | #clock-cells = <0>; |
| 43 | clock-frequency = <1000000>; |
| 44 | clock-output-names = "v2m:refclk1mhz"; |
| 45 | }; |
| 46 | |
| 47 | v2m_refclk32khz: refclk32khz { |
| 48 | compatible = "fixed-clock"; |
| 49 | #clock-cells = <0>; |
| 50 | clock-frequency = <32768>; |
| 51 | clock-output-names = "v2m:refclk32khz"; |
| 52 | }; |
| 53 | |
| 54 | iofpga@3,00000000 { |
| 55 | compatible = "arm,amba-bus", "simple-bus"; |
| 56 | #address-cells = <1>; |
| 57 | #size-cells = <1>; |
| 58 | ranges = <0 3 0 0x200000>; |
| 59 | |
Roberto Vargas | e230f4d | 2018-04-23 14:44:54 +0100 | [diff] [blame^] | 60 | v2m_sysreg: sysreg@10000 { |
Soby Mathew | 5882c57 | 2018-02-09 10:40:49 +0000 | [diff] [blame] | 61 | compatible = "arm,vexpress-sysreg"; |
| 62 | reg = <0x010000 0x1000>; |
| 63 | gpio-controller; |
| 64 | #gpio-cells = <2>; |
| 65 | }; |
| 66 | |
Roberto Vargas | e230f4d | 2018-04-23 14:44:54 +0100 | [diff] [blame^] | 67 | v2m_sysctl: sysctl@20000 { |
Soby Mathew | 5882c57 | 2018-02-09 10:40:49 +0000 | [diff] [blame] | 68 | compatible = "arm,sp810", "arm,primecell"; |
| 69 | reg = <0x020000 0x1000>; |
| 70 | clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; |
| 71 | clock-names = "refclk", "timclk", "apb_pclk"; |
| 72 | #clock-cells = <1>; |
| 73 | clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; |
| 74 | }; |
| 75 | |
Roberto Vargas | e230f4d | 2018-04-23 14:44:54 +0100 | [diff] [blame^] | 76 | aaci@40000 { |
Soby Mathew | 5882c57 | 2018-02-09 10:40:49 +0000 | [diff] [blame] | 77 | compatible = "arm,pl041", "arm,primecell"; |
| 78 | reg = <0x040000 0x1000>; |
| 79 | interrupts = <11>; |
| 80 | clocks = <&v2m_clk24mhz>; |
| 81 | clock-names = "apb_pclk"; |
| 82 | }; |
| 83 | |
Roberto Vargas | e230f4d | 2018-04-23 14:44:54 +0100 | [diff] [blame^] | 84 | mmci@50000 { |
Soby Mathew | 5882c57 | 2018-02-09 10:40:49 +0000 | [diff] [blame] | 85 | compatible = "arm,pl180", "arm,primecell"; |
| 86 | reg = <0x050000 0x1000>; |
| 87 | interrupts = <9 10>; |
| 88 | cd-gpios = <&v2m_sysreg 0 0>; |
| 89 | wp-gpios = <&v2m_sysreg 1 0>; |
| 90 | max-frequency = <12000000>; |
| 91 | vmmc-supply = <&v2m_fixed_3v3>; |
| 92 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; |
| 93 | clock-names = "mclk", "apb_pclk"; |
| 94 | }; |
| 95 | |
Roberto Vargas | e230f4d | 2018-04-23 14:44:54 +0100 | [diff] [blame^] | 96 | kmi@60000 { |
Soby Mathew | 5882c57 | 2018-02-09 10:40:49 +0000 | [diff] [blame] | 97 | compatible = "arm,pl050", "arm,primecell"; |
| 98 | reg = <0x060000 0x1000>; |
| 99 | interrupts = <12>; |
| 100 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; |
| 101 | clock-names = "KMIREFCLK", "apb_pclk"; |
| 102 | }; |
| 103 | |
Roberto Vargas | e230f4d | 2018-04-23 14:44:54 +0100 | [diff] [blame^] | 104 | kmi@70000 { |
Soby Mathew | 5882c57 | 2018-02-09 10:40:49 +0000 | [diff] [blame] | 105 | compatible = "arm,pl050", "arm,primecell"; |
| 106 | reg = <0x070000 0x1000>; |
| 107 | interrupts = <13>; |
| 108 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; |
| 109 | clock-names = "KMIREFCLK", "apb_pclk"; |
| 110 | }; |
| 111 | |
Roberto Vargas | e230f4d | 2018-04-23 14:44:54 +0100 | [diff] [blame^] | 112 | v2m_serial0: uart@90000 { |
Soby Mathew | 5882c57 | 2018-02-09 10:40:49 +0000 | [diff] [blame] | 113 | compatible = "arm,pl011", "arm,primecell"; |
| 114 | reg = <0x090000 0x1000>; |
| 115 | interrupts = <5>; |
| 116 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; |
| 117 | clock-names = "uartclk", "apb_pclk"; |
| 118 | }; |
| 119 | |
Roberto Vargas | e230f4d | 2018-04-23 14:44:54 +0100 | [diff] [blame^] | 120 | v2m_serial1: uart@a0000 { |
Soby Mathew | 5882c57 | 2018-02-09 10:40:49 +0000 | [diff] [blame] | 121 | compatible = "arm,pl011", "arm,primecell"; |
| 122 | reg = <0x0a0000 0x1000>; |
| 123 | interrupts = <6>; |
| 124 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; |
| 125 | clock-names = "uartclk", "apb_pclk"; |
| 126 | }; |
| 127 | |
Roberto Vargas | e230f4d | 2018-04-23 14:44:54 +0100 | [diff] [blame^] | 128 | v2m_serial2: uart@b0000 { |
Soby Mathew | 5882c57 | 2018-02-09 10:40:49 +0000 | [diff] [blame] | 129 | compatible = "arm,pl011", "arm,primecell"; |
| 130 | reg = <0x0b0000 0x1000>; |
| 131 | interrupts = <7>; |
| 132 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; |
| 133 | clock-names = "uartclk", "apb_pclk"; |
| 134 | }; |
| 135 | |
Roberto Vargas | e230f4d | 2018-04-23 14:44:54 +0100 | [diff] [blame^] | 136 | v2m_serial3: uart@c0000 { |
Soby Mathew | 5882c57 | 2018-02-09 10:40:49 +0000 | [diff] [blame] | 137 | compatible = "arm,pl011", "arm,primecell"; |
| 138 | reg = <0x0c0000 0x1000>; |
| 139 | interrupts = <8>; |
| 140 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; |
| 141 | clock-names = "uartclk", "apb_pclk"; |
| 142 | }; |
| 143 | |
Roberto Vargas | e230f4d | 2018-04-23 14:44:54 +0100 | [diff] [blame^] | 144 | wdt@f0000 { |
Soby Mathew | 5882c57 | 2018-02-09 10:40:49 +0000 | [diff] [blame] | 145 | compatible = "arm,sp805", "arm,primecell"; |
| 146 | reg = <0x0f0000 0x1000>; |
| 147 | interrupts = <0>; |
| 148 | clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; |
| 149 | clock-names = "wdogclk", "apb_pclk"; |
| 150 | }; |
| 151 | |
| 152 | v2m_timer01: timer@110000 { |
| 153 | compatible = "arm,sp804", "arm,primecell"; |
| 154 | reg = <0x110000 0x1000>; |
| 155 | interrupts = <2>; |
| 156 | clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; |
| 157 | clock-names = "timclken1", "timclken2", "apb_pclk"; |
| 158 | }; |
| 159 | |
| 160 | v2m_timer23: timer@120000 { |
| 161 | compatible = "arm,sp804", "arm,primecell"; |
| 162 | reg = <0x120000 0x1000>; |
| 163 | interrupts = <3>; |
| 164 | clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; |
| 165 | clock-names = "timclken1", "timclken2", "apb_pclk"; |
| 166 | }; |
| 167 | |
| 168 | rtc@170000 { |
| 169 | compatible = "arm,pl031", "arm,primecell"; |
| 170 | reg = <0x170000 0x1000>; |
| 171 | interrupts = <4>; |
| 172 | clocks = <&v2m_clk24mhz>; |
| 173 | clock-names = "apb_pclk"; |
| 174 | }; |
| 175 | |
| 176 | clcd@1f0000 { |
| 177 | compatible = "arm,pl111", "arm,primecell"; |
| 178 | reg = <0x1f0000 0x1000>; |
| 179 | interrupts = <14>; |
| 180 | clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; |
| 181 | clock-names = "clcdclk", "apb_pclk"; |
| 182 | mode = "XVGA"; |
| 183 | use_dma = <0>; |
| 184 | framebuffer = <0x18000000 0x00180000>; |
| 185 | }; |
| 186 | |
Roberto Vargas | e230f4d | 2018-04-23 14:44:54 +0100 | [diff] [blame^] | 187 | virtio_block@130000 { |
Soby Mathew | 5882c57 | 2018-02-09 10:40:49 +0000 | [diff] [blame] | 188 | compatible = "virtio,mmio"; |
| 189 | reg = <0x130000 0x1000>; |
| 190 | interrupts = <0x2a>; |
| 191 | }; |
| 192 | }; |
| 193 | |
| 194 | v2m_fixed_3v3: fixedregulator@0 { |
| 195 | compatible = "regulator-fixed"; |
| 196 | regulator-name = "3V3"; |
| 197 | regulator-min-microvolt = <3300000>; |
| 198 | regulator-max-microvolt = <3300000>; |
| 199 | regulator-always-on; |
| 200 | }; |
| 201 | |
| 202 | mcc { |
| 203 | compatible = "arm,vexpress,config-bus", "simple-bus"; |
| 204 | arm,vexpress,config-bridge = <&v2m_sysreg>; |
| 205 | |
| 206 | v2m_oscclk1: osc@1 { |
| 207 | /* CLCD clock */ |
| 208 | compatible = "arm,vexpress-osc"; |
| 209 | arm,vexpress-sysreg,func = <1 1>; |
| 210 | freq-range = <23750000 63500000>; |
| 211 | #clock-cells = <0>; |
| 212 | clock-output-names = "v2m:oscclk1"; |
| 213 | }; |
| 214 | |
| 215 | /* |
| 216 | * Not supported in FVP models |
| 217 | * |
| 218 | * reset@0 { |
| 219 | * compatible = "arm,vexpress-reset"; |
| 220 | * arm,vexpress-sysreg,func = <5 0>; |
| 221 | * }; |
| 222 | */ |
| 223 | |
| 224 | muxfpga@0 { |
| 225 | compatible = "arm,vexpress-muxfpga"; |
| 226 | arm,vexpress-sysreg,func = <7 0>; |
| 227 | }; |
| 228 | |
| 229 | /* |
| 230 | * Not used - Superseded by PSCI sys_poweroff |
| 231 | * |
| 232 | * shutdown@0 { |
| 233 | * compatible = "arm,vexpress-shutdown"; |
| 234 | * arm,vexpress-sysreg,func = <8 0>; |
| 235 | * }; |
| 236 | */ |
| 237 | |
| 238 | /* |
| 239 | * Not used - Superseded by PSCI sys_reset |
| 240 | * |
| 241 | * reboot@0 { |
| 242 | * compatible = "arm,vexpress-reboot"; |
| 243 | * arm,vexpress-sysreg,func = <9 0>; |
| 244 | * }; |
| 245 | */ |
| 246 | |
| 247 | dvimode@0 { |
| 248 | compatible = "arm,vexpress-dvimode"; |
| 249 | arm,vexpress-sysreg,func = <11 0>; |
| 250 | }; |
| 251 | }; |
| 252 | }; |