Robert Sloan | c9abfe4 | 2018-11-26 12:19:07 -0800 | [diff] [blame] | 1 | // This file is generated from a similarly-named Perl script in the BoringSSL |
| 2 | // source tree. Do not edit by hand. |
| 3 | |
Pete Bentley | 0c61efe | 2019-08-13 09:32:23 +0100 | [diff] [blame^] | 4 | #if !defined(__has_feature) |
| 5 | #define __has_feature(x) 0 |
| 6 | #endif |
Robert Sloan | 726e9d1 | 2018-09-11 11:45:04 -0700 | [diff] [blame] | 7 | #if __has_feature(memory_sanitizer) && !defined(OPENSSL_NO_ASM) |
| 8 | #define OPENSSL_NO_ASM |
| 9 | #endif |
Robert Sloan | 726e9d1 | 2018-09-11 11:45:04 -0700 | [diff] [blame] | 10 | |
| 11 | #if !defined(OPENSSL_NO_ASM) |
Robert Sloan | 8ff0355 | 2017-06-14 12:40:58 -0700 | [diff] [blame] | 12 | #if defined(__arm__) |
Robert Sloan | 726e9d1 | 2018-09-11 11:45:04 -0700 | [diff] [blame] | 13 | #if defined(BORINGSSL_PREFIX) |
| 14 | #include <boringssl_prefix_symbols_asm.h> |
| 15 | #endif |
Robert Sloan | 8ff0355 | 2017-06-14 12:40:58 -0700 | [diff] [blame] | 16 | #include <openssl/arm_arch.h> |
| 17 | |
Robert Sloan | 5581810 | 2017-12-18 11:26:17 -0800 | [diff] [blame] | 18 | @ Silence ARMv8 deprecated IT instruction warnings. This file is used by both |
| 19 | @ ARMv7 and ARMv8 processors and does not use ARMv8 instructions. |
| 20 | .arch armv7-a |
| 21 | |
Robert Sloan | 8ff0355 | 2017-06-14 12:40:58 -0700 | [diff] [blame] | 22 | .text |
| 23 | #if defined(__thumb2__) |
| 24 | .syntax unified |
| 25 | .thumb |
| 26 | #else |
| 27 | .code 32 |
| 28 | #endif |
| 29 | |
| 30 | #if __ARM_MAX_ARCH__>=7 |
| 31 | .align 5 |
| 32 | .LOPENSSL_armcap: |
| 33 | .word OPENSSL_armcap_P-.Lbn_mul_mont |
| 34 | #endif |
| 35 | |
| 36 | .globl bn_mul_mont |
| 37 | .hidden bn_mul_mont |
| 38 | .type bn_mul_mont,%function |
| 39 | |
| 40 | .align 5 |
| 41 | bn_mul_mont: |
| 42 | .Lbn_mul_mont: |
| 43 | ldr ip,[sp,#4] @ load num |
| 44 | stmdb sp!,{r0,r2} @ sp points at argument block |
| 45 | #if __ARM_MAX_ARCH__>=7 |
| 46 | tst ip,#7 |
| 47 | bne .Lialu |
| 48 | adr r0,.Lbn_mul_mont |
| 49 | ldr r2,.LOPENSSL_armcap |
| 50 | ldr r0,[r0,r2] |
| 51 | #ifdef __APPLE__ |
| 52 | ldr r0,[r0] |
| 53 | #endif |
| 54 | tst r0,#ARMV7_NEON @ NEON available? |
| 55 | ldmia sp, {r0,r2} |
| 56 | beq .Lialu |
| 57 | add sp,sp,#8 |
| 58 | b bn_mul8x_mont_neon |
| 59 | .align 4 |
| 60 | .Lialu: |
| 61 | #endif |
| 62 | cmp ip,#2 |
| 63 | mov r0,ip @ load num |
| 64 | #ifdef __thumb2__ |
| 65 | ittt lt |
| 66 | #endif |
| 67 | movlt r0,#0 |
| 68 | addlt sp,sp,#2*4 |
| 69 | blt .Labrt |
| 70 | |
| 71 | stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} @ save 10 registers |
| 72 | |
| 73 | mov r0,r0,lsl#2 @ rescale r0 for byte count |
| 74 | sub sp,sp,r0 @ alloca(4*num) |
| 75 | sub sp,sp,#4 @ +extra dword |
| 76 | sub r0,r0,#4 @ "num=num-1" |
| 77 | add r4,r2,r0 @ &bp[num-1] |
| 78 | |
| 79 | add r0,sp,r0 @ r0 to point at &tp[num-1] |
| 80 | ldr r8,[r0,#14*4] @ &n0 |
| 81 | ldr r2,[r2] @ bp[0] |
| 82 | ldr r5,[r1],#4 @ ap[0],ap++ |
| 83 | ldr r6,[r3],#4 @ np[0],np++ |
| 84 | ldr r8,[r8] @ *n0 |
| 85 | str r4,[r0,#15*4] @ save &bp[num] |
| 86 | |
| 87 | umull r10,r11,r5,r2 @ ap[0]*bp[0] |
| 88 | str r8,[r0,#14*4] @ save n0 value |
| 89 | mul r8,r10,r8 @ "tp[0]"*n0 |
| 90 | mov r12,#0 |
| 91 | umlal r10,r12,r6,r8 @ np[0]*n0+"t[0]" |
| 92 | mov r4,sp |
| 93 | |
| 94 | .L1st: |
| 95 | ldr r5,[r1],#4 @ ap[j],ap++ |
| 96 | mov r10,r11 |
| 97 | ldr r6,[r3],#4 @ np[j],np++ |
| 98 | mov r11,#0 |
| 99 | umlal r10,r11,r5,r2 @ ap[j]*bp[0] |
| 100 | mov r14,#0 |
| 101 | umlal r12,r14,r6,r8 @ np[j]*n0 |
| 102 | adds r12,r12,r10 |
| 103 | str r12,[r4],#4 @ tp[j-1]=,tp++ |
| 104 | adc r12,r14,#0 |
| 105 | cmp r4,r0 |
| 106 | bne .L1st |
| 107 | |
| 108 | adds r12,r12,r11 |
| 109 | ldr r4,[r0,#13*4] @ restore bp |
| 110 | mov r14,#0 |
| 111 | ldr r8,[r0,#14*4] @ restore n0 |
| 112 | adc r14,r14,#0 |
| 113 | str r12,[r0] @ tp[num-1]= |
| 114 | mov r7,sp |
| 115 | str r14,[r0,#4] @ tp[num]= |
| 116 | |
| 117 | .Louter: |
| 118 | sub r7,r0,r7 @ "original" r0-1 value |
| 119 | sub r1,r1,r7 @ "rewind" ap to &ap[1] |
| 120 | ldr r2,[r4,#4]! @ *(++bp) |
| 121 | sub r3,r3,r7 @ "rewind" np to &np[1] |
| 122 | ldr r5,[r1,#-4] @ ap[0] |
| 123 | ldr r10,[sp] @ tp[0] |
| 124 | ldr r6,[r3,#-4] @ np[0] |
| 125 | ldr r7,[sp,#4] @ tp[1] |
| 126 | |
| 127 | mov r11,#0 |
| 128 | umlal r10,r11,r5,r2 @ ap[0]*bp[i]+tp[0] |
| 129 | str r4,[r0,#13*4] @ save bp |
| 130 | mul r8,r10,r8 |
| 131 | mov r12,#0 |
| 132 | umlal r10,r12,r6,r8 @ np[0]*n0+"tp[0]" |
| 133 | mov r4,sp |
| 134 | |
| 135 | .Linner: |
| 136 | ldr r5,[r1],#4 @ ap[j],ap++ |
| 137 | adds r10,r11,r7 @ +=tp[j] |
| 138 | ldr r6,[r3],#4 @ np[j],np++ |
| 139 | mov r11,#0 |
| 140 | umlal r10,r11,r5,r2 @ ap[j]*bp[i] |
| 141 | mov r14,#0 |
| 142 | umlal r12,r14,r6,r8 @ np[j]*n0 |
| 143 | adc r11,r11,#0 |
| 144 | ldr r7,[r4,#8] @ tp[j+1] |
| 145 | adds r12,r12,r10 |
| 146 | str r12,[r4],#4 @ tp[j-1]=,tp++ |
| 147 | adc r12,r14,#0 |
| 148 | cmp r4,r0 |
| 149 | bne .Linner |
| 150 | |
| 151 | adds r12,r12,r11 |
| 152 | mov r14,#0 |
| 153 | ldr r4,[r0,#13*4] @ restore bp |
| 154 | adc r14,r14,#0 |
| 155 | ldr r8,[r0,#14*4] @ restore n0 |
| 156 | adds r12,r12,r7 |
| 157 | ldr r7,[r0,#15*4] @ restore &bp[num] |
| 158 | adc r14,r14,#0 |
| 159 | str r12,[r0] @ tp[num-1]= |
| 160 | str r14,[r0,#4] @ tp[num]= |
| 161 | |
| 162 | cmp r4,r7 |
| 163 | #ifdef __thumb2__ |
| 164 | itt ne |
| 165 | #endif |
| 166 | movne r7,sp |
| 167 | bne .Louter |
| 168 | |
| 169 | ldr r2,[r0,#12*4] @ pull rp |
| 170 | mov r5,sp |
| 171 | add r0,r0,#4 @ r0 to point at &tp[num] |
| 172 | sub r5,r0,r5 @ "original" num value |
| 173 | mov r4,sp @ "rewind" r4 |
| 174 | mov r1,r4 @ "borrow" r1 |
| 175 | sub r3,r3,r5 @ "rewind" r3 to &np[0] |
| 176 | |
| 177 | subs r7,r7,r7 @ "clear" carry flag |
| 178 | .Lsub: ldr r7,[r4],#4 |
| 179 | ldr r6,[r3],#4 |
| 180 | sbcs r7,r7,r6 @ tp[j]-np[j] |
| 181 | str r7,[r2],#4 @ rp[j]= |
| 182 | teq r4,r0 @ preserve carry |
| 183 | bne .Lsub |
| 184 | sbcs r14,r14,#0 @ upmost carry |
| 185 | mov r4,sp @ "rewind" r4 |
| 186 | sub r2,r2,r5 @ "rewind" r2 |
| 187 | |
Adam Vartanian | bfcf3a7 | 2018-08-10 14:55:24 +0100 | [diff] [blame] | 188 | .Lcopy: ldr r7,[r4] @ conditional copy |
| 189 | ldr r5,[r2] |
Robert Sloan | 8ff0355 | 2017-06-14 12:40:58 -0700 | [diff] [blame] | 190 | str sp,[r4],#4 @ zap tp |
Adam Vartanian | bfcf3a7 | 2018-08-10 14:55:24 +0100 | [diff] [blame] | 191 | #ifdef __thumb2__ |
| 192 | it cc |
| 193 | #endif |
| 194 | movcc r5,r7 |
| 195 | str r5,[r2],#4 |
| 196 | teq r4,r0 @ preserve carry |
Robert Sloan | 8ff0355 | 2017-06-14 12:40:58 -0700 | [diff] [blame] | 197 | bne .Lcopy |
| 198 | |
| 199 | mov sp,r0 |
| 200 | add sp,sp,#4 @ skip over tp[num+1] |
| 201 | ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} @ restore registers |
| 202 | add sp,sp,#2*4 @ skip over {r0,r2} |
| 203 | mov r0,#1 |
| 204 | .Labrt: |
| 205 | #if __ARM_ARCH__>=5 |
| 206 | bx lr @ bx lr |
| 207 | #else |
| 208 | tst lr,#1 |
| 209 | moveq pc,lr @ be binary compatible with V4, yet |
| 210 | .word 0xe12fff1e @ interoperable with Thumb ISA:-) |
| 211 | #endif |
| 212 | .size bn_mul_mont,.-bn_mul_mont |
| 213 | #if __ARM_MAX_ARCH__>=7 |
| 214 | .arch armv7-a |
| 215 | .fpu neon |
| 216 | |
| 217 | .type bn_mul8x_mont_neon,%function |
| 218 | .align 5 |
| 219 | bn_mul8x_mont_neon: |
| 220 | mov ip,sp |
| 221 | stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11} |
| 222 | vstmdb sp!,{d8,d9,d10,d11,d12,d13,d14,d15} @ ABI specification says so |
| 223 | ldmia ip,{r4,r5} @ load rest of parameter block |
| 224 | mov ip,sp |
| 225 | |
| 226 | cmp r5,#8 |
| 227 | bhi .LNEON_8n |
| 228 | |
| 229 | @ special case for r5==8, everything is in register bank... |
| 230 | |
| 231 | vld1.32 {d28[0]}, [r2,:32]! |
| 232 | veor d8,d8,d8 |
| 233 | sub r7,sp,r5,lsl#4 |
| 234 | vld1.32 {d0,d1,d2,d3}, [r1]! @ can't specify :32 :-( |
| 235 | and r7,r7,#-64 |
| 236 | vld1.32 {d30[0]}, [r4,:32] |
| 237 | mov sp,r7 @ alloca |
| 238 | vzip.16 d28,d8 |
| 239 | |
| 240 | vmull.u32 q6,d28,d0[0] |
| 241 | vmull.u32 q7,d28,d0[1] |
| 242 | vmull.u32 q8,d28,d1[0] |
| 243 | vshl.i64 d29,d13,#16 |
| 244 | vmull.u32 q9,d28,d1[1] |
| 245 | |
| 246 | vadd.u64 d29,d29,d12 |
| 247 | veor d8,d8,d8 |
| 248 | vmul.u32 d29,d29,d30 |
| 249 | |
| 250 | vmull.u32 q10,d28,d2[0] |
| 251 | vld1.32 {d4,d5,d6,d7}, [r3]! |
| 252 | vmull.u32 q11,d28,d2[1] |
| 253 | vmull.u32 q12,d28,d3[0] |
| 254 | vzip.16 d29,d8 |
| 255 | vmull.u32 q13,d28,d3[1] |
| 256 | |
| 257 | vmlal.u32 q6,d29,d4[0] |
| 258 | sub r9,r5,#1 |
| 259 | vmlal.u32 q7,d29,d4[1] |
| 260 | vmlal.u32 q8,d29,d5[0] |
| 261 | vmlal.u32 q9,d29,d5[1] |
| 262 | |
| 263 | vmlal.u32 q10,d29,d6[0] |
| 264 | vmov q5,q6 |
| 265 | vmlal.u32 q11,d29,d6[1] |
| 266 | vmov q6,q7 |
| 267 | vmlal.u32 q12,d29,d7[0] |
| 268 | vmov q7,q8 |
| 269 | vmlal.u32 q13,d29,d7[1] |
| 270 | vmov q8,q9 |
| 271 | vmov q9,q10 |
| 272 | vshr.u64 d10,d10,#16 |
| 273 | vmov q10,q11 |
| 274 | vmov q11,q12 |
| 275 | vadd.u64 d10,d10,d11 |
| 276 | vmov q12,q13 |
| 277 | veor q13,q13 |
| 278 | vshr.u64 d10,d10,#16 |
| 279 | |
| 280 | b .LNEON_outer8 |
| 281 | |
| 282 | .align 4 |
| 283 | .LNEON_outer8: |
| 284 | vld1.32 {d28[0]}, [r2,:32]! |
| 285 | veor d8,d8,d8 |
| 286 | vzip.16 d28,d8 |
| 287 | vadd.u64 d12,d12,d10 |
| 288 | |
| 289 | vmlal.u32 q6,d28,d0[0] |
| 290 | vmlal.u32 q7,d28,d0[1] |
| 291 | vmlal.u32 q8,d28,d1[0] |
| 292 | vshl.i64 d29,d13,#16 |
| 293 | vmlal.u32 q9,d28,d1[1] |
| 294 | |
| 295 | vadd.u64 d29,d29,d12 |
| 296 | veor d8,d8,d8 |
| 297 | subs r9,r9,#1 |
| 298 | vmul.u32 d29,d29,d30 |
| 299 | |
| 300 | vmlal.u32 q10,d28,d2[0] |
| 301 | vmlal.u32 q11,d28,d2[1] |
| 302 | vmlal.u32 q12,d28,d3[0] |
| 303 | vzip.16 d29,d8 |
| 304 | vmlal.u32 q13,d28,d3[1] |
| 305 | |
| 306 | vmlal.u32 q6,d29,d4[0] |
| 307 | vmlal.u32 q7,d29,d4[1] |
| 308 | vmlal.u32 q8,d29,d5[0] |
| 309 | vmlal.u32 q9,d29,d5[1] |
| 310 | |
| 311 | vmlal.u32 q10,d29,d6[0] |
| 312 | vmov q5,q6 |
| 313 | vmlal.u32 q11,d29,d6[1] |
| 314 | vmov q6,q7 |
| 315 | vmlal.u32 q12,d29,d7[0] |
| 316 | vmov q7,q8 |
| 317 | vmlal.u32 q13,d29,d7[1] |
| 318 | vmov q8,q9 |
| 319 | vmov q9,q10 |
| 320 | vshr.u64 d10,d10,#16 |
| 321 | vmov q10,q11 |
| 322 | vmov q11,q12 |
| 323 | vadd.u64 d10,d10,d11 |
| 324 | vmov q12,q13 |
| 325 | veor q13,q13 |
| 326 | vshr.u64 d10,d10,#16 |
| 327 | |
| 328 | bne .LNEON_outer8 |
| 329 | |
| 330 | vadd.u64 d12,d12,d10 |
| 331 | mov r7,sp |
| 332 | vshr.u64 d10,d12,#16 |
| 333 | mov r8,r5 |
| 334 | vadd.u64 d13,d13,d10 |
| 335 | add r6,sp,#96 |
| 336 | vshr.u64 d10,d13,#16 |
| 337 | vzip.16 d12,d13 |
| 338 | |
| 339 | b .LNEON_tail_entry |
| 340 | |
| 341 | .align 4 |
| 342 | .LNEON_8n: |
| 343 | veor q6,q6,q6 |
| 344 | sub r7,sp,#128 |
| 345 | veor q7,q7,q7 |
| 346 | sub r7,r7,r5,lsl#4 |
| 347 | veor q8,q8,q8 |
| 348 | and r7,r7,#-64 |
| 349 | veor q9,q9,q9 |
| 350 | mov sp,r7 @ alloca |
| 351 | veor q10,q10,q10 |
| 352 | add r7,r7,#256 |
| 353 | veor q11,q11,q11 |
| 354 | sub r8,r5,#8 |
| 355 | veor q12,q12,q12 |
| 356 | veor q13,q13,q13 |
| 357 | |
| 358 | .LNEON_8n_init: |
| 359 | vst1.64 {q6,q7},[r7,:256]! |
| 360 | subs r8,r8,#8 |
| 361 | vst1.64 {q8,q9},[r7,:256]! |
| 362 | vst1.64 {q10,q11},[r7,:256]! |
| 363 | vst1.64 {q12,q13},[r7,:256]! |
| 364 | bne .LNEON_8n_init |
| 365 | |
| 366 | add r6,sp,#256 |
| 367 | vld1.32 {d0,d1,d2,d3},[r1]! |
| 368 | add r10,sp,#8 |
| 369 | vld1.32 {d30[0]},[r4,:32] |
| 370 | mov r9,r5 |
| 371 | b .LNEON_8n_outer |
| 372 | |
| 373 | .align 4 |
| 374 | .LNEON_8n_outer: |
| 375 | vld1.32 {d28[0]},[r2,:32]! @ *b++ |
| 376 | veor d8,d8,d8 |
| 377 | vzip.16 d28,d8 |
| 378 | add r7,sp,#128 |
| 379 | vld1.32 {d4,d5,d6,d7},[r3]! |
| 380 | |
| 381 | vmlal.u32 q6,d28,d0[0] |
| 382 | vmlal.u32 q7,d28,d0[1] |
| 383 | veor d8,d8,d8 |
| 384 | vmlal.u32 q8,d28,d1[0] |
| 385 | vshl.i64 d29,d13,#16 |
| 386 | vmlal.u32 q9,d28,d1[1] |
| 387 | vadd.u64 d29,d29,d12 |
| 388 | vmlal.u32 q10,d28,d2[0] |
| 389 | vmul.u32 d29,d29,d30 |
| 390 | vmlal.u32 q11,d28,d2[1] |
| 391 | vst1.32 {d28},[sp,:64] @ put aside smashed b[8*i+0] |
| 392 | vmlal.u32 q12,d28,d3[0] |
| 393 | vzip.16 d29,d8 |
| 394 | vmlal.u32 q13,d28,d3[1] |
| 395 | vld1.32 {d28[0]},[r2,:32]! @ *b++ |
| 396 | vmlal.u32 q6,d29,d4[0] |
| 397 | veor d10,d10,d10 |
| 398 | vmlal.u32 q7,d29,d4[1] |
| 399 | vzip.16 d28,d10 |
| 400 | vmlal.u32 q8,d29,d5[0] |
| 401 | vshr.u64 d12,d12,#16 |
| 402 | vmlal.u32 q9,d29,d5[1] |
| 403 | vmlal.u32 q10,d29,d6[0] |
| 404 | vadd.u64 d12,d12,d13 |
| 405 | vmlal.u32 q11,d29,d6[1] |
| 406 | vshr.u64 d12,d12,#16 |
| 407 | vmlal.u32 q12,d29,d7[0] |
| 408 | vmlal.u32 q13,d29,d7[1] |
| 409 | vadd.u64 d14,d14,d12 |
| 410 | vst1.32 {d29},[r10,:64]! @ put aside smashed m[8*i+0] |
| 411 | vmlal.u32 q7,d28,d0[0] |
| 412 | vld1.64 {q6},[r6,:128]! |
| 413 | vmlal.u32 q8,d28,d0[1] |
| 414 | veor d8,d8,d8 |
| 415 | vmlal.u32 q9,d28,d1[0] |
| 416 | vshl.i64 d29,d15,#16 |
| 417 | vmlal.u32 q10,d28,d1[1] |
| 418 | vadd.u64 d29,d29,d14 |
| 419 | vmlal.u32 q11,d28,d2[0] |
| 420 | vmul.u32 d29,d29,d30 |
| 421 | vmlal.u32 q12,d28,d2[1] |
| 422 | vst1.32 {d28},[r10,:64]! @ put aside smashed b[8*i+1] |
| 423 | vmlal.u32 q13,d28,d3[0] |
| 424 | vzip.16 d29,d8 |
| 425 | vmlal.u32 q6,d28,d3[1] |
| 426 | vld1.32 {d28[0]},[r2,:32]! @ *b++ |
| 427 | vmlal.u32 q7,d29,d4[0] |
| 428 | veor d10,d10,d10 |
| 429 | vmlal.u32 q8,d29,d4[1] |
| 430 | vzip.16 d28,d10 |
| 431 | vmlal.u32 q9,d29,d5[0] |
| 432 | vshr.u64 d14,d14,#16 |
| 433 | vmlal.u32 q10,d29,d5[1] |
| 434 | vmlal.u32 q11,d29,d6[0] |
| 435 | vadd.u64 d14,d14,d15 |
| 436 | vmlal.u32 q12,d29,d6[1] |
| 437 | vshr.u64 d14,d14,#16 |
| 438 | vmlal.u32 q13,d29,d7[0] |
| 439 | vmlal.u32 q6,d29,d7[1] |
| 440 | vadd.u64 d16,d16,d14 |
| 441 | vst1.32 {d29},[r10,:64]! @ put aside smashed m[8*i+1] |
| 442 | vmlal.u32 q8,d28,d0[0] |
| 443 | vld1.64 {q7},[r6,:128]! |
| 444 | vmlal.u32 q9,d28,d0[1] |
| 445 | veor d8,d8,d8 |
| 446 | vmlal.u32 q10,d28,d1[0] |
| 447 | vshl.i64 d29,d17,#16 |
| 448 | vmlal.u32 q11,d28,d1[1] |
| 449 | vadd.u64 d29,d29,d16 |
| 450 | vmlal.u32 q12,d28,d2[0] |
| 451 | vmul.u32 d29,d29,d30 |
| 452 | vmlal.u32 q13,d28,d2[1] |
| 453 | vst1.32 {d28},[r10,:64]! @ put aside smashed b[8*i+2] |
| 454 | vmlal.u32 q6,d28,d3[0] |
| 455 | vzip.16 d29,d8 |
| 456 | vmlal.u32 q7,d28,d3[1] |
| 457 | vld1.32 {d28[0]},[r2,:32]! @ *b++ |
| 458 | vmlal.u32 q8,d29,d4[0] |
| 459 | veor d10,d10,d10 |
| 460 | vmlal.u32 q9,d29,d4[1] |
| 461 | vzip.16 d28,d10 |
| 462 | vmlal.u32 q10,d29,d5[0] |
| 463 | vshr.u64 d16,d16,#16 |
| 464 | vmlal.u32 q11,d29,d5[1] |
| 465 | vmlal.u32 q12,d29,d6[0] |
| 466 | vadd.u64 d16,d16,d17 |
| 467 | vmlal.u32 q13,d29,d6[1] |
| 468 | vshr.u64 d16,d16,#16 |
| 469 | vmlal.u32 q6,d29,d7[0] |
| 470 | vmlal.u32 q7,d29,d7[1] |
| 471 | vadd.u64 d18,d18,d16 |
| 472 | vst1.32 {d29},[r10,:64]! @ put aside smashed m[8*i+2] |
| 473 | vmlal.u32 q9,d28,d0[0] |
| 474 | vld1.64 {q8},[r6,:128]! |
| 475 | vmlal.u32 q10,d28,d0[1] |
| 476 | veor d8,d8,d8 |
| 477 | vmlal.u32 q11,d28,d1[0] |
| 478 | vshl.i64 d29,d19,#16 |
| 479 | vmlal.u32 q12,d28,d1[1] |
| 480 | vadd.u64 d29,d29,d18 |
| 481 | vmlal.u32 q13,d28,d2[0] |
| 482 | vmul.u32 d29,d29,d30 |
| 483 | vmlal.u32 q6,d28,d2[1] |
| 484 | vst1.32 {d28},[r10,:64]! @ put aside smashed b[8*i+3] |
| 485 | vmlal.u32 q7,d28,d3[0] |
| 486 | vzip.16 d29,d8 |
| 487 | vmlal.u32 q8,d28,d3[1] |
| 488 | vld1.32 {d28[0]},[r2,:32]! @ *b++ |
| 489 | vmlal.u32 q9,d29,d4[0] |
| 490 | veor d10,d10,d10 |
| 491 | vmlal.u32 q10,d29,d4[1] |
| 492 | vzip.16 d28,d10 |
| 493 | vmlal.u32 q11,d29,d5[0] |
| 494 | vshr.u64 d18,d18,#16 |
| 495 | vmlal.u32 q12,d29,d5[1] |
| 496 | vmlal.u32 q13,d29,d6[0] |
| 497 | vadd.u64 d18,d18,d19 |
| 498 | vmlal.u32 q6,d29,d6[1] |
| 499 | vshr.u64 d18,d18,#16 |
| 500 | vmlal.u32 q7,d29,d7[0] |
| 501 | vmlal.u32 q8,d29,d7[1] |
| 502 | vadd.u64 d20,d20,d18 |
| 503 | vst1.32 {d29},[r10,:64]! @ put aside smashed m[8*i+3] |
| 504 | vmlal.u32 q10,d28,d0[0] |
| 505 | vld1.64 {q9},[r6,:128]! |
| 506 | vmlal.u32 q11,d28,d0[1] |
| 507 | veor d8,d8,d8 |
| 508 | vmlal.u32 q12,d28,d1[0] |
| 509 | vshl.i64 d29,d21,#16 |
| 510 | vmlal.u32 q13,d28,d1[1] |
| 511 | vadd.u64 d29,d29,d20 |
| 512 | vmlal.u32 q6,d28,d2[0] |
| 513 | vmul.u32 d29,d29,d30 |
| 514 | vmlal.u32 q7,d28,d2[1] |
| 515 | vst1.32 {d28},[r10,:64]! @ put aside smashed b[8*i+4] |
| 516 | vmlal.u32 q8,d28,d3[0] |
| 517 | vzip.16 d29,d8 |
| 518 | vmlal.u32 q9,d28,d3[1] |
| 519 | vld1.32 {d28[0]},[r2,:32]! @ *b++ |
| 520 | vmlal.u32 q10,d29,d4[0] |
| 521 | veor d10,d10,d10 |
| 522 | vmlal.u32 q11,d29,d4[1] |
| 523 | vzip.16 d28,d10 |
| 524 | vmlal.u32 q12,d29,d5[0] |
| 525 | vshr.u64 d20,d20,#16 |
| 526 | vmlal.u32 q13,d29,d5[1] |
| 527 | vmlal.u32 q6,d29,d6[0] |
| 528 | vadd.u64 d20,d20,d21 |
| 529 | vmlal.u32 q7,d29,d6[1] |
| 530 | vshr.u64 d20,d20,#16 |
| 531 | vmlal.u32 q8,d29,d7[0] |
| 532 | vmlal.u32 q9,d29,d7[1] |
| 533 | vadd.u64 d22,d22,d20 |
| 534 | vst1.32 {d29},[r10,:64]! @ put aside smashed m[8*i+4] |
| 535 | vmlal.u32 q11,d28,d0[0] |
| 536 | vld1.64 {q10},[r6,:128]! |
| 537 | vmlal.u32 q12,d28,d0[1] |
| 538 | veor d8,d8,d8 |
| 539 | vmlal.u32 q13,d28,d1[0] |
| 540 | vshl.i64 d29,d23,#16 |
| 541 | vmlal.u32 q6,d28,d1[1] |
| 542 | vadd.u64 d29,d29,d22 |
| 543 | vmlal.u32 q7,d28,d2[0] |
| 544 | vmul.u32 d29,d29,d30 |
| 545 | vmlal.u32 q8,d28,d2[1] |
| 546 | vst1.32 {d28},[r10,:64]! @ put aside smashed b[8*i+5] |
| 547 | vmlal.u32 q9,d28,d3[0] |
| 548 | vzip.16 d29,d8 |
| 549 | vmlal.u32 q10,d28,d3[1] |
| 550 | vld1.32 {d28[0]},[r2,:32]! @ *b++ |
| 551 | vmlal.u32 q11,d29,d4[0] |
| 552 | veor d10,d10,d10 |
| 553 | vmlal.u32 q12,d29,d4[1] |
| 554 | vzip.16 d28,d10 |
| 555 | vmlal.u32 q13,d29,d5[0] |
| 556 | vshr.u64 d22,d22,#16 |
| 557 | vmlal.u32 q6,d29,d5[1] |
| 558 | vmlal.u32 q7,d29,d6[0] |
| 559 | vadd.u64 d22,d22,d23 |
| 560 | vmlal.u32 q8,d29,d6[1] |
| 561 | vshr.u64 d22,d22,#16 |
| 562 | vmlal.u32 q9,d29,d7[0] |
| 563 | vmlal.u32 q10,d29,d7[1] |
| 564 | vadd.u64 d24,d24,d22 |
| 565 | vst1.32 {d29},[r10,:64]! @ put aside smashed m[8*i+5] |
| 566 | vmlal.u32 q12,d28,d0[0] |
| 567 | vld1.64 {q11},[r6,:128]! |
| 568 | vmlal.u32 q13,d28,d0[1] |
| 569 | veor d8,d8,d8 |
| 570 | vmlal.u32 q6,d28,d1[0] |
| 571 | vshl.i64 d29,d25,#16 |
| 572 | vmlal.u32 q7,d28,d1[1] |
| 573 | vadd.u64 d29,d29,d24 |
| 574 | vmlal.u32 q8,d28,d2[0] |
| 575 | vmul.u32 d29,d29,d30 |
| 576 | vmlal.u32 q9,d28,d2[1] |
| 577 | vst1.32 {d28},[r10,:64]! @ put aside smashed b[8*i+6] |
| 578 | vmlal.u32 q10,d28,d3[0] |
| 579 | vzip.16 d29,d8 |
| 580 | vmlal.u32 q11,d28,d3[1] |
| 581 | vld1.32 {d28[0]},[r2,:32]! @ *b++ |
| 582 | vmlal.u32 q12,d29,d4[0] |
| 583 | veor d10,d10,d10 |
| 584 | vmlal.u32 q13,d29,d4[1] |
| 585 | vzip.16 d28,d10 |
| 586 | vmlal.u32 q6,d29,d5[0] |
| 587 | vshr.u64 d24,d24,#16 |
| 588 | vmlal.u32 q7,d29,d5[1] |
| 589 | vmlal.u32 q8,d29,d6[0] |
| 590 | vadd.u64 d24,d24,d25 |
| 591 | vmlal.u32 q9,d29,d6[1] |
| 592 | vshr.u64 d24,d24,#16 |
| 593 | vmlal.u32 q10,d29,d7[0] |
| 594 | vmlal.u32 q11,d29,d7[1] |
| 595 | vadd.u64 d26,d26,d24 |
| 596 | vst1.32 {d29},[r10,:64]! @ put aside smashed m[8*i+6] |
| 597 | vmlal.u32 q13,d28,d0[0] |
| 598 | vld1.64 {q12},[r6,:128]! |
| 599 | vmlal.u32 q6,d28,d0[1] |
| 600 | veor d8,d8,d8 |
| 601 | vmlal.u32 q7,d28,d1[0] |
| 602 | vshl.i64 d29,d27,#16 |
| 603 | vmlal.u32 q8,d28,d1[1] |
| 604 | vadd.u64 d29,d29,d26 |
| 605 | vmlal.u32 q9,d28,d2[0] |
| 606 | vmul.u32 d29,d29,d30 |
| 607 | vmlal.u32 q10,d28,d2[1] |
| 608 | vst1.32 {d28},[r10,:64]! @ put aside smashed b[8*i+7] |
| 609 | vmlal.u32 q11,d28,d3[0] |
| 610 | vzip.16 d29,d8 |
| 611 | vmlal.u32 q12,d28,d3[1] |
| 612 | vld1.32 {d28},[sp,:64] @ pull smashed b[8*i+0] |
| 613 | vmlal.u32 q13,d29,d4[0] |
| 614 | vld1.32 {d0,d1,d2,d3},[r1]! |
| 615 | vmlal.u32 q6,d29,d4[1] |
| 616 | vmlal.u32 q7,d29,d5[0] |
| 617 | vshr.u64 d26,d26,#16 |
| 618 | vmlal.u32 q8,d29,d5[1] |
| 619 | vmlal.u32 q9,d29,d6[0] |
| 620 | vadd.u64 d26,d26,d27 |
| 621 | vmlal.u32 q10,d29,d6[1] |
| 622 | vshr.u64 d26,d26,#16 |
| 623 | vmlal.u32 q11,d29,d7[0] |
| 624 | vmlal.u32 q12,d29,d7[1] |
| 625 | vadd.u64 d12,d12,d26 |
| 626 | vst1.32 {d29},[r10,:64] @ put aside smashed m[8*i+7] |
| 627 | add r10,sp,#8 @ rewind |
| 628 | sub r8,r5,#8 |
| 629 | b .LNEON_8n_inner |
| 630 | |
| 631 | .align 4 |
| 632 | .LNEON_8n_inner: |
| 633 | subs r8,r8,#8 |
| 634 | vmlal.u32 q6,d28,d0[0] |
| 635 | vld1.64 {q13},[r6,:128] |
| 636 | vmlal.u32 q7,d28,d0[1] |
| 637 | vld1.32 {d29},[r10,:64]! @ pull smashed m[8*i+0] |
| 638 | vmlal.u32 q8,d28,d1[0] |
| 639 | vld1.32 {d4,d5,d6,d7},[r3]! |
| 640 | vmlal.u32 q9,d28,d1[1] |
| 641 | it ne |
| 642 | addne r6,r6,#16 @ don't advance in last iteration |
| 643 | vmlal.u32 q10,d28,d2[0] |
| 644 | vmlal.u32 q11,d28,d2[1] |
| 645 | vmlal.u32 q12,d28,d3[0] |
| 646 | vmlal.u32 q13,d28,d3[1] |
| 647 | vld1.32 {d28},[r10,:64]! @ pull smashed b[8*i+1] |
| 648 | vmlal.u32 q6,d29,d4[0] |
| 649 | vmlal.u32 q7,d29,d4[1] |
| 650 | vmlal.u32 q8,d29,d5[0] |
| 651 | vmlal.u32 q9,d29,d5[1] |
| 652 | vmlal.u32 q10,d29,d6[0] |
| 653 | vmlal.u32 q11,d29,d6[1] |
| 654 | vmlal.u32 q12,d29,d7[0] |
| 655 | vmlal.u32 q13,d29,d7[1] |
| 656 | vst1.64 {q6},[r7,:128]! |
| 657 | vmlal.u32 q7,d28,d0[0] |
| 658 | vld1.64 {q6},[r6,:128] |
| 659 | vmlal.u32 q8,d28,d0[1] |
| 660 | vld1.32 {d29},[r10,:64]! @ pull smashed m[8*i+1] |
| 661 | vmlal.u32 q9,d28,d1[0] |
| 662 | it ne |
| 663 | addne r6,r6,#16 @ don't advance in last iteration |
| 664 | vmlal.u32 q10,d28,d1[1] |
| 665 | vmlal.u32 q11,d28,d2[0] |
| 666 | vmlal.u32 q12,d28,d2[1] |
| 667 | vmlal.u32 q13,d28,d3[0] |
| 668 | vmlal.u32 q6,d28,d3[1] |
| 669 | vld1.32 {d28},[r10,:64]! @ pull smashed b[8*i+2] |
| 670 | vmlal.u32 q7,d29,d4[0] |
| 671 | vmlal.u32 q8,d29,d4[1] |
| 672 | vmlal.u32 q9,d29,d5[0] |
| 673 | vmlal.u32 q10,d29,d5[1] |
| 674 | vmlal.u32 q11,d29,d6[0] |
| 675 | vmlal.u32 q12,d29,d6[1] |
| 676 | vmlal.u32 q13,d29,d7[0] |
| 677 | vmlal.u32 q6,d29,d7[1] |
| 678 | vst1.64 {q7},[r7,:128]! |
| 679 | vmlal.u32 q8,d28,d0[0] |
| 680 | vld1.64 {q7},[r6,:128] |
| 681 | vmlal.u32 q9,d28,d0[1] |
| 682 | vld1.32 {d29},[r10,:64]! @ pull smashed m[8*i+2] |
| 683 | vmlal.u32 q10,d28,d1[0] |
| 684 | it ne |
| 685 | addne r6,r6,#16 @ don't advance in last iteration |
| 686 | vmlal.u32 q11,d28,d1[1] |
| 687 | vmlal.u32 q12,d28,d2[0] |
| 688 | vmlal.u32 q13,d28,d2[1] |
| 689 | vmlal.u32 q6,d28,d3[0] |
| 690 | vmlal.u32 q7,d28,d3[1] |
| 691 | vld1.32 {d28},[r10,:64]! @ pull smashed b[8*i+3] |
| 692 | vmlal.u32 q8,d29,d4[0] |
| 693 | vmlal.u32 q9,d29,d4[1] |
| 694 | vmlal.u32 q10,d29,d5[0] |
| 695 | vmlal.u32 q11,d29,d5[1] |
| 696 | vmlal.u32 q12,d29,d6[0] |
| 697 | vmlal.u32 q13,d29,d6[1] |
| 698 | vmlal.u32 q6,d29,d7[0] |
| 699 | vmlal.u32 q7,d29,d7[1] |
| 700 | vst1.64 {q8},[r7,:128]! |
| 701 | vmlal.u32 q9,d28,d0[0] |
| 702 | vld1.64 {q8},[r6,:128] |
| 703 | vmlal.u32 q10,d28,d0[1] |
| 704 | vld1.32 {d29},[r10,:64]! @ pull smashed m[8*i+3] |
| 705 | vmlal.u32 q11,d28,d1[0] |
| 706 | it ne |
| 707 | addne r6,r6,#16 @ don't advance in last iteration |
| 708 | vmlal.u32 q12,d28,d1[1] |
| 709 | vmlal.u32 q13,d28,d2[0] |
| 710 | vmlal.u32 q6,d28,d2[1] |
| 711 | vmlal.u32 q7,d28,d3[0] |
| 712 | vmlal.u32 q8,d28,d3[1] |
| 713 | vld1.32 {d28},[r10,:64]! @ pull smashed b[8*i+4] |
| 714 | vmlal.u32 q9,d29,d4[0] |
| 715 | vmlal.u32 q10,d29,d4[1] |
| 716 | vmlal.u32 q11,d29,d5[0] |
| 717 | vmlal.u32 q12,d29,d5[1] |
| 718 | vmlal.u32 q13,d29,d6[0] |
| 719 | vmlal.u32 q6,d29,d6[1] |
| 720 | vmlal.u32 q7,d29,d7[0] |
| 721 | vmlal.u32 q8,d29,d7[1] |
| 722 | vst1.64 {q9},[r7,:128]! |
| 723 | vmlal.u32 q10,d28,d0[0] |
| 724 | vld1.64 {q9},[r6,:128] |
| 725 | vmlal.u32 q11,d28,d0[1] |
| 726 | vld1.32 {d29},[r10,:64]! @ pull smashed m[8*i+4] |
| 727 | vmlal.u32 q12,d28,d1[0] |
| 728 | it ne |
| 729 | addne r6,r6,#16 @ don't advance in last iteration |
| 730 | vmlal.u32 q13,d28,d1[1] |
| 731 | vmlal.u32 q6,d28,d2[0] |
| 732 | vmlal.u32 q7,d28,d2[1] |
| 733 | vmlal.u32 q8,d28,d3[0] |
| 734 | vmlal.u32 q9,d28,d3[1] |
| 735 | vld1.32 {d28},[r10,:64]! @ pull smashed b[8*i+5] |
| 736 | vmlal.u32 q10,d29,d4[0] |
| 737 | vmlal.u32 q11,d29,d4[1] |
| 738 | vmlal.u32 q12,d29,d5[0] |
| 739 | vmlal.u32 q13,d29,d5[1] |
| 740 | vmlal.u32 q6,d29,d6[0] |
| 741 | vmlal.u32 q7,d29,d6[1] |
| 742 | vmlal.u32 q8,d29,d7[0] |
| 743 | vmlal.u32 q9,d29,d7[1] |
| 744 | vst1.64 {q10},[r7,:128]! |
| 745 | vmlal.u32 q11,d28,d0[0] |
| 746 | vld1.64 {q10},[r6,:128] |
| 747 | vmlal.u32 q12,d28,d0[1] |
| 748 | vld1.32 {d29},[r10,:64]! @ pull smashed m[8*i+5] |
| 749 | vmlal.u32 q13,d28,d1[0] |
| 750 | it ne |
| 751 | addne r6,r6,#16 @ don't advance in last iteration |
| 752 | vmlal.u32 q6,d28,d1[1] |
| 753 | vmlal.u32 q7,d28,d2[0] |
| 754 | vmlal.u32 q8,d28,d2[1] |
| 755 | vmlal.u32 q9,d28,d3[0] |
| 756 | vmlal.u32 q10,d28,d3[1] |
| 757 | vld1.32 {d28},[r10,:64]! @ pull smashed b[8*i+6] |
| 758 | vmlal.u32 q11,d29,d4[0] |
| 759 | vmlal.u32 q12,d29,d4[1] |
| 760 | vmlal.u32 q13,d29,d5[0] |
| 761 | vmlal.u32 q6,d29,d5[1] |
| 762 | vmlal.u32 q7,d29,d6[0] |
| 763 | vmlal.u32 q8,d29,d6[1] |
| 764 | vmlal.u32 q9,d29,d7[0] |
| 765 | vmlal.u32 q10,d29,d7[1] |
| 766 | vst1.64 {q11},[r7,:128]! |
| 767 | vmlal.u32 q12,d28,d0[0] |
| 768 | vld1.64 {q11},[r6,:128] |
| 769 | vmlal.u32 q13,d28,d0[1] |
| 770 | vld1.32 {d29},[r10,:64]! @ pull smashed m[8*i+6] |
| 771 | vmlal.u32 q6,d28,d1[0] |
| 772 | it ne |
| 773 | addne r6,r6,#16 @ don't advance in last iteration |
| 774 | vmlal.u32 q7,d28,d1[1] |
| 775 | vmlal.u32 q8,d28,d2[0] |
| 776 | vmlal.u32 q9,d28,d2[1] |
| 777 | vmlal.u32 q10,d28,d3[0] |
| 778 | vmlal.u32 q11,d28,d3[1] |
| 779 | vld1.32 {d28},[r10,:64]! @ pull smashed b[8*i+7] |
| 780 | vmlal.u32 q12,d29,d4[0] |
| 781 | vmlal.u32 q13,d29,d4[1] |
| 782 | vmlal.u32 q6,d29,d5[0] |
| 783 | vmlal.u32 q7,d29,d5[1] |
| 784 | vmlal.u32 q8,d29,d6[0] |
| 785 | vmlal.u32 q9,d29,d6[1] |
| 786 | vmlal.u32 q10,d29,d7[0] |
| 787 | vmlal.u32 q11,d29,d7[1] |
| 788 | vst1.64 {q12},[r7,:128]! |
| 789 | vmlal.u32 q13,d28,d0[0] |
| 790 | vld1.64 {q12},[r6,:128] |
| 791 | vmlal.u32 q6,d28,d0[1] |
| 792 | vld1.32 {d29},[r10,:64]! @ pull smashed m[8*i+7] |
| 793 | vmlal.u32 q7,d28,d1[0] |
| 794 | it ne |
| 795 | addne r6,r6,#16 @ don't advance in last iteration |
| 796 | vmlal.u32 q8,d28,d1[1] |
| 797 | vmlal.u32 q9,d28,d2[0] |
| 798 | vmlal.u32 q10,d28,d2[1] |
| 799 | vmlal.u32 q11,d28,d3[0] |
| 800 | vmlal.u32 q12,d28,d3[1] |
| 801 | it eq |
| 802 | subeq r1,r1,r5,lsl#2 @ rewind |
| 803 | vmlal.u32 q13,d29,d4[0] |
| 804 | vld1.32 {d28},[sp,:64] @ pull smashed b[8*i+0] |
| 805 | vmlal.u32 q6,d29,d4[1] |
| 806 | vld1.32 {d0,d1,d2,d3},[r1]! |
| 807 | vmlal.u32 q7,d29,d5[0] |
| 808 | add r10,sp,#8 @ rewind |
| 809 | vmlal.u32 q8,d29,d5[1] |
| 810 | vmlal.u32 q9,d29,d6[0] |
| 811 | vmlal.u32 q10,d29,d6[1] |
| 812 | vmlal.u32 q11,d29,d7[0] |
| 813 | vst1.64 {q13},[r7,:128]! |
| 814 | vmlal.u32 q12,d29,d7[1] |
| 815 | |
| 816 | bne .LNEON_8n_inner |
| 817 | add r6,sp,#128 |
| 818 | vst1.64 {q6,q7},[r7,:256]! |
| 819 | veor q2,q2,q2 @ d4-d5 |
| 820 | vst1.64 {q8,q9},[r7,:256]! |
| 821 | veor q3,q3,q3 @ d6-d7 |
| 822 | vst1.64 {q10,q11},[r7,:256]! |
| 823 | vst1.64 {q12},[r7,:128] |
| 824 | |
| 825 | subs r9,r9,#8 |
| 826 | vld1.64 {q6,q7},[r6,:256]! |
| 827 | vld1.64 {q8,q9},[r6,:256]! |
| 828 | vld1.64 {q10,q11},[r6,:256]! |
| 829 | vld1.64 {q12,q13},[r6,:256]! |
| 830 | |
| 831 | itt ne |
| 832 | subne r3,r3,r5,lsl#2 @ rewind |
| 833 | bne .LNEON_8n_outer |
| 834 | |
| 835 | add r7,sp,#128 |
| 836 | vst1.64 {q2,q3}, [sp,:256]! @ start wiping stack frame |
| 837 | vshr.u64 d10,d12,#16 |
| 838 | vst1.64 {q2,q3},[sp,:256]! |
| 839 | vadd.u64 d13,d13,d10 |
| 840 | vst1.64 {q2,q3}, [sp,:256]! |
| 841 | vshr.u64 d10,d13,#16 |
| 842 | vst1.64 {q2,q3}, [sp,:256]! |
| 843 | vzip.16 d12,d13 |
| 844 | |
| 845 | mov r8,r5 |
| 846 | b .LNEON_tail_entry |
| 847 | |
| 848 | .align 4 |
| 849 | .LNEON_tail: |
| 850 | vadd.u64 d12,d12,d10 |
| 851 | vshr.u64 d10,d12,#16 |
| 852 | vld1.64 {q8,q9}, [r6, :256]! |
| 853 | vadd.u64 d13,d13,d10 |
| 854 | vld1.64 {q10,q11}, [r6, :256]! |
| 855 | vshr.u64 d10,d13,#16 |
| 856 | vld1.64 {q12,q13}, [r6, :256]! |
| 857 | vzip.16 d12,d13 |
| 858 | |
| 859 | .LNEON_tail_entry: |
| 860 | vadd.u64 d14,d14,d10 |
| 861 | vst1.32 {d12[0]}, [r7, :32]! |
| 862 | vshr.u64 d10,d14,#16 |
| 863 | vadd.u64 d15,d15,d10 |
| 864 | vshr.u64 d10,d15,#16 |
| 865 | vzip.16 d14,d15 |
| 866 | vadd.u64 d16,d16,d10 |
| 867 | vst1.32 {d14[0]}, [r7, :32]! |
| 868 | vshr.u64 d10,d16,#16 |
| 869 | vadd.u64 d17,d17,d10 |
| 870 | vshr.u64 d10,d17,#16 |
| 871 | vzip.16 d16,d17 |
| 872 | vadd.u64 d18,d18,d10 |
| 873 | vst1.32 {d16[0]}, [r7, :32]! |
| 874 | vshr.u64 d10,d18,#16 |
| 875 | vadd.u64 d19,d19,d10 |
| 876 | vshr.u64 d10,d19,#16 |
| 877 | vzip.16 d18,d19 |
| 878 | vadd.u64 d20,d20,d10 |
| 879 | vst1.32 {d18[0]}, [r7, :32]! |
| 880 | vshr.u64 d10,d20,#16 |
| 881 | vadd.u64 d21,d21,d10 |
| 882 | vshr.u64 d10,d21,#16 |
| 883 | vzip.16 d20,d21 |
| 884 | vadd.u64 d22,d22,d10 |
| 885 | vst1.32 {d20[0]}, [r7, :32]! |
| 886 | vshr.u64 d10,d22,#16 |
| 887 | vadd.u64 d23,d23,d10 |
| 888 | vshr.u64 d10,d23,#16 |
| 889 | vzip.16 d22,d23 |
| 890 | vadd.u64 d24,d24,d10 |
| 891 | vst1.32 {d22[0]}, [r7, :32]! |
| 892 | vshr.u64 d10,d24,#16 |
| 893 | vadd.u64 d25,d25,d10 |
| 894 | vshr.u64 d10,d25,#16 |
| 895 | vzip.16 d24,d25 |
| 896 | vadd.u64 d26,d26,d10 |
| 897 | vst1.32 {d24[0]}, [r7, :32]! |
| 898 | vshr.u64 d10,d26,#16 |
| 899 | vadd.u64 d27,d27,d10 |
| 900 | vshr.u64 d10,d27,#16 |
| 901 | vzip.16 d26,d27 |
| 902 | vld1.64 {q6,q7}, [r6, :256]! |
| 903 | subs r8,r8,#8 |
| 904 | vst1.32 {d26[0]}, [r7, :32]! |
| 905 | bne .LNEON_tail |
| 906 | |
| 907 | vst1.32 {d10[0]}, [r7, :32] @ top-most bit |
| 908 | sub r3,r3,r5,lsl#2 @ rewind r3 |
| 909 | subs r1,sp,#0 @ clear carry flag |
| 910 | add r2,sp,r5,lsl#2 |
| 911 | |
| 912 | .LNEON_sub: |
| 913 | ldmia r1!, {r4,r5,r6,r7} |
| 914 | ldmia r3!, {r8,r9,r10,r11} |
| 915 | sbcs r8, r4,r8 |
| 916 | sbcs r9, r5,r9 |
| 917 | sbcs r10,r6,r10 |
| 918 | sbcs r11,r7,r11 |
| 919 | teq r1,r2 @ preserves carry |
| 920 | stmia r0!, {r8,r9,r10,r11} |
| 921 | bne .LNEON_sub |
| 922 | |
| 923 | ldr r10, [r1] @ load top-most bit |
| 924 | mov r11,sp |
| 925 | veor q0,q0,q0 |
| 926 | sub r11,r2,r11 @ this is num*4 |
| 927 | veor q1,q1,q1 |
| 928 | mov r1,sp |
| 929 | sub r0,r0,r11 @ rewind r0 |
| 930 | mov r3,r2 @ second 3/4th of frame |
| 931 | sbcs r10,r10,#0 @ result is carry flag |
| 932 | |
| 933 | .LNEON_copy_n_zap: |
| 934 | ldmia r1!, {r4,r5,r6,r7} |
| 935 | ldmia r0, {r8,r9,r10,r11} |
| 936 | it cc |
| 937 | movcc r8, r4 |
| 938 | vst1.64 {q0,q1}, [r3,:256]! @ wipe |
| 939 | itt cc |
| 940 | movcc r9, r5 |
| 941 | movcc r10,r6 |
| 942 | vst1.64 {q0,q1}, [r3,:256]! @ wipe |
| 943 | it cc |
| 944 | movcc r11,r7 |
| 945 | ldmia r1, {r4,r5,r6,r7} |
| 946 | stmia r0!, {r8,r9,r10,r11} |
| 947 | sub r1,r1,#16 |
| 948 | ldmia r0, {r8,r9,r10,r11} |
| 949 | it cc |
| 950 | movcc r8, r4 |
| 951 | vst1.64 {q0,q1}, [r1,:256]! @ wipe |
| 952 | itt cc |
| 953 | movcc r9, r5 |
| 954 | movcc r10,r6 |
| 955 | vst1.64 {q0,q1}, [r3,:256]! @ wipe |
| 956 | it cc |
| 957 | movcc r11,r7 |
| 958 | teq r1,r2 @ preserves carry |
| 959 | stmia r0!, {r8,r9,r10,r11} |
| 960 | bne .LNEON_copy_n_zap |
| 961 | |
| 962 | mov sp,ip |
| 963 | vldmia sp!,{d8,d9,d10,d11,d12,d13,d14,d15} |
| 964 | ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11} |
| 965 | bx lr @ bx lr |
| 966 | .size bn_mul8x_mont_neon,.-bn_mul8x_mont_neon |
| 967 | #endif |
| 968 | .byte 77,111,110,116,103,111,109,101,114,121,32,109,117,108,116,105,112,108,105,99,97,116,105,111,110,32,102,111,114,32,65,82,77,118,52,47,78,69,79,78,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0 |
| 969 | .align 2 |
| 970 | .align 2 |
| 971 | #if __ARM_MAX_ARCH__>=7 |
| 972 | .comm OPENSSL_armcap_P,4,4 |
| 973 | .hidden OPENSSL_armcap_P |
| 974 | #endif |
| 975 | #endif |
Robert Sloan | 726e9d1 | 2018-09-11 11:45:04 -0700 | [diff] [blame] | 976 | #endif // !OPENSSL_NO_ASM |