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Adam Langleyd9e397b2015-01-22 14:27:53 -08001/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
2 * All rights reserved.
3 *
4 * This package is an SSL implementation written
5 * by Eric Young (eay@cryptsoft.com).
6 * The implementation was written so as to conform with Netscapes SSL.
7 *
8 * This library is free for commercial and non-commercial use as long as
9 * the following conditions are aheared to. The following conditions
10 * apply to all code found in this distribution, be it the RC4, RSA,
11 * lhash, DES, etc., code; not just the SSL code. The SSL documentation
12 * included with this distribution is covered by the same copyright terms
13 * except that the holder is Tim Hudson (tjh@cryptsoft.com).
14 *
15 * Copyright remains Eric Young's, and as such any Copyright notices in
16 * the code are not to be removed.
17 * If this package is used in a product, Eric Young should be given attribution
18 * as the author of the parts of the library used.
19 * This can be in the form of a textual message at program startup or
20 * in documentation (online or textual) provided with the package.
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions
24 * are met:
25 * 1. Redistributions of source code must retain the copyright
26 * notice, this list of conditions and the following disclaimer.
27 * 2. Redistributions in binary form must reproduce the above copyright
28 * notice, this list of conditions and the following disclaimer in the
29 * documentation and/or other materials provided with the distribution.
30 * 3. All advertising materials mentioning features or use of this software
31 * must display the following acknowledgement:
32 * "This product includes cryptographic software written by
33 * Eric Young (eay@cryptsoft.com)"
34 * The word 'cryptographic' can be left out if the rouines from the library
35 * being used are not cryptographic related :-).
36 * 4. If you include any Windows specific code (or a derivative thereof) from
37 * the apps directory (application code) you must include an acknowledgement:
38 * "This product includes software written by Tim Hudson (tjh@cryptsoft.com)"
39 *
40 * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
50 * SUCH DAMAGE.
51 *
52 * The licence and distribution terms for any publically available version or
53 * derivative of this code cannot be changed. i.e. this code cannot simply be
54 * copied and put under another distribution licence
55 * [including the GNU Public Licence.] */
56
Adam Langleyd9e397b2015-01-22 14:27:53 -080057#include <openssl/cpu.h>
58
59
60#if !defined(OPENSSL_NO_ASM) && (defined(OPENSSL_X86) || defined(OPENSSL_X86_64))
61
62#include <inttypes.h>
Adam Langleyd9e397b2015-01-22 14:27:53 -080063#include <stdio.h>
David Benjamin4969cc92016-04-22 15:02:23 -040064#include <stdlib.h>
Adam Langleyd9e397b2015-01-22 14:27:53 -080065#include <string.h>
66
Robert Sloan8f860b12017-08-28 07:37:06 -070067#if defined(_MSC_VER)
David Benjamin6e899c72016-06-09 18:02:18 -040068OPENSSL_MSVC_PRAGMA(warning(push, 3))
Kenny Rootb8494592015-09-25 02:29:14 +000069#include <immintrin.h>
70#include <intrin.h>
David Benjamin6e899c72016-06-09 18:02:18 -040071OPENSSL_MSVC_PRAGMA(warning(pop))
Kenny Rootb8494592015-09-25 02:29:14 +000072#endif
73
David Benjamin4969cc92016-04-22 15:02:23 -040074#include "internal.h"
75
Kenny Rootb8494592015-09-25 02:29:14 +000076
Robert Sloan8f860b12017-08-28 07:37:06 -070077// OPENSSL_cpuid runs the cpuid instruction. |leaf| is passed in as EAX and ECX
78// is set to zero. It writes EAX, EBX, ECX, and EDX to |*out_eax| through
79// |*out_edx|.
Kenny Rootb8494592015-09-25 02:29:14 +000080static void OPENSSL_cpuid(uint32_t *out_eax, uint32_t *out_ebx,
81 uint32_t *out_ecx, uint32_t *out_edx, uint32_t leaf) {
Robert Sloan8f860b12017-08-28 07:37:06 -070082#if defined(_MSC_VER)
Kenny Rootb8494592015-09-25 02:29:14 +000083 int tmp[4];
84 __cpuid(tmp, (int)leaf);
85 *out_eax = (uint32_t)tmp[0];
86 *out_ebx = (uint32_t)tmp[1];
87 *out_ecx = (uint32_t)tmp[2];
88 *out_edx = (uint32_t)tmp[3];
89#elif defined(__pic__) && defined(OPENSSL_32_BIT)
Robert Sloan8f860b12017-08-28 07:37:06 -070090 // Inline assembly may not clobber the PIC register. For 32-bit, this is EBX.
91 // See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=47602.
Kenny Rootb8494592015-09-25 02:29:14 +000092 __asm__ volatile (
93 "xor %%ecx, %%ecx\n"
94 "mov %%ebx, %%edi\n"
95 "cpuid\n"
96 "xchg %%edi, %%ebx\n"
97 : "=a"(*out_eax), "=D"(*out_ebx), "=c"(*out_ecx), "=d"(*out_edx)
98 : "a"(leaf)
99 );
100#else
101 __asm__ volatile (
102 "xor %%ecx, %%ecx\n"
103 "cpuid\n"
104 : "=a"(*out_eax), "=b"(*out_ebx), "=c"(*out_ecx), "=d"(*out_edx)
105 : "a"(leaf)
106 );
107#endif
108}
109
Robert Sloan8f860b12017-08-28 07:37:06 -0700110// OPENSSL_xgetbv returns the value of an Intel Extended Control Register (XCR).
111// Currently only XCR0 is defined by Intel so |xcr| should always be zero.
Kenny Rootb8494592015-09-25 02:29:14 +0000112static uint64_t OPENSSL_xgetbv(uint32_t xcr) {
Robert Sloan8f860b12017-08-28 07:37:06 -0700113#if defined(_MSC_VER)
Kenny Rootb8494592015-09-25 02:29:14 +0000114 return (uint64_t)_xgetbv(xcr);
115#else
116 uint32_t eax, edx;
117 __asm__ volatile ("xgetbv" : "=a"(eax), "=d"(edx) : "c"(xcr));
118 return (((uint64_t)edx) << 32) | eax;
119#endif
120}
Adam Langleyd9e397b2015-01-22 14:27:53 -0800121
Robert Sloan8f860b12017-08-28 07:37:06 -0700122// handle_cpu_env applies the value from |in| to the CPUID values in |out[0]|
123// and |out[1]|. See the comment in |OPENSSL_cpuid_setup| about this.
Adam Langleyd9e397b2015-01-22 14:27:53 -0800124static void handle_cpu_env(uint32_t *out, const char *in) {
125 const int invert = in[0] == '~';
126 uint64_t v;
127
David Benjamin4969cc92016-04-22 15:02:23 -0400128 if (!sscanf(in + invert, "%" PRIu64, &v)) {
Adam Langleyd9e397b2015-01-22 14:27:53 -0800129 return;
130 }
131
132 if (invert) {
133 out[0] &= ~v;
134 out[1] &= ~(v >> 32);
135 } else {
136 out[0] = v;
137 out[1] = v >> 32;
138 }
139}
140
141void OPENSSL_cpuid_setup(void) {
Robert Sloan8f860b12017-08-28 07:37:06 -0700142 // Determine the vendor and maximum input value.
Kenny Rootb8494592015-09-25 02:29:14 +0000143 uint32_t eax, ebx, ecx, edx;
144 OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 0);
145
146 uint32_t num_ids = eax;
147
148 int is_intel = ebx == 0x756e6547 /* Genu */ &&
149 edx == 0x49656e69 /* ineI */ &&
150 ecx == 0x6c65746e /* ntel */;
Kenny Rootb8494592015-09-25 02:29:14 +0000151
Robert Sloan5cbb5c82018-04-24 11:35:46 -0700152 uint32_t extended_features[2] = {0};
Kenny Rootb8494592015-09-25 02:29:14 +0000153 if (num_ids >= 7) {
154 OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 7);
Robert Sloan5cbb5c82018-04-24 11:35:46 -0700155 extended_features[0] = ebx;
156 extended_features[1] = ecx;
Kenny Rootb8494592015-09-25 02:29:14 +0000157 }
158
Kenny Rootb8494592015-09-25 02:29:14 +0000159 OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 1);
160
Robert Sloan11c28bd2018-12-17 12:09:20 -0800161 // Force the hyper-threading bit so that the more conservative path is always
162 // chosen.
163 edx |= 1u << 28;
Kenny Rootb8494592015-09-25 02:29:14 +0000164
Robert Sloan8f860b12017-08-28 07:37:06 -0700165 // Reserved bit #20 was historically repurposed to control the in-memory
166 // representation of RC4 state. Always set it to zero.
Robert Sloan29c1d2c2017-10-30 14:10:28 -0700167 edx &= ~(1u << 20);
Kenny Rootb8494592015-09-25 02:29:14 +0000168
Robert Sloan8f860b12017-08-28 07:37:06 -0700169 // Reserved bit #30 is repurposed to signal an Intel CPU.
Kenny Rootb8494592015-09-25 02:29:14 +0000170 if (is_intel) {
Robert Sloan29c1d2c2017-10-30 14:10:28 -0700171 edx |= (1u << 30);
Robert Sloanfe7cd212017-08-07 09:03:39 -0700172
Robert Sloan8f860b12017-08-28 07:37:06 -0700173 // Clear the XSAVE bit on Knights Landing to mimic Silvermont. This enables
174 // some Silvermont-specific codepaths which perform better. See OpenSSL
175 // commit 64d92d74985ebb3d0be58a9718f9e080a14a8e7f.
Robert Sloanfe7cd212017-08-07 09:03:39 -0700176 if ((eax & 0x0fff0ff0) == 0x00050670 /* Knights Landing */ ||
177 (eax & 0x0fff0ff0) == 0x00080650 /* Knights Mill (per SDE) */) {
Robert Sloan29c1d2c2017-10-30 14:10:28 -0700178 ecx &= ~(1u << 26);
Robert Sloanfe7cd212017-08-07 09:03:39 -0700179 }
Kenny Rootb8494592015-09-25 02:29:14 +0000180 } else {
Robert Sloan29c1d2c2017-10-30 14:10:28 -0700181 edx &= ~(1u << 30);
Kenny Rootb8494592015-09-25 02:29:14 +0000182 }
183
Robert Sloan11c28bd2018-12-17 12:09:20 -0800184 // The SDBG bit is repurposed to denote AMD XOP support. Don't ever use AMD
185 // XOP code paths.
186 ecx &= ~(1u << 11);
Kenny Rootb8494592015-09-25 02:29:14 +0000187
188 uint64_t xcr0 = 0;
Robert Sloan29c1d2c2017-10-30 14:10:28 -0700189 if (ecx & (1u << 27)) {
Robert Sloan8f860b12017-08-28 07:37:06 -0700190 // XCR0 may only be queried if the OSXSAVE bit is set.
Kenny Rootb8494592015-09-25 02:29:14 +0000191 xcr0 = OPENSSL_xgetbv(0);
192 }
Robert Sloan8f860b12017-08-28 07:37:06 -0700193 // See Intel manual, volume 1, section 14.3.
Kenny Rootb8494592015-09-25 02:29:14 +0000194 if ((xcr0 & 6) != 6) {
Robert Sloan8f860b12017-08-28 07:37:06 -0700195 // YMM registers cannot be used.
Robert Sloan29c1d2c2017-10-30 14:10:28 -0700196 ecx &= ~(1u << 28); // AVX
197 ecx &= ~(1u << 12); // FMA
198 ecx &= ~(1u << 11); // AMD XOP
Robert Sloan8f860b12017-08-28 07:37:06 -0700199 // Clear AVX2 and AVX512* bits.
200 //
201 // TODO(davidben): Should bits 17 and 26-28 also be cleared? Upstream
202 // doesn't clear those.
Robert Sloan5cbb5c82018-04-24 11:35:46 -0700203 extended_features[0] &=
Robert Sloan29c1d2c2017-10-30 14:10:28 -0700204 ~((1u << 5) | (1u << 16) | (1u << 21) | (1u << 30) | (1u << 31));
Robert Sloanfe7cd212017-08-07 09:03:39 -0700205 }
Robert Sloan8f860b12017-08-28 07:37:06 -0700206 // See Intel manual, volume 1, section 15.2.
Robert Sloanfe7cd212017-08-07 09:03:39 -0700207 if ((xcr0 & 0xe6) != 0xe6) {
Robert Sloan8f860b12017-08-28 07:37:06 -0700208 // Clear AVX512F. Note we don't touch other AVX512 extensions because they
209 // can be used with YMM.
Robert Sloan5cbb5c82018-04-24 11:35:46 -0700210 extended_features[0] &= ~(1u << 16);
Robert Sloanfe7cd212017-08-07 09:03:39 -0700211 }
212
Robert Sloan8f860b12017-08-28 07:37:06 -0700213 // Disable ADX instructions on Knights Landing. See OpenSSL commit
214 // 64d92d74985ebb3d0be58a9718f9e080a14a8e7f.
Robert Sloan29c1d2c2017-10-30 14:10:28 -0700215 if ((ecx & (1u << 26)) == 0) {
Robert Sloan5cbb5c82018-04-24 11:35:46 -0700216 extended_features[0] &= ~(1u << 19);
Kenny Rootb8494592015-09-25 02:29:14 +0000217 }
218
219 OPENSSL_ia32cap_P[0] = edx;
220 OPENSSL_ia32cap_P[1] = ecx;
Robert Sloan5cbb5c82018-04-24 11:35:46 -0700221 OPENSSL_ia32cap_P[2] = extended_features[0];
222 OPENSSL_ia32cap_P[3] = extended_features[1];
Kenny Rootb8494592015-09-25 02:29:14 +0000223
Adam Langleyd9e397b2015-01-22 14:27:53 -0800224 const char *env1, *env2;
Adam Langleyd9e397b2015-01-22 14:27:53 -0800225 env1 = getenv("OPENSSL_ia32cap");
226 if (env1 == NULL) {
227 return;
228 }
229
Robert Sloan8f860b12017-08-28 07:37:06 -0700230 // OPENSSL_ia32cap can contain zero, one or two values, separated with a ':'.
231 // Each value is a 64-bit, unsigned value which may start with "0x" to
232 // indicate a hex value. Prior to the 64-bit value, a '~' may be given.
233 //
234 // If '~' isn't present, then the value is taken as the result of the CPUID.
235 // Otherwise the value is inverted and ANDed with the probed CPUID result.
236 //
237 // The first value determines OPENSSL_ia32cap_P[0] and [1]. The second [2]
238 // and [3].
Adam Langleyd9e397b2015-01-22 14:27:53 -0800239
240 handle_cpu_env(&OPENSSL_ia32cap_P[0], env1);
241 env2 = strchr(env1, ':');
242 if (env2 != NULL) {
243 handle_cpu_env(&OPENSSL_ia32cap_P[2], env2 + 1);
244 }
245}
246
Robert Sloan8f860b12017-08-28 07:37:06 -0700247#endif // !OPENSSL_NO_ASM && (OPENSSL_X86 || OPENSSL_X86_64)