Kenny Root | b849459 | 2015-09-25 02:29:14 +0000 | [diff] [blame] | 1 | #if defined(__arm__) |
Robert Sloan | 8ff0355 | 2017-06-14 12:40:58 -0700 | [diff] [blame] | 2 | @ Copyright 2007-2016 The OpenSSL Project Authors. All Rights Reserved. |
| 3 | @ |
| 4 | @ Licensed under the OpenSSL license (the "License"). You may not use |
| 5 | @ this file except in compliance with the License. You can obtain a copy |
| 6 | @ in the file LICENSE in the source distribution or at |
| 7 | @ https://www.openssl.org/source/license.html |
| 8 | |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 9 | |
| 10 | @ ==================================================================== |
| 11 | @ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL |
| 12 | @ project. The module is, however, dual licensed under OpenSSL and |
| 13 | @ CRYPTOGAMS licenses depending on where you obtain it. For further |
| 14 | @ details see http://www.openssl.org/~appro/cryptogams/. |
| 15 | @ |
| 16 | @ Permission to use under GPL terms is granted. |
| 17 | @ ==================================================================== |
| 18 | |
| 19 | @ SHA512 block procedure for ARMv4. September 2007. |
| 20 | |
| 21 | @ This code is ~4.5 (four and a half) times faster than code generated |
| 22 | @ by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue |
| 23 | @ Xscale PXA250 core]. |
| 24 | @ |
| 25 | @ July 2010. |
| 26 | @ |
| 27 | @ Rescheduling for dual-issue pipeline resulted in 6% improvement on |
| 28 | @ Cortex A8 core and ~40 cycles per processed byte. |
| 29 | |
| 30 | @ February 2011. |
| 31 | @ |
| 32 | @ Profiler-assisted and platform-specific optimization resulted in 7% |
| 33 | @ improvement on Coxtex A8 core and ~38 cycles per byte. |
| 34 | |
| 35 | @ March 2011. |
| 36 | @ |
| 37 | @ Add NEON implementation. On Cortex A8 it was measured to process |
| 38 | @ one byte in 23.3 cycles or ~60% faster than integer-only code. |
| 39 | |
| 40 | @ August 2012. |
| 41 | @ |
| 42 | @ Improve NEON performance by 12% on Snapdragon S4. In absolute |
| 43 | @ terms it's 22.6 cycles per byte, which is disappointing result. |
| 44 | @ Technical writers asserted that 3-way S4 pipeline can sustain |
| 45 | @ multiple NEON instructions per cycle, but dual NEON issue could |
| 46 | @ not be observed, see http://www.openssl.org/~appro/Snapdragon-S4.html |
| 47 | @ for further details. On side note Cortex-A15 processes one byte in |
| 48 | @ 16 cycles. |
| 49 | |
| 50 | @ Byte order [in]dependence. ========================================= |
| 51 | @ |
| 52 | @ Originally caller was expected to maintain specific *dword* order in |
| 53 | @ h[0-7], namely with most significant dword at *lower* address, which |
| 54 | @ was reflected in below two parameters as 0 and 4. Now caller is |
| 55 | @ expected to maintain native byte order for whole 64-bit values. |
| 56 | #ifndef __KERNEL__ |
Kenny Root | b849459 | 2015-09-25 02:29:14 +0000 | [diff] [blame] | 57 | # include <openssl/arm_arch.h> |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 58 | # define VFP_ABI_PUSH vstmdb sp!,{d8-d15} |
| 59 | # define VFP_ABI_POP vldmia sp!,{d8-d15} |
| 60 | #else |
| 61 | # define __ARM_ARCH__ __LINUX_ARM_ARCH__ |
| 62 | # define __ARM_MAX_ARCH__ 7 |
| 63 | # define VFP_ABI_PUSH |
| 64 | # define VFP_ABI_POP |
| 65 | #endif |
| 66 | |
Robert Sloan | 5581810 | 2017-12-18 11:26:17 -0800 | [diff] [blame] | 67 | @ Silence ARMv8 deprecated IT instruction warnings. This file is used by both |
| 68 | @ ARMv7 and ARMv8 processors and does not use ARMv8 instructions. |
| 69 | .arch armv7-a |
| 70 | |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 71 | #ifdef __ARMEL__ |
| 72 | # define LO 0 |
| 73 | # define HI 4 |
| 74 | # define WORD64(hi0,lo0,hi1,lo1) .word lo0,hi0, lo1,hi1 |
| 75 | #else |
| 76 | # define HI 0 |
| 77 | # define LO 4 |
| 78 | # define WORD64(hi0,lo0,hi1,lo1) .word hi0,lo0, hi1,lo1 |
| 79 | #endif |
| 80 | |
| 81 | .text |
Robert Sloan | 8ff0355 | 2017-06-14 12:40:58 -0700 | [diff] [blame] | 82 | #if defined(__thumb2__) |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 83 | .syntax unified |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 84 | .thumb |
Robert Sloan | 8ff0355 | 2017-06-14 12:40:58 -0700 | [diff] [blame] | 85 | # define adrl adr |
| 86 | #else |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 87 | .code 32 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 88 | #endif |
| 89 | |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 90 | .type K512,%object |
| 91 | .align 5 |
| 92 | K512: |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 93 | WORD64(0x428a2f98,0xd728ae22, 0x71374491,0x23ef65cd) |
| 94 | WORD64(0xb5c0fbcf,0xec4d3b2f, 0xe9b5dba5,0x8189dbbc) |
| 95 | WORD64(0x3956c25b,0xf348b538, 0x59f111f1,0xb605d019) |
| 96 | WORD64(0x923f82a4,0xaf194f9b, 0xab1c5ed5,0xda6d8118) |
| 97 | WORD64(0xd807aa98,0xa3030242, 0x12835b01,0x45706fbe) |
| 98 | WORD64(0x243185be,0x4ee4b28c, 0x550c7dc3,0xd5ffb4e2) |
| 99 | WORD64(0x72be5d74,0xf27b896f, 0x80deb1fe,0x3b1696b1) |
| 100 | WORD64(0x9bdc06a7,0x25c71235, 0xc19bf174,0xcf692694) |
| 101 | WORD64(0xe49b69c1,0x9ef14ad2, 0xefbe4786,0x384f25e3) |
| 102 | WORD64(0x0fc19dc6,0x8b8cd5b5, 0x240ca1cc,0x77ac9c65) |
| 103 | WORD64(0x2de92c6f,0x592b0275, 0x4a7484aa,0x6ea6e483) |
| 104 | WORD64(0x5cb0a9dc,0xbd41fbd4, 0x76f988da,0x831153b5) |
| 105 | WORD64(0x983e5152,0xee66dfab, 0xa831c66d,0x2db43210) |
| 106 | WORD64(0xb00327c8,0x98fb213f, 0xbf597fc7,0xbeef0ee4) |
| 107 | WORD64(0xc6e00bf3,0x3da88fc2, 0xd5a79147,0x930aa725) |
| 108 | WORD64(0x06ca6351,0xe003826f, 0x14292967,0x0a0e6e70) |
| 109 | WORD64(0x27b70a85,0x46d22ffc, 0x2e1b2138,0x5c26c926) |
| 110 | WORD64(0x4d2c6dfc,0x5ac42aed, 0x53380d13,0x9d95b3df) |
| 111 | WORD64(0x650a7354,0x8baf63de, 0x766a0abb,0x3c77b2a8) |
| 112 | WORD64(0x81c2c92e,0x47edaee6, 0x92722c85,0x1482353b) |
| 113 | WORD64(0xa2bfe8a1,0x4cf10364, 0xa81a664b,0xbc423001) |
| 114 | WORD64(0xc24b8b70,0xd0f89791, 0xc76c51a3,0x0654be30) |
| 115 | WORD64(0xd192e819,0xd6ef5218, 0xd6990624,0x5565a910) |
| 116 | WORD64(0xf40e3585,0x5771202a, 0x106aa070,0x32bbd1b8) |
| 117 | WORD64(0x19a4c116,0xb8d2d0c8, 0x1e376c08,0x5141ab53) |
| 118 | WORD64(0x2748774c,0xdf8eeb99, 0x34b0bcb5,0xe19b48a8) |
| 119 | WORD64(0x391c0cb3,0xc5c95a63, 0x4ed8aa4a,0xe3418acb) |
| 120 | WORD64(0x5b9cca4f,0x7763e373, 0x682e6ff3,0xd6b2b8a3) |
| 121 | WORD64(0x748f82ee,0x5defb2fc, 0x78a5636f,0x43172f60) |
| 122 | WORD64(0x84c87814,0xa1f0ab72, 0x8cc70208,0x1a6439ec) |
| 123 | WORD64(0x90befffa,0x23631e28, 0xa4506ceb,0xde82bde9) |
| 124 | WORD64(0xbef9a3f7,0xb2c67915, 0xc67178f2,0xe372532b) |
| 125 | WORD64(0xca273ece,0xea26619c, 0xd186b8c7,0x21c0c207) |
| 126 | WORD64(0xeada7dd6,0xcde0eb1e, 0xf57d4f7f,0xee6ed178) |
| 127 | WORD64(0x06f067aa,0x72176fba, 0x0a637dc5,0xa2c898a6) |
| 128 | WORD64(0x113f9804,0xbef90dae, 0x1b710b35,0x131c471b) |
| 129 | WORD64(0x28db77f5,0x23047d84, 0x32caab7b,0x40c72493) |
| 130 | WORD64(0x3c9ebe0a,0x15c9bebc, 0x431d67c4,0x9c100d4c) |
| 131 | WORD64(0x4cc5d4be,0xcb3e42b6, 0x597f299c,0xfc657e2a) |
| 132 | WORD64(0x5fcb6fab,0x3ad6faec, 0x6c44198c,0x4a475817) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 133 | .size K512,.-K512 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 134 | #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 135 | .LOPENSSL_armcap: |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 136 | .word OPENSSL_armcap_P-.Lsha512_block_data_order |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 137 | .skip 32-4 |
| 138 | #else |
| 139 | .skip 32 |
| 140 | #endif |
| 141 | |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 142 | .globl sha512_block_data_order |
David Benjamin | 4969cc9 | 2016-04-22 15:02:23 -0400 | [diff] [blame] | 143 | .hidden sha512_block_data_order |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 144 | .type sha512_block_data_order,%function |
| 145 | sha512_block_data_order: |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 146 | .Lsha512_block_data_order: |
Robert Sloan | 8ff0355 | 2017-06-14 12:40:58 -0700 | [diff] [blame] | 147 | #if __ARM_ARCH__<7 && !defined(__thumb2__) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 148 | sub r3,pc,#8 @ sha512_block_data_order |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 149 | #else |
Robert Sloan | 8ff0355 | 2017-06-14 12:40:58 -0700 | [diff] [blame] | 150 | adr r3,.Lsha512_block_data_order |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 151 | #endif |
| 152 | #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 153 | ldr r12,.LOPENSSL_armcap |
| 154 | ldr r12,[r3,r12] @ OPENSSL_armcap_P |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 155 | #ifdef __APPLE__ |
| 156 | ldr r12,[r12] |
| 157 | #endif |
David Benjamin | 4969cc9 | 2016-04-22 15:02:23 -0400 | [diff] [blame] | 158 | tst r12,#ARMV7_NEON |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 159 | bne .LNEON |
| 160 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 161 | add r2,r1,r2,lsl#7 @ len to point at the end of inp |
| 162 | stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 163 | sub r14,r3,#672 @ K512 |
| 164 | sub sp,sp,#9*8 |
| 165 | |
| 166 | ldr r7,[r0,#32+LO] |
| 167 | ldr r8,[r0,#32+HI] |
| 168 | ldr r9, [r0,#48+LO] |
| 169 | ldr r10, [r0,#48+HI] |
| 170 | ldr r11, [r0,#56+LO] |
| 171 | ldr r12, [r0,#56+HI] |
| 172 | .Loop: |
| 173 | str r9, [sp,#48+0] |
| 174 | str r10, [sp,#48+4] |
| 175 | str r11, [sp,#56+0] |
| 176 | str r12, [sp,#56+4] |
| 177 | ldr r5,[r0,#0+LO] |
| 178 | ldr r6,[r0,#0+HI] |
| 179 | ldr r3,[r0,#8+LO] |
| 180 | ldr r4,[r0,#8+HI] |
| 181 | ldr r9, [r0,#16+LO] |
| 182 | ldr r10, [r0,#16+HI] |
| 183 | ldr r11, [r0,#24+LO] |
| 184 | ldr r12, [r0,#24+HI] |
| 185 | str r3,[sp,#8+0] |
| 186 | str r4,[sp,#8+4] |
| 187 | str r9, [sp,#16+0] |
| 188 | str r10, [sp,#16+4] |
| 189 | str r11, [sp,#24+0] |
| 190 | str r12, [sp,#24+4] |
| 191 | ldr r3,[r0,#40+LO] |
| 192 | ldr r4,[r0,#40+HI] |
| 193 | str r3,[sp,#40+0] |
| 194 | str r4,[sp,#40+4] |
| 195 | |
| 196 | .L00_15: |
| 197 | #if __ARM_ARCH__<7 |
| 198 | ldrb r3,[r1,#7] |
| 199 | ldrb r9, [r1,#6] |
| 200 | ldrb r10, [r1,#5] |
| 201 | ldrb r11, [r1,#4] |
| 202 | ldrb r4,[r1,#3] |
| 203 | ldrb r12, [r1,#2] |
| 204 | orr r3,r3,r9,lsl#8 |
| 205 | ldrb r9, [r1,#1] |
| 206 | orr r3,r3,r10,lsl#16 |
| 207 | ldrb r10, [r1],#8 |
| 208 | orr r3,r3,r11,lsl#24 |
| 209 | orr r4,r4,r12,lsl#8 |
| 210 | orr r4,r4,r9,lsl#16 |
| 211 | orr r4,r4,r10,lsl#24 |
| 212 | #else |
| 213 | ldr r3,[r1,#4] |
| 214 | ldr r4,[r1],#8 |
| 215 | #ifdef __ARMEL__ |
| 216 | rev r3,r3 |
| 217 | rev r4,r4 |
| 218 | #endif |
| 219 | #endif |
| 220 | @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41)) |
| 221 | @ LO lo>>14^hi<<18 ^ lo>>18^hi<<14 ^ hi>>9^lo<<23 |
| 222 | @ HI hi>>14^lo<<18 ^ hi>>18^lo<<14 ^ lo>>9^hi<<23 |
| 223 | mov r9,r7,lsr#14 |
| 224 | str r3,[sp,#64+0] |
| 225 | mov r10,r8,lsr#14 |
| 226 | str r4,[sp,#64+4] |
| 227 | eor r9,r9,r8,lsl#18 |
| 228 | ldr r11,[sp,#56+0] @ h.lo |
| 229 | eor r10,r10,r7,lsl#18 |
| 230 | ldr r12,[sp,#56+4] @ h.hi |
| 231 | eor r9,r9,r7,lsr#18 |
| 232 | eor r10,r10,r8,lsr#18 |
| 233 | eor r9,r9,r8,lsl#14 |
| 234 | eor r10,r10,r7,lsl#14 |
| 235 | eor r9,r9,r8,lsr#9 |
| 236 | eor r10,r10,r7,lsr#9 |
| 237 | eor r9,r9,r7,lsl#23 |
| 238 | eor r10,r10,r8,lsl#23 @ Sigma1(e) |
| 239 | adds r3,r3,r9 |
| 240 | ldr r9,[sp,#40+0] @ f.lo |
| 241 | adc r4,r4,r10 @ T += Sigma1(e) |
| 242 | ldr r10,[sp,#40+4] @ f.hi |
| 243 | adds r3,r3,r11 |
| 244 | ldr r11,[sp,#48+0] @ g.lo |
| 245 | adc r4,r4,r12 @ T += h |
| 246 | ldr r12,[sp,#48+4] @ g.hi |
| 247 | |
| 248 | eor r9,r9,r11 |
| 249 | str r7,[sp,#32+0] |
| 250 | eor r10,r10,r12 |
| 251 | str r8,[sp,#32+4] |
| 252 | and r9,r9,r7 |
| 253 | str r5,[sp,#0+0] |
| 254 | and r10,r10,r8 |
| 255 | str r6,[sp,#0+4] |
| 256 | eor r9,r9,r11 |
| 257 | ldr r11,[r14,#LO] @ K[i].lo |
| 258 | eor r10,r10,r12 @ Ch(e,f,g) |
| 259 | ldr r12,[r14,#HI] @ K[i].hi |
| 260 | |
| 261 | adds r3,r3,r9 |
| 262 | ldr r7,[sp,#24+0] @ d.lo |
| 263 | adc r4,r4,r10 @ T += Ch(e,f,g) |
| 264 | ldr r8,[sp,#24+4] @ d.hi |
| 265 | adds r3,r3,r11 |
| 266 | and r9,r11,#0xff |
| 267 | adc r4,r4,r12 @ T += K[i] |
| 268 | adds r7,r7,r3 |
| 269 | ldr r11,[sp,#8+0] @ b.lo |
| 270 | adc r8,r8,r4 @ d += T |
| 271 | teq r9,#148 |
| 272 | |
| 273 | ldr r12,[sp,#16+0] @ c.lo |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 274 | #if __ARM_ARCH__>=7 |
| 275 | it eq @ Thumb2 thing, sanity check in ARM |
| 276 | #endif |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 277 | orreq r14,r14,#1 |
| 278 | @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39)) |
| 279 | @ LO lo>>28^hi<<4 ^ hi>>2^lo<<30 ^ hi>>7^lo<<25 |
| 280 | @ HI hi>>28^lo<<4 ^ lo>>2^hi<<30 ^ lo>>7^hi<<25 |
| 281 | mov r9,r5,lsr#28 |
| 282 | mov r10,r6,lsr#28 |
| 283 | eor r9,r9,r6,lsl#4 |
| 284 | eor r10,r10,r5,lsl#4 |
| 285 | eor r9,r9,r6,lsr#2 |
| 286 | eor r10,r10,r5,lsr#2 |
| 287 | eor r9,r9,r5,lsl#30 |
| 288 | eor r10,r10,r6,lsl#30 |
| 289 | eor r9,r9,r6,lsr#7 |
| 290 | eor r10,r10,r5,lsr#7 |
| 291 | eor r9,r9,r5,lsl#25 |
| 292 | eor r10,r10,r6,lsl#25 @ Sigma0(a) |
| 293 | adds r3,r3,r9 |
| 294 | and r9,r5,r11 |
| 295 | adc r4,r4,r10 @ T += Sigma0(a) |
| 296 | |
| 297 | ldr r10,[sp,#8+4] @ b.hi |
| 298 | orr r5,r5,r11 |
| 299 | ldr r11,[sp,#16+4] @ c.hi |
| 300 | and r5,r5,r12 |
| 301 | and r12,r6,r10 |
| 302 | orr r6,r6,r10 |
| 303 | orr r5,r5,r9 @ Maj(a,b,c).lo |
| 304 | and r6,r6,r11 |
| 305 | adds r5,r5,r3 |
| 306 | orr r6,r6,r12 @ Maj(a,b,c).hi |
| 307 | sub sp,sp,#8 |
| 308 | adc r6,r6,r4 @ h += T |
| 309 | tst r14,#1 |
| 310 | add r14,r14,#8 |
| 311 | tst r14,#1 |
| 312 | beq .L00_15 |
| 313 | ldr r9,[sp,#184+0] |
| 314 | ldr r10,[sp,#184+4] |
| 315 | bic r14,r14,#1 |
| 316 | .L16_79: |
| 317 | @ sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7)) |
| 318 | @ LO lo>>1^hi<<31 ^ lo>>8^hi<<24 ^ lo>>7^hi<<25 |
| 319 | @ HI hi>>1^lo<<31 ^ hi>>8^lo<<24 ^ hi>>7 |
| 320 | mov r3,r9,lsr#1 |
| 321 | ldr r11,[sp,#80+0] |
| 322 | mov r4,r10,lsr#1 |
| 323 | ldr r12,[sp,#80+4] |
| 324 | eor r3,r3,r10,lsl#31 |
| 325 | eor r4,r4,r9,lsl#31 |
| 326 | eor r3,r3,r9,lsr#8 |
| 327 | eor r4,r4,r10,lsr#8 |
| 328 | eor r3,r3,r10,lsl#24 |
| 329 | eor r4,r4,r9,lsl#24 |
| 330 | eor r3,r3,r9,lsr#7 |
| 331 | eor r4,r4,r10,lsr#7 |
| 332 | eor r3,r3,r10,lsl#25 |
| 333 | |
| 334 | @ sigma1(x) (ROTR((x),19) ^ ROTR((x),61) ^ ((x)>>6)) |
| 335 | @ LO lo>>19^hi<<13 ^ hi>>29^lo<<3 ^ lo>>6^hi<<26 |
| 336 | @ HI hi>>19^lo<<13 ^ lo>>29^hi<<3 ^ hi>>6 |
| 337 | mov r9,r11,lsr#19 |
| 338 | mov r10,r12,lsr#19 |
| 339 | eor r9,r9,r12,lsl#13 |
| 340 | eor r10,r10,r11,lsl#13 |
| 341 | eor r9,r9,r12,lsr#29 |
| 342 | eor r10,r10,r11,lsr#29 |
| 343 | eor r9,r9,r11,lsl#3 |
| 344 | eor r10,r10,r12,lsl#3 |
| 345 | eor r9,r9,r11,lsr#6 |
| 346 | eor r10,r10,r12,lsr#6 |
| 347 | ldr r11,[sp,#120+0] |
| 348 | eor r9,r9,r12,lsl#26 |
| 349 | |
| 350 | ldr r12,[sp,#120+4] |
| 351 | adds r3,r3,r9 |
| 352 | ldr r9,[sp,#192+0] |
| 353 | adc r4,r4,r10 |
| 354 | |
| 355 | ldr r10,[sp,#192+4] |
| 356 | adds r3,r3,r11 |
| 357 | adc r4,r4,r12 |
| 358 | adds r3,r3,r9 |
| 359 | adc r4,r4,r10 |
| 360 | @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41)) |
| 361 | @ LO lo>>14^hi<<18 ^ lo>>18^hi<<14 ^ hi>>9^lo<<23 |
| 362 | @ HI hi>>14^lo<<18 ^ hi>>18^lo<<14 ^ lo>>9^hi<<23 |
| 363 | mov r9,r7,lsr#14 |
| 364 | str r3,[sp,#64+0] |
| 365 | mov r10,r8,lsr#14 |
| 366 | str r4,[sp,#64+4] |
| 367 | eor r9,r9,r8,lsl#18 |
| 368 | ldr r11,[sp,#56+0] @ h.lo |
| 369 | eor r10,r10,r7,lsl#18 |
| 370 | ldr r12,[sp,#56+4] @ h.hi |
| 371 | eor r9,r9,r7,lsr#18 |
| 372 | eor r10,r10,r8,lsr#18 |
| 373 | eor r9,r9,r8,lsl#14 |
| 374 | eor r10,r10,r7,lsl#14 |
| 375 | eor r9,r9,r8,lsr#9 |
| 376 | eor r10,r10,r7,lsr#9 |
| 377 | eor r9,r9,r7,lsl#23 |
| 378 | eor r10,r10,r8,lsl#23 @ Sigma1(e) |
| 379 | adds r3,r3,r9 |
| 380 | ldr r9,[sp,#40+0] @ f.lo |
| 381 | adc r4,r4,r10 @ T += Sigma1(e) |
| 382 | ldr r10,[sp,#40+4] @ f.hi |
| 383 | adds r3,r3,r11 |
| 384 | ldr r11,[sp,#48+0] @ g.lo |
| 385 | adc r4,r4,r12 @ T += h |
| 386 | ldr r12,[sp,#48+4] @ g.hi |
| 387 | |
| 388 | eor r9,r9,r11 |
| 389 | str r7,[sp,#32+0] |
| 390 | eor r10,r10,r12 |
| 391 | str r8,[sp,#32+4] |
| 392 | and r9,r9,r7 |
| 393 | str r5,[sp,#0+0] |
| 394 | and r10,r10,r8 |
| 395 | str r6,[sp,#0+4] |
| 396 | eor r9,r9,r11 |
| 397 | ldr r11,[r14,#LO] @ K[i].lo |
| 398 | eor r10,r10,r12 @ Ch(e,f,g) |
| 399 | ldr r12,[r14,#HI] @ K[i].hi |
| 400 | |
| 401 | adds r3,r3,r9 |
| 402 | ldr r7,[sp,#24+0] @ d.lo |
| 403 | adc r4,r4,r10 @ T += Ch(e,f,g) |
| 404 | ldr r8,[sp,#24+4] @ d.hi |
| 405 | adds r3,r3,r11 |
| 406 | and r9,r11,#0xff |
| 407 | adc r4,r4,r12 @ T += K[i] |
| 408 | adds r7,r7,r3 |
| 409 | ldr r11,[sp,#8+0] @ b.lo |
| 410 | adc r8,r8,r4 @ d += T |
| 411 | teq r9,#23 |
| 412 | |
| 413 | ldr r12,[sp,#16+0] @ c.lo |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 414 | #if __ARM_ARCH__>=7 |
| 415 | it eq @ Thumb2 thing, sanity check in ARM |
| 416 | #endif |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 417 | orreq r14,r14,#1 |
| 418 | @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39)) |
| 419 | @ LO lo>>28^hi<<4 ^ hi>>2^lo<<30 ^ hi>>7^lo<<25 |
| 420 | @ HI hi>>28^lo<<4 ^ lo>>2^hi<<30 ^ lo>>7^hi<<25 |
| 421 | mov r9,r5,lsr#28 |
| 422 | mov r10,r6,lsr#28 |
| 423 | eor r9,r9,r6,lsl#4 |
| 424 | eor r10,r10,r5,lsl#4 |
| 425 | eor r9,r9,r6,lsr#2 |
| 426 | eor r10,r10,r5,lsr#2 |
| 427 | eor r9,r9,r5,lsl#30 |
| 428 | eor r10,r10,r6,lsl#30 |
| 429 | eor r9,r9,r6,lsr#7 |
| 430 | eor r10,r10,r5,lsr#7 |
| 431 | eor r9,r9,r5,lsl#25 |
| 432 | eor r10,r10,r6,lsl#25 @ Sigma0(a) |
| 433 | adds r3,r3,r9 |
| 434 | and r9,r5,r11 |
| 435 | adc r4,r4,r10 @ T += Sigma0(a) |
| 436 | |
| 437 | ldr r10,[sp,#8+4] @ b.hi |
| 438 | orr r5,r5,r11 |
| 439 | ldr r11,[sp,#16+4] @ c.hi |
| 440 | and r5,r5,r12 |
| 441 | and r12,r6,r10 |
| 442 | orr r6,r6,r10 |
| 443 | orr r5,r5,r9 @ Maj(a,b,c).lo |
| 444 | and r6,r6,r11 |
| 445 | adds r5,r5,r3 |
| 446 | orr r6,r6,r12 @ Maj(a,b,c).hi |
| 447 | sub sp,sp,#8 |
| 448 | adc r6,r6,r4 @ h += T |
| 449 | tst r14,#1 |
| 450 | add r14,r14,#8 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 451 | #if __ARM_ARCH__>=7 |
| 452 | ittt eq @ Thumb2 thing, sanity check in ARM |
| 453 | #endif |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 454 | ldreq r9,[sp,#184+0] |
| 455 | ldreq r10,[sp,#184+4] |
| 456 | beq .L16_79 |
| 457 | bic r14,r14,#1 |
| 458 | |
| 459 | ldr r3,[sp,#8+0] |
| 460 | ldr r4,[sp,#8+4] |
| 461 | ldr r9, [r0,#0+LO] |
| 462 | ldr r10, [r0,#0+HI] |
| 463 | ldr r11, [r0,#8+LO] |
| 464 | ldr r12, [r0,#8+HI] |
| 465 | adds r9,r5,r9 |
| 466 | str r9, [r0,#0+LO] |
| 467 | adc r10,r6,r10 |
| 468 | str r10, [r0,#0+HI] |
| 469 | adds r11,r3,r11 |
| 470 | str r11, [r0,#8+LO] |
| 471 | adc r12,r4,r12 |
| 472 | str r12, [r0,#8+HI] |
| 473 | |
| 474 | ldr r5,[sp,#16+0] |
| 475 | ldr r6,[sp,#16+4] |
| 476 | ldr r3,[sp,#24+0] |
| 477 | ldr r4,[sp,#24+4] |
| 478 | ldr r9, [r0,#16+LO] |
| 479 | ldr r10, [r0,#16+HI] |
| 480 | ldr r11, [r0,#24+LO] |
| 481 | ldr r12, [r0,#24+HI] |
| 482 | adds r9,r5,r9 |
| 483 | str r9, [r0,#16+LO] |
| 484 | adc r10,r6,r10 |
| 485 | str r10, [r0,#16+HI] |
| 486 | adds r11,r3,r11 |
| 487 | str r11, [r0,#24+LO] |
| 488 | adc r12,r4,r12 |
| 489 | str r12, [r0,#24+HI] |
| 490 | |
| 491 | ldr r3,[sp,#40+0] |
| 492 | ldr r4,[sp,#40+4] |
| 493 | ldr r9, [r0,#32+LO] |
| 494 | ldr r10, [r0,#32+HI] |
| 495 | ldr r11, [r0,#40+LO] |
| 496 | ldr r12, [r0,#40+HI] |
| 497 | adds r7,r7,r9 |
| 498 | str r7,[r0,#32+LO] |
| 499 | adc r8,r8,r10 |
| 500 | str r8,[r0,#32+HI] |
| 501 | adds r11,r3,r11 |
| 502 | str r11, [r0,#40+LO] |
| 503 | adc r12,r4,r12 |
| 504 | str r12, [r0,#40+HI] |
| 505 | |
| 506 | ldr r5,[sp,#48+0] |
| 507 | ldr r6,[sp,#48+4] |
| 508 | ldr r3,[sp,#56+0] |
| 509 | ldr r4,[sp,#56+4] |
| 510 | ldr r9, [r0,#48+LO] |
| 511 | ldr r10, [r0,#48+HI] |
| 512 | ldr r11, [r0,#56+LO] |
| 513 | ldr r12, [r0,#56+HI] |
| 514 | adds r9,r5,r9 |
| 515 | str r9, [r0,#48+LO] |
| 516 | adc r10,r6,r10 |
| 517 | str r10, [r0,#48+HI] |
| 518 | adds r11,r3,r11 |
| 519 | str r11, [r0,#56+LO] |
| 520 | adc r12,r4,r12 |
| 521 | str r12, [r0,#56+HI] |
| 522 | |
| 523 | add sp,sp,#640 |
| 524 | sub r14,r14,#640 |
| 525 | |
| 526 | teq r1,r2 |
| 527 | bne .Loop |
| 528 | |
| 529 | add sp,sp,#8*9 @ destroy frame |
| 530 | #if __ARM_ARCH__>=5 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 531 | ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,pc} |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 532 | #else |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 533 | ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 534 | tst lr,#1 |
| 535 | moveq pc,lr @ be binary compatible with V4, yet |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 536 | .word 0xe12fff1e @ interoperable with Thumb ISA:-) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 537 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 538 | .size sha512_block_data_order,.-sha512_block_data_order |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 539 | #if __ARM_MAX_ARCH__>=7 |
| 540 | .arch armv7-a |
| 541 | .fpu neon |
| 542 | |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 543 | .globl sha512_block_data_order_neon |
David Benjamin | 4969cc9 | 2016-04-22 15:02:23 -0400 | [diff] [blame] | 544 | .hidden sha512_block_data_order_neon |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 545 | .type sha512_block_data_order_neon,%function |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 546 | .align 4 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 547 | sha512_block_data_order_neon: |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 548 | .LNEON: |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 549 | dmb @ errata #451034 on early Cortex A8 |
| 550 | add r2,r1,r2,lsl#7 @ len to point at the end of inp |
| 551 | adr r3,K512 |
| 552 | VFP_ABI_PUSH |
| 553 | vldmia r0,{d16,d17,d18,d19,d20,d21,d22,d23} @ load context |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 554 | .Loop_neon: |
| 555 | vshr.u64 d24,d20,#14 @ 0 |
| 556 | #if 0<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 557 | vld1.64 {d0},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 558 | #endif |
| 559 | vshr.u64 d25,d20,#18 |
| 560 | #if 0>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 561 | vadd.i64 d16,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 562 | #endif |
| 563 | vshr.u64 d26,d20,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 564 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 565 | vsli.64 d24,d20,#50 |
| 566 | vsli.64 d25,d20,#46 |
| 567 | vmov d29,d20 |
| 568 | vsli.64 d26,d20,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 569 | #if 0<16 && defined(__ARMEL__) |
| 570 | vrev64.8 d0,d0 |
| 571 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 572 | veor d25,d24 |
| 573 | vbsl d29,d21,d22 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 574 | vshr.u64 d24,d16,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 575 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 576 | vadd.i64 d27,d29,d23 |
| 577 | vshr.u64 d25,d16,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 578 | vsli.64 d24,d16,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 579 | vadd.i64 d27,d26 |
| 580 | vshr.u64 d26,d16,#39 |
| 581 | vadd.i64 d28,d0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 582 | vsli.64 d25,d16,#30 |
| 583 | veor d30,d16,d17 |
| 584 | vsli.64 d26,d16,#25 |
| 585 | veor d23,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 586 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 587 | vbsl d30,d18,d17 @ Maj(a,b,c) |
| 588 | veor d23,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 589 | vadd.i64 d19,d27 |
| 590 | vadd.i64 d30,d27 |
| 591 | @ vadd.i64 d23,d30 |
| 592 | vshr.u64 d24,d19,#14 @ 1 |
| 593 | #if 1<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 594 | vld1.64 {d1},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 595 | #endif |
| 596 | vshr.u64 d25,d19,#18 |
| 597 | #if 1>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 598 | vadd.i64 d23,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 599 | #endif |
| 600 | vshr.u64 d26,d19,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 601 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 602 | vsli.64 d24,d19,#50 |
| 603 | vsli.64 d25,d19,#46 |
| 604 | vmov d29,d19 |
| 605 | vsli.64 d26,d19,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 606 | #if 1<16 && defined(__ARMEL__) |
| 607 | vrev64.8 d1,d1 |
| 608 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 609 | veor d25,d24 |
| 610 | vbsl d29,d20,d21 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 611 | vshr.u64 d24,d23,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 612 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 613 | vadd.i64 d27,d29,d22 |
| 614 | vshr.u64 d25,d23,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 615 | vsli.64 d24,d23,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 616 | vadd.i64 d27,d26 |
| 617 | vshr.u64 d26,d23,#39 |
| 618 | vadd.i64 d28,d1 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 619 | vsli.64 d25,d23,#30 |
| 620 | veor d30,d23,d16 |
| 621 | vsli.64 d26,d23,#25 |
| 622 | veor d22,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 623 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 624 | vbsl d30,d17,d16 @ Maj(a,b,c) |
| 625 | veor d22,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 626 | vadd.i64 d18,d27 |
| 627 | vadd.i64 d30,d27 |
| 628 | @ vadd.i64 d22,d30 |
| 629 | vshr.u64 d24,d18,#14 @ 2 |
| 630 | #if 2<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 631 | vld1.64 {d2},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 632 | #endif |
| 633 | vshr.u64 d25,d18,#18 |
| 634 | #if 2>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 635 | vadd.i64 d22,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 636 | #endif |
| 637 | vshr.u64 d26,d18,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 638 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 639 | vsli.64 d24,d18,#50 |
| 640 | vsli.64 d25,d18,#46 |
| 641 | vmov d29,d18 |
| 642 | vsli.64 d26,d18,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 643 | #if 2<16 && defined(__ARMEL__) |
| 644 | vrev64.8 d2,d2 |
| 645 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 646 | veor d25,d24 |
| 647 | vbsl d29,d19,d20 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 648 | vshr.u64 d24,d22,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 649 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 650 | vadd.i64 d27,d29,d21 |
| 651 | vshr.u64 d25,d22,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 652 | vsli.64 d24,d22,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 653 | vadd.i64 d27,d26 |
| 654 | vshr.u64 d26,d22,#39 |
| 655 | vadd.i64 d28,d2 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 656 | vsli.64 d25,d22,#30 |
| 657 | veor d30,d22,d23 |
| 658 | vsli.64 d26,d22,#25 |
| 659 | veor d21,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 660 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 661 | vbsl d30,d16,d23 @ Maj(a,b,c) |
| 662 | veor d21,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 663 | vadd.i64 d17,d27 |
| 664 | vadd.i64 d30,d27 |
| 665 | @ vadd.i64 d21,d30 |
| 666 | vshr.u64 d24,d17,#14 @ 3 |
| 667 | #if 3<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 668 | vld1.64 {d3},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 669 | #endif |
| 670 | vshr.u64 d25,d17,#18 |
| 671 | #if 3>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 672 | vadd.i64 d21,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 673 | #endif |
| 674 | vshr.u64 d26,d17,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 675 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 676 | vsli.64 d24,d17,#50 |
| 677 | vsli.64 d25,d17,#46 |
| 678 | vmov d29,d17 |
| 679 | vsli.64 d26,d17,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 680 | #if 3<16 && defined(__ARMEL__) |
| 681 | vrev64.8 d3,d3 |
| 682 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 683 | veor d25,d24 |
| 684 | vbsl d29,d18,d19 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 685 | vshr.u64 d24,d21,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 686 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 687 | vadd.i64 d27,d29,d20 |
| 688 | vshr.u64 d25,d21,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 689 | vsli.64 d24,d21,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 690 | vadd.i64 d27,d26 |
| 691 | vshr.u64 d26,d21,#39 |
| 692 | vadd.i64 d28,d3 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 693 | vsli.64 d25,d21,#30 |
| 694 | veor d30,d21,d22 |
| 695 | vsli.64 d26,d21,#25 |
| 696 | veor d20,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 697 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 698 | vbsl d30,d23,d22 @ Maj(a,b,c) |
| 699 | veor d20,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 700 | vadd.i64 d16,d27 |
| 701 | vadd.i64 d30,d27 |
| 702 | @ vadd.i64 d20,d30 |
| 703 | vshr.u64 d24,d16,#14 @ 4 |
| 704 | #if 4<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 705 | vld1.64 {d4},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 706 | #endif |
| 707 | vshr.u64 d25,d16,#18 |
| 708 | #if 4>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 709 | vadd.i64 d20,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 710 | #endif |
| 711 | vshr.u64 d26,d16,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 712 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 713 | vsli.64 d24,d16,#50 |
| 714 | vsli.64 d25,d16,#46 |
| 715 | vmov d29,d16 |
| 716 | vsli.64 d26,d16,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 717 | #if 4<16 && defined(__ARMEL__) |
| 718 | vrev64.8 d4,d4 |
| 719 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 720 | veor d25,d24 |
| 721 | vbsl d29,d17,d18 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 722 | vshr.u64 d24,d20,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 723 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 724 | vadd.i64 d27,d29,d19 |
| 725 | vshr.u64 d25,d20,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 726 | vsli.64 d24,d20,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 727 | vadd.i64 d27,d26 |
| 728 | vshr.u64 d26,d20,#39 |
| 729 | vadd.i64 d28,d4 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 730 | vsli.64 d25,d20,#30 |
| 731 | veor d30,d20,d21 |
| 732 | vsli.64 d26,d20,#25 |
| 733 | veor d19,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 734 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 735 | vbsl d30,d22,d21 @ Maj(a,b,c) |
| 736 | veor d19,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 737 | vadd.i64 d23,d27 |
| 738 | vadd.i64 d30,d27 |
| 739 | @ vadd.i64 d19,d30 |
| 740 | vshr.u64 d24,d23,#14 @ 5 |
| 741 | #if 5<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 742 | vld1.64 {d5},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 743 | #endif |
| 744 | vshr.u64 d25,d23,#18 |
| 745 | #if 5>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 746 | vadd.i64 d19,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 747 | #endif |
| 748 | vshr.u64 d26,d23,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 749 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 750 | vsli.64 d24,d23,#50 |
| 751 | vsli.64 d25,d23,#46 |
| 752 | vmov d29,d23 |
| 753 | vsli.64 d26,d23,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 754 | #if 5<16 && defined(__ARMEL__) |
| 755 | vrev64.8 d5,d5 |
| 756 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 757 | veor d25,d24 |
| 758 | vbsl d29,d16,d17 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 759 | vshr.u64 d24,d19,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 760 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 761 | vadd.i64 d27,d29,d18 |
| 762 | vshr.u64 d25,d19,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 763 | vsli.64 d24,d19,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 764 | vadd.i64 d27,d26 |
| 765 | vshr.u64 d26,d19,#39 |
| 766 | vadd.i64 d28,d5 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 767 | vsli.64 d25,d19,#30 |
| 768 | veor d30,d19,d20 |
| 769 | vsli.64 d26,d19,#25 |
| 770 | veor d18,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 771 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 772 | vbsl d30,d21,d20 @ Maj(a,b,c) |
| 773 | veor d18,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 774 | vadd.i64 d22,d27 |
| 775 | vadd.i64 d30,d27 |
| 776 | @ vadd.i64 d18,d30 |
| 777 | vshr.u64 d24,d22,#14 @ 6 |
| 778 | #if 6<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 779 | vld1.64 {d6},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 780 | #endif |
| 781 | vshr.u64 d25,d22,#18 |
| 782 | #if 6>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 783 | vadd.i64 d18,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 784 | #endif |
| 785 | vshr.u64 d26,d22,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 786 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 787 | vsli.64 d24,d22,#50 |
| 788 | vsli.64 d25,d22,#46 |
| 789 | vmov d29,d22 |
| 790 | vsli.64 d26,d22,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 791 | #if 6<16 && defined(__ARMEL__) |
| 792 | vrev64.8 d6,d6 |
| 793 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 794 | veor d25,d24 |
| 795 | vbsl d29,d23,d16 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 796 | vshr.u64 d24,d18,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 797 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 798 | vadd.i64 d27,d29,d17 |
| 799 | vshr.u64 d25,d18,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 800 | vsli.64 d24,d18,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 801 | vadd.i64 d27,d26 |
| 802 | vshr.u64 d26,d18,#39 |
| 803 | vadd.i64 d28,d6 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 804 | vsli.64 d25,d18,#30 |
| 805 | veor d30,d18,d19 |
| 806 | vsli.64 d26,d18,#25 |
| 807 | veor d17,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 808 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 809 | vbsl d30,d20,d19 @ Maj(a,b,c) |
| 810 | veor d17,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 811 | vadd.i64 d21,d27 |
| 812 | vadd.i64 d30,d27 |
| 813 | @ vadd.i64 d17,d30 |
| 814 | vshr.u64 d24,d21,#14 @ 7 |
| 815 | #if 7<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 816 | vld1.64 {d7},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 817 | #endif |
| 818 | vshr.u64 d25,d21,#18 |
| 819 | #if 7>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 820 | vadd.i64 d17,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 821 | #endif |
| 822 | vshr.u64 d26,d21,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 823 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 824 | vsli.64 d24,d21,#50 |
| 825 | vsli.64 d25,d21,#46 |
| 826 | vmov d29,d21 |
| 827 | vsli.64 d26,d21,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 828 | #if 7<16 && defined(__ARMEL__) |
| 829 | vrev64.8 d7,d7 |
| 830 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 831 | veor d25,d24 |
| 832 | vbsl d29,d22,d23 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 833 | vshr.u64 d24,d17,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 834 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 835 | vadd.i64 d27,d29,d16 |
| 836 | vshr.u64 d25,d17,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 837 | vsli.64 d24,d17,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 838 | vadd.i64 d27,d26 |
| 839 | vshr.u64 d26,d17,#39 |
| 840 | vadd.i64 d28,d7 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 841 | vsli.64 d25,d17,#30 |
| 842 | veor d30,d17,d18 |
| 843 | vsli.64 d26,d17,#25 |
| 844 | veor d16,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 845 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 846 | vbsl d30,d19,d18 @ Maj(a,b,c) |
| 847 | veor d16,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 848 | vadd.i64 d20,d27 |
| 849 | vadd.i64 d30,d27 |
| 850 | @ vadd.i64 d16,d30 |
| 851 | vshr.u64 d24,d20,#14 @ 8 |
| 852 | #if 8<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 853 | vld1.64 {d8},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 854 | #endif |
| 855 | vshr.u64 d25,d20,#18 |
| 856 | #if 8>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 857 | vadd.i64 d16,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 858 | #endif |
| 859 | vshr.u64 d26,d20,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 860 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 861 | vsli.64 d24,d20,#50 |
| 862 | vsli.64 d25,d20,#46 |
| 863 | vmov d29,d20 |
| 864 | vsli.64 d26,d20,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 865 | #if 8<16 && defined(__ARMEL__) |
| 866 | vrev64.8 d8,d8 |
| 867 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 868 | veor d25,d24 |
| 869 | vbsl d29,d21,d22 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 870 | vshr.u64 d24,d16,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 871 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 872 | vadd.i64 d27,d29,d23 |
| 873 | vshr.u64 d25,d16,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 874 | vsli.64 d24,d16,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 875 | vadd.i64 d27,d26 |
| 876 | vshr.u64 d26,d16,#39 |
| 877 | vadd.i64 d28,d8 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 878 | vsli.64 d25,d16,#30 |
| 879 | veor d30,d16,d17 |
| 880 | vsli.64 d26,d16,#25 |
| 881 | veor d23,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 882 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 883 | vbsl d30,d18,d17 @ Maj(a,b,c) |
| 884 | veor d23,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 885 | vadd.i64 d19,d27 |
| 886 | vadd.i64 d30,d27 |
| 887 | @ vadd.i64 d23,d30 |
| 888 | vshr.u64 d24,d19,#14 @ 9 |
| 889 | #if 9<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 890 | vld1.64 {d9},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 891 | #endif |
| 892 | vshr.u64 d25,d19,#18 |
| 893 | #if 9>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 894 | vadd.i64 d23,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 895 | #endif |
| 896 | vshr.u64 d26,d19,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 897 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 898 | vsli.64 d24,d19,#50 |
| 899 | vsli.64 d25,d19,#46 |
| 900 | vmov d29,d19 |
| 901 | vsli.64 d26,d19,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 902 | #if 9<16 && defined(__ARMEL__) |
| 903 | vrev64.8 d9,d9 |
| 904 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 905 | veor d25,d24 |
| 906 | vbsl d29,d20,d21 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 907 | vshr.u64 d24,d23,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 908 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 909 | vadd.i64 d27,d29,d22 |
| 910 | vshr.u64 d25,d23,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 911 | vsli.64 d24,d23,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 912 | vadd.i64 d27,d26 |
| 913 | vshr.u64 d26,d23,#39 |
| 914 | vadd.i64 d28,d9 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 915 | vsli.64 d25,d23,#30 |
| 916 | veor d30,d23,d16 |
| 917 | vsli.64 d26,d23,#25 |
| 918 | veor d22,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 919 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 920 | vbsl d30,d17,d16 @ Maj(a,b,c) |
| 921 | veor d22,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 922 | vadd.i64 d18,d27 |
| 923 | vadd.i64 d30,d27 |
| 924 | @ vadd.i64 d22,d30 |
| 925 | vshr.u64 d24,d18,#14 @ 10 |
| 926 | #if 10<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 927 | vld1.64 {d10},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 928 | #endif |
| 929 | vshr.u64 d25,d18,#18 |
| 930 | #if 10>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 931 | vadd.i64 d22,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 932 | #endif |
| 933 | vshr.u64 d26,d18,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 934 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 935 | vsli.64 d24,d18,#50 |
| 936 | vsli.64 d25,d18,#46 |
| 937 | vmov d29,d18 |
| 938 | vsli.64 d26,d18,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 939 | #if 10<16 && defined(__ARMEL__) |
| 940 | vrev64.8 d10,d10 |
| 941 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 942 | veor d25,d24 |
| 943 | vbsl d29,d19,d20 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 944 | vshr.u64 d24,d22,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 945 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 946 | vadd.i64 d27,d29,d21 |
| 947 | vshr.u64 d25,d22,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 948 | vsli.64 d24,d22,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 949 | vadd.i64 d27,d26 |
| 950 | vshr.u64 d26,d22,#39 |
| 951 | vadd.i64 d28,d10 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 952 | vsli.64 d25,d22,#30 |
| 953 | veor d30,d22,d23 |
| 954 | vsli.64 d26,d22,#25 |
| 955 | veor d21,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 956 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 957 | vbsl d30,d16,d23 @ Maj(a,b,c) |
| 958 | veor d21,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 959 | vadd.i64 d17,d27 |
| 960 | vadd.i64 d30,d27 |
| 961 | @ vadd.i64 d21,d30 |
| 962 | vshr.u64 d24,d17,#14 @ 11 |
| 963 | #if 11<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 964 | vld1.64 {d11},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 965 | #endif |
| 966 | vshr.u64 d25,d17,#18 |
| 967 | #if 11>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 968 | vadd.i64 d21,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 969 | #endif |
| 970 | vshr.u64 d26,d17,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 971 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 972 | vsli.64 d24,d17,#50 |
| 973 | vsli.64 d25,d17,#46 |
| 974 | vmov d29,d17 |
| 975 | vsli.64 d26,d17,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 976 | #if 11<16 && defined(__ARMEL__) |
| 977 | vrev64.8 d11,d11 |
| 978 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 979 | veor d25,d24 |
| 980 | vbsl d29,d18,d19 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 981 | vshr.u64 d24,d21,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 982 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 983 | vadd.i64 d27,d29,d20 |
| 984 | vshr.u64 d25,d21,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 985 | vsli.64 d24,d21,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 986 | vadd.i64 d27,d26 |
| 987 | vshr.u64 d26,d21,#39 |
| 988 | vadd.i64 d28,d11 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 989 | vsli.64 d25,d21,#30 |
| 990 | veor d30,d21,d22 |
| 991 | vsli.64 d26,d21,#25 |
| 992 | veor d20,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 993 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 994 | vbsl d30,d23,d22 @ Maj(a,b,c) |
| 995 | veor d20,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 996 | vadd.i64 d16,d27 |
| 997 | vadd.i64 d30,d27 |
| 998 | @ vadd.i64 d20,d30 |
| 999 | vshr.u64 d24,d16,#14 @ 12 |
| 1000 | #if 12<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1001 | vld1.64 {d12},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1002 | #endif |
| 1003 | vshr.u64 d25,d16,#18 |
| 1004 | #if 12>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1005 | vadd.i64 d20,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1006 | #endif |
| 1007 | vshr.u64 d26,d16,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1008 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1009 | vsli.64 d24,d16,#50 |
| 1010 | vsli.64 d25,d16,#46 |
| 1011 | vmov d29,d16 |
| 1012 | vsli.64 d26,d16,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1013 | #if 12<16 && defined(__ARMEL__) |
| 1014 | vrev64.8 d12,d12 |
| 1015 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1016 | veor d25,d24 |
| 1017 | vbsl d29,d17,d18 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1018 | vshr.u64 d24,d20,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1019 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1020 | vadd.i64 d27,d29,d19 |
| 1021 | vshr.u64 d25,d20,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1022 | vsli.64 d24,d20,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1023 | vadd.i64 d27,d26 |
| 1024 | vshr.u64 d26,d20,#39 |
| 1025 | vadd.i64 d28,d12 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1026 | vsli.64 d25,d20,#30 |
| 1027 | veor d30,d20,d21 |
| 1028 | vsli.64 d26,d20,#25 |
| 1029 | veor d19,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1030 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1031 | vbsl d30,d22,d21 @ Maj(a,b,c) |
| 1032 | veor d19,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1033 | vadd.i64 d23,d27 |
| 1034 | vadd.i64 d30,d27 |
| 1035 | @ vadd.i64 d19,d30 |
| 1036 | vshr.u64 d24,d23,#14 @ 13 |
| 1037 | #if 13<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1038 | vld1.64 {d13},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1039 | #endif |
| 1040 | vshr.u64 d25,d23,#18 |
| 1041 | #if 13>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1042 | vadd.i64 d19,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1043 | #endif |
| 1044 | vshr.u64 d26,d23,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1045 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1046 | vsli.64 d24,d23,#50 |
| 1047 | vsli.64 d25,d23,#46 |
| 1048 | vmov d29,d23 |
| 1049 | vsli.64 d26,d23,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1050 | #if 13<16 && defined(__ARMEL__) |
| 1051 | vrev64.8 d13,d13 |
| 1052 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1053 | veor d25,d24 |
| 1054 | vbsl d29,d16,d17 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1055 | vshr.u64 d24,d19,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1056 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1057 | vadd.i64 d27,d29,d18 |
| 1058 | vshr.u64 d25,d19,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1059 | vsli.64 d24,d19,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1060 | vadd.i64 d27,d26 |
| 1061 | vshr.u64 d26,d19,#39 |
| 1062 | vadd.i64 d28,d13 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1063 | vsli.64 d25,d19,#30 |
| 1064 | veor d30,d19,d20 |
| 1065 | vsli.64 d26,d19,#25 |
| 1066 | veor d18,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1067 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1068 | vbsl d30,d21,d20 @ Maj(a,b,c) |
| 1069 | veor d18,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1070 | vadd.i64 d22,d27 |
| 1071 | vadd.i64 d30,d27 |
| 1072 | @ vadd.i64 d18,d30 |
| 1073 | vshr.u64 d24,d22,#14 @ 14 |
| 1074 | #if 14<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1075 | vld1.64 {d14},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1076 | #endif |
| 1077 | vshr.u64 d25,d22,#18 |
| 1078 | #if 14>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1079 | vadd.i64 d18,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1080 | #endif |
| 1081 | vshr.u64 d26,d22,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1082 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1083 | vsli.64 d24,d22,#50 |
| 1084 | vsli.64 d25,d22,#46 |
| 1085 | vmov d29,d22 |
| 1086 | vsli.64 d26,d22,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1087 | #if 14<16 && defined(__ARMEL__) |
| 1088 | vrev64.8 d14,d14 |
| 1089 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1090 | veor d25,d24 |
| 1091 | vbsl d29,d23,d16 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1092 | vshr.u64 d24,d18,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1093 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1094 | vadd.i64 d27,d29,d17 |
| 1095 | vshr.u64 d25,d18,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1096 | vsli.64 d24,d18,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1097 | vadd.i64 d27,d26 |
| 1098 | vshr.u64 d26,d18,#39 |
| 1099 | vadd.i64 d28,d14 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1100 | vsli.64 d25,d18,#30 |
| 1101 | veor d30,d18,d19 |
| 1102 | vsli.64 d26,d18,#25 |
| 1103 | veor d17,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1104 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1105 | vbsl d30,d20,d19 @ Maj(a,b,c) |
| 1106 | veor d17,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1107 | vadd.i64 d21,d27 |
| 1108 | vadd.i64 d30,d27 |
| 1109 | @ vadd.i64 d17,d30 |
| 1110 | vshr.u64 d24,d21,#14 @ 15 |
| 1111 | #if 15<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1112 | vld1.64 {d15},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1113 | #endif |
| 1114 | vshr.u64 d25,d21,#18 |
| 1115 | #if 15>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1116 | vadd.i64 d17,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1117 | #endif |
| 1118 | vshr.u64 d26,d21,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1119 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1120 | vsli.64 d24,d21,#50 |
| 1121 | vsli.64 d25,d21,#46 |
| 1122 | vmov d29,d21 |
| 1123 | vsli.64 d26,d21,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1124 | #if 15<16 && defined(__ARMEL__) |
| 1125 | vrev64.8 d15,d15 |
| 1126 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1127 | veor d25,d24 |
| 1128 | vbsl d29,d22,d23 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1129 | vshr.u64 d24,d17,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1130 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1131 | vadd.i64 d27,d29,d16 |
| 1132 | vshr.u64 d25,d17,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1133 | vsli.64 d24,d17,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1134 | vadd.i64 d27,d26 |
| 1135 | vshr.u64 d26,d17,#39 |
| 1136 | vadd.i64 d28,d15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1137 | vsli.64 d25,d17,#30 |
| 1138 | veor d30,d17,d18 |
| 1139 | vsli.64 d26,d17,#25 |
| 1140 | veor d16,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1141 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1142 | vbsl d30,d19,d18 @ Maj(a,b,c) |
| 1143 | veor d16,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1144 | vadd.i64 d20,d27 |
| 1145 | vadd.i64 d30,d27 |
| 1146 | @ vadd.i64 d16,d30 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1147 | mov r12,#4 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1148 | .L16_79_neon: |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1149 | subs r12,#1 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1150 | vshr.u64 q12,q7,#19 |
| 1151 | vshr.u64 q13,q7,#61 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1152 | vadd.i64 d16,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1153 | vshr.u64 q15,q7,#6 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1154 | vsli.64 q12,q7,#45 |
| 1155 | vext.8 q14,q0,q1,#8 @ X[i+1] |
| 1156 | vsli.64 q13,q7,#3 |
| 1157 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1158 | vshr.u64 q12,q14,#1 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1159 | veor q15,q13 @ sigma1(X[i+14]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1160 | vshr.u64 q13,q14,#8 |
| 1161 | vadd.i64 q0,q15 |
| 1162 | vshr.u64 q15,q14,#7 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1163 | vsli.64 q12,q14,#63 |
| 1164 | vsli.64 q13,q14,#56 |
| 1165 | vext.8 q14,q4,q5,#8 @ X[i+9] |
| 1166 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1167 | vshr.u64 d24,d20,#14 @ from NEON_00_15 |
| 1168 | vadd.i64 q0,q14 |
| 1169 | vshr.u64 d25,d20,#18 @ from NEON_00_15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1170 | veor q15,q13 @ sigma0(X[i+1]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1171 | vshr.u64 d26,d20,#41 @ from NEON_00_15 |
| 1172 | vadd.i64 q0,q15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1173 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1174 | vsli.64 d24,d20,#50 |
| 1175 | vsli.64 d25,d20,#46 |
| 1176 | vmov d29,d20 |
| 1177 | vsli.64 d26,d20,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1178 | #if 16<16 && defined(__ARMEL__) |
| 1179 | vrev64.8 , |
| 1180 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1181 | veor d25,d24 |
| 1182 | vbsl d29,d21,d22 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1183 | vshr.u64 d24,d16,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1184 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1185 | vadd.i64 d27,d29,d23 |
| 1186 | vshr.u64 d25,d16,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1187 | vsli.64 d24,d16,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1188 | vadd.i64 d27,d26 |
| 1189 | vshr.u64 d26,d16,#39 |
| 1190 | vadd.i64 d28,d0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1191 | vsli.64 d25,d16,#30 |
| 1192 | veor d30,d16,d17 |
| 1193 | vsli.64 d26,d16,#25 |
| 1194 | veor d23,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1195 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1196 | vbsl d30,d18,d17 @ Maj(a,b,c) |
| 1197 | veor d23,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1198 | vadd.i64 d19,d27 |
| 1199 | vadd.i64 d30,d27 |
| 1200 | @ vadd.i64 d23,d30 |
| 1201 | vshr.u64 d24,d19,#14 @ 17 |
| 1202 | #if 17<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1203 | vld1.64 {d1},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1204 | #endif |
| 1205 | vshr.u64 d25,d19,#18 |
| 1206 | #if 17>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1207 | vadd.i64 d23,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1208 | #endif |
| 1209 | vshr.u64 d26,d19,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1210 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1211 | vsli.64 d24,d19,#50 |
| 1212 | vsli.64 d25,d19,#46 |
| 1213 | vmov d29,d19 |
| 1214 | vsli.64 d26,d19,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1215 | #if 17<16 && defined(__ARMEL__) |
| 1216 | vrev64.8 , |
| 1217 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1218 | veor d25,d24 |
| 1219 | vbsl d29,d20,d21 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1220 | vshr.u64 d24,d23,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1221 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1222 | vadd.i64 d27,d29,d22 |
| 1223 | vshr.u64 d25,d23,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1224 | vsli.64 d24,d23,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1225 | vadd.i64 d27,d26 |
| 1226 | vshr.u64 d26,d23,#39 |
| 1227 | vadd.i64 d28,d1 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1228 | vsli.64 d25,d23,#30 |
| 1229 | veor d30,d23,d16 |
| 1230 | vsli.64 d26,d23,#25 |
| 1231 | veor d22,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1232 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1233 | vbsl d30,d17,d16 @ Maj(a,b,c) |
| 1234 | veor d22,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1235 | vadd.i64 d18,d27 |
| 1236 | vadd.i64 d30,d27 |
| 1237 | @ vadd.i64 d22,d30 |
| 1238 | vshr.u64 q12,q0,#19 |
| 1239 | vshr.u64 q13,q0,#61 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1240 | vadd.i64 d22,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1241 | vshr.u64 q15,q0,#6 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1242 | vsli.64 q12,q0,#45 |
| 1243 | vext.8 q14,q1,q2,#8 @ X[i+1] |
| 1244 | vsli.64 q13,q0,#3 |
| 1245 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1246 | vshr.u64 q12,q14,#1 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1247 | veor q15,q13 @ sigma1(X[i+14]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1248 | vshr.u64 q13,q14,#8 |
| 1249 | vadd.i64 q1,q15 |
| 1250 | vshr.u64 q15,q14,#7 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1251 | vsli.64 q12,q14,#63 |
| 1252 | vsli.64 q13,q14,#56 |
| 1253 | vext.8 q14,q5,q6,#8 @ X[i+9] |
| 1254 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1255 | vshr.u64 d24,d18,#14 @ from NEON_00_15 |
| 1256 | vadd.i64 q1,q14 |
| 1257 | vshr.u64 d25,d18,#18 @ from NEON_00_15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1258 | veor q15,q13 @ sigma0(X[i+1]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1259 | vshr.u64 d26,d18,#41 @ from NEON_00_15 |
| 1260 | vadd.i64 q1,q15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1261 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1262 | vsli.64 d24,d18,#50 |
| 1263 | vsli.64 d25,d18,#46 |
| 1264 | vmov d29,d18 |
| 1265 | vsli.64 d26,d18,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1266 | #if 18<16 && defined(__ARMEL__) |
| 1267 | vrev64.8 , |
| 1268 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1269 | veor d25,d24 |
| 1270 | vbsl d29,d19,d20 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1271 | vshr.u64 d24,d22,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1272 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1273 | vadd.i64 d27,d29,d21 |
| 1274 | vshr.u64 d25,d22,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1275 | vsli.64 d24,d22,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1276 | vadd.i64 d27,d26 |
| 1277 | vshr.u64 d26,d22,#39 |
| 1278 | vadd.i64 d28,d2 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1279 | vsli.64 d25,d22,#30 |
| 1280 | veor d30,d22,d23 |
| 1281 | vsli.64 d26,d22,#25 |
| 1282 | veor d21,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1283 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1284 | vbsl d30,d16,d23 @ Maj(a,b,c) |
| 1285 | veor d21,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1286 | vadd.i64 d17,d27 |
| 1287 | vadd.i64 d30,d27 |
| 1288 | @ vadd.i64 d21,d30 |
| 1289 | vshr.u64 d24,d17,#14 @ 19 |
| 1290 | #if 19<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1291 | vld1.64 {d3},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1292 | #endif |
| 1293 | vshr.u64 d25,d17,#18 |
| 1294 | #if 19>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1295 | vadd.i64 d21,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1296 | #endif |
| 1297 | vshr.u64 d26,d17,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1298 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1299 | vsli.64 d24,d17,#50 |
| 1300 | vsli.64 d25,d17,#46 |
| 1301 | vmov d29,d17 |
| 1302 | vsli.64 d26,d17,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1303 | #if 19<16 && defined(__ARMEL__) |
| 1304 | vrev64.8 , |
| 1305 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1306 | veor d25,d24 |
| 1307 | vbsl d29,d18,d19 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1308 | vshr.u64 d24,d21,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1309 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1310 | vadd.i64 d27,d29,d20 |
| 1311 | vshr.u64 d25,d21,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1312 | vsli.64 d24,d21,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1313 | vadd.i64 d27,d26 |
| 1314 | vshr.u64 d26,d21,#39 |
| 1315 | vadd.i64 d28,d3 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1316 | vsli.64 d25,d21,#30 |
| 1317 | veor d30,d21,d22 |
| 1318 | vsli.64 d26,d21,#25 |
| 1319 | veor d20,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1320 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1321 | vbsl d30,d23,d22 @ Maj(a,b,c) |
| 1322 | veor d20,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1323 | vadd.i64 d16,d27 |
| 1324 | vadd.i64 d30,d27 |
| 1325 | @ vadd.i64 d20,d30 |
| 1326 | vshr.u64 q12,q1,#19 |
| 1327 | vshr.u64 q13,q1,#61 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1328 | vadd.i64 d20,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1329 | vshr.u64 q15,q1,#6 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1330 | vsli.64 q12,q1,#45 |
| 1331 | vext.8 q14,q2,q3,#8 @ X[i+1] |
| 1332 | vsli.64 q13,q1,#3 |
| 1333 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1334 | vshr.u64 q12,q14,#1 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1335 | veor q15,q13 @ sigma1(X[i+14]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1336 | vshr.u64 q13,q14,#8 |
| 1337 | vadd.i64 q2,q15 |
| 1338 | vshr.u64 q15,q14,#7 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1339 | vsli.64 q12,q14,#63 |
| 1340 | vsli.64 q13,q14,#56 |
| 1341 | vext.8 q14,q6,q7,#8 @ X[i+9] |
| 1342 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1343 | vshr.u64 d24,d16,#14 @ from NEON_00_15 |
| 1344 | vadd.i64 q2,q14 |
| 1345 | vshr.u64 d25,d16,#18 @ from NEON_00_15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1346 | veor q15,q13 @ sigma0(X[i+1]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1347 | vshr.u64 d26,d16,#41 @ from NEON_00_15 |
| 1348 | vadd.i64 q2,q15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1349 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1350 | vsli.64 d24,d16,#50 |
| 1351 | vsli.64 d25,d16,#46 |
| 1352 | vmov d29,d16 |
| 1353 | vsli.64 d26,d16,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1354 | #if 20<16 && defined(__ARMEL__) |
| 1355 | vrev64.8 , |
| 1356 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1357 | veor d25,d24 |
| 1358 | vbsl d29,d17,d18 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1359 | vshr.u64 d24,d20,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1360 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1361 | vadd.i64 d27,d29,d19 |
| 1362 | vshr.u64 d25,d20,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1363 | vsli.64 d24,d20,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1364 | vadd.i64 d27,d26 |
| 1365 | vshr.u64 d26,d20,#39 |
| 1366 | vadd.i64 d28,d4 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1367 | vsli.64 d25,d20,#30 |
| 1368 | veor d30,d20,d21 |
| 1369 | vsli.64 d26,d20,#25 |
| 1370 | veor d19,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1371 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1372 | vbsl d30,d22,d21 @ Maj(a,b,c) |
| 1373 | veor d19,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1374 | vadd.i64 d23,d27 |
| 1375 | vadd.i64 d30,d27 |
| 1376 | @ vadd.i64 d19,d30 |
| 1377 | vshr.u64 d24,d23,#14 @ 21 |
| 1378 | #if 21<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1379 | vld1.64 {d5},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1380 | #endif |
| 1381 | vshr.u64 d25,d23,#18 |
| 1382 | #if 21>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1383 | vadd.i64 d19,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1384 | #endif |
| 1385 | vshr.u64 d26,d23,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1386 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1387 | vsli.64 d24,d23,#50 |
| 1388 | vsli.64 d25,d23,#46 |
| 1389 | vmov d29,d23 |
| 1390 | vsli.64 d26,d23,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1391 | #if 21<16 && defined(__ARMEL__) |
| 1392 | vrev64.8 , |
| 1393 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1394 | veor d25,d24 |
| 1395 | vbsl d29,d16,d17 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1396 | vshr.u64 d24,d19,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1397 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1398 | vadd.i64 d27,d29,d18 |
| 1399 | vshr.u64 d25,d19,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1400 | vsli.64 d24,d19,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1401 | vadd.i64 d27,d26 |
| 1402 | vshr.u64 d26,d19,#39 |
| 1403 | vadd.i64 d28,d5 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1404 | vsli.64 d25,d19,#30 |
| 1405 | veor d30,d19,d20 |
| 1406 | vsli.64 d26,d19,#25 |
| 1407 | veor d18,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1408 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1409 | vbsl d30,d21,d20 @ Maj(a,b,c) |
| 1410 | veor d18,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1411 | vadd.i64 d22,d27 |
| 1412 | vadd.i64 d30,d27 |
| 1413 | @ vadd.i64 d18,d30 |
| 1414 | vshr.u64 q12,q2,#19 |
| 1415 | vshr.u64 q13,q2,#61 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1416 | vadd.i64 d18,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1417 | vshr.u64 q15,q2,#6 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1418 | vsli.64 q12,q2,#45 |
| 1419 | vext.8 q14,q3,q4,#8 @ X[i+1] |
| 1420 | vsli.64 q13,q2,#3 |
| 1421 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1422 | vshr.u64 q12,q14,#1 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1423 | veor q15,q13 @ sigma1(X[i+14]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1424 | vshr.u64 q13,q14,#8 |
| 1425 | vadd.i64 q3,q15 |
| 1426 | vshr.u64 q15,q14,#7 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1427 | vsli.64 q12,q14,#63 |
| 1428 | vsli.64 q13,q14,#56 |
| 1429 | vext.8 q14,q7,q0,#8 @ X[i+9] |
| 1430 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1431 | vshr.u64 d24,d22,#14 @ from NEON_00_15 |
| 1432 | vadd.i64 q3,q14 |
| 1433 | vshr.u64 d25,d22,#18 @ from NEON_00_15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1434 | veor q15,q13 @ sigma0(X[i+1]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1435 | vshr.u64 d26,d22,#41 @ from NEON_00_15 |
| 1436 | vadd.i64 q3,q15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1437 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1438 | vsli.64 d24,d22,#50 |
| 1439 | vsli.64 d25,d22,#46 |
| 1440 | vmov d29,d22 |
| 1441 | vsli.64 d26,d22,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1442 | #if 22<16 && defined(__ARMEL__) |
| 1443 | vrev64.8 , |
| 1444 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1445 | veor d25,d24 |
| 1446 | vbsl d29,d23,d16 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1447 | vshr.u64 d24,d18,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1448 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1449 | vadd.i64 d27,d29,d17 |
| 1450 | vshr.u64 d25,d18,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1451 | vsli.64 d24,d18,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1452 | vadd.i64 d27,d26 |
| 1453 | vshr.u64 d26,d18,#39 |
| 1454 | vadd.i64 d28,d6 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1455 | vsli.64 d25,d18,#30 |
| 1456 | veor d30,d18,d19 |
| 1457 | vsli.64 d26,d18,#25 |
| 1458 | veor d17,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1459 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1460 | vbsl d30,d20,d19 @ Maj(a,b,c) |
| 1461 | veor d17,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1462 | vadd.i64 d21,d27 |
| 1463 | vadd.i64 d30,d27 |
| 1464 | @ vadd.i64 d17,d30 |
| 1465 | vshr.u64 d24,d21,#14 @ 23 |
| 1466 | #if 23<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1467 | vld1.64 {d7},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1468 | #endif |
| 1469 | vshr.u64 d25,d21,#18 |
| 1470 | #if 23>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1471 | vadd.i64 d17,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1472 | #endif |
| 1473 | vshr.u64 d26,d21,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1474 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1475 | vsli.64 d24,d21,#50 |
| 1476 | vsli.64 d25,d21,#46 |
| 1477 | vmov d29,d21 |
| 1478 | vsli.64 d26,d21,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1479 | #if 23<16 && defined(__ARMEL__) |
| 1480 | vrev64.8 , |
| 1481 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1482 | veor d25,d24 |
| 1483 | vbsl d29,d22,d23 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1484 | vshr.u64 d24,d17,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1485 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1486 | vadd.i64 d27,d29,d16 |
| 1487 | vshr.u64 d25,d17,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1488 | vsli.64 d24,d17,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1489 | vadd.i64 d27,d26 |
| 1490 | vshr.u64 d26,d17,#39 |
| 1491 | vadd.i64 d28,d7 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1492 | vsli.64 d25,d17,#30 |
| 1493 | veor d30,d17,d18 |
| 1494 | vsli.64 d26,d17,#25 |
| 1495 | veor d16,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1496 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1497 | vbsl d30,d19,d18 @ Maj(a,b,c) |
| 1498 | veor d16,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1499 | vadd.i64 d20,d27 |
| 1500 | vadd.i64 d30,d27 |
| 1501 | @ vadd.i64 d16,d30 |
| 1502 | vshr.u64 q12,q3,#19 |
| 1503 | vshr.u64 q13,q3,#61 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1504 | vadd.i64 d16,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1505 | vshr.u64 q15,q3,#6 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1506 | vsli.64 q12,q3,#45 |
| 1507 | vext.8 q14,q4,q5,#8 @ X[i+1] |
| 1508 | vsli.64 q13,q3,#3 |
| 1509 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1510 | vshr.u64 q12,q14,#1 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1511 | veor q15,q13 @ sigma1(X[i+14]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1512 | vshr.u64 q13,q14,#8 |
| 1513 | vadd.i64 q4,q15 |
| 1514 | vshr.u64 q15,q14,#7 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1515 | vsli.64 q12,q14,#63 |
| 1516 | vsli.64 q13,q14,#56 |
| 1517 | vext.8 q14,q0,q1,#8 @ X[i+9] |
| 1518 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1519 | vshr.u64 d24,d20,#14 @ from NEON_00_15 |
| 1520 | vadd.i64 q4,q14 |
| 1521 | vshr.u64 d25,d20,#18 @ from NEON_00_15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1522 | veor q15,q13 @ sigma0(X[i+1]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1523 | vshr.u64 d26,d20,#41 @ from NEON_00_15 |
| 1524 | vadd.i64 q4,q15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1525 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1526 | vsli.64 d24,d20,#50 |
| 1527 | vsli.64 d25,d20,#46 |
| 1528 | vmov d29,d20 |
| 1529 | vsli.64 d26,d20,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1530 | #if 24<16 && defined(__ARMEL__) |
| 1531 | vrev64.8 , |
| 1532 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1533 | veor d25,d24 |
| 1534 | vbsl d29,d21,d22 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1535 | vshr.u64 d24,d16,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1536 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1537 | vadd.i64 d27,d29,d23 |
| 1538 | vshr.u64 d25,d16,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1539 | vsli.64 d24,d16,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1540 | vadd.i64 d27,d26 |
| 1541 | vshr.u64 d26,d16,#39 |
| 1542 | vadd.i64 d28,d8 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1543 | vsli.64 d25,d16,#30 |
| 1544 | veor d30,d16,d17 |
| 1545 | vsli.64 d26,d16,#25 |
| 1546 | veor d23,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1547 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1548 | vbsl d30,d18,d17 @ Maj(a,b,c) |
| 1549 | veor d23,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1550 | vadd.i64 d19,d27 |
| 1551 | vadd.i64 d30,d27 |
| 1552 | @ vadd.i64 d23,d30 |
| 1553 | vshr.u64 d24,d19,#14 @ 25 |
| 1554 | #if 25<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1555 | vld1.64 {d9},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1556 | #endif |
| 1557 | vshr.u64 d25,d19,#18 |
| 1558 | #if 25>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1559 | vadd.i64 d23,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1560 | #endif |
| 1561 | vshr.u64 d26,d19,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1562 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1563 | vsli.64 d24,d19,#50 |
| 1564 | vsli.64 d25,d19,#46 |
| 1565 | vmov d29,d19 |
| 1566 | vsli.64 d26,d19,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1567 | #if 25<16 && defined(__ARMEL__) |
| 1568 | vrev64.8 , |
| 1569 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1570 | veor d25,d24 |
| 1571 | vbsl d29,d20,d21 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1572 | vshr.u64 d24,d23,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1573 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1574 | vadd.i64 d27,d29,d22 |
| 1575 | vshr.u64 d25,d23,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1576 | vsli.64 d24,d23,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1577 | vadd.i64 d27,d26 |
| 1578 | vshr.u64 d26,d23,#39 |
| 1579 | vadd.i64 d28,d9 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1580 | vsli.64 d25,d23,#30 |
| 1581 | veor d30,d23,d16 |
| 1582 | vsli.64 d26,d23,#25 |
| 1583 | veor d22,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1584 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1585 | vbsl d30,d17,d16 @ Maj(a,b,c) |
| 1586 | veor d22,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1587 | vadd.i64 d18,d27 |
| 1588 | vadd.i64 d30,d27 |
| 1589 | @ vadd.i64 d22,d30 |
| 1590 | vshr.u64 q12,q4,#19 |
| 1591 | vshr.u64 q13,q4,#61 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1592 | vadd.i64 d22,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1593 | vshr.u64 q15,q4,#6 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1594 | vsli.64 q12,q4,#45 |
| 1595 | vext.8 q14,q5,q6,#8 @ X[i+1] |
| 1596 | vsli.64 q13,q4,#3 |
| 1597 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1598 | vshr.u64 q12,q14,#1 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1599 | veor q15,q13 @ sigma1(X[i+14]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1600 | vshr.u64 q13,q14,#8 |
| 1601 | vadd.i64 q5,q15 |
| 1602 | vshr.u64 q15,q14,#7 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1603 | vsli.64 q12,q14,#63 |
| 1604 | vsli.64 q13,q14,#56 |
| 1605 | vext.8 q14,q1,q2,#8 @ X[i+9] |
| 1606 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1607 | vshr.u64 d24,d18,#14 @ from NEON_00_15 |
| 1608 | vadd.i64 q5,q14 |
| 1609 | vshr.u64 d25,d18,#18 @ from NEON_00_15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1610 | veor q15,q13 @ sigma0(X[i+1]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1611 | vshr.u64 d26,d18,#41 @ from NEON_00_15 |
| 1612 | vadd.i64 q5,q15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1613 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1614 | vsli.64 d24,d18,#50 |
| 1615 | vsli.64 d25,d18,#46 |
| 1616 | vmov d29,d18 |
| 1617 | vsli.64 d26,d18,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1618 | #if 26<16 && defined(__ARMEL__) |
| 1619 | vrev64.8 , |
| 1620 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1621 | veor d25,d24 |
| 1622 | vbsl d29,d19,d20 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1623 | vshr.u64 d24,d22,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1624 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1625 | vadd.i64 d27,d29,d21 |
| 1626 | vshr.u64 d25,d22,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1627 | vsli.64 d24,d22,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1628 | vadd.i64 d27,d26 |
| 1629 | vshr.u64 d26,d22,#39 |
| 1630 | vadd.i64 d28,d10 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1631 | vsli.64 d25,d22,#30 |
| 1632 | veor d30,d22,d23 |
| 1633 | vsli.64 d26,d22,#25 |
| 1634 | veor d21,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1635 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1636 | vbsl d30,d16,d23 @ Maj(a,b,c) |
| 1637 | veor d21,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1638 | vadd.i64 d17,d27 |
| 1639 | vadd.i64 d30,d27 |
| 1640 | @ vadd.i64 d21,d30 |
| 1641 | vshr.u64 d24,d17,#14 @ 27 |
| 1642 | #if 27<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1643 | vld1.64 {d11},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1644 | #endif |
| 1645 | vshr.u64 d25,d17,#18 |
| 1646 | #if 27>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1647 | vadd.i64 d21,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1648 | #endif |
| 1649 | vshr.u64 d26,d17,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1650 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1651 | vsli.64 d24,d17,#50 |
| 1652 | vsli.64 d25,d17,#46 |
| 1653 | vmov d29,d17 |
| 1654 | vsli.64 d26,d17,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1655 | #if 27<16 && defined(__ARMEL__) |
| 1656 | vrev64.8 , |
| 1657 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1658 | veor d25,d24 |
| 1659 | vbsl d29,d18,d19 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1660 | vshr.u64 d24,d21,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1661 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1662 | vadd.i64 d27,d29,d20 |
| 1663 | vshr.u64 d25,d21,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1664 | vsli.64 d24,d21,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1665 | vadd.i64 d27,d26 |
| 1666 | vshr.u64 d26,d21,#39 |
| 1667 | vadd.i64 d28,d11 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1668 | vsli.64 d25,d21,#30 |
| 1669 | veor d30,d21,d22 |
| 1670 | vsli.64 d26,d21,#25 |
| 1671 | veor d20,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1672 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1673 | vbsl d30,d23,d22 @ Maj(a,b,c) |
| 1674 | veor d20,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1675 | vadd.i64 d16,d27 |
| 1676 | vadd.i64 d30,d27 |
| 1677 | @ vadd.i64 d20,d30 |
| 1678 | vshr.u64 q12,q5,#19 |
| 1679 | vshr.u64 q13,q5,#61 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1680 | vadd.i64 d20,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1681 | vshr.u64 q15,q5,#6 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1682 | vsli.64 q12,q5,#45 |
| 1683 | vext.8 q14,q6,q7,#8 @ X[i+1] |
| 1684 | vsli.64 q13,q5,#3 |
| 1685 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1686 | vshr.u64 q12,q14,#1 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1687 | veor q15,q13 @ sigma1(X[i+14]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1688 | vshr.u64 q13,q14,#8 |
| 1689 | vadd.i64 q6,q15 |
| 1690 | vshr.u64 q15,q14,#7 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1691 | vsli.64 q12,q14,#63 |
| 1692 | vsli.64 q13,q14,#56 |
| 1693 | vext.8 q14,q2,q3,#8 @ X[i+9] |
| 1694 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1695 | vshr.u64 d24,d16,#14 @ from NEON_00_15 |
| 1696 | vadd.i64 q6,q14 |
| 1697 | vshr.u64 d25,d16,#18 @ from NEON_00_15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1698 | veor q15,q13 @ sigma0(X[i+1]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1699 | vshr.u64 d26,d16,#41 @ from NEON_00_15 |
| 1700 | vadd.i64 q6,q15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1701 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1702 | vsli.64 d24,d16,#50 |
| 1703 | vsli.64 d25,d16,#46 |
| 1704 | vmov d29,d16 |
| 1705 | vsli.64 d26,d16,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1706 | #if 28<16 && defined(__ARMEL__) |
| 1707 | vrev64.8 , |
| 1708 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1709 | veor d25,d24 |
| 1710 | vbsl d29,d17,d18 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1711 | vshr.u64 d24,d20,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1712 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1713 | vadd.i64 d27,d29,d19 |
| 1714 | vshr.u64 d25,d20,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1715 | vsli.64 d24,d20,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1716 | vadd.i64 d27,d26 |
| 1717 | vshr.u64 d26,d20,#39 |
| 1718 | vadd.i64 d28,d12 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1719 | vsli.64 d25,d20,#30 |
| 1720 | veor d30,d20,d21 |
| 1721 | vsli.64 d26,d20,#25 |
| 1722 | veor d19,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1723 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1724 | vbsl d30,d22,d21 @ Maj(a,b,c) |
| 1725 | veor d19,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1726 | vadd.i64 d23,d27 |
| 1727 | vadd.i64 d30,d27 |
| 1728 | @ vadd.i64 d19,d30 |
| 1729 | vshr.u64 d24,d23,#14 @ 29 |
| 1730 | #if 29<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1731 | vld1.64 {d13},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1732 | #endif |
| 1733 | vshr.u64 d25,d23,#18 |
| 1734 | #if 29>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1735 | vadd.i64 d19,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1736 | #endif |
| 1737 | vshr.u64 d26,d23,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1738 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1739 | vsli.64 d24,d23,#50 |
| 1740 | vsli.64 d25,d23,#46 |
| 1741 | vmov d29,d23 |
| 1742 | vsli.64 d26,d23,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1743 | #if 29<16 && defined(__ARMEL__) |
| 1744 | vrev64.8 , |
| 1745 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1746 | veor d25,d24 |
| 1747 | vbsl d29,d16,d17 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1748 | vshr.u64 d24,d19,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1749 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1750 | vadd.i64 d27,d29,d18 |
| 1751 | vshr.u64 d25,d19,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1752 | vsli.64 d24,d19,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1753 | vadd.i64 d27,d26 |
| 1754 | vshr.u64 d26,d19,#39 |
| 1755 | vadd.i64 d28,d13 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1756 | vsli.64 d25,d19,#30 |
| 1757 | veor d30,d19,d20 |
| 1758 | vsli.64 d26,d19,#25 |
| 1759 | veor d18,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1760 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1761 | vbsl d30,d21,d20 @ Maj(a,b,c) |
| 1762 | veor d18,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1763 | vadd.i64 d22,d27 |
| 1764 | vadd.i64 d30,d27 |
| 1765 | @ vadd.i64 d18,d30 |
| 1766 | vshr.u64 q12,q6,#19 |
| 1767 | vshr.u64 q13,q6,#61 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1768 | vadd.i64 d18,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1769 | vshr.u64 q15,q6,#6 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1770 | vsli.64 q12,q6,#45 |
| 1771 | vext.8 q14,q7,q0,#8 @ X[i+1] |
| 1772 | vsli.64 q13,q6,#3 |
| 1773 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1774 | vshr.u64 q12,q14,#1 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1775 | veor q15,q13 @ sigma1(X[i+14]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1776 | vshr.u64 q13,q14,#8 |
| 1777 | vadd.i64 q7,q15 |
| 1778 | vshr.u64 q15,q14,#7 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1779 | vsli.64 q12,q14,#63 |
| 1780 | vsli.64 q13,q14,#56 |
| 1781 | vext.8 q14,q3,q4,#8 @ X[i+9] |
| 1782 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1783 | vshr.u64 d24,d22,#14 @ from NEON_00_15 |
| 1784 | vadd.i64 q7,q14 |
| 1785 | vshr.u64 d25,d22,#18 @ from NEON_00_15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1786 | veor q15,q13 @ sigma0(X[i+1]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1787 | vshr.u64 d26,d22,#41 @ from NEON_00_15 |
| 1788 | vadd.i64 q7,q15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1789 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1790 | vsli.64 d24,d22,#50 |
| 1791 | vsli.64 d25,d22,#46 |
| 1792 | vmov d29,d22 |
| 1793 | vsli.64 d26,d22,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1794 | #if 30<16 && defined(__ARMEL__) |
| 1795 | vrev64.8 , |
| 1796 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1797 | veor d25,d24 |
| 1798 | vbsl d29,d23,d16 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1799 | vshr.u64 d24,d18,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1800 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1801 | vadd.i64 d27,d29,d17 |
| 1802 | vshr.u64 d25,d18,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1803 | vsli.64 d24,d18,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1804 | vadd.i64 d27,d26 |
| 1805 | vshr.u64 d26,d18,#39 |
| 1806 | vadd.i64 d28,d14 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1807 | vsli.64 d25,d18,#30 |
| 1808 | veor d30,d18,d19 |
| 1809 | vsli.64 d26,d18,#25 |
| 1810 | veor d17,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1811 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1812 | vbsl d30,d20,d19 @ Maj(a,b,c) |
| 1813 | veor d17,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1814 | vadd.i64 d21,d27 |
| 1815 | vadd.i64 d30,d27 |
| 1816 | @ vadd.i64 d17,d30 |
| 1817 | vshr.u64 d24,d21,#14 @ 31 |
| 1818 | #if 31<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1819 | vld1.64 {d15},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1820 | #endif |
| 1821 | vshr.u64 d25,d21,#18 |
| 1822 | #if 31>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1823 | vadd.i64 d17,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1824 | #endif |
| 1825 | vshr.u64 d26,d21,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1826 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1827 | vsli.64 d24,d21,#50 |
| 1828 | vsli.64 d25,d21,#46 |
| 1829 | vmov d29,d21 |
| 1830 | vsli.64 d26,d21,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1831 | #if 31<16 && defined(__ARMEL__) |
| 1832 | vrev64.8 , |
| 1833 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1834 | veor d25,d24 |
| 1835 | vbsl d29,d22,d23 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1836 | vshr.u64 d24,d17,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1837 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1838 | vadd.i64 d27,d29,d16 |
| 1839 | vshr.u64 d25,d17,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1840 | vsli.64 d24,d17,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1841 | vadd.i64 d27,d26 |
| 1842 | vshr.u64 d26,d17,#39 |
| 1843 | vadd.i64 d28,d15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1844 | vsli.64 d25,d17,#30 |
| 1845 | veor d30,d17,d18 |
| 1846 | vsli.64 d26,d17,#25 |
| 1847 | veor d16,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1848 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1849 | vbsl d30,d19,d18 @ Maj(a,b,c) |
| 1850 | veor d16,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1851 | vadd.i64 d20,d27 |
| 1852 | vadd.i64 d30,d27 |
| 1853 | @ vadd.i64 d16,d30 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1854 | bne .L16_79_neon |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1855 | |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1856 | vadd.i64 d16,d30 @ h+=Maj from the past |
| 1857 | vldmia r0,{d24,d25,d26,d27,d28,d29,d30,d31} @ load context to temp |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1858 | vadd.i64 q8,q12 @ vectorized accumulate |
| 1859 | vadd.i64 q9,q13 |
| 1860 | vadd.i64 q10,q14 |
| 1861 | vadd.i64 q11,q15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1862 | vstmia r0,{d16,d17,d18,d19,d20,d21,d22,d23} @ save context |
| 1863 | teq r1,r2 |
| 1864 | sub r3,#640 @ rewind K512 |
| 1865 | bne .Loop_neon |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1866 | |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1867 | VFP_ABI_POP |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1868 | bx lr @ .word 0xe12fff1e |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1869 | .size sha512_block_data_order_neon,.-sha512_block_data_order_neon |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1870 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1871 | .byte 83,72,65,53,49,50,32,98,108,111,99,107,32,116,114,97,110,115,102,111,114,109,32,102,111,114,32,65,82,77,118,52,47,78,69,79,78,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1872 | .align 2 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1873 | .align 2 |
| 1874 | #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1875 | .comm OPENSSL_armcap_P,4,4 |
Adam Langley | 13066f1 | 2015-02-13 14:47:35 -0800 | [diff] [blame] | 1876 | .hidden OPENSSL_armcap_P |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1877 | #endif |
David Benjamin | 4969cc9 | 2016-04-22 15:02:23 -0400 | [diff] [blame] | 1878 | #endif |