Robert Sloan | 8ff0355 | 2017-06-14 12:40:58 -0700 | [diff] [blame^] | 1 | #include <openssl/arm_arch.h> |
| 2 | |
| 3 | .text |
| 4 | #if defined(__thumb2__) |
| 5 | .syntax unified |
| 6 | .thumb |
| 7 | #else |
| 8 | .code 32 |
| 9 | #endif |
| 10 | |
| 11 | .globl _sha1_block_data_order |
| 12 | .private_extern _sha1_block_data_order |
| 13 | #ifdef __thumb2__ |
| 14 | .thumb_func _sha1_block_data_order |
| 15 | #endif |
| 16 | |
| 17 | .align 5 |
| 18 | _sha1_block_data_order: |
| 19 | #if __ARM_MAX_ARCH__>=7 |
| 20 | Lsha1_block: |
| 21 | adr r3,Lsha1_block |
| 22 | ldr r12,LOPENSSL_armcap |
| 23 | ldr r12,[r3,r12] @ OPENSSL_armcap_P |
| 24 | #ifdef __APPLE__ |
| 25 | ldr r12,[r12] |
| 26 | #endif |
| 27 | tst r12,#ARMV8_SHA1 |
| 28 | bne LARMv8 |
| 29 | tst r12,#ARMV7_NEON |
| 30 | bne LNEON |
| 31 | #endif |
| 32 | stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} |
| 33 | add r2,r1,r2,lsl#6 @ r2 to point at the end of r1 |
| 34 | ldmia r0,{r3,r4,r5,r6,r7} |
| 35 | Lloop: |
| 36 | ldr r8,LK_00_19 |
| 37 | mov r14,sp |
| 38 | sub sp,sp,#15*4 |
| 39 | mov r5,r5,ror#30 |
| 40 | mov r6,r6,ror#30 |
| 41 | mov r7,r7,ror#30 @ [6] |
| 42 | L_00_15: |
| 43 | #if __ARM_ARCH__<7 |
| 44 | ldrb r10,[r1,#2] |
| 45 | ldrb r9,[r1,#3] |
| 46 | ldrb r11,[r1,#1] |
| 47 | add r7,r8,r7,ror#2 @ E+=K_00_19 |
| 48 | ldrb r12,[r1],#4 |
| 49 | orr r9,r9,r10,lsl#8 |
| 50 | eor r10,r5,r6 @ F_xx_xx |
| 51 | orr r9,r9,r11,lsl#16 |
| 52 | add r7,r7,r3,ror#27 @ E+=ROR(A,27) |
| 53 | orr r9,r9,r12,lsl#24 |
| 54 | #else |
| 55 | ldr r9,[r1],#4 @ handles unaligned |
| 56 | add r7,r8,r7,ror#2 @ E+=K_00_19 |
| 57 | eor r10,r5,r6 @ F_xx_xx |
| 58 | add r7,r7,r3,ror#27 @ E+=ROR(A,27) |
| 59 | #ifdef __ARMEL__ |
| 60 | rev r9,r9 @ byte swap |
| 61 | #endif |
| 62 | #endif |
| 63 | and r10,r4,r10,ror#2 |
| 64 | add r7,r7,r9 @ E+=X[i] |
| 65 | eor r10,r10,r6,ror#2 @ F_00_19(B,C,D) |
| 66 | str r9,[r14,#-4]! |
| 67 | add r7,r7,r10 @ E+=F_00_19(B,C,D) |
| 68 | #if __ARM_ARCH__<7 |
| 69 | ldrb r10,[r1,#2] |
| 70 | ldrb r9,[r1,#3] |
| 71 | ldrb r11,[r1,#1] |
| 72 | add r6,r8,r6,ror#2 @ E+=K_00_19 |
| 73 | ldrb r12,[r1],#4 |
| 74 | orr r9,r9,r10,lsl#8 |
| 75 | eor r10,r4,r5 @ F_xx_xx |
| 76 | orr r9,r9,r11,lsl#16 |
| 77 | add r6,r6,r7,ror#27 @ E+=ROR(A,27) |
| 78 | orr r9,r9,r12,lsl#24 |
| 79 | #else |
| 80 | ldr r9,[r1],#4 @ handles unaligned |
| 81 | add r6,r8,r6,ror#2 @ E+=K_00_19 |
| 82 | eor r10,r4,r5 @ F_xx_xx |
| 83 | add r6,r6,r7,ror#27 @ E+=ROR(A,27) |
| 84 | #ifdef __ARMEL__ |
| 85 | rev r9,r9 @ byte swap |
| 86 | #endif |
| 87 | #endif |
| 88 | and r10,r3,r10,ror#2 |
| 89 | add r6,r6,r9 @ E+=X[i] |
| 90 | eor r10,r10,r5,ror#2 @ F_00_19(B,C,D) |
| 91 | str r9,[r14,#-4]! |
| 92 | add r6,r6,r10 @ E+=F_00_19(B,C,D) |
| 93 | #if __ARM_ARCH__<7 |
| 94 | ldrb r10,[r1,#2] |
| 95 | ldrb r9,[r1,#3] |
| 96 | ldrb r11,[r1,#1] |
| 97 | add r5,r8,r5,ror#2 @ E+=K_00_19 |
| 98 | ldrb r12,[r1],#4 |
| 99 | orr r9,r9,r10,lsl#8 |
| 100 | eor r10,r3,r4 @ F_xx_xx |
| 101 | orr r9,r9,r11,lsl#16 |
| 102 | add r5,r5,r6,ror#27 @ E+=ROR(A,27) |
| 103 | orr r9,r9,r12,lsl#24 |
| 104 | #else |
| 105 | ldr r9,[r1],#4 @ handles unaligned |
| 106 | add r5,r8,r5,ror#2 @ E+=K_00_19 |
| 107 | eor r10,r3,r4 @ F_xx_xx |
| 108 | add r5,r5,r6,ror#27 @ E+=ROR(A,27) |
| 109 | #ifdef __ARMEL__ |
| 110 | rev r9,r9 @ byte swap |
| 111 | #endif |
| 112 | #endif |
| 113 | and r10,r7,r10,ror#2 |
| 114 | add r5,r5,r9 @ E+=X[i] |
| 115 | eor r10,r10,r4,ror#2 @ F_00_19(B,C,D) |
| 116 | str r9,[r14,#-4]! |
| 117 | add r5,r5,r10 @ E+=F_00_19(B,C,D) |
| 118 | #if __ARM_ARCH__<7 |
| 119 | ldrb r10,[r1,#2] |
| 120 | ldrb r9,[r1,#3] |
| 121 | ldrb r11,[r1,#1] |
| 122 | add r4,r8,r4,ror#2 @ E+=K_00_19 |
| 123 | ldrb r12,[r1],#4 |
| 124 | orr r9,r9,r10,lsl#8 |
| 125 | eor r10,r7,r3 @ F_xx_xx |
| 126 | orr r9,r9,r11,lsl#16 |
| 127 | add r4,r4,r5,ror#27 @ E+=ROR(A,27) |
| 128 | orr r9,r9,r12,lsl#24 |
| 129 | #else |
| 130 | ldr r9,[r1],#4 @ handles unaligned |
| 131 | add r4,r8,r4,ror#2 @ E+=K_00_19 |
| 132 | eor r10,r7,r3 @ F_xx_xx |
| 133 | add r4,r4,r5,ror#27 @ E+=ROR(A,27) |
| 134 | #ifdef __ARMEL__ |
| 135 | rev r9,r9 @ byte swap |
| 136 | #endif |
| 137 | #endif |
| 138 | and r10,r6,r10,ror#2 |
| 139 | add r4,r4,r9 @ E+=X[i] |
| 140 | eor r10,r10,r3,ror#2 @ F_00_19(B,C,D) |
| 141 | str r9,[r14,#-4]! |
| 142 | add r4,r4,r10 @ E+=F_00_19(B,C,D) |
| 143 | #if __ARM_ARCH__<7 |
| 144 | ldrb r10,[r1,#2] |
| 145 | ldrb r9,[r1,#3] |
| 146 | ldrb r11,[r1,#1] |
| 147 | add r3,r8,r3,ror#2 @ E+=K_00_19 |
| 148 | ldrb r12,[r1],#4 |
| 149 | orr r9,r9,r10,lsl#8 |
| 150 | eor r10,r6,r7 @ F_xx_xx |
| 151 | orr r9,r9,r11,lsl#16 |
| 152 | add r3,r3,r4,ror#27 @ E+=ROR(A,27) |
| 153 | orr r9,r9,r12,lsl#24 |
| 154 | #else |
| 155 | ldr r9,[r1],#4 @ handles unaligned |
| 156 | add r3,r8,r3,ror#2 @ E+=K_00_19 |
| 157 | eor r10,r6,r7 @ F_xx_xx |
| 158 | add r3,r3,r4,ror#27 @ E+=ROR(A,27) |
| 159 | #ifdef __ARMEL__ |
| 160 | rev r9,r9 @ byte swap |
| 161 | #endif |
| 162 | #endif |
| 163 | and r10,r5,r10,ror#2 |
| 164 | add r3,r3,r9 @ E+=X[i] |
| 165 | eor r10,r10,r7,ror#2 @ F_00_19(B,C,D) |
| 166 | str r9,[r14,#-4]! |
| 167 | add r3,r3,r10 @ E+=F_00_19(B,C,D) |
| 168 | #if defined(__thumb2__) |
| 169 | mov r12,sp |
| 170 | teq r14,r12 |
| 171 | #else |
| 172 | teq r14,sp |
| 173 | #endif |
| 174 | bne L_00_15 @ [((11+4)*5+2)*3] |
| 175 | sub sp,sp,#25*4 |
| 176 | #if __ARM_ARCH__<7 |
| 177 | ldrb r10,[r1,#2] |
| 178 | ldrb r9,[r1,#3] |
| 179 | ldrb r11,[r1,#1] |
| 180 | add r7,r8,r7,ror#2 @ E+=K_00_19 |
| 181 | ldrb r12,[r1],#4 |
| 182 | orr r9,r9,r10,lsl#8 |
| 183 | eor r10,r5,r6 @ F_xx_xx |
| 184 | orr r9,r9,r11,lsl#16 |
| 185 | add r7,r7,r3,ror#27 @ E+=ROR(A,27) |
| 186 | orr r9,r9,r12,lsl#24 |
| 187 | #else |
| 188 | ldr r9,[r1],#4 @ handles unaligned |
| 189 | add r7,r8,r7,ror#2 @ E+=K_00_19 |
| 190 | eor r10,r5,r6 @ F_xx_xx |
| 191 | add r7,r7,r3,ror#27 @ E+=ROR(A,27) |
| 192 | #ifdef __ARMEL__ |
| 193 | rev r9,r9 @ byte swap |
| 194 | #endif |
| 195 | #endif |
| 196 | and r10,r4,r10,ror#2 |
| 197 | add r7,r7,r9 @ E+=X[i] |
| 198 | eor r10,r10,r6,ror#2 @ F_00_19(B,C,D) |
| 199 | str r9,[r14,#-4]! |
| 200 | add r7,r7,r10 @ E+=F_00_19(B,C,D) |
| 201 | ldr r9,[r14,#15*4] |
| 202 | ldr r10,[r14,#13*4] |
| 203 | ldr r11,[r14,#7*4] |
| 204 | add r6,r8,r6,ror#2 @ E+=K_xx_xx |
| 205 | ldr r12,[r14,#2*4] |
| 206 | eor r9,r9,r10 |
| 207 | eor r11,r11,r12 @ 1 cycle stall |
| 208 | eor r10,r4,r5 @ F_xx_xx |
| 209 | mov r9,r9,ror#31 |
| 210 | add r6,r6,r7,ror#27 @ E+=ROR(A,27) |
| 211 | eor r9,r9,r11,ror#31 |
| 212 | str r9,[r14,#-4]! |
| 213 | and r10,r3,r10,ror#2 @ F_xx_xx |
| 214 | @ F_xx_xx |
| 215 | add r6,r6,r9 @ E+=X[i] |
| 216 | eor r10,r10,r5,ror#2 @ F_00_19(B,C,D) |
| 217 | add r6,r6,r10 @ E+=F_00_19(B,C,D) |
| 218 | ldr r9,[r14,#15*4] |
| 219 | ldr r10,[r14,#13*4] |
| 220 | ldr r11,[r14,#7*4] |
| 221 | add r5,r8,r5,ror#2 @ E+=K_xx_xx |
| 222 | ldr r12,[r14,#2*4] |
| 223 | eor r9,r9,r10 |
| 224 | eor r11,r11,r12 @ 1 cycle stall |
| 225 | eor r10,r3,r4 @ F_xx_xx |
| 226 | mov r9,r9,ror#31 |
| 227 | add r5,r5,r6,ror#27 @ E+=ROR(A,27) |
| 228 | eor r9,r9,r11,ror#31 |
| 229 | str r9,[r14,#-4]! |
| 230 | and r10,r7,r10,ror#2 @ F_xx_xx |
| 231 | @ F_xx_xx |
| 232 | add r5,r5,r9 @ E+=X[i] |
| 233 | eor r10,r10,r4,ror#2 @ F_00_19(B,C,D) |
| 234 | add r5,r5,r10 @ E+=F_00_19(B,C,D) |
| 235 | ldr r9,[r14,#15*4] |
| 236 | ldr r10,[r14,#13*4] |
| 237 | ldr r11,[r14,#7*4] |
| 238 | add r4,r8,r4,ror#2 @ E+=K_xx_xx |
| 239 | ldr r12,[r14,#2*4] |
| 240 | eor r9,r9,r10 |
| 241 | eor r11,r11,r12 @ 1 cycle stall |
| 242 | eor r10,r7,r3 @ F_xx_xx |
| 243 | mov r9,r9,ror#31 |
| 244 | add r4,r4,r5,ror#27 @ E+=ROR(A,27) |
| 245 | eor r9,r9,r11,ror#31 |
| 246 | str r9,[r14,#-4]! |
| 247 | and r10,r6,r10,ror#2 @ F_xx_xx |
| 248 | @ F_xx_xx |
| 249 | add r4,r4,r9 @ E+=X[i] |
| 250 | eor r10,r10,r3,ror#2 @ F_00_19(B,C,D) |
| 251 | add r4,r4,r10 @ E+=F_00_19(B,C,D) |
| 252 | ldr r9,[r14,#15*4] |
| 253 | ldr r10,[r14,#13*4] |
| 254 | ldr r11,[r14,#7*4] |
| 255 | add r3,r8,r3,ror#2 @ E+=K_xx_xx |
| 256 | ldr r12,[r14,#2*4] |
| 257 | eor r9,r9,r10 |
| 258 | eor r11,r11,r12 @ 1 cycle stall |
| 259 | eor r10,r6,r7 @ F_xx_xx |
| 260 | mov r9,r9,ror#31 |
| 261 | add r3,r3,r4,ror#27 @ E+=ROR(A,27) |
| 262 | eor r9,r9,r11,ror#31 |
| 263 | str r9,[r14,#-4]! |
| 264 | and r10,r5,r10,ror#2 @ F_xx_xx |
| 265 | @ F_xx_xx |
| 266 | add r3,r3,r9 @ E+=X[i] |
| 267 | eor r10,r10,r7,ror#2 @ F_00_19(B,C,D) |
| 268 | add r3,r3,r10 @ E+=F_00_19(B,C,D) |
| 269 | |
| 270 | ldr r8,LK_20_39 @ [+15+16*4] |
| 271 | cmn sp,#0 @ [+3], clear carry to denote 20_39 |
| 272 | L_20_39_or_60_79: |
| 273 | ldr r9,[r14,#15*4] |
| 274 | ldr r10,[r14,#13*4] |
| 275 | ldr r11,[r14,#7*4] |
| 276 | add r7,r8,r7,ror#2 @ E+=K_xx_xx |
| 277 | ldr r12,[r14,#2*4] |
| 278 | eor r9,r9,r10 |
| 279 | eor r11,r11,r12 @ 1 cycle stall |
| 280 | eor r10,r5,r6 @ F_xx_xx |
| 281 | mov r9,r9,ror#31 |
| 282 | add r7,r7,r3,ror#27 @ E+=ROR(A,27) |
| 283 | eor r9,r9,r11,ror#31 |
| 284 | str r9,[r14,#-4]! |
| 285 | eor r10,r4,r10,ror#2 @ F_xx_xx |
| 286 | @ F_xx_xx |
| 287 | add r7,r7,r9 @ E+=X[i] |
| 288 | add r7,r7,r10 @ E+=F_20_39(B,C,D) |
| 289 | ldr r9,[r14,#15*4] |
| 290 | ldr r10,[r14,#13*4] |
| 291 | ldr r11,[r14,#7*4] |
| 292 | add r6,r8,r6,ror#2 @ E+=K_xx_xx |
| 293 | ldr r12,[r14,#2*4] |
| 294 | eor r9,r9,r10 |
| 295 | eor r11,r11,r12 @ 1 cycle stall |
| 296 | eor r10,r4,r5 @ F_xx_xx |
| 297 | mov r9,r9,ror#31 |
| 298 | add r6,r6,r7,ror#27 @ E+=ROR(A,27) |
| 299 | eor r9,r9,r11,ror#31 |
| 300 | str r9,[r14,#-4]! |
| 301 | eor r10,r3,r10,ror#2 @ F_xx_xx |
| 302 | @ F_xx_xx |
| 303 | add r6,r6,r9 @ E+=X[i] |
| 304 | add r6,r6,r10 @ E+=F_20_39(B,C,D) |
| 305 | ldr r9,[r14,#15*4] |
| 306 | ldr r10,[r14,#13*4] |
| 307 | ldr r11,[r14,#7*4] |
| 308 | add r5,r8,r5,ror#2 @ E+=K_xx_xx |
| 309 | ldr r12,[r14,#2*4] |
| 310 | eor r9,r9,r10 |
| 311 | eor r11,r11,r12 @ 1 cycle stall |
| 312 | eor r10,r3,r4 @ F_xx_xx |
| 313 | mov r9,r9,ror#31 |
| 314 | add r5,r5,r6,ror#27 @ E+=ROR(A,27) |
| 315 | eor r9,r9,r11,ror#31 |
| 316 | str r9,[r14,#-4]! |
| 317 | eor r10,r7,r10,ror#2 @ F_xx_xx |
| 318 | @ F_xx_xx |
| 319 | add r5,r5,r9 @ E+=X[i] |
| 320 | add r5,r5,r10 @ E+=F_20_39(B,C,D) |
| 321 | ldr r9,[r14,#15*4] |
| 322 | ldr r10,[r14,#13*4] |
| 323 | ldr r11,[r14,#7*4] |
| 324 | add r4,r8,r4,ror#2 @ E+=K_xx_xx |
| 325 | ldr r12,[r14,#2*4] |
| 326 | eor r9,r9,r10 |
| 327 | eor r11,r11,r12 @ 1 cycle stall |
| 328 | eor r10,r7,r3 @ F_xx_xx |
| 329 | mov r9,r9,ror#31 |
| 330 | add r4,r4,r5,ror#27 @ E+=ROR(A,27) |
| 331 | eor r9,r9,r11,ror#31 |
| 332 | str r9,[r14,#-4]! |
| 333 | eor r10,r6,r10,ror#2 @ F_xx_xx |
| 334 | @ F_xx_xx |
| 335 | add r4,r4,r9 @ E+=X[i] |
| 336 | add r4,r4,r10 @ E+=F_20_39(B,C,D) |
| 337 | ldr r9,[r14,#15*4] |
| 338 | ldr r10,[r14,#13*4] |
| 339 | ldr r11,[r14,#7*4] |
| 340 | add r3,r8,r3,ror#2 @ E+=K_xx_xx |
| 341 | ldr r12,[r14,#2*4] |
| 342 | eor r9,r9,r10 |
| 343 | eor r11,r11,r12 @ 1 cycle stall |
| 344 | eor r10,r6,r7 @ F_xx_xx |
| 345 | mov r9,r9,ror#31 |
| 346 | add r3,r3,r4,ror#27 @ E+=ROR(A,27) |
| 347 | eor r9,r9,r11,ror#31 |
| 348 | str r9,[r14,#-4]! |
| 349 | eor r10,r5,r10,ror#2 @ F_xx_xx |
| 350 | @ F_xx_xx |
| 351 | add r3,r3,r9 @ E+=X[i] |
| 352 | add r3,r3,r10 @ E+=F_20_39(B,C,D) |
| 353 | #if defined(__thumb2__) |
| 354 | mov r12,sp |
| 355 | teq r14,r12 |
| 356 | #else |
| 357 | teq r14,sp @ preserve carry |
| 358 | #endif |
| 359 | bne L_20_39_or_60_79 @ [+((12+3)*5+2)*4] |
| 360 | bcs L_done @ [+((12+3)*5+2)*4], spare 300 bytes |
| 361 | |
| 362 | ldr r8,LK_40_59 |
| 363 | sub sp,sp,#20*4 @ [+2] |
| 364 | L_40_59: |
| 365 | ldr r9,[r14,#15*4] |
| 366 | ldr r10,[r14,#13*4] |
| 367 | ldr r11,[r14,#7*4] |
| 368 | add r7,r8,r7,ror#2 @ E+=K_xx_xx |
| 369 | ldr r12,[r14,#2*4] |
| 370 | eor r9,r9,r10 |
| 371 | eor r11,r11,r12 @ 1 cycle stall |
| 372 | eor r10,r5,r6 @ F_xx_xx |
| 373 | mov r9,r9,ror#31 |
| 374 | add r7,r7,r3,ror#27 @ E+=ROR(A,27) |
| 375 | eor r9,r9,r11,ror#31 |
| 376 | str r9,[r14,#-4]! |
| 377 | and r10,r4,r10,ror#2 @ F_xx_xx |
| 378 | and r11,r5,r6 @ F_xx_xx |
| 379 | add r7,r7,r9 @ E+=X[i] |
| 380 | add r7,r7,r10 @ E+=F_40_59(B,C,D) |
| 381 | add r7,r7,r11,ror#2 |
| 382 | ldr r9,[r14,#15*4] |
| 383 | ldr r10,[r14,#13*4] |
| 384 | ldr r11,[r14,#7*4] |
| 385 | add r6,r8,r6,ror#2 @ E+=K_xx_xx |
| 386 | ldr r12,[r14,#2*4] |
| 387 | eor r9,r9,r10 |
| 388 | eor r11,r11,r12 @ 1 cycle stall |
| 389 | eor r10,r4,r5 @ F_xx_xx |
| 390 | mov r9,r9,ror#31 |
| 391 | add r6,r6,r7,ror#27 @ E+=ROR(A,27) |
| 392 | eor r9,r9,r11,ror#31 |
| 393 | str r9,[r14,#-4]! |
| 394 | and r10,r3,r10,ror#2 @ F_xx_xx |
| 395 | and r11,r4,r5 @ F_xx_xx |
| 396 | add r6,r6,r9 @ E+=X[i] |
| 397 | add r6,r6,r10 @ E+=F_40_59(B,C,D) |
| 398 | add r6,r6,r11,ror#2 |
| 399 | ldr r9,[r14,#15*4] |
| 400 | ldr r10,[r14,#13*4] |
| 401 | ldr r11,[r14,#7*4] |
| 402 | add r5,r8,r5,ror#2 @ E+=K_xx_xx |
| 403 | ldr r12,[r14,#2*4] |
| 404 | eor r9,r9,r10 |
| 405 | eor r11,r11,r12 @ 1 cycle stall |
| 406 | eor r10,r3,r4 @ F_xx_xx |
| 407 | mov r9,r9,ror#31 |
| 408 | add r5,r5,r6,ror#27 @ E+=ROR(A,27) |
| 409 | eor r9,r9,r11,ror#31 |
| 410 | str r9,[r14,#-4]! |
| 411 | and r10,r7,r10,ror#2 @ F_xx_xx |
| 412 | and r11,r3,r4 @ F_xx_xx |
| 413 | add r5,r5,r9 @ E+=X[i] |
| 414 | add r5,r5,r10 @ E+=F_40_59(B,C,D) |
| 415 | add r5,r5,r11,ror#2 |
| 416 | ldr r9,[r14,#15*4] |
| 417 | ldr r10,[r14,#13*4] |
| 418 | ldr r11,[r14,#7*4] |
| 419 | add r4,r8,r4,ror#2 @ E+=K_xx_xx |
| 420 | ldr r12,[r14,#2*4] |
| 421 | eor r9,r9,r10 |
| 422 | eor r11,r11,r12 @ 1 cycle stall |
| 423 | eor r10,r7,r3 @ F_xx_xx |
| 424 | mov r9,r9,ror#31 |
| 425 | add r4,r4,r5,ror#27 @ E+=ROR(A,27) |
| 426 | eor r9,r9,r11,ror#31 |
| 427 | str r9,[r14,#-4]! |
| 428 | and r10,r6,r10,ror#2 @ F_xx_xx |
| 429 | and r11,r7,r3 @ F_xx_xx |
| 430 | add r4,r4,r9 @ E+=X[i] |
| 431 | add r4,r4,r10 @ E+=F_40_59(B,C,D) |
| 432 | add r4,r4,r11,ror#2 |
| 433 | ldr r9,[r14,#15*4] |
| 434 | ldr r10,[r14,#13*4] |
| 435 | ldr r11,[r14,#7*4] |
| 436 | add r3,r8,r3,ror#2 @ E+=K_xx_xx |
| 437 | ldr r12,[r14,#2*4] |
| 438 | eor r9,r9,r10 |
| 439 | eor r11,r11,r12 @ 1 cycle stall |
| 440 | eor r10,r6,r7 @ F_xx_xx |
| 441 | mov r9,r9,ror#31 |
| 442 | add r3,r3,r4,ror#27 @ E+=ROR(A,27) |
| 443 | eor r9,r9,r11,ror#31 |
| 444 | str r9,[r14,#-4]! |
| 445 | and r10,r5,r10,ror#2 @ F_xx_xx |
| 446 | and r11,r6,r7 @ F_xx_xx |
| 447 | add r3,r3,r9 @ E+=X[i] |
| 448 | add r3,r3,r10 @ E+=F_40_59(B,C,D) |
| 449 | add r3,r3,r11,ror#2 |
| 450 | #if defined(__thumb2__) |
| 451 | mov r12,sp |
| 452 | teq r14,r12 |
| 453 | #else |
| 454 | teq r14,sp |
| 455 | #endif |
| 456 | bne L_40_59 @ [+((12+5)*5+2)*4] |
| 457 | |
| 458 | ldr r8,LK_60_79 |
| 459 | sub sp,sp,#20*4 |
| 460 | cmp sp,#0 @ set carry to denote 60_79 |
| 461 | b L_20_39_or_60_79 @ [+4], spare 300 bytes |
| 462 | L_done: |
| 463 | add sp,sp,#80*4 @ "deallocate" stack frame |
| 464 | ldmia r0,{r8,r9,r10,r11,r12} |
| 465 | add r3,r8,r3 |
| 466 | add r4,r9,r4 |
| 467 | add r5,r10,r5,ror#2 |
| 468 | add r6,r11,r6,ror#2 |
| 469 | add r7,r12,r7,ror#2 |
| 470 | stmia r0,{r3,r4,r5,r6,r7} |
| 471 | teq r1,r2 |
| 472 | bne Lloop @ [+18], total 1307 |
| 473 | |
| 474 | #if __ARM_ARCH__>=5 |
| 475 | ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,pc} |
| 476 | #else |
| 477 | ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} |
| 478 | tst lr,#1 |
| 479 | moveq pc,lr @ be binary compatible with V4, yet |
| 480 | .word 0xe12fff1e @ interoperable with Thumb ISA:-) |
| 481 | #endif |
| 482 | |
| 483 | |
| 484 | .align 5 |
| 485 | LK_00_19:.word 0x5a827999 |
| 486 | LK_20_39:.word 0x6ed9eba1 |
| 487 | LK_40_59:.word 0x8f1bbcdc |
| 488 | LK_60_79:.word 0xca62c1d6 |
| 489 | #if __ARM_MAX_ARCH__>=7 |
| 490 | LOPENSSL_armcap: |
| 491 | .word OPENSSL_armcap_P-Lsha1_block |
| 492 | #endif |
| 493 | .byte 83,72,65,49,32,98,108,111,99,107,32,116,114,97,110,115,102,111,114,109,32,102,111,114,32,65,82,77,118,52,47,78,69,79,78,47,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0 |
| 494 | .align 2 |
| 495 | .align 5 |
| 496 | #if __ARM_MAX_ARCH__>=7 |
| 497 | |
| 498 | |
| 499 | |
| 500 | #ifdef __thumb2__ |
| 501 | .thumb_func sha1_block_data_order_neon |
| 502 | #endif |
| 503 | .align 4 |
| 504 | sha1_block_data_order_neon: |
| 505 | LNEON: |
| 506 | stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} |
| 507 | add r2,r1,r2,lsl#6 @ r2 to point at the end of r1 |
| 508 | @ dmb @ errata #451034 on early Cortex A8 |
| 509 | @ vstmdb sp!,{d8-d15} @ ABI specification says so |
| 510 | mov r14,sp |
| 511 | sub r12,sp,#64 |
| 512 | adr r8,LK_00_19 |
| 513 | bic r12,r12,#15 @ align for 128-bit stores |
| 514 | |
| 515 | ldmia r0,{r3,r4,r5,r6,r7} @ load context |
| 516 | mov sp,r12 @ alloca |
| 517 | |
| 518 | vld1.8 {q0,q1},[r1]! @ handles unaligned |
| 519 | veor q15,q15,q15 |
| 520 | vld1.8 {q2,q3},[r1]! |
| 521 | vld1.32 {d28[],d29[]},[r8,:32]! @ load K_00_19 |
| 522 | vrev32.8 q0,q0 @ yes, even on |
| 523 | vrev32.8 q1,q1 @ big-endian... |
| 524 | vrev32.8 q2,q2 |
| 525 | vadd.i32 q8,q0,q14 |
| 526 | vrev32.8 q3,q3 |
| 527 | vadd.i32 q9,q1,q14 |
| 528 | vst1.32 {q8},[r12,:128]! |
| 529 | vadd.i32 q10,q2,q14 |
| 530 | vst1.32 {q9},[r12,:128]! |
| 531 | vst1.32 {q10},[r12,:128]! |
| 532 | ldr r9,[sp] @ big RAW stall |
| 533 | |
| 534 | Loop_neon: |
| 535 | vext.8 q8,q0,q1,#8 |
| 536 | bic r10,r6,r4 |
| 537 | add r7,r7,r9 |
| 538 | and r11,r5,r4 |
| 539 | vadd.i32 q13,q3,q14 |
| 540 | ldr r9,[sp,#4] |
| 541 | add r7,r7,r3,ror#27 |
| 542 | vext.8 q12,q3,q15,#4 |
| 543 | eor r11,r11,r10 |
| 544 | mov r4,r4,ror#2 |
| 545 | add r7,r7,r11 |
| 546 | veor q8,q8,q0 |
| 547 | bic r10,r5,r3 |
| 548 | add r6,r6,r9 |
| 549 | veor q12,q12,q2 |
| 550 | and r11,r4,r3 |
| 551 | ldr r9,[sp,#8] |
| 552 | veor q12,q12,q8 |
| 553 | add r6,r6,r7,ror#27 |
| 554 | eor r11,r11,r10 |
| 555 | vst1.32 {q13},[r12,:128]! |
| 556 | sub r12,r12,#64 |
| 557 | mov r3,r3,ror#2 |
| 558 | add r6,r6,r11 |
| 559 | vext.8 q13,q15,q12,#4 |
| 560 | bic r10,r4,r7 |
| 561 | add r5,r5,r9 |
| 562 | vadd.i32 q8,q12,q12 |
| 563 | and r11,r3,r7 |
| 564 | ldr r9,[sp,#12] |
| 565 | vsri.32 q8,q12,#31 |
| 566 | add r5,r5,r6,ror#27 |
| 567 | eor r11,r11,r10 |
| 568 | mov r7,r7,ror#2 |
| 569 | vshr.u32 q12,q13,#30 |
| 570 | add r5,r5,r11 |
| 571 | bic r10,r3,r6 |
| 572 | vshl.u32 q13,q13,#2 |
| 573 | add r4,r4,r9 |
| 574 | and r11,r7,r6 |
| 575 | veor q8,q8,q12 |
| 576 | ldr r9,[sp,#16] |
| 577 | add r4,r4,r5,ror#27 |
| 578 | veor q8,q8,q13 |
| 579 | eor r11,r11,r10 |
| 580 | mov r6,r6,ror#2 |
| 581 | add r4,r4,r11 |
| 582 | vext.8 q9,q1,q2,#8 |
| 583 | bic r10,r7,r5 |
| 584 | add r3,r3,r9 |
| 585 | and r11,r6,r5 |
| 586 | vadd.i32 q13,q8,q14 |
| 587 | ldr r9,[sp,#20] |
| 588 | vld1.32 {d28[],d29[]},[r8,:32]! |
| 589 | add r3,r3,r4,ror#27 |
| 590 | vext.8 q12,q8,q15,#4 |
| 591 | eor r11,r11,r10 |
| 592 | mov r5,r5,ror#2 |
| 593 | add r3,r3,r11 |
| 594 | veor q9,q9,q1 |
| 595 | bic r10,r6,r4 |
| 596 | add r7,r7,r9 |
| 597 | veor q12,q12,q3 |
| 598 | and r11,r5,r4 |
| 599 | ldr r9,[sp,#24] |
| 600 | veor q12,q12,q9 |
| 601 | add r7,r7,r3,ror#27 |
| 602 | eor r11,r11,r10 |
| 603 | vst1.32 {q13},[r12,:128]! |
| 604 | mov r4,r4,ror#2 |
| 605 | add r7,r7,r11 |
| 606 | vext.8 q13,q15,q12,#4 |
| 607 | bic r10,r5,r3 |
| 608 | add r6,r6,r9 |
| 609 | vadd.i32 q9,q12,q12 |
| 610 | and r11,r4,r3 |
| 611 | ldr r9,[sp,#28] |
| 612 | vsri.32 q9,q12,#31 |
| 613 | add r6,r6,r7,ror#27 |
| 614 | eor r11,r11,r10 |
| 615 | mov r3,r3,ror#2 |
| 616 | vshr.u32 q12,q13,#30 |
| 617 | add r6,r6,r11 |
| 618 | bic r10,r4,r7 |
| 619 | vshl.u32 q13,q13,#2 |
| 620 | add r5,r5,r9 |
| 621 | and r11,r3,r7 |
| 622 | veor q9,q9,q12 |
| 623 | ldr r9,[sp,#32] |
| 624 | add r5,r5,r6,ror#27 |
| 625 | veor q9,q9,q13 |
| 626 | eor r11,r11,r10 |
| 627 | mov r7,r7,ror#2 |
| 628 | add r5,r5,r11 |
| 629 | vext.8 q10,q2,q3,#8 |
| 630 | bic r10,r3,r6 |
| 631 | add r4,r4,r9 |
| 632 | and r11,r7,r6 |
| 633 | vadd.i32 q13,q9,q14 |
| 634 | ldr r9,[sp,#36] |
| 635 | add r4,r4,r5,ror#27 |
| 636 | vext.8 q12,q9,q15,#4 |
| 637 | eor r11,r11,r10 |
| 638 | mov r6,r6,ror#2 |
| 639 | add r4,r4,r11 |
| 640 | veor q10,q10,q2 |
| 641 | bic r10,r7,r5 |
| 642 | add r3,r3,r9 |
| 643 | veor q12,q12,q8 |
| 644 | and r11,r6,r5 |
| 645 | ldr r9,[sp,#40] |
| 646 | veor q12,q12,q10 |
| 647 | add r3,r3,r4,ror#27 |
| 648 | eor r11,r11,r10 |
| 649 | vst1.32 {q13},[r12,:128]! |
| 650 | mov r5,r5,ror#2 |
| 651 | add r3,r3,r11 |
| 652 | vext.8 q13,q15,q12,#4 |
| 653 | bic r10,r6,r4 |
| 654 | add r7,r7,r9 |
| 655 | vadd.i32 q10,q12,q12 |
| 656 | and r11,r5,r4 |
| 657 | ldr r9,[sp,#44] |
| 658 | vsri.32 q10,q12,#31 |
| 659 | add r7,r7,r3,ror#27 |
| 660 | eor r11,r11,r10 |
| 661 | mov r4,r4,ror#2 |
| 662 | vshr.u32 q12,q13,#30 |
| 663 | add r7,r7,r11 |
| 664 | bic r10,r5,r3 |
| 665 | vshl.u32 q13,q13,#2 |
| 666 | add r6,r6,r9 |
| 667 | and r11,r4,r3 |
| 668 | veor q10,q10,q12 |
| 669 | ldr r9,[sp,#48] |
| 670 | add r6,r6,r7,ror#27 |
| 671 | veor q10,q10,q13 |
| 672 | eor r11,r11,r10 |
| 673 | mov r3,r3,ror#2 |
| 674 | add r6,r6,r11 |
| 675 | vext.8 q11,q3,q8,#8 |
| 676 | bic r10,r4,r7 |
| 677 | add r5,r5,r9 |
| 678 | and r11,r3,r7 |
| 679 | vadd.i32 q13,q10,q14 |
| 680 | ldr r9,[sp,#52] |
| 681 | add r5,r5,r6,ror#27 |
| 682 | vext.8 q12,q10,q15,#4 |
| 683 | eor r11,r11,r10 |
| 684 | mov r7,r7,ror#2 |
| 685 | add r5,r5,r11 |
| 686 | veor q11,q11,q3 |
| 687 | bic r10,r3,r6 |
| 688 | add r4,r4,r9 |
| 689 | veor q12,q12,q9 |
| 690 | and r11,r7,r6 |
| 691 | ldr r9,[sp,#56] |
| 692 | veor q12,q12,q11 |
| 693 | add r4,r4,r5,ror#27 |
| 694 | eor r11,r11,r10 |
| 695 | vst1.32 {q13},[r12,:128]! |
| 696 | mov r6,r6,ror#2 |
| 697 | add r4,r4,r11 |
| 698 | vext.8 q13,q15,q12,#4 |
| 699 | bic r10,r7,r5 |
| 700 | add r3,r3,r9 |
| 701 | vadd.i32 q11,q12,q12 |
| 702 | and r11,r6,r5 |
| 703 | ldr r9,[sp,#60] |
| 704 | vsri.32 q11,q12,#31 |
| 705 | add r3,r3,r4,ror#27 |
| 706 | eor r11,r11,r10 |
| 707 | mov r5,r5,ror#2 |
| 708 | vshr.u32 q12,q13,#30 |
| 709 | add r3,r3,r11 |
| 710 | bic r10,r6,r4 |
| 711 | vshl.u32 q13,q13,#2 |
| 712 | add r7,r7,r9 |
| 713 | and r11,r5,r4 |
| 714 | veor q11,q11,q12 |
| 715 | ldr r9,[sp,#0] |
| 716 | add r7,r7,r3,ror#27 |
| 717 | veor q11,q11,q13 |
| 718 | eor r11,r11,r10 |
| 719 | mov r4,r4,ror#2 |
| 720 | add r7,r7,r11 |
| 721 | vext.8 q12,q10,q11,#8 |
| 722 | bic r10,r5,r3 |
| 723 | add r6,r6,r9 |
| 724 | and r11,r4,r3 |
| 725 | veor q0,q0,q8 |
| 726 | ldr r9,[sp,#4] |
| 727 | add r6,r6,r7,ror#27 |
| 728 | veor q0,q0,q1 |
| 729 | eor r11,r11,r10 |
| 730 | mov r3,r3,ror#2 |
| 731 | vadd.i32 q13,q11,q14 |
| 732 | add r6,r6,r11 |
| 733 | bic r10,r4,r7 |
| 734 | veor q12,q12,q0 |
| 735 | add r5,r5,r9 |
| 736 | and r11,r3,r7 |
| 737 | vshr.u32 q0,q12,#30 |
| 738 | ldr r9,[sp,#8] |
| 739 | add r5,r5,r6,ror#27 |
| 740 | vst1.32 {q13},[r12,:128]! |
| 741 | sub r12,r12,#64 |
| 742 | eor r11,r11,r10 |
| 743 | mov r7,r7,ror#2 |
| 744 | vsli.32 q0,q12,#2 |
| 745 | add r5,r5,r11 |
| 746 | bic r10,r3,r6 |
| 747 | add r4,r4,r9 |
| 748 | and r11,r7,r6 |
| 749 | ldr r9,[sp,#12] |
| 750 | add r4,r4,r5,ror#27 |
| 751 | eor r11,r11,r10 |
| 752 | mov r6,r6,ror#2 |
| 753 | add r4,r4,r11 |
| 754 | bic r10,r7,r5 |
| 755 | add r3,r3,r9 |
| 756 | and r11,r6,r5 |
| 757 | ldr r9,[sp,#16] |
| 758 | add r3,r3,r4,ror#27 |
| 759 | eor r11,r11,r10 |
| 760 | mov r5,r5,ror#2 |
| 761 | add r3,r3,r11 |
| 762 | vext.8 q12,q11,q0,#8 |
| 763 | eor r10,r4,r6 |
| 764 | add r7,r7,r9 |
| 765 | ldr r9,[sp,#20] |
| 766 | veor q1,q1,q9 |
| 767 | eor r11,r10,r5 |
| 768 | add r7,r7,r3,ror#27 |
| 769 | veor q1,q1,q2 |
| 770 | mov r4,r4,ror#2 |
| 771 | add r7,r7,r11 |
| 772 | vadd.i32 q13,q0,q14 |
| 773 | eor r10,r3,r5 |
| 774 | add r6,r6,r9 |
| 775 | veor q12,q12,q1 |
| 776 | ldr r9,[sp,#24] |
| 777 | eor r11,r10,r4 |
| 778 | vshr.u32 q1,q12,#30 |
| 779 | add r6,r6,r7,ror#27 |
| 780 | mov r3,r3,ror#2 |
| 781 | vst1.32 {q13},[r12,:128]! |
| 782 | add r6,r6,r11 |
| 783 | eor r10,r7,r4 |
| 784 | vsli.32 q1,q12,#2 |
| 785 | add r5,r5,r9 |
| 786 | ldr r9,[sp,#28] |
| 787 | eor r11,r10,r3 |
| 788 | add r5,r5,r6,ror#27 |
| 789 | mov r7,r7,ror#2 |
| 790 | add r5,r5,r11 |
| 791 | eor r10,r6,r3 |
| 792 | add r4,r4,r9 |
| 793 | ldr r9,[sp,#32] |
| 794 | eor r11,r10,r7 |
| 795 | add r4,r4,r5,ror#27 |
| 796 | mov r6,r6,ror#2 |
| 797 | add r4,r4,r11 |
| 798 | vext.8 q12,q0,q1,#8 |
| 799 | eor r10,r5,r7 |
| 800 | add r3,r3,r9 |
| 801 | ldr r9,[sp,#36] |
| 802 | veor q2,q2,q10 |
| 803 | eor r11,r10,r6 |
| 804 | add r3,r3,r4,ror#27 |
| 805 | veor q2,q2,q3 |
| 806 | mov r5,r5,ror#2 |
| 807 | add r3,r3,r11 |
| 808 | vadd.i32 q13,q1,q14 |
| 809 | eor r10,r4,r6 |
| 810 | vld1.32 {d28[],d29[]},[r8,:32]! |
| 811 | add r7,r7,r9 |
| 812 | veor q12,q12,q2 |
| 813 | ldr r9,[sp,#40] |
| 814 | eor r11,r10,r5 |
| 815 | vshr.u32 q2,q12,#30 |
| 816 | add r7,r7,r3,ror#27 |
| 817 | mov r4,r4,ror#2 |
| 818 | vst1.32 {q13},[r12,:128]! |
| 819 | add r7,r7,r11 |
| 820 | eor r10,r3,r5 |
| 821 | vsli.32 q2,q12,#2 |
| 822 | add r6,r6,r9 |
| 823 | ldr r9,[sp,#44] |
| 824 | eor r11,r10,r4 |
| 825 | add r6,r6,r7,ror#27 |
| 826 | mov r3,r3,ror#2 |
| 827 | add r6,r6,r11 |
| 828 | eor r10,r7,r4 |
| 829 | add r5,r5,r9 |
| 830 | ldr r9,[sp,#48] |
| 831 | eor r11,r10,r3 |
| 832 | add r5,r5,r6,ror#27 |
| 833 | mov r7,r7,ror#2 |
| 834 | add r5,r5,r11 |
| 835 | vext.8 q12,q1,q2,#8 |
| 836 | eor r10,r6,r3 |
| 837 | add r4,r4,r9 |
| 838 | ldr r9,[sp,#52] |
| 839 | veor q3,q3,q11 |
| 840 | eor r11,r10,r7 |
| 841 | add r4,r4,r5,ror#27 |
| 842 | veor q3,q3,q8 |
| 843 | mov r6,r6,ror#2 |
| 844 | add r4,r4,r11 |
| 845 | vadd.i32 q13,q2,q14 |
| 846 | eor r10,r5,r7 |
| 847 | add r3,r3,r9 |
| 848 | veor q12,q12,q3 |
| 849 | ldr r9,[sp,#56] |
| 850 | eor r11,r10,r6 |
| 851 | vshr.u32 q3,q12,#30 |
| 852 | add r3,r3,r4,ror#27 |
| 853 | mov r5,r5,ror#2 |
| 854 | vst1.32 {q13},[r12,:128]! |
| 855 | add r3,r3,r11 |
| 856 | eor r10,r4,r6 |
| 857 | vsli.32 q3,q12,#2 |
| 858 | add r7,r7,r9 |
| 859 | ldr r9,[sp,#60] |
| 860 | eor r11,r10,r5 |
| 861 | add r7,r7,r3,ror#27 |
| 862 | mov r4,r4,ror#2 |
| 863 | add r7,r7,r11 |
| 864 | eor r10,r3,r5 |
| 865 | add r6,r6,r9 |
| 866 | ldr r9,[sp,#0] |
| 867 | eor r11,r10,r4 |
| 868 | add r6,r6,r7,ror#27 |
| 869 | mov r3,r3,ror#2 |
| 870 | add r6,r6,r11 |
| 871 | vext.8 q12,q2,q3,#8 |
| 872 | eor r10,r7,r4 |
| 873 | add r5,r5,r9 |
| 874 | ldr r9,[sp,#4] |
| 875 | veor q8,q8,q0 |
| 876 | eor r11,r10,r3 |
| 877 | add r5,r5,r6,ror#27 |
| 878 | veor q8,q8,q9 |
| 879 | mov r7,r7,ror#2 |
| 880 | add r5,r5,r11 |
| 881 | vadd.i32 q13,q3,q14 |
| 882 | eor r10,r6,r3 |
| 883 | add r4,r4,r9 |
| 884 | veor q12,q12,q8 |
| 885 | ldr r9,[sp,#8] |
| 886 | eor r11,r10,r7 |
| 887 | vshr.u32 q8,q12,#30 |
| 888 | add r4,r4,r5,ror#27 |
| 889 | mov r6,r6,ror#2 |
| 890 | vst1.32 {q13},[r12,:128]! |
| 891 | sub r12,r12,#64 |
| 892 | add r4,r4,r11 |
| 893 | eor r10,r5,r7 |
| 894 | vsli.32 q8,q12,#2 |
| 895 | add r3,r3,r9 |
| 896 | ldr r9,[sp,#12] |
| 897 | eor r11,r10,r6 |
| 898 | add r3,r3,r4,ror#27 |
| 899 | mov r5,r5,ror#2 |
| 900 | add r3,r3,r11 |
| 901 | eor r10,r4,r6 |
| 902 | add r7,r7,r9 |
| 903 | ldr r9,[sp,#16] |
| 904 | eor r11,r10,r5 |
| 905 | add r7,r7,r3,ror#27 |
| 906 | mov r4,r4,ror#2 |
| 907 | add r7,r7,r11 |
| 908 | vext.8 q12,q3,q8,#8 |
| 909 | eor r10,r3,r5 |
| 910 | add r6,r6,r9 |
| 911 | ldr r9,[sp,#20] |
| 912 | veor q9,q9,q1 |
| 913 | eor r11,r10,r4 |
| 914 | add r6,r6,r7,ror#27 |
| 915 | veor q9,q9,q10 |
| 916 | mov r3,r3,ror#2 |
| 917 | add r6,r6,r11 |
| 918 | vadd.i32 q13,q8,q14 |
| 919 | eor r10,r7,r4 |
| 920 | add r5,r5,r9 |
| 921 | veor q12,q12,q9 |
| 922 | ldr r9,[sp,#24] |
| 923 | eor r11,r10,r3 |
| 924 | vshr.u32 q9,q12,#30 |
| 925 | add r5,r5,r6,ror#27 |
| 926 | mov r7,r7,ror#2 |
| 927 | vst1.32 {q13},[r12,:128]! |
| 928 | add r5,r5,r11 |
| 929 | eor r10,r6,r3 |
| 930 | vsli.32 q9,q12,#2 |
| 931 | add r4,r4,r9 |
| 932 | ldr r9,[sp,#28] |
| 933 | eor r11,r10,r7 |
| 934 | add r4,r4,r5,ror#27 |
| 935 | mov r6,r6,ror#2 |
| 936 | add r4,r4,r11 |
| 937 | eor r10,r5,r7 |
| 938 | add r3,r3,r9 |
| 939 | ldr r9,[sp,#32] |
| 940 | eor r11,r10,r6 |
| 941 | add r3,r3,r4,ror#27 |
| 942 | mov r5,r5,ror#2 |
| 943 | add r3,r3,r11 |
| 944 | vext.8 q12,q8,q9,#8 |
| 945 | add r7,r7,r9 |
| 946 | and r10,r5,r6 |
| 947 | ldr r9,[sp,#36] |
| 948 | veor q10,q10,q2 |
| 949 | add r7,r7,r3,ror#27 |
| 950 | eor r11,r5,r6 |
| 951 | veor q10,q10,q11 |
| 952 | add r7,r7,r10 |
| 953 | and r11,r11,r4 |
| 954 | vadd.i32 q13,q9,q14 |
| 955 | mov r4,r4,ror#2 |
| 956 | add r7,r7,r11 |
| 957 | veor q12,q12,q10 |
| 958 | add r6,r6,r9 |
| 959 | and r10,r4,r5 |
| 960 | vshr.u32 q10,q12,#30 |
| 961 | ldr r9,[sp,#40] |
| 962 | add r6,r6,r7,ror#27 |
| 963 | vst1.32 {q13},[r12,:128]! |
| 964 | eor r11,r4,r5 |
| 965 | add r6,r6,r10 |
| 966 | vsli.32 q10,q12,#2 |
| 967 | and r11,r11,r3 |
| 968 | mov r3,r3,ror#2 |
| 969 | add r6,r6,r11 |
| 970 | add r5,r5,r9 |
| 971 | and r10,r3,r4 |
| 972 | ldr r9,[sp,#44] |
| 973 | add r5,r5,r6,ror#27 |
| 974 | eor r11,r3,r4 |
| 975 | add r5,r5,r10 |
| 976 | and r11,r11,r7 |
| 977 | mov r7,r7,ror#2 |
| 978 | add r5,r5,r11 |
| 979 | add r4,r4,r9 |
| 980 | and r10,r7,r3 |
| 981 | ldr r9,[sp,#48] |
| 982 | add r4,r4,r5,ror#27 |
| 983 | eor r11,r7,r3 |
| 984 | add r4,r4,r10 |
| 985 | and r11,r11,r6 |
| 986 | mov r6,r6,ror#2 |
| 987 | add r4,r4,r11 |
| 988 | vext.8 q12,q9,q10,#8 |
| 989 | add r3,r3,r9 |
| 990 | and r10,r6,r7 |
| 991 | ldr r9,[sp,#52] |
| 992 | veor q11,q11,q3 |
| 993 | add r3,r3,r4,ror#27 |
| 994 | eor r11,r6,r7 |
| 995 | veor q11,q11,q0 |
| 996 | add r3,r3,r10 |
| 997 | and r11,r11,r5 |
| 998 | vadd.i32 q13,q10,q14 |
| 999 | mov r5,r5,ror#2 |
| 1000 | vld1.32 {d28[],d29[]},[r8,:32]! |
| 1001 | add r3,r3,r11 |
| 1002 | veor q12,q12,q11 |
| 1003 | add r7,r7,r9 |
| 1004 | and r10,r5,r6 |
| 1005 | vshr.u32 q11,q12,#30 |
| 1006 | ldr r9,[sp,#56] |
| 1007 | add r7,r7,r3,ror#27 |
| 1008 | vst1.32 {q13},[r12,:128]! |
| 1009 | eor r11,r5,r6 |
| 1010 | add r7,r7,r10 |
| 1011 | vsli.32 q11,q12,#2 |
| 1012 | and r11,r11,r4 |
| 1013 | mov r4,r4,ror#2 |
| 1014 | add r7,r7,r11 |
| 1015 | add r6,r6,r9 |
| 1016 | and r10,r4,r5 |
| 1017 | ldr r9,[sp,#60] |
| 1018 | add r6,r6,r7,ror#27 |
| 1019 | eor r11,r4,r5 |
| 1020 | add r6,r6,r10 |
| 1021 | and r11,r11,r3 |
| 1022 | mov r3,r3,ror#2 |
| 1023 | add r6,r6,r11 |
| 1024 | add r5,r5,r9 |
| 1025 | and r10,r3,r4 |
| 1026 | ldr r9,[sp,#0] |
| 1027 | add r5,r5,r6,ror#27 |
| 1028 | eor r11,r3,r4 |
| 1029 | add r5,r5,r10 |
| 1030 | and r11,r11,r7 |
| 1031 | mov r7,r7,ror#2 |
| 1032 | add r5,r5,r11 |
| 1033 | vext.8 q12,q10,q11,#8 |
| 1034 | add r4,r4,r9 |
| 1035 | and r10,r7,r3 |
| 1036 | ldr r9,[sp,#4] |
| 1037 | veor q0,q0,q8 |
| 1038 | add r4,r4,r5,ror#27 |
| 1039 | eor r11,r7,r3 |
| 1040 | veor q0,q0,q1 |
| 1041 | add r4,r4,r10 |
| 1042 | and r11,r11,r6 |
| 1043 | vadd.i32 q13,q11,q14 |
| 1044 | mov r6,r6,ror#2 |
| 1045 | add r4,r4,r11 |
| 1046 | veor q12,q12,q0 |
| 1047 | add r3,r3,r9 |
| 1048 | and r10,r6,r7 |
| 1049 | vshr.u32 q0,q12,#30 |
| 1050 | ldr r9,[sp,#8] |
| 1051 | add r3,r3,r4,ror#27 |
| 1052 | vst1.32 {q13},[r12,:128]! |
| 1053 | sub r12,r12,#64 |
| 1054 | eor r11,r6,r7 |
| 1055 | add r3,r3,r10 |
| 1056 | vsli.32 q0,q12,#2 |
| 1057 | and r11,r11,r5 |
| 1058 | mov r5,r5,ror#2 |
| 1059 | add r3,r3,r11 |
| 1060 | add r7,r7,r9 |
| 1061 | and r10,r5,r6 |
| 1062 | ldr r9,[sp,#12] |
| 1063 | add r7,r7,r3,ror#27 |
| 1064 | eor r11,r5,r6 |
| 1065 | add r7,r7,r10 |
| 1066 | and r11,r11,r4 |
| 1067 | mov r4,r4,ror#2 |
| 1068 | add r7,r7,r11 |
| 1069 | add r6,r6,r9 |
| 1070 | and r10,r4,r5 |
| 1071 | ldr r9,[sp,#16] |
| 1072 | add r6,r6,r7,ror#27 |
| 1073 | eor r11,r4,r5 |
| 1074 | add r6,r6,r10 |
| 1075 | and r11,r11,r3 |
| 1076 | mov r3,r3,ror#2 |
| 1077 | add r6,r6,r11 |
| 1078 | vext.8 q12,q11,q0,#8 |
| 1079 | add r5,r5,r9 |
| 1080 | and r10,r3,r4 |
| 1081 | ldr r9,[sp,#20] |
| 1082 | veor q1,q1,q9 |
| 1083 | add r5,r5,r6,ror#27 |
| 1084 | eor r11,r3,r4 |
| 1085 | veor q1,q1,q2 |
| 1086 | add r5,r5,r10 |
| 1087 | and r11,r11,r7 |
| 1088 | vadd.i32 q13,q0,q14 |
| 1089 | mov r7,r7,ror#2 |
| 1090 | add r5,r5,r11 |
| 1091 | veor q12,q12,q1 |
| 1092 | add r4,r4,r9 |
| 1093 | and r10,r7,r3 |
| 1094 | vshr.u32 q1,q12,#30 |
| 1095 | ldr r9,[sp,#24] |
| 1096 | add r4,r4,r5,ror#27 |
| 1097 | vst1.32 {q13},[r12,:128]! |
| 1098 | eor r11,r7,r3 |
| 1099 | add r4,r4,r10 |
| 1100 | vsli.32 q1,q12,#2 |
| 1101 | and r11,r11,r6 |
| 1102 | mov r6,r6,ror#2 |
| 1103 | add r4,r4,r11 |
| 1104 | add r3,r3,r9 |
| 1105 | and r10,r6,r7 |
| 1106 | ldr r9,[sp,#28] |
| 1107 | add r3,r3,r4,ror#27 |
| 1108 | eor r11,r6,r7 |
| 1109 | add r3,r3,r10 |
| 1110 | and r11,r11,r5 |
| 1111 | mov r5,r5,ror#2 |
| 1112 | add r3,r3,r11 |
| 1113 | add r7,r7,r9 |
| 1114 | and r10,r5,r6 |
| 1115 | ldr r9,[sp,#32] |
| 1116 | add r7,r7,r3,ror#27 |
| 1117 | eor r11,r5,r6 |
| 1118 | add r7,r7,r10 |
| 1119 | and r11,r11,r4 |
| 1120 | mov r4,r4,ror#2 |
| 1121 | add r7,r7,r11 |
| 1122 | vext.8 q12,q0,q1,#8 |
| 1123 | add r6,r6,r9 |
| 1124 | and r10,r4,r5 |
| 1125 | ldr r9,[sp,#36] |
| 1126 | veor q2,q2,q10 |
| 1127 | add r6,r6,r7,ror#27 |
| 1128 | eor r11,r4,r5 |
| 1129 | veor q2,q2,q3 |
| 1130 | add r6,r6,r10 |
| 1131 | and r11,r11,r3 |
| 1132 | vadd.i32 q13,q1,q14 |
| 1133 | mov r3,r3,ror#2 |
| 1134 | add r6,r6,r11 |
| 1135 | veor q12,q12,q2 |
| 1136 | add r5,r5,r9 |
| 1137 | and r10,r3,r4 |
| 1138 | vshr.u32 q2,q12,#30 |
| 1139 | ldr r9,[sp,#40] |
| 1140 | add r5,r5,r6,ror#27 |
| 1141 | vst1.32 {q13},[r12,:128]! |
| 1142 | eor r11,r3,r4 |
| 1143 | add r5,r5,r10 |
| 1144 | vsli.32 q2,q12,#2 |
| 1145 | and r11,r11,r7 |
| 1146 | mov r7,r7,ror#2 |
| 1147 | add r5,r5,r11 |
| 1148 | add r4,r4,r9 |
| 1149 | and r10,r7,r3 |
| 1150 | ldr r9,[sp,#44] |
| 1151 | add r4,r4,r5,ror#27 |
| 1152 | eor r11,r7,r3 |
| 1153 | add r4,r4,r10 |
| 1154 | and r11,r11,r6 |
| 1155 | mov r6,r6,ror#2 |
| 1156 | add r4,r4,r11 |
| 1157 | add r3,r3,r9 |
| 1158 | and r10,r6,r7 |
| 1159 | ldr r9,[sp,#48] |
| 1160 | add r3,r3,r4,ror#27 |
| 1161 | eor r11,r6,r7 |
| 1162 | add r3,r3,r10 |
| 1163 | and r11,r11,r5 |
| 1164 | mov r5,r5,ror#2 |
| 1165 | add r3,r3,r11 |
| 1166 | vext.8 q12,q1,q2,#8 |
| 1167 | eor r10,r4,r6 |
| 1168 | add r7,r7,r9 |
| 1169 | ldr r9,[sp,#52] |
| 1170 | veor q3,q3,q11 |
| 1171 | eor r11,r10,r5 |
| 1172 | add r7,r7,r3,ror#27 |
| 1173 | veor q3,q3,q8 |
| 1174 | mov r4,r4,ror#2 |
| 1175 | add r7,r7,r11 |
| 1176 | vadd.i32 q13,q2,q14 |
| 1177 | eor r10,r3,r5 |
| 1178 | add r6,r6,r9 |
| 1179 | veor q12,q12,q3 |
| 1180 | ldr r9,[sp,#56] |
| 1181 | eor r11,r10,r4 |
| 1182 | vshr.u32 q3,q12,#30 |
| 1183 | add r6,r6,r7,ror#27 |
| 1184 | mov r3,r3,ror#2 |
| 1185 | vst1.32 {q13},[r12,:128]! |
| 1186 | add r6,r6,r11 |
| 1187 | eor r10,r7,r4 |
| 1188 | vsli.32 q3,q12,#2 |
| 1189 | add r5,r5,r9 |
| 1190 | ldr r9,[sp,#60] |
| 1191 | eor r11,r10,r3 |
| 1192 | add r5,r5,r6,ror#27 |
| 1193 | mov r7,r7,ror#2 |
| 1194 | add r5,r5,r11 |
| 1195 | eor r10,r6,r3 |
| 1196 | add r4,r4,r9 |
| 1197 | ldr r9,[sp,#0] |
| 1198 | eor r11,r10,r7 |
| 1199 | add r4,r4,r5,ror#27 |
| 1200 | mov r6,r6,ror#2 |
| 1201 | add r4,r4,r11 |
| 1202 | vadd.i32 q13,q3,q14 |
| 1203 | eor r10,r5,r7 |
| 1204 | add r3,r3,r9 |
| 1205 | vst1.32 {q13},[r12,:128]! |
| 1206 | sub r12,r12,#64 |
| 1207 | teq r1,r2 |
| 1208 | sub r8,r8,#16 |
| 1209 | it eq |
| 1210 | subeq r1,r1,#64 |
| 1211 | vld1.8 {q0,q1},[r1]! |
| 1212 | ldr r9,[sp,#4] |
| 1213 | eor r11,r10,r6 |
| 1214 | vld1.8 {q2,q3},[r1]! |
| 1215 | add r3,r3,r4,ror#27 |
| 1216 | mov r5,r5,ror#2 |
| 1217 | vld1.32 {d28[],d29[]},[r8,:32]! |
| 1218 | add r3,r3,r11 |
| 1219 | eor r10,r4,r6 |
| 1220 | vrev32.8 q0,q0 |
| 1221 | add r7,r7,r9 |
| 1222 | ldr r9,[sp,#8] |
| 1223 | eor r11,r10,r5 |
| 1224 | add r7,r7,r3,ror#27 |
| 1225 | mov r4,r4,ror#2 |
| 1226 | add r7,r7,r11 |
| 1227 | eor r10,r3,r5 |
| 1228 | add r6,r6,r9 |
| 1229 | ldr r9,[sp,#12] |
| 1230 | eor r11,r10,r4 |
| 1231 | add r6,r6,r7,ror#27 |
| 1232 | mov r3,r3,ror#2 |
| 1233 | add r6,r6,r11 |
| 1234 | eor r10,r7,r4 |
| 1235 | add r5,r5,r9 |
| 1236 | ldr r9,[sp,#16] |
| 1237 | eor r11,r10,r3 |
| 1238 | add r5,r5,r6,ror#27 |
| 1239 | mov r7,r7,ror#2 |
| 1240 | add r5,r5,r11 |
| 1241 | vrev32.8 q1,q1 |
| 1242 | eor r10,r6,r3 |
| 1243 | add r4,r4,r9 |
| 1244 | vadd.i32 q8,q0,q14 |
| 1245 | ldr r9,[sp,#20] |
| 1246 | eor r11,r10,r7 |
| 1247 | vst1.32 {q8},[r12,:128]! |
| 1248 | add r4,r4,r5,ror#27 |
| 1249 | mov r6,r6,ror#2 |
| 1250 | add r4,r4,r11 |
| 1251 | eor r10,r5,r7 |
| 1252 | add r3,r3,r9 |
| 1253 | ldr r9,[sp,#24] |
| 1254 | eor r11,r10,r6 |
| 1255 | add r3,r3,r4,ror#27 |
| 1256 | mov r5,r5,ror#2 |
| 1257 | add r3,r3,r11 |
| 1258 | eor r10,r4,r6 |
| 1259 | add r7,r7,r9 |
| 1260 | ldr r9,[sp,#28] |
| 1261 | eor r11,r10,r5 |
| 1262 | add r7,r7,r3,ror#27 |
| 1263 | mov r4,r4,ror#2 |
| 1264 | add r7,r7,r11 |
| 1265 | eor r10,r3,r5 |
| 1266 | add r6,r6,r9 |
| 1267 | ldr r9,[sp,#32] |
| 1268 | eor r11,r10,r4 |
| 1269 | add r6,r6,r7,ror#27 |
| 1270 | mov r3,r3,ror#2 |
| 1271 | add r6,r6,r11 |
| 1272 | vrev32.8 q2,q2 |
| 1273 | eor r10,r7,r4 |
| 1274 | add r5,r5,r9 |
| 1275 | vadd.i32 q9,q1,q14 |
| 1276 | ldr r9,[sp,#36] |
| 1277 | eor r11,r10,r3 |
| 1278 | vst1.32 {q9},[r12,:128]! |
| 1279 | add r5,r5,r6,ror#27 |
| 1280 | mov r7,r7,ror#2 |
| 1281 | add r5,r5,r11 |
| 1282 | eor r10,r6,r3 |
| 1283 | add r4,r4,r9 |
| 1284 | ldr r9,[sp,#40] |
| 1285 | eor r11,r10,r7 |
| 1286 | add r4,r4,r5,ror#27 |
| 1287 | mov r6,r6,ror#2 |
| 1288 | add r4,r4,r11 |
| 1289 | eor r10,r5,r7 |
| 1290 | add r3,r3,r9 |
| 1291 | ldr r9,[sp,#44] |
| 1292 | eor r11,r10,r6 |
| 1293 | add r3,r3,r4,ror#27 |
| 1294 | mov r5,r5,ror#2 |
| 1295 | add r3,r3,r11 |
| 1296 | eor r10,r4,r6 |
| 1297 | add r7,r7,r9 |
| 1298 | ldr r9,[sp,#48] |
| 1299 | eor r11,r10,r5 |
| 1300 | add r7,r7,r3,ror#27 |
| 1301 | mov r4,r4,ror#2 |
| 1302 | add r7,r7,r11 |
| 1303 | vrev32.8 q3,q3 |
| 1304 | eor r10,r3,r5 |
| 1305 | add r6,r6,r9 |
| 1306 | vadd.i32 q10,q2,q14 |
| 1307 | ldr r9,[sp,#52] |
| 1308 | eor r11,r10,r4 |
| 1309 | vst1.32 {q10},[r12,:128]! |
| 1310 | add r6,r6,r7,ror#27 |
| 1311 | mov r3,r3,ror#2 |
| 1312 | add r6,r6,r11 |
| 1313 | eor r10,r7,r4 |
| 1314 | add r5,r5,r9 |
| 1315 | ldr r9,[sp,#56] |
| 1316 | eor r11,r10,r3 |
| 1317 | add r5,r5,r6,ror#27 |
| 1318 | mov r7,r7,ror#2 |
| 1319 | add r5,r5,r11 |
| 1320 | eor r10,r6,r3 |
| 1321 | add r4,r4,r9 |
| 1322 | ldr r9,[sp,#60] |
| 1323 | eor r11,r10,r7 |
| 1324 | add r4,r4,r5,ror#27 |
| 1325 | mov r6,r6,ror#2 |
| 1326 | add r4,r4,r11 |
| 1327 | eor r10,r5,r7 |
| 1328 | add r3,r3,r9 |
| 1329 | eor r11,r10,r6 |
| 1330 | add r3,r3,r4,ror#27 |
| 1331 | mov r5,r5,ror#2 |
| 1332 | add r3,r3,r11 |
| 1333 | ldmia r0,{r9,r10,r11,r12} @ accumulate context |
| 1334 | add r3,r3,r9 |
| 1335 | ldr r9,[r0,#16] |
| 1336 | add r4,r4,r10 |
| 1337 | add r5,r5,r11 |
| 1338 | add r6,r6,r12 |
| 1339 | it eq |
| 1340 | moveq sp,r14 |
| 1341 | add r7,r7,r9 |
| 1342 | it ne |
| 1343 | ldrne r9,[sp] |
| 1344 | stmia r0,{r3,r4,r5,r6,r7} |
| 1345 | itt ne |
| 1346 | addne r12,sp,#3*16 |
| 1347 | bne Loop_neon |
| 1348 | |
| 1349 | @ vldmia sp!,{d8-d15} |
| 1350 | ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,pc} |
| 1351 | |
| 1352 | #endif |
| 1353 | #if __ARM_MAX_ARCH__>=7 |
| 1354 | |
| 1355 | # if defined(__thumb2__) |
| 1356 | # define INST(a,b,c,d) .byte c,d|0xf,a,b |
| 1357 | # else |
| 1358 | # define INST(a,b,c,d) .byte a,b,c,d|0x10 |
| 1359 | # endif |
| 1360 | |
| 1361 | #ifdef __thumb2__ |
| 1362 | .thumb_func sha1_block_data_order_armv8 |
| 1363 | #endif |
| 1364 | .align 5 |
| 1365 | sha1_block_data_order_armv8: |
| 1366 | LARMv8: |
| 1367 | vstmdb sp!,{d8,d9,d10,d11,d12,d13,d14,d15} @ ABI specification says so |
| 1368 | |
| 1369 | veor q1,q1,q1 |
| 1370 | adr r3,LK_00_19 |
| 1371 | vld1.32 {q0},[r0]! |
| 1372 | vld1.32 {d2[0]},[r0] |
| 1373 | sub r0,r0,#16 |
| 1374 | vld1.32 {d16[],d17[]},[r3,:32]! |
| 1375 | vld1.32 {d18[],d19[]},[r3,:32]! |
| 1376 | vld1.32 {d20[],d21[]},[r3,:32]! |
| 1377 | vld1.32 {d22[],d23[]},[r3,:32] |
| 1378 | |
| 1379 | Loop_v8: |
| 1380 | vld1.8 {q4,q5},[r1]! |
| 1381 | vld1.8 {q6,q7},[r1]! |
| 1382 | vrev32.8 q4,q4 |
| 1383 | vrev32.8 q5,q5 |
| 1384 | |
| 1385 | vadd.i32 q12,q8,q4 |
| 1386 | vrev32.8 q6,q6 |
| 1387 | vmov q14,q0 @ offload |
| 1388 | subs r2,r2,#1 |
| 1389 | |
| 1390 | vadd.i32 q13,q8,q5 |
| 1391 | vrev32.8 q7,q7 |
| 1392 | INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 0 |
| 1393 | INST(0x68,0x0c,0x02,0xe2) @ sha1c q0,q1,q12 |
| 1394 | vadd.i32 q12,q8,q6 |
| 1395 | INST(0x4c,0x8c,0x3a,0xe2) @ sha1su0 q4,q5,q6 |
| 1396 | INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 1 |
| 1397 | INST(0x6a,0x0c,0x06,0xe2) @ sha1c q0,q3,q13 |
| 1398 | vadd.i32 q13,q8,q7 |
| 1399 | INST(0x8e,0x83,0xba,0xf3) @ sha1su1 q4,q7 |
| 1400 | INST(0x4e,0xac,0x3c,0xe2) @ sha1su0 q5,q6,q7 |
| 1401 | INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 2 |
| 1402 | INST(0x68,0x0c,0x04,0xe2) @ sha1c q0,q2,q12 |
| 1403 | vadd.i32 q12,q8,q4 |
| 1404 | INST(0x88,0xa3,0xba,0xf3) @ sha1su1 q5,q4 |
| 1405 | INST(0x48,0xcc,0x3e,0xe2) @ sha1su0 q6,q7,q4 |
| 1406 | INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 3 |
| 1407 | INST(0x6a,0x0c,0x06,0xe2) @ sha1c q0,q3,q13 |
| 1408 | vadd.i32 q13,q9,q5 |
| 1409 | INST(0x8a,0xc3,0xba,0xf3) @ sha1su1 q6,q5 |
| 1410 | INST(0x4a,0xec,0x38,0xe2) @ sha1su0 q7,q4,q5 |
| 1411 | INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 4 |
| 1412 | INST(0x68,0x0c,0x04,0xe2) @ sha1c q0,q2,q12 |
| 1413 | vadd.i32 q12,q9,q6 |
| 1414 | INST(0x8c,0xe3,0xba,0xf3) @ sha1su1 q7,q6 |
| 1415 | INST(0x4c,0x8c,0x3a,0xe2) @ sha1su0 q4,q5,q6 |
| 1416 | INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 5 |
| 1417 | INST(0x6a,0x0c,0x16,0xe2) @ sha1p q0,q3,q13 |
| 1418 | vadd.i32 q13,q9,q7 |
| 1419 | INST(0x8e,0x83,0xba,0xf3) @ sha1su1 q4,q7 |
| 1420 | INST(0x4e,0xac,0x3c,0xe2) @ sha1su0 q5,q6,q7 |
| 1421 | INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 6 |
| 1422 | INST(0x68,0x0c,0x14,0xe2) @ sha1p q0,q2,q12 |
| 1423 | vadd.i32 q12,q9,q4 |
| 1424 | INST(0x88,0xa3,0xba,0xf3) @ sha1su1 q5,q4 |
| 1425 | INST(0x48,0xcc,0x3e,0xe2) @ sha1su0 q6,q7,q4 |
| 1426 | INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 7 |
| 1427 | INST(0x6a,0x0c,0x16,0xe2) @ sha1p q0,q3,q13 |
| 1428 | vadd.i32 q13,q9,q5 |
| 1429 | INST(0x8a,0xc3,0xba,0xf3) @ sha1su1 q6,q5 |
| 1430 | INST(0x4a,0xec,0x38,0xe2) @ sha1su0 q7,q4,q5 |
| 1431 | INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 8 |
| 1432 | INST(0x68,0x0c,0x14,0xe2) @ sha1p q0,q2,q12 |
| 1433 | vadd.i32 q12,q10,q6 |
| 1434 | INST(0x8c,0xe3,0xba,0xf3) @ sha1su1 q7,q6 |
| 1435 | INST(0x4c,0x8c,0x3a,0xe2) @ sha1su0 q4,q5,q6 |
| 1436 | INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 9 |
| 1437 | INST(0x6a,0x0c,0x16,0xe2) @ sha1p q0,q3,q13 |
| 1438 | vadd.i32 q13,q10,q7 |
| 1439 | INST(0x8e,0x83,0xba,0xf3) @ sha1su1 q4,q7 |
| 1440 | INST(0x4e,0xac,0x3c,0xe2) @ sha1su0 q5,q6,q7 |
| 1441 | INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 10 |
| 1442 | INST(0x68,0x0c,0x24,0xe2) @ sha1m q0,q2,q12 |
| 1443 | vadd.i32 q12,q10,q4 |
| 1444 | INST(0x88,0xa3,0xba,0xf3) @ sha1su1 q5,q4 |
| 1445 | INST(0x48,0xcc,0x3e,0xe2) @ sha1su0 q6,q7,q4 |
| 1446 | INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 11 |
| 1447 | INST(0x6a,0x0c,0x26,0xe2) @ sha1m q0,q3,q13 |
| 1448 | vadd.i32 q13,q10,q5 |
| 1449 | INST(0x8a,0xc3,0xba,0xf3) @ sha1su1 q6,q5 |
| 1450 | INST(0x4a,0xec,0x38,0xe2) @ sha1su0 q7,q4,q5 |
| 1451 | INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 12 |
| 1452 | INST(0x68,0x0c,0x24,0xe2) @ sha1m q0,q2,q12 |
| 1453 | vadd.i32 q12,q10,q6 |
| 1454 | INST(0x8c,0xe3,0xba,0xf3) @ sha1su1 q7,q6 |
| 1455 | INST(0x4c,0x8c,0x3a,0xe2) @ sha1su0 q4,q5,q6 |
| 1456 | INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 13 |
| 1457 | INST(0x6a,0x0c,0x26,0xe2) @ sha1m q0,q3,q13 |
| 1458 | vadd.i32 q13,q11,q7 |
| 1459 | INST(0x8e,0x83,0xba,0xf3) @ sha1su1 q4,q7 |
| 1460 | INST(0x4e,0xac,0x3c,0xe2) @ sha1su0 q5,q6,q7 |
| 1461 | INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 14 |
| 1462 | INST(0x68,0x0c,0x24,0xe2) @ sha1m q0,q2,q12 |
| 1463 | vadd.i32 q12,q11,q4 |
| 1464 | INST(0x88,0xa3,0xba,0xf3) @ sha1su1 q5,q4 |
| 1465 | INST(0x48,0xcc,0x3e,0xe2) @ sha1su0 q6,q7,q4 |
| 1466 | INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 15 |
| 1467 | INST(0x6a,0x0c,0x16,0xe2) @ sha1p q0,q3,q13 |
| 1468 | vadd.i32 q13,q11,q5 |
| 1469 | INST(0x8a,0xc3,0xba,0xf3) @ sha1su1 q6,q5 |
| 1470 | INST(0x4a,0xec,0x38,0xe2) @ sha1su0 q7,q4,q5 |
| 1471 | INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 16 |
| 1472 | INST(0x68,0x0c,0x14,0xe2) @ sha1p q0,q2,q12 |
| 1473 | vadd.i32 q12,q11,q6 |
| 1474 | INST(0x8c,0xe3,0xba,0xf3) @ sha1su1 q7,q6 |
| 1475 | INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 17 |
| 1476 | INST(0x6a,0x0c,0x16,0xe2) @ sha1p q0,q3,q13 |
| 1477 | vadd.i32 q13,q11,q7 |
| 1478 | |
| 1479 | INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 18 |
| 1480 | INST(0x68,0x0c,0x14,0xe2) @ sha1p q0,q2,q12 |
| 1481 | |
| 1482 | INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 19 |
| 1483 | INST(0x6a,0x0c,0x16,0xe2) @ sha1p q0,q3,q13 |
| 1484 | |
| 1485 | vadd.i32 q1,q1,q2 |
| 1486 | vadd.i32 q0,q0,q14 |
| 1487 | bne Loop_v8 |
| 1488 | |
| 1489 | vst1.32 {q0},[r0]! |
| 1490 | vst1.32 {d2[0]},[r0] |
| 1491 | |
| 1492 | vldmia sp!,{d8,d9,d10,d11,d12,d13,d14,d15} |
| 1493 | bx lr @ bx lr |
| 1494 | |
| 1495 | #endif |
| 1496 | #if __ARM_MAX_ARCH__>=7 |
| 1497 | .comm _OPENSSL_armcap_P,4 |
| 1498 | .non_lazy_symbol_pointer |
| 1499 | OPENSSL_armcap_P: |
| 1500 | .indirect_symbol _OPENSSL_armcap_P |
| 1501 | .long 0 |
| 1502 | .private_extern _OPENSSL_armcap_P |
| 1503 | #endif |