Robert Sloan | 726e9d1 | 2018-09-11 11:45:04 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2018, Google Inc. |
| 2 | * |
| 3 | * Permission to use, copy, modify, and/or distribute this software for any |
| 4 | * purpose with or without fee is hereby granted, provided that the above |
| 5 | * copyright notice and this permission notice appear in all copies. |
| 6 | * |
| 7 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 8 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 9 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
| 10 | * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 11 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION |
| 12 | * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN |
| 13 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ |
| 14 | |
| 15 | #include "cpu-arm-linux.h" |
| 16 | |
| 17 | #include <string.h> |
| 18 | |
| 19 | #include <gtest/gtest.h> |
| 20 | |
| 21 | |
Robert Sloan | 726e9d1 | 2018-09-11 11:45:04 -0700 | [diff] [blame] | 22 | TEST(ARMLinuxTest, CPUInfo) { |
| 23 | struct CPUInfoTest { |
| 24 | const char *cpuinfo; |
| 25 | unsigned long hwcap; |
| 26 | unsigned long hwcap2; |
| 27 | bool broken_neon; |
| 28 | } kTests[] = { |
| 29 | // https://crbug.com/341598#c33 |
| 30 | { |
| 31 | "Processor: ARMv7 Processory rev 0 (v71)\n" |
| 32 | "processor: 0\n" |
| 33 | "BogoMIPS: 13.50\n" |
| 34 | "\n" |
| 35 | "Processor: 1\n" |
| 36 | "BogoMIPS: 13.50\n" |
| 37 | "\n" |
| 38 | "Features: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 " |
| 39 | "idiva idivt\n" |
| 40 | "CPU implementer : 0x51\n" |
| 41 | "CPU architecture: 7\n" |
| 42 | "CPU variant: 0x1\n" |
| 43 | "CPU part: 0x04d\n" |
| 44 | "CPU revision: 0\n" |
| 45 | "\n" |
| 46 | "Hardware: SAMSUNG M2\n" |
| 47 | "Revision: 0010\n" |
| 48 | "Serial: 00001e030000354e\n", |
| 49 | HWCAP_NEON, |
| 50 | 0, |
| 51 | true, |
| 52 | }, |
| 53 | // https://crbug.com/341598#c39 |
| 54 | { |
| 55 | "Processor : ARMv7 Processor rev 0 (v7l)\n" |
| 56 | "processor : 0\n" |
| 57 | "BogoMIPS : 13.53\n" |
| 58 | "\n" |
| 59 | "Features : swp half thumb fastmult vfp edsp neon vfpv3 tls " |
| 60 | "vfpv4\n" |
| 61 | "CPU implementer : 0x51\n" |
| 62 | "CPU architecture: 7\n" |
| 63 | "CPU variant : 0x1\n" |
| 64 | "CPU part : 0x04d\n" |
| 65 | "CPU revision : 0\n" |
| 66 | "\n" |
| 67 | "Hardware : SAMSUNG M2_ATT\n" |
| 68 | "Revision : 0010\n" |
| 69 | "Serial : 0000df0c00004d4c\n", |
| 70 | HWCAP_NEON, |
| 71 | 0, |
| 72 | true, |
| 73 | }, |
| 74 | // Nexus 4 from https://crbug.com/341598#c43 |
| 75 | { |
| 76 | "Processor : ARMv7 Processor rev 2 (v7l)\n" |
| 77 | "processor : 0\n" |
| 78 | "BogoMIPS : 13.53\n" |
| 79 | "\n" |
| 80 | "processor : 1\n" |
| 81 | "BogoMIPS : 13.53\n" |
| 82 | "\n" |
| 83 | "processor : 2\n" |
| 84 | "BogoMIPS : 13.53\n" |
| 85 | "\n" |
| 86 | "processor : 3\n" |
| 87 | "BogoMIPS : 13.53\n" |
| 88 | "\n" |
| 89 | "Features : swp half thumb fastmult vfp edsp neon vfpv3 tls " |
| 90 | "vfpv4 \n" |
| 91 | "CPU implementer : 0x51\n" |
| 92 | "CPU architecture: 7\n" |
| 93 | "CPU variant : 0x0\n" |
| 94 | "CPU part : 0x06f\n" |
| 95 | "CPU revision : 2\n" |
| 96 | "\n" |
| 97 | "Hardware : QCT APQ8064 MAKO\n" |
| 98 | "Revision : 000b\n" |
| 99 | "Serial : 0000000000000000\n", |
| 100 | HWCAP_NEON, |
| 101 | 0, |
| 102 | false, |
| 103 | }, |
| 104 | // Razr M from https://crbug.com/341598#c43 |
| 105 | { |
| 106 | "Processor : ARMv7 Processor rev 4 (v7l)\n" |
| 107 | "processor : 0\n" |
| 108 | "BogoMIPS : 13.53\n" |
| 109 | "\n" |
| 110 | "Features : swp half thumb fastmult vfp edsp neon vfpv3 tls " |
| 111 | "vfpv4\n" |
| 112 | "CPU implementer : 0x51\n" |
| 113 | "CPU architecture: 7\n" |
| 114 | "CPU variant : 0x1\n" |
| 115 | "CPU part : 0x04d\n" |
| 116 | "CPU revision : 4\n" |
| 117 | "\n" |
| 118 | "Hardware : msm8960dt\n" |
| 119 | "Revision : 82a0\n" |
| 120 | "Serial : 0001000201fe37a5\n", |
| 121 | HWCAP_NEON, |
| 122 | 0, |
| 123 | false, |
| 124 | }, |
| 125 | // Pixel 2 (truncated slightly) |
| 126 | { |
| 127 | "Processor : AArch64 Processor rev 1 (aarch64)\n" |
| 128 | "processor : 0\n" |
| 129 | "BogoMIPS : 38.00\n" |
| 130 | "Features : fp asimd evtstrm aes pmull sha1 sha2 crc32\n" |
| 131 | "CPU implementer : 0x51\n" |
| 132 | "CPU architecture: 8\n" |
| 133 | "CPU variant : 0xa\n" |
| 134 | "CPU part : 0x801\n" |
| 135 | "CPU revision : 4\n" |
| 136 | "\n" |
| 137 | "processor : 1\n" |
| 138 | "BogoMIPS : 38.00\n" |
| 139 | "Features : fp asimd evtstrm aes pmull sha1 sha2 crc32\n" |
| 140 | "CPU implementer : 0x51\n" |
| 141 | "CPU architecture: 8\n" |
| 142 | "CPU variant : 0xa\n" |
| 143 | "CPU part : 0x801\n" |
| 144 | "CPU revision : 4\n" |
| 145 | "\n" |
| 146 | "processor : 2\n" |
| 147 | "BogoMIPS : 38.00\n" |
| 148 | "Features : fp asimd evtstrm aes pmull sha1 sha2 crc32\n" |
| 149 | "CPU implementer : 0x51\n" |
| 150 | "CPU architecture: 8\n" |
| 151 | "CPU variant : 0xa\n" |
| 152 | "CPU part : 0x801\n" |
| 153 | "CPU revision : 4\n" |
| 154 | "\n" |
| 155 | "processor : 3\n" |
| 156 | "BogoMIPS : 38.00\n" |
| 157 | "Features : fp asimd evtstrm aes pmull sha1 sha2 crc32\n" |
| 158 | "CPU implementer : 0x51\n" |
| 159 | "CPU architecture: 8\n" |
| 160 | "CPU variant : 0xa\n" |
| 161 | "CPU part : 0x801\n" |
| 162 | "CPU revision : 4\n" |
| 163 | // (Extra processors omitted.) |
| 164 | "\n" |
| 165 | "Hardware : Qualcomm Technologies, Inc MSM8998\n", |
| 166 | HWCAP_NEON, // CPU architecture 8 implies NEON. |
| 167 | HWCAP2_AES | HWCAP2_PMULL | HWCAP2_SHA1 | HWCAP2_SHA2, |
| 168 | false, |
| 169 | }, |
| 170 | // Nexus 4 from |
| 171 | // Garbage should be tolerated. |
| 172 | { |
| 173 | "Blah blah blah this is definitely an ARM CPU", |
| 174 | 0, |
| 175 | 0, |
| 176 | false, |
| 177 | }, |
| 178 | // A hypothetical ARMv8 CPU without crc32 (and thus no trailing space |
| 179 | // after the last crypto entry). |
| 180 | { |
| 181 | "Features : aes pmull sha1 sha2\n" |
| 182 | "CPU architecture: 8\n", |
| 183 | HWCAP_NEON, |
| 184 | HWCAP2_AES | HWCAP2_PMULL | HWCAP2_SHA1 | HWCAP2_SHA2, |
| 185 | false, |
| 186 | }, |
| 187 | // Various combinations of ARMv8 flags. |
| 188 | { |
| 189 | "Features : aes sha1 sha2\n" |
| 190 | "CPU architecture: 8\n", |
| 191 | HWCAP_NEON, |
| 192 | HWCAP2_AES | HWCAP2_SHA1 | HWCAP2_SHA2, |
| 193 | false, |
| 194 | }, |
| 195 | { |
| 196 | "Features : pmull sha2\n" |
| 197 | "CPU architecture: 8\n", |
| 198 | HWCAP_NEON, |
| 199 | HWCAP2_PMULL | HWCAP2_SHA2, |
| 200 | false, |
| 201 | }, |
| 202 | { |
| 203 | "Features : aes aes aes not_aes aes aes \n" |
| 204 | "CPU architecture: 8\n", |
| 205 | HWCAP_NEON, |
| 206 | HWCAP2_AES, |
| 207 | false, |
| 208 | }, |
| 209 | { |
| 210 | "Features : \n" |
| 211 | "CPU architecture: 8\n", |
| 212 | HWCAP_NEON, |
| 213 | 0, |
| 214 | false, |
| 215 | }, |
| 216 | { |
| 217 | "Features : nothing\n" |
| 218 | "CPU architecture: 8\n", |
| 219 | HWCAP_NEON, |
| 220 | 0, |
| 221 | false, |
| 222 | }, |
| 223 | }; |
| 224 | |
| 225 | for (const auto &t : kTests) { |
| 226 | SCOPED_TRACE(t.cpuinfo); |
| 227 | STRING_PIECE sp = {t.cpuinfo, strlen(t.cpuinfo)}; |
| 228 | EXPECT_EQ(t.hwcap, crypto_get_arm_hwcap_from_cpuinfo(&sp)); |
| 229 | EXPECT_EQ(t.hwcap2, crypto_get_arm_hwcap2_from_cpuinfo(&sp)); |
| 230 | EXPECT_EQ(t.broken_neon ? 1 : 0, crypto_cpuinfo_has_broken_neon(&sp)); |
| 231 | } |
| 232 | } |