Robert Sloan | c9abfe4 | 2018-11-26 12:19:07 -0800 | [diff] [blame] | 1 | // This file is generated from a similarly-named Perl script in the BoringSSL |
| 2 | // source tree. Do not edit by hand. |
| 3 | |
Robert Sloan | 726e9d1 | 2018-09-11 11:45:04 -0700 | [diff] [blame] | 4 | #if defined(__has_feature) |
| 5 | #if __has_feature(memory_sanitizer) && !defined(OPENSSL_NO_ASM) |
| 6 | #define OPENSSL_NO_ASM |
| 7 | #endif |
| 8 | #endif |
| 9 | |
| 10 | #if !defined(OPENSSL_NO_ASM) |
Kenny Root | b849459 | 2015-09-25 02:29:14 +0000 | [diff] [blame] | 11 | #if defined(__arm__) |
Robert Sloan | 726e9d1 | 2018-09-11 11:45:04 -0700 | [diff] [blame] | 12 | #if defined(BORINGSSL_PREFIX) |
| 13 | #include <boringssl_prefix_symbols_asm.h> |
| 14 | #endif |
Robert Sloan | 8ff0355 | 2017-06-14 12:40:58 -0700 | [diff] [blame] | 15 | @ Copyright 2007-2016 The OpenSSL Project Authors. All Rights Reserved. |
| 16 | @ |
| 17 | @ Licensed under the OpenSSL license (the "License"). You may not use |
| 18 | @ this file except in compliance with the License. You can obtain a copy |
| 19 | @ in the file LICENSE in the source distribution or at |
| 20 | @ https://www.openssl.org/source/license.html |
| 21 | |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 22 | |
| 23 | @ ==================================================================== |
| 24 | @ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL |
| 25 | @ project. The module is, however, dual licensed under OpenSSL and |
| 26 | @ CRYPTOGAMS licenses depending on where you obtain it. For further |
| 27 | @ details see http://www.openssl.org/~appro/cryptogams/. |
| 28 | @ |
| 29 | @ Permission to use under GPL terms is granted. |
| 30 | @ ==================================================================== |
| 31 | |
| 32 | @ SHA512 block procedure for ARMv4. September 2007. |
| 33 | |
| 34 | @ This code is ~4.5 (four and a half) times faster than code generated |
| 35 | @ by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue |
| 36 | @ Xscale PXA250 core]. |
| 37 | @ |
| 38 | @ July 2010. |
| 39 | @ |
| 40 | @ Rescheduling for dual-issue pipeline resulted in 6% improvement on |
| 41 | @ Cortex A8 core and ~40 cycles per processed byte. |
| 42 | |
| 43 | @ February 2011. |
| 44 | @ |
| 45 | @ Profiler-assisted and platform-specific optimization resulted in 7% |
| 46 | @ improvement on Coxtex A8 core and ~38 cycles per byte. |
| 47 | |
| 48 | @ March 2011. |
| 49 | @ |
| 50 | @ Add NEON implementation. On Cortex A8 it was measured to process |
| 51 | @ one byte in 23.3 cycles or ~60% faster than integer-only code. |
| 52 | |
| 53 | @ August 2012. |
| 54 | @ |
| 55 | @ Improve NEON performance by 12% on Snapdragon S4. In absolute |
| 56 | @ terms it's 22.6 cycles per byte, which is disappointing result. |
| 57 | @ Technical writers asserted that 3-way S4 pipeline can sustain |
| 58 | @ multiple NEON instructions per cycle, but dual NEON issue could |
| 59 | @ not be observed, see http://www.openssl.org/~appro/Snapdragon-S4.html |
| 60 | @ for further details. On side note Cortex-A15 processes one byte in |
| 61 | @ 16 cycles. |
| 62 | |
| 63 | @ Byte order [in]dependence. ========================================= |
| 64 | @ |
| 65 | @ Originally caller was expected to maintain specific *dword* order in |
| 66 | @ h[0-7], namely with most significant dword at *lower* address, which |
| 67 | @ was reflected in below two parameters as 0 and 4. Now caller is |
| 68 | @ expected to maintain native byte order for whole 64-bit values. |
| 69 | #ifndef __KERNEL__ |
Kenny Root | b849459 | 2015-09-25 02:29:14 +0000 | [diff] [blame] | 70 | # include <openssl/arm_arch.h> |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 71 | # define VFP_ABI_PUSH vstmdb sp!,{d8-d15} |
| 72 | # define VFP_ABI_POP vldmia sp!,{d8-d15} |
| 73 | #else |
| 74 | # define __ARM_ARCH__ __LINUX_ARM_ARCH__ |
| 75 | # define __ARM_MAX_ARCH__ 7 |
| 76 | # define VFP_ABI_PUSH |
| 77 | # define VFP_ABI_POP |
| 78 | #endif |
| 79 | |
Robert Sloan | 5581810 | 2017-12-18 11:26:17 -0800 | [diff] [blame] | 80 | @ Silence ARMv8 deprecated IT instruction warnings. This file is used by both |
| 81 | @ ARMv7 and ARMv8 processors and does not use ARMv8 instructions. |
| 82 | .arch armv7-a |
| 83 | |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 84 | #ifdef __ARMEL__ |
| 85 | # define LO 0 |
| 86 | # define HI 4 |
| 87 | # define WORD64(hi0,lo0,hi1,lo1) .word lo0,hi0, lo1,hi1 |
| 88 | #else |
| 89 | # define HI 0 |
| 90 | # define LO 4 |
| 91 | # define WORD64(hi0,lo0,hi1,lo1) .word hi0,lo0, hi1,lo1 |
| 92 | #endif |
| 93 | |
| 94 | .text |
Robert Sloan | 8ff0355 | 2017-06-14 12:40:58 -0700 | [diff] [blame] | 95 | #if defined(__thumb2__) |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 96 | .syntax unified |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 97 | .thumb |
Robert Sloan | 8ff0355 | 2017-06-14 12:40:58 -0700 | [diff] [blame] | 98 | # define adrl adr |
| 99 | #else |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 100 | .code 32 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 101 | #endif |
| 102 | |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 103 | .type K512,%object |
| 104 | .align 5 |
| 105 | K512: |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 106 | WORD64(0x428a2f98,0xd728ae22, 0x71374491,0x23ef65cd) |
| 107 | WORD64(0xb5c0fbcf,0xec4d3b2f, 0xe9b5dba5,0x8189dbbc) |
| 108 | WORD64(0x3956c25b,0xf348b538, 0x59f111f1,0xb605d019) |
| 109 | WORD64(0x923f82a4,0xaf194f9b, 0xab1c5ed5,0xda6d8118) |
| 110 | WORD64(0xd807aa98,0xa3030242, 0x12835b01,0x45706fbe) |
| 111 | WORD64(0x243185be,0x4ee4b28c, 0x550c7dc3,0xd5ffb4e2) |
| 112 | WORD64(0x72be5d74,0xf27b896f, 0x80deb1fe,0x3b1696b1) |
| 113 | WORD64(0x9bdc06a7,0x25c71235, 0xc19bf174,0xcf692694) |
| 114 | WORD64(0xe49b69c1,0x9ef14ad2, 0xefbe4786,0x384f25e3) |
| 115 | WORD64(0x0fc19dc6,0x8b8cd5b5, 0x240ca1cc,0x77ac9c65) |
| 116 | WORD64(0x2de92c6f,0x592b0275, 0x4a7484aa,0x6ea6e483) |
| 117 | WORD64(0x5cb0a9dc,0xbd41fbd4, 0x76f988da,0x831153b5) |
| 118 | WORD64(0x983e5152,0xee66dfab, 0xa831c66d,0x2db43210) |
| 119 | WORD64(0xb00327c8,0x98fb213f, 0xbf597fc7,0xbeef0ee4) |
| 120 | WORD64(0xc6e00bf3,0x3da88fc2, 0xd5a79147,0x930aa725) |
| 121 | WORD64(0x06ca6351,0xe003826f, 0x14292967,0x0a0e6e70) |
| 122 | WORD64(0x27b70a85,0x46d22ffc, 0x2e1b2138,0x5c26c926) |
| 123 | WORD64(0x4d2c6dfc,0x5ac42aed, 0x53380d13,0x9d95b3df) |
| 124 | WORD64(0x650a7354,0x8baf63de, 0x766a0abb,0x3c77b2a8) |
| 125 | WORD64(0x81c2c92e,0x47edaee6, 0x92722c85,0x1482353b) |
| 126 | WORD64(0xa2bfe8a1,0x4cf10364, 0xa81a664b,0xbc423001) |
| 127 | WORD64(0xc24b8b70,0xd0f89791, 0xc76c51a3,0x0654be30) |
| 128 | WORD64(0xd192e819,0xd6ef5218, 0xd6990624,0x5565a910) |
| 129 | WORD64(0xf40e3585,0x5771202a, 0x106aa070,0x32bbd1b8) |
| 130 | WORD64(0x19a4c116,0xb8d2d0c8, 0x1e376c08,0x5141ab53) |
| 131 | WORD64(0x2748774c,0xdf8eeb99, 0x34b0bcb5,0xe19b48a8) |
| 132 | WORD64(0x391c0cb3,0xc5c95a63, 0x4ed8aa4a,0xe3418acb) |
| 133 | WORD64(0x5b9cca4f,0x7763e373, 0x682e6ff3,0xd6b2b8a3) |
| 134 | WORD64(0x748f82ee,0x5defb2fc, 0x78a5636f,0x43172f60) |
| 135 | WORD64(0x84c87814,0xa1f0ab72, 0x8cc70208,0x1a6439ec) |
| 136 | WORD64(0x90befffa,0x23631e28, 0xa4506ceb,0xde82bde9) |
| 137 | WORD64(0xbef9a3f7,0xb2c67915, 0xc67178f2,0xe372532b) |
| 138 | WORD64(0xca273ece,0xea26619c, 0xd186b8c7,0x21c0c207) |
| 139 | WORD64(0xeada7dd6,0xcde0eb1e, 0xf57d4f7f,0xee6ed178) |
| 140 | WORD64(0x06f067aa,0x72176fba, 0x0a637dc5,0xa2c898a6) |
| 141 | WORD64(0x113f9804,0xbef90dae, 0x1b710b35,0x131c471b) |
| 142 | WORD64(0x28db77f5,0x23047d84, 0x32caab7b,0x40c72493) |
| 143 | WORD64(0x3c9ebe0a,0x15c9bebc, 0x431d67c4,0x9c100d4c) |
| 144 | WORD64(0x4cc5d4be,0xcb3e42b6, 0x597f299c,0xfc657e2a) |
| 145 | WORD64(0x5fcb6fab,0x3ad6faec, 0x6c44198c,0x4a475817) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 146 | .size K512,.-K512 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 147 | #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 148 | .LOPENSSL_armcap: |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 149 | .word OPENSSL_armcap_P-.Lsha512_block_data_order |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 150 | .skip 32-4 |
| 151 | #else |
| 152 | .skip 32 |
| 153 | #endif |
| 154 | |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 155 | .globl sha512_block_data_order |
David Benjamin | 4969cc9 | 2016-04-22 15:02:23 -0400 | [diff] [blame] | 156 | .hidden sha512_block_data_order |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 157 | .type sha512_block_data_order,%function |
| 158 | sha512_block_data_order: |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 159 | .Lsha512_block_data_order: |
Robert Sloan | 8ff0355 | 2017-06-14 12:40:58 -0700 | [diff] [blame] | 160 | #if __ARM_ARCH__<7 && !defined(__thumb2__) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 161 | sub r3,pc,#8 @ sha512_block_data_order |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 162 | #else |
Robert Sloan | 8ff0355 | 2017-06-14 12:40:58 -0700 | [diff] [blame] | 163 | adr r3,.Lsha512_block_data_order |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 164 | #endif |
| 165 | #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 166 | ldr r12,.LOPENSSL_armcap |
| 167 | ldr r12,[r3,r12] @ OPENSSL_armcap_P |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 168 | #ifdef __APPLE__ |
| 169 | ldr r12,[r12] |
| 170 | #endif |
David Benjamin | 4969cc9 | 2016-04-22 15:02:23 -0400 | [diff] [blame] | 171 | tst r12,#ARMV7_NEON |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 172 | bne .LNEON |
| 173 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 174 | add r2,r1,r2,lsl#7 @ len to point at the end of inp |
| 175 | stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 176 | sub r14,r3,#672 @ K512 |
| 177 | sub sp,sp,#9*8 |
| 178 | |
| 179 | ldr r7,[r0,#32+LO] |
| 180 | ldr r8,[r0,#32+HI] |
| 181 | ldr r9, [r0,#48+LO] |
| 182 | ldr r10, [r0,#48+HI] |
| 183 | ldr r11, [r0,#56+LO] |
| 184 | ldr r12, [r0,#56+HI] |
| 185 | .Loop: |
| 186 | str r9, [sp,#48+0] |
| 187 | str r10, [sp,#48+4] |
| 188 | str r11, [sp,#56+0] |
| 189 | str r12, [sp,#56+4] |
| 190 | ldr r5,[r0,#0+LO] |
| 191 | ldr r6,[r0,#0+HI] |
| 192 | ldr r3,[r0,#8+LO] |
| 193 | ldr r4,[r0,#8+HI] |
| 194 | ldr r9, [r0,#16+LO] |
| 195 | ldr r10, [r0,#16+HI] |
| 196 | ldr r11, [r0,#24+LO] |
| 197 | ldr r12, [r0,#24+HI] |
| 198 | str r3,[sp,#8+0] |
| 199 | str r4,[sp,#8+4] |
| 200 | str r9, [sp,#16+0] |
| 201 | str r10, [sp,#16+4] |
| 202 | str r11, [sp,#24+0] |
| 203 | str r12, [sp,#24+4] |
| 204 | ldr r3,[r0,#40+LO] |
| 205 | ldr r4,[r0,#40+HI] |
| 206 | str r3,[sp,#40+0] |
| 207 | str r4,[sp,#40+4] |
| 208 | |
| 209 | .L00_15: |
| 210 | #if __ARM_ARCH__<7 |
| 211 | ldrb r3,[r1,#7] |
| 212 | ldrb r9, [r1,#6] |
| 213 | ldrb r10, [r1,#5] |
| 214 | ldrb r11, [r1,#4] |
| 215 | ldrb r4,[r1,#3] |
| 216 | ldrb r12, [r1,#2] |
| 217 | orr r3,r3,r9,lsl#8 |
| 218 | ldrb r9, [r1,#1] |
| 219 | orr r3,r3,r10,lsl#16 |
| 220 | ldrb r10, [r1],#8 |
| 221 | orr r3,r3,r11,lsl#24 |
| 222 | orr r4,r4,r12,lsl#8 |
| 223 | orr r4,r4,r9,lsl#16 |
| 224 | orr r4,r4,r10,lsl#24 |
| 225 | #else |
| 226 | ldr r3,[r1,#4] |
| 227 | ldr r4,[r1],#8 |
| 228 | #ifdef __ARMEL__ |
| 229 | rev r3,r3 |
| 230 | rev r4,r4 |
| 231 | #endif |
| 232 | #endif |
| 233 | @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41)) |
| 234 | @ LO lo>>14^hi<<18 ^ lo>>18^hi<<14 ^ hi>>9^lo<<23 |
| 235 | @ HI hi>>14^lo<<18 ^ hi>>18^lo<<14 ^ lo>>9^hi<<23 |
| 236 | mov r9,r7,lsr#14 |
| 237 | str r3,[sp,#64+0] |
| 238 | mov r10,r8,lsr#14 |
| 239 | str r4,[sp,#64+4] |
| 240 | eor r9,r9,r8,lsl#18 |
| 241 | ldr r11,[sp,#56+0] @ h.lo |
| 242 | eor r10,r10,r7,lsl#18 |
| 243 | ldr r12,[sp,#56+4] @ h.hi |
| 244 | eor r9,r9,r7,lsr#18 |
| 245 | eor r10,r10,r8,lsr#18 |
| 246 | eor r9,r9,r8,lsl#14 |
| 247 | eor r10,r10,r7,lsl#14 |
| 248 | eor r9,r9,r8,lsr#9 |
| 249 | eor r10,r10,r7,lsr#9 |
| 250 | eor r9,r9,r7,lsl#23 |
| 251 | eor r10,r10,r8,lsl#23 @ Sigma1(e) |
| 252 | adds r3,r3,r9 |
| 253 | ldr r9,[sp,#40+0] @ f.lo |
| 254 | adc r4,r4,r10 @ T += Sigma1(e) |
| 255 | ldr r10,[sp,#40+4] @ f.hi |
| 256 | adds r3,r3,r11 |
| 257 | ldr r11,[sp,#48+0] @ g.lo |
| 258 | adc r4,r4,r12 @ T += h |
| 259 | ldr r12,[sp,#48+4] @ g.hi |
| 260 | |
| 261 | eor r9,r9,r11 |
| 262 | str r7,[sp,#32+0] |
| 263 | eor r10,r10,r12 |
| 264 | str r8,[sp,#32+4] |
| 265 | and r9,r9,r7 |
| 266 | str r5,[sp,#0+0] |
| 267 | and r10,r10,r8 |
| 268 | str r6,[sp,#0+4] |
| 269 | eor r9,r9,r11 |
| 270 | ldr r11,[r14,#LO] @ K[i].lo |
| 271 | eor r10,r10,r12 @ Ch(e,f,g) |
| 272 | ldr r12,[r14,#HI] @ K[i].hi |
| 273 | |
| 274 | adds r3,r3,r9 |
| 275 | ldr r7,[sp,#24+0] @ d.lo |
| 276 | adc r4,r4,r10 @ T += Ch(e,f,g) |
| 277 | ldr r8,[sp,#24+4] @ d.hi |
| 278 | adds r3,r3,r11 |
| 279 | and r9,r11,#0xff |
| 280 | adc r4,r4,r12 @ T += K[i] |
| 281 | adds r7,r7,r3 |
| 282 | ldr r11,[sp,#8+0] @ b.lo |
| 283 | adc r8,r8,r4 @ d += T |
| 284 | teq r9,#148 |
| 285 | |
| 286 | ldr r12,[sp,#16+0] @ c.lo |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 287 | #if __ARM_ARCH__>=7 |
| 288 | it eq @ Thumb2 thing, sanity check in ARM |
| 289 | #endif |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 290 | orreq r14,r14,#1 |
| 291 | @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39)) |
| 292 | @ LO lo>>28^hi<<4 ^ hi>>2^lo<<30 ^ hi>>7^lo<<25 |
| 293 | @ HI hi>>28^lo<<4 ^ lo>>2^hi<<30 ^ lo>>7^hi<<25 |
| 294 | mov r9,r5,lsr#28 |
| 295 | mov r10,r6,lsr#28 |
| 296 | eor r9,r9,r6,lsl#4 |
| 297 | eor r10,r10,r5,lsl#4 |
| 298 | eor r9,r9,r6,lsr#2 |
| 299 | eor r10,r10,r5,lsr#2 |
| 300 | eor r9,r9,r5,lsl#30 |
| 301 | eor r10,r10,r6,lsl#30 |
| 302 | eor r9,r9,r6,lsr#7 |
| 303 | eor r10,r10,r5,lsr#7 |
| 304 | eor r9,r9,r5,lsl#25 |
| 305 | eor r10,r10,r6,lsl#25 @ Sigma0(a) |
| 306 | adds r3,r3,r9 |
| 307 | and r9,r5,r11 |
| 308 | adc r4,r4,r10 @ T += Sigma0(a) |
| 309 | |
| 310 | ldr r10,[sp,#8+4] @ b.hi |
| 311 | orr r5,r5,r11 |
| 312 | ldr r11,[sp,#16+4] @ c.hi |
| 313 | and r5,r5,r12 |
| 314 | and r12,r6,r10 |
| 315 | orr r6,r6,r10 |
| 316 | orr r5,r5,r9 @ Maj(a,b,c).lo |
| 317 | and r6,r6,r11 |
| 318 | adds r5,r5,r3 |
| 319 | orr r6,r6,r12 @ Maj(a,b,c).hi |
| 320 | sub sp,sp,#8 |
| 321 | adc r6,r6,r4 @ h += T |
| 322 | tst r14,#1 |
| 323 | add r14,r14,#8 |
| 324 | tst r14,#1 |
| 325 | beq .L00_15 |
| 326 | ldr r9,[sp,#184+0] |
| 327 | ldr r10,[sp,#184+4] |
| 328 | bic r14,r14,#1 |
| 329 | .L16_79: |
| 330 | @ sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7)) |
| 331 | @ LO lo>>1^hi<<31 ^ lo>>8^hi<<24 ^ lo>>7^hi<<25 |
| 332 | @ HI hi>>1^lo<<31 ^ hi>>8^lo<<24 ^ hi>>7 |
| 333 | mov r3,r9,lsr#1 |
| 334 | ldr r11,[sp,#80+0] |
| 335 | mov r4,r10,lsr#1 |
| 336 | ldr r12,[sp,#80+4] |
| 337 | eor r3,r3,r10,lsl#31 |
| 338 | eor r4,r4,r9,lsl#31 |
| 339 | eor r3,r3,r9,lsr#8 |
| 340 | eor r4,r4,r10,lsr#8 |
| 341 | eor r3,r3,r10,lsl#24 |
| 342 | eor r4,r4,r9,lsl#24 |
| 343 | eor r3,r3,r9,lsr#7 |
| 344 | eor r4,r4,r10,lsr#7 |
| 345 | eor r3,r3,r10,lsl#25 |
| 346 | |
| 347 | @ sigma1(x) (ROTR((x),19) ^ ROTR((x),61) ^ ((x)>>6)) |
| 348 | @ LO lo>>19^hi<<13 ^ hi>>29^lo<<3 ^ lo>>6^hi<<26 |
| 349 | @ HI hi>>19^lo<<13 ^ lo>>29^hi<<3 ^ hi>>6 |
| 350 | mov r9,r11,lsr#19 |
| 351 | mov r10,r12,lsr#19 |
| 352 | eor r9,r9,r12,lsl#13 |
| 353 | eor r10,r10,r11,lsl#13 |
| 354 | eor r9,r9,r12,lsr#29 |
| 355 | eor r10,r10,r11,lsr#29 |
| 356 | eor r9,r9,r11,lsl#3 |
| 357 | eor r10,r10,r12,lsl#3 |
| 358 | eor r9,r9,r11,lsr#6 |
| 359 | eor r10,r10,r12,lsr#6 |
| 360 | ldr r11,[sp,#120+0] |
| 361 | eor r9,r9,r12,lsl#26 |
| 362 | |
| 363 | ldr r12,[sp,#120+4] |
| 364 | adds r3,r3,r9 |
| 365 | ldr r9,[sp,#192+0] |
| 366 | adc r4,r4,r10 |
| 367 | |
| 368 | ldr r10,[sp,#192+4] |
| 369 | adds r3,r3,r11 |
| 370 | adc r4,r4,r12 |
| 371 | adds r3,r3,r9 |
| 372 | adc r4,r4,r10 |
| 373 | @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41)) |
| 374 | @ LO lo>>14^hi<<18 ^ lo>>18^hi<<14 ^ hi>>9^lo<<23 |
| 375 | @ HI hi>>14^lo<<18 ^ hi>>18^lo<<14 ^ lo>>9^hi<<23 |
| 376 | mov r9,r7,lsr#14 |
| 377 | str r3,[sp,#64+0] |
| 378 | mov r10,r8,lsr#14 |
| 379 | str r4,[sp,#64+4] |
| 380 | eor r9,r9,r8,lsl#18 |
| 381 | ldr r11,[sp,#56+0] @ h.lo |
| 382 | eor r10,r10,r7,lsl#18 |
| 383 | ldr r12,[sp,#56+4] @ h.hi |
| 384 | eor r9,r9,r7,lsr#18 |
| 385 | eor r10,r10,r8,lsr#18 |
| 386 | eor r9,r9,r8,lsl#14 |
| 387 | eor r10,r10,r7,lsl#14 |
| 388 | eor r9,r9,r8,lsr#9 |
| 389 | eor r10,r10,r7,lsr#9 |
| 390 | eor r9,r9,r7,lsl#23 |
| 391 | eor r10,r10,r8,lsl#23 @ Sigma1(e) |
| 392 | adds r3,r3,r9 |
| 393 | ldr r9,[sp,#40+0] @ f.lo |
| 394 | adc r4,r4,r10 @ T += Sigma1(e) |
| 395 | ldr r10,[sp,#40+4] @ f.hi |
| 396 | adds r3,r3,r11 |
| 397 | ldr r11,[sp,#48+0] @ g.lo |
| 398 | adc r4,r4,r12 @ T += h |
| 399 | ldr r12,[sp,#48+4] @ g.hi |
| 400 | |
| 401 | eor r9,r9,r11 |
| 402 | str r7,[sp,#32+0] |
| 403 | eor r10,r10,r12 |
| 404 | str r8,[sp,#32+4] |
| 405 | and r9,r9,r7 |
| 406 | str r5,[sp,#0+0] |
| 407 | and r10,r10,r8 |
| 408 | str r6,[sp,#0+4] |
| 409 | eor r9,r9,r11 |
| 410 | ldr r11,[r14,#LO] @ K[i].lo |
| 411 | eor r10,r10,r12 @ Ch(e,f,g) |
| 412 | ldr r12,[r14,#HI] @ K[i].hi |
| 413 | |
| 414 | adds r3,r3,r9 |
| 415 | ldr r7,[sp,#24+0] @ d.lo |
| 416 | adc r4,r4,r10 @ T += Ch(e,f,g) |
| 417 | ldr r8,[sp,#24+4] @ d.hi |
| 418 | adds r3,r3,r11 |
| 419 | and r9,r11,#0xff |
| 420 | adc r4,r4,r12 @ T += K[i] |
| 421 | adds r7,r7,r3 |
| 422 | ldr r11,[sp,#8+0] @ b.lo |
| 423 | adc r8,r8,r4 @ d += T |
| 424 | teq r9,#23 |
| 425 | |
| 426 | ldr r12,[sp,#16+0] @ c.lo |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 427 | #if __ARM_ARCH__>=7 |
| 428 | it eq @ Thumb2 thing, sanity check in ARM |
| 429 | #endif |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 430 | orreq r14,r14,#1 |
| 431 | @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39)) |
| 432 | @ LO lo>>28^hi<<4 ^ hi>>2^lo<<30 ^ hi>>7^lo<<25 |
| 433 | @ HI hi>>28^lo<<4 ^ lo>>2^hi<<30 ^ lo>>7^hi<<25 |
| 434 | mov r9,r5,lsr#28 |
| 435 | mov r10,r6,lsr#28 |
| 436 | eor r9,r9,r6,lsl#4 |
| 437 | eor r10,r10,r5,lsl#4 |
| 438 | eor r9,r9,r6,lsr#2 |
| 439 | eor r10,r10,r5,lsr#2 |
| 440 | eor r9,r9,r5,lsl#30 |
| 441 | eor r10,r10,r6,lsl#30 |
| 442 | eor r9,r9,r6,lsr#7 |
| 443 | eor r10,r10,r5,lsr#7 |
| 444 | eor r9,r9,r5,lsl#25 |
| 445 | eor r10,r10,r6,lsl#25 @ Sigma0(a) |
| 446 | adds r3,r3,r9 |
| 447 | and r9,r5,r11 |
| 448 | adc r4,r4,r10 @ T += Sigma0(a) |
| 449 | |
| 450 | ldr r10,[sp,#8+4] @ b.hi |
| 451 | orr r5,r5,r11 |
| 452 | ldr r11,[sp,#16+4] @ c.hi |
| 453 | and r5,r5,r12 |
| 454 | and r12,r6,r10 |
| 455 | orr r6,r6,r10 |
| 456 | orr r5,r5,r9 @ Maj(a,b,c).lo |
| 457 | and r6,r6,r11 |
| 458 | adds r5,r5,r3 |
| 459 | orr r6,r6,r12 @ Maj(a,b,c).hi |
| 460 | sub sp,sp,#8 |
| 461 | adc r6,r6,r4 @ h += T |
| 462 | tst r14,#1 |
| 463 | add r14,r14,#8 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 464 | #if __ARM_ARCH__>=7 |
| 465 | ittt eq @ Thumb2 thing, sanity check in ARM |
| 466 | #endif |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 467 | ldreq r9,[sp,#184+0] |
| 468 | ldreq r10,[sp,#184+4] |
| 469 | beq .L16_79 |
| 470 | bic r14,r14,#1 |
| 471 | |
| 472 | ldr r3,[sp,#8+0] |
| 473 | ldr r4,[sp,#8+4] |
| 474 | ldr r9, [r0,#0+LO] |
| 475 | ldr r10, [r0,#0+HI] |
| 476 | ldr r11, [r0,#8+LO] |
| 477 | ldr r12, [r0,#8+HI] |
| 478 | adds r9,r5,r9 |
| 479 | str r9, [r0,#0+LO] |
| 480 | adc r10,r6,r10 |
| 481 | str r10, [r0,#0+HI] |
| 482 | adds r11,r3,r11 |
| 483 | str r11, [r0,#8+LO] |
| 484 | adc r12,r4,r12 |
| 485 | str r12, [r0,#8+HI] |
| 486 | |
| 487 | ldr r5,[sp,#16+0] |
| 488 | ldr r6,[sp,#16+4] |
| 489 | ldr r3,[sp,#24+0] |
| 490 | ldr r4,[sp,#24+4] |
| 491 | ldr r9, [r0,#16+LO] |
| 492 | ldr r10, [r0,#16+HI] |
| 493 | ldr r11, [r0,#24+LO] |
| 494 | ldr r12, [r0,#24+HI] |
| 495 | adds r9,r5,r9 |
| 496 | str r9, [r0,#16+LO] |
| 497 | adc r10,r6,r10 |
| 498 | str r10, [r0,#16+HI] |
| 499 | adds r11,r3,r11 |
| 500 | str r11, [r0,#24+LO] |
| 501 | adc r12,r4,r12 |
| 502 | str r12, [r0,#24+HI] |
| 503 | |
| 504 | ldr r3,[sp,#40+0] |
| 505 | ldr r4,[sp,#40+4] |
| 506 | ldr r9, [r0,#32+LO] |
| 507 | ldr r10, [r0,#32+HI] |
| 508 | ldr r11, [r0,#40+LO] |
| 509 | ldr r12, [r0,#40+HI] |
| 510 | adds r7,r7,r9 |
| 511 | str r7,[r0,#32+LO] |
| 512 | adc r8,r8,r10 |
| 513 | str r8,[r0,#32+HI] |
| 514 | adds r11,r3,r11 |
| 515 | str r11, [r0,#40+LO] |
| 516 | adc r12,r4,r12 |
| 517 | str r12, [r0,#40+HI] |
| 518 | |
| 519 | ldr r5,[sp,#48+0] |
| 520 | ldr r6,[sp,#48+4] |
| 521 | ldr r3,[sp,#56+0] |
| 522 | ldr r4,[sp,#56+4] |
| 523 | ldr r9, [r0,#48+LO] |
| 524 | ldr r10, [r0,#48+HI] |
| 525 | ldr r11, [r0,#56+LO] |
| 526 | ldr r12, [r0,#56+HI] |
| 527 | adds r9,r5,r9 |
| 528 | str r9, [r0,#48+LO] |
| 529 | adc r10,r6,r10 |
| 530 | str r10, [r0,#48+HI] |
| 531 | adds r11,r3,r11 |
| 532 | str r11, [r0,#56+LO] |
| 533 | adc r12,r4,r12 |
| 534 | str r12, [r0,#56+HI] |
| 535 | |
| 536 | add sp,sp,#640 |
| 537 | sub r14,r14,#640 |
| 538 | |
| 539 | teq r1,r2 |
| 540 | bne .Loop |
| 541 | |
| 542 | add sp,sp,#8*9 @ destroy frame |
| 543 | #if __ARM_ARCH__>=5 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 544 | ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,pc} |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 545 | #else |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 546 | ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 547 | tst lr,#1 |
| 548 | moveq pc,lr @ be binary compatible with V4, yet |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 549 | .word 0xe12fff1e @ interoperable with Thumb ISA:-) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 550 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 551 | .size sha512_block_data_order,.-sha512_block_data_order |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 552 | #if __ARM_MAX_ARCH__>=7 |
| 553 | .arch armv7-a |
| 554 | .fpu neon |
| 555 | |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 556 | .globl sha512_block_data_order_neon |
David Benjamin | 4969cc9 | 2016-04-22 15:02:23 -0400 | [diff] [blame] | 557 | .hidden sha512_block_data_order_neon |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 558 | .type sha512_block_data_order_neon,%function |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 559 | .align 4 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 560 | sha512_block_data_order_neon: |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 561 | .LNEON: |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 562 | dmb @ errata #451034 on early Cortex A8 |
| 563 | add r2,r1,r2,lsl#7 @ len to point at the end of inp |
| 564 | adr r3,K512 |
| 565 | VFP_ABI_PUSH |
| 566 | vldmia r0,{d16,d17,d18,d19,d20,d21,d22,d23} @ load context |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 567 | .Loop_neon: |
| 568 | vshr.u64 d24,d20,#14 @ 0 |
| 569 | #if 0<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 570 | vld1.64 {d0},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 571 | #endif |
| 572 | vshr.u64 d25,d20,#18 |
| 573 | #if 0>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 574 | vadd.i64 d16,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 575 | #endif |
| 576 | vshr.u64 d26,d20,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 577 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 578 | vsli.64 d24,d20,#50 |
| 579 | vsli.64 d25,d20,#46 |
| 580 | vmov d29,d20 |
| 581 | vsli.64 d26,d20,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 582 | #if 0<16 && defined(__ARMEL__) |
| 583 | vrev64.8 d0,d0 |
| 584 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 585 | veor d25,d24 |
| 586 | vbsl d29,d21,d22 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 587 | vshr.u64 d24,d16,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 588 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 589 | vadd.i64 d27,d29,d23 |
| 590 | vshr.u64 d25,d16,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 591 | vsli.64 d24,d16,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 592 | vadd.i64 d27,d26 |
| 593 | vshr.u64 d26,d16,#39 |
| 594 | vadd.i64 d28,d0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 595 | vsli.64 d25,d16,#30 |
| 596 | veor d30,d16,d17 |
| 597 | vsli.64 d26,d16,#25 |
| 598 | veor d23,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 599 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 600 | vbsl d30,d18,d17 @ Maj(a,b,c) |
| 601 | veor d23,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 602 | vadd.i64 d19,d27 |
| 603 | vadd.i64 d30,d27 |
| 604 | @ vadd.i64 d23,d30 |
| 605 | vshr.u64 d24,d19,#14 @ 1 |
| 606 | #if 1<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 607 | vld1.64 {d1},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 608 | #endif |
| 609 | vshr.u64 d25,d19,#18 |
| 610 | #if 1>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 611 | vadd.i64 d23,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 612 | #endif |
| 613 | vshr.u64 d26,d19,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 614 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 615 | vsli.64 d24,d19,#50 |
| 616 | vsli.64 d25,d19,#46 |
| 617 | vmov d29,d19 |
| 618 | vsli.64 d26,d19,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 619 | #if 1<16 && defined(__ARMEL__) |
| 620 | vrev64.8 d1,d1 |
| 621 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 622 | veor d25,d24 |
| 623 | vbsl d29,d20,d21 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 624 | vshr.u64 d24,d23,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 625 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 626 | vadd.i64 d27,d29,d22 |
| 627 | vshr.u64 d25,d23,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 628 | vsli.64 d24,d23,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 629 | vadd.i64 d27,d26 |
| 630 | vshr.u64 d26,d23,#39 |
| 631 | vadd.i64 d28,d1 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 632 | vsli.64 d25,d23,#30 |
| 633 | veor d30,d23,d16 |
| 634 | vsli.64 d26,d23,#25 |
| 635 | veor d22,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 636 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 637 | vbsl d30,d17,d16 @ Maj(a,b,c) |
| 638 | veor d22,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 639 | vadd.i64 d18,d27 |
| 640 | vadd.i64 d30,d27 |
| 641 | @ vadd.i64 d22,d30 |
| 642 | vshr.u64 d24,d18,#14 @ 2 |
| 643 | #if 2<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 644 | vld1.64 {d2},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 645 | #endif |
| 646 | vshr.u64 d25,d18,#18 |
| 647 | #if 2>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 648 | vadd.i64 d22,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 649 | #endif |
| 650 | vshr.u64 d26,d18,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 651 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 652 | vsli.64 d24,d18,#50 |
| 653 | vsli.64 d25,d18,#46 |
| 654 | vmov d29,d18 |
| 655 | vsli.64 d26,d18,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 656 | #if 2<16 && defined(__ARMEL__) |
| 657 | vrev64.8 d2,d2 |
| 658 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 659 | veor d25,d24 |
| 660 | vbsl d29,d19,d20 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 661 | vshr.u64 d24,d22,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 662 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 663 | vadd.i64 d27,d29,d21 |
| 664 | vshr.u64 d25,d22,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 665 | vsli.64 d24,d22,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 666 | vadd.i64 d27,d26 |
| 667 | vshr.u64 d26,d22,#39 |
| 668 | vadd.i64 d28,d2 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 669 | vsli.64 d25,d22,#30 |
| 670 | veor d30,d22,d23 |
| 671 | vsli.64 d26,d22,#25 |
| 672 | veor d21,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 673 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 674 | vbsl d30,d16,d23 @ Maj(a,b,c) |
| 675 | veor d21,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 676 | vadd.i64 d17,d27 |
| 677 | vadd.i64 d30,d27 |
| 678 | @ vadd.i64 d21,d30 |
| 679 | vshr.u64 d24,d17,#14 @ 3 |
| 680 | #if 3<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 681 | vld1.64 {d3},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 682 | #endif |
| 683 | vshr.u64 d25,d17,#18 |
| 684 | #if 3>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 685 | vadd.i64 d21,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 686 | #endif |
| 687 | vshr.u64 d26,d17,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 688 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 689 | vsli.64 d24,d17,#50 |
| 690 | vsli.64 d25,d17,#46 |
| 691 | vmov d29,d17 |
| 692 | vsli.64 d26,d17,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 693 | #if 3<16 && defined(__ARMEL__) |
| 694 | vrev64.8 d3,d3 |
| 695 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 696 | veor d25,d24 |
| 697 | vbsl d29,d18,d19 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 698 | vshr.u64 d24,d21,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 699 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 700 | vadd.i64 d27,d29,d20 |
| 701 | vshr.u64 d25,d21,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 702 | vsli.64 d24,d21,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 703 | vadd.i64 d27,d26 |
| 704 | vshr.u64 d26,d21,#39 |
| 705 | vadd.i64 d28,d3 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 706 | vsli.64 d25,d21,#30 |
| 707 | veor d30,d21,d22 |
| 708 | vsli.64 d26,d21,#25 |
| 709 | veor d20,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 710 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 711 | vbsl d30,d23,d22 @ Maj(a,b,c) |
| 712 | veor d20,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 713 | vadd.i64 d16,d27 |
| 714 | vadd.i64 d30,d27 |
| 715 | @ vadd.i64 d20,d30 |
| 716 | vshr.u64 d24,d16,#14 @ 4 |
| 717 | #if 4<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 718 | vld1.64 {d4},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 719 | #endif |
| 720 | vshr.u64 d25,d16,#18 |
| 721 | #if 4>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 722 | vadd.i64 d20,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 723 | #endif |
| 724 | vshr.u64 d26,d16,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 725 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 726 | vsli.64 d24,d16,#50 |
| 727 | vsli.64 d25,d16,#46 |
| 728 | vmov d29,d16 |
| 729 | vsli.64 d26,d16,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 730 | #if 4<16 && defined(__ARMEL__) |
| 731 | vrev64.8 d4,d4 |
| 732 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 733 | veor d25,d24 |
| 734 | vbsl d29,d17,d18 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 735 | vshr.u64 d24,d20,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 736 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 737 | vadd.i64 d27,d29,d19 |
| 738 | vshr.u64 d25,d20,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 739 | vsli.64 d24,d20,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 740 | vadd.i64 d27,d26 |
| 741 | vshr.u64 d26,d20,#39 |
| 742 | vadd.i64 d28,d4 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 743 | vsli.64 d25,d20,#30 |
| 744 | veor d30,d20,d21 |
| 745 | vsli.64 d26,d20,#25 |
| 746 | veor d19,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 747 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 748 | vbsl d30,d22,d21 @ Maj(a,b,c) |
| 749 | veor d19,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 750 | vadd.i64 d23,d27 |
| 751 | vadd.i64 d30,d27 |
| 752 | @ vadd.i64 d19,d30 |
| 753 | vshr.u64 d24,d23,#14 @ 5 |
| 754 | #if 5<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 755 | vld1.64 {d5},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 756 | #endif |
| 757 | vshr.u64 d25,d23,#18 |
| 758 | #if 5>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 759 | vadd.i64 d19,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 760 | #endif |
| 761 | vshr.u64 d26,d23,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 762 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 763 | vsli.64 d24,d23,#50 |
| 764 | vsli.64 d25,d23,#46 |
| 765 | vmov d29,d23 |
| 766 | vsli.64 d26,d23,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 767 | #if 5<16 && defined(__ARMEL__) |
| 768 | vrev64.8 d5,d5 |
| 769 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 770 | veor d25,d24 |
| 771 | vbsl d29,d16,d17 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 772 | vshr.u64 d24,d19,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 773 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 774 | vadd.i64 d27,d29,d18 |
| 775 | vshr.u64 d25,d19,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 776 | vsli.64 d24,d19,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 777 | vadd.i64 d27,d26 |
| 778 | vshr.u64 d26,d19,#39 |
| 779 | vadd.i64 d28,d5 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 780 | vsli.64 d25,d19,#30 |
| 781 | veor d30,d19,d20 |
| 782 | vsli.64 d26,d19,#25 |
| 783 | veor d18,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 784 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 785 | vbsl d30,d21,d20 @ Maj(a,b,c) |
| 786 | veor d18,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 787 | vadd.i64 d22,d27 |
| 788 | vadd.i64 d30,d27 |
| 789 | @ vadd.i64 d18,d30 |
| 790 | vshr.u64 d24,d22,#14 @ 6 |
| 791 | #if 6<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 792 | vld1.64 {d6},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 793 | #endif |
| 794 | vshr.u64 d25,d22,#18 |
| 795 | #if 6>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 796 | vadd.i64 d18,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 797 | #endif |
| 798 | vshr.u64 d26,d22,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 799 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 800 | vsli.64 d24,d22,#50 |
| 801 | vsli.64 d25,d22,#46 |
| 802 | vmov d29,d22 |
| 803 | vsli.64 d26,d22,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 804 | #if 6<16 && defined(__ARMEL__) |
| 805 | vrev64.8 d6,d6 |
| 806 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 807 | veor d25,d24 |
| 808 | vbsl d29,d23,d16 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 809 | vshr.u64 d24,d18,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 810 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 811 | vadd.i64 d27,d29,d17 |
| 812 | vshr.u64 d25,d18,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 813 | vsli.64 d24,d18,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 814 | vadd.i64 d27,d26 |
| 815 | vshr.u64 d26,d18,#39 |
| 816 | vadd.i64 d28,d6 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 817 | vsli.64 d25,d18,#30 |
| 818 | veor d30,d18,d19 |
| 819 | vsli.64 d26,d18,#25 |
| 820 | veor d17,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 821 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 822 | vbsl d30,d20,d19 @ Maj(a,b,c) |
| 823 | veor d17,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 824 | vadd.i64 d21,d27 |
| 825 | vadd.i64 d30,d27 |
| 826 | @ vadd.i64 d17,d30 |
| 827 | vshr.u64 d24,d21,#14 @ 7 |
| 828 | #if 7<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 829 | vld1.64 {d7},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 830 | #endif |
| 831 | vshr.u64 d25,d21,#18 |
| 832 | #if 7>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 833 | vadd.i64 d17,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 834 | #endif |
| 835 | vshr.u64 d26,d21,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 836 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 837 | vsli.64 d24,d21,#50 |
| 838 | vsli.64 d25,d21,#46 |
| 839 | vmov d29,d21 |
| 840 | vsli.64 d26,d21,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 841 | #if 7<16 && defined(__ARMEL__) |
| 842 | vrev64.8 d7,d7 |
| 843 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 844 | veor d25,d24 |
| 845 | vbsl d29,d22,d23 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 846 | vshr.u64 d24,d17,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 847 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 848 | vadd.i64 d27,d29,d16 |
| 849 | vshr.u64 d25,d17,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 850 | vsli.64 d24,d17,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 851 | vadd.i64 d27,d26 |
| 852 | vshr.u64 d26,d17,#39 |
| 853 | vadd.i64 d28,d7 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 854 | vsli.64 d25,d17,#30 |
| 855 | veor d30,d17,d18 |
| 856 | vsli.64 d26,d17,#25 |
| 857 | veor d16,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 858 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 859 | vbsl d30,d19,d18 @ Maj(a,b,c) |
| 860 | veor d16,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 861 | vadd.i64 d20,d27 |
| 862 | vadd.i64 d30,d27 |
| 863 | @ vadd.i64 d16,d30 |
| 864 | vshr.u64 d24,d20,#14 @ 8 |
| 865 | #if 8<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 866 | vld1.64 {d8},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 867 | #endif |
| 868 | vshr.u64 d25,d20,#18 |
| 869 | #if 8>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 870 | vadd.i64 d16,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 871 | #endif |
| 872 | vshr.u64 d26,d20,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 873 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 874 | vsli.64 d24,d20,#50 |
| 875 | vsli.64 d25,d20,#46 |
| 876 | vmov d29,d20 |
| 877 | vsli.64 d26,d20,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 878 | #if 8<16 && defined(__ARMEL__) |
| 879 | vrev64.8 d8,d8 |
| 880 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 881 | veor d25,d24 |
| 882 | vbsl d29,d21,d22 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 883 | vshr.u64 d24,d16,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 884 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 885 | vadd.i64 d27,d29,d23 |
| 886 | vshr.u64 d25,d16,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 887 | vsli.64 d24,d16,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 888 | vadd.i64 d27,d26 |
| 889 | vshr.u64 d26,d16,#39 |
| 890 | vadd.i64 d28,d8 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 891 | vsli.64 d25,d16,#30 |
| 892 | veor d30,d16,d17 |
| 893 | vsli.64 d26,d16,#25 |
| 894 | veor d23,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 895 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 896 | vbsl d30,d18,d17 @ Maj(a,b,c) |
| 897 | veor d23,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 898 | vadd.i64 d19,d27 |
| 899 | vadd.i64 d30,d27 |
| 900 | @ vadd.i64 d23,d30 |
| 901 | vshr.u64 d24,d19,#14 @ 9 |
| 902 | #if 9<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 903 | vld1.64 {d9},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 904 | #endif |
| 905 | vshr.u64 d25,d19,#18 |
| 906 | #if 9>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 907 | vadd.i64 d23,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 908 | #endif |
| 909 | vshr.u64 d26,d19,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 910 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 911 | vsli.64 d24,d19,#50 |
| 912 | vsli.64 d25,d19,#46 |
| 913 | vmov d29,d19 |
| 914 | vsli.64 d26,d19,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 915 | #if 9<16 && defined(__ARMEL__) |
| 916 | vrev64.8 d9,d9 |
| 917 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 918 | veor d25,d24 |
| 919 | vbsl d29,d20,d21 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 920 | vshr.u64 d24,d23,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 921 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 922 | vadd.i64 d27,d29,d22 |
| 923 | vshr.u64 d25,d23,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 924 | vsli.64 d24,d23,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 925 | vadd.i64 d27,d26 |
| 926 | vshr.u64 d26,d23,#39 |
| 927 | vadd.i64 d28,d9 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 928 | vsli.64 d25,d23,#30 |
| 929 | veor d30,d23,d16 |
| 930 | vsli.64 d26,d23,#25 |
| 931 | veor d22,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 932 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 933 | vbsl d30,d17,d16 @ Maj(a,b,c) |
| 934 | veor d22,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 935 | vadd.i64 d18,d27 |
| 936 | vadd.i64 d30,d27 |
| 937 | @ vadd.i64 d22,d30 |
| 938 | vshr.u64 d24,d18,#14 @ 10 |
| 939 | #if 10<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 940 | vld1.64 {d10},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 941 | #endif |
| 942 | vshr.u64 d25,d18,#18 |
| 943 | #if 10>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 944 | vadd.i64 d22,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 945 | #endif |
| 946 | vshr.u64 d26,d18,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 947 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 948 | vsli.64 d24,d18,#50 |
| 949 | vsli.64 d25,d18,#46 |
| 950 | vmov d29,d18 |
| 951 | vsli.64 d26,d18,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 952 | #if 10<16 && defined(__ARMEL__) |
| 953 | vrev64.8 d10,d10 |
| 954 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 955 | veor d25,d24 |
| 956 | vbsl d29,d19,d20 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 957 | vshr.u64 d24,d22,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 958 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 959 | vadd.i64 d27,d29,d21 |
| 960 | vshr.u64 d25,d22,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 961 | vsli.64 d24,d22,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 962 | vadd.i64 d27,d26 |
| 963 | vshr.u64 d26,d22,#39 |
| 964 | vadd.i64 d28,d10 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 965 | vsli.64 d25,d22,#30 |
| 966 | veor d30,d22,d23 |
| 967 | vsli.64 d26,d22,#25 |
| 968 | veor d21,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 969 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 970 | vbsl d30,d16,d23 @ Maj(a,b,c) |
| 971 | veor d21,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 972 | vadd.i64 d17,d27 |
| 973 | vadd.i64 d30,d27 |
| 974 | @ vadd.i64 d21,d30 |
| 975 | vshr.u64 d24,d17,#14 @ 11 |
| 976 | #if 11<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 977 | vld1.64 {d11},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 978 | #endif |
| 979 | vshr.u64 d25,d17,#18 |
| 980 | #if 11>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 981 | vadd.i64 d21,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 982 | #endif |
| 983 | vshr.u64 d26,d17,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 984 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 985 | vsli.64 d24,d17,#50 |
| 986 | vsli.64 d25,d17,#46 |
| 987 | vmov d29,d17 |
| 988 | vsli.64 d26,d17,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 989 | #if 11<16 && defined(__ARMEL__) |
| 990 | vrev64.8 d11,d11 |
| 991 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 992 | veor d25,d24 |
| 993 | vbsl d29,d18,d19 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 994 | vshr.u64 d24,d21,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 995 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 996 | vadd.i64 d27,d29,d20 |
| 997 | vshr.u64 d25,d21,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 998 | vsli.64 d24,d21,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 999 | vadd.i64 d27,d26 |
| 1000 | vshr.u64 d26,d21,#39 |
| 1001 | vadd.i64 d28,d11 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1002 | vsli.64 d25,d21,#30 |
| 1003 | veor d30,d21,d22 |
| 1004 | vsli.64 d26,d21,#25 |
| 1005 | veor d20,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1006 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1007 | vbsl d30,d23,d22 @ Maj(a,b,c) |
| 1008 | veor d20,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1009 | vadd.i64 d16,d27 |
| 1010 | vadd.i64 d30,d27 |
| 1011 | @ vadd.i64 d20,d30 |
| 1012 | vshr.u64 d24,d16,#14 @ 12 |
| 1013 | #if 12<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1014 | vld1.64 {d12},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1015 | #endif |
| 1016 | vshr.u64 d25,d16,#18 |
| 1017 | #if 12>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1018 | vadd.i64 d20,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1019 | #endif |
| 1020 | vshr.u64 d26,d16,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1021 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1022 | vsli.64 d24,d16,#50 |
| 1023 | vsli.64 d25,d16,#46 |
| 1024 | vmov d29,d16 |
| 1025 | vsli.64 d26,d16,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1026 | #if 12<16 && defined(__ARMEL__) |
| 1027 | vrev64.8 d12,d12 |
| 1028 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1029 | veor d25,d24 |
| 1030 | vbsl d29,d17,d18 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1031 | vshr.u64 d24,d20,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1032 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1033 | vadd.i64 d27,d29,d19 |
| 1034 | vshr.u64 d25,d20,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1035 | vsli.64 d24,d20,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1036 | vadd.i64 d27,d26 |
| 1037 | vshr.u64 d26,d20,#39 |
| 1038 | vadd.i64 d28,d12 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1039 | vsli.64 d25,d20,#30 |
| 1040 | veor d30,d20,d21 |
| 1041 | vsli.64 d26,d20,#25 |
| 1042 | veor d19,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1043 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1044 | vbsl d30,d22,d21 @ Maj(a,b,c) |
| 1045 | veor d19,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1046 | vadd.i64 d23,d27 |
| 1047 | vadd.i64 d30,d27 |
| 1048 | @ vadd.i64 d19,d30 |
| 1049 | vshr.u64 d24,d23,#14 @ 13 |
| 1050 | #if 13<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1051 | vld1.64 {d13},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1052 | #endif |
| 1053 | vshr.u64 d25,d23,#18 |
| 1054 | #if 13>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1055 | vadd.i64 d19,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1056 | #endif |
| 1057 | vshr.u64 d26,d23,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1058 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1059 | vsli.64 d24,d23,#50 |
| 1060 | vsli.64 d25,d23,#46 |
| 1061 | vmov d29,d23 |
| 1062 | vsli.64 d26,d23,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1063 | #if 13<16 && defined(__ARMEL__) |
| 1064 | vrev64.8 d13,d13 |
| 1065 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1066 | veor d25,d24 |
| 1067 | vbsl d29,d16,d17 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1068 | vshr.u64 d24,d19,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1069 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1070 | vadd.i64 d27,d29,d18 |
| 1071 | vshr.u64 d25,d19,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1072 | vsli.64 d24,d19,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1073 | vadd.i64 d27,d26 |
| 1074 | vshr.u64 d26,d19,#39 |
| 1075 | vadd.i64 d28,d13 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1076 | vsli.64 d25,d19,#30 |
| 1077 | veor d30,d19,d20 |
| 1078 | vsli.64 d26,d19,#25 |
| 1079 | veor d18,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1080 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1081 | vbsl d30,d21,d20 @ Maj(a,b,c) |
| 1082 | veor d18,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1083 | vadd.i64 d22,d27 |
| 1084 | vadd.i64 d30,d27 |
| 1085 | @ vadd.i64 d18,d30 |
| 1086 | vshr.u64 d24,d22,#14 @ 14 |
| 1087 | #if 14<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1088 | vld1.64 {d14},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1089 | #endif |
| 1090 | vshr.u64 d25,d22,#18 |
| 1091 | #if 14>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1092 | vadd.i64 d18,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1093 | #endif |
| 1094 | vshr.u64 d26,d22,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1095 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1096 | vsli.64 d24,d22,#50 |
| 1097 | vsli.64 d25,d22,#46 |
| 1098 | vmov d29,d22 |
| 1099 | vsli.64 d26,d22,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1100 | #if 14<16 && defined(__ARMEL__) |
| 1101 | vrev64.8 d14,d14 |
| 1102 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1103 | veor d25,d24 |
| 1104 | vbsl d29,d23,d16 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1105 | vshr.u64 d24,d18,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1106 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1107 | vadd.i64 d27,d29,d17 |
| 1108 | vshr.u64 d25,d18,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1109 | vsli.64 d24,d18,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1110 | vadd.i64 d27,d26 |
| 1111 | vshr.u64 d26,d18,#39 |
| 1112 | vadd.i64 d28,d14 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1113 | vsli.64 d25,d18,#30 |
| 1114 | veor d30,d18,d19 |
| 1115 | vsli.64 d26,d18,#25 |
| 1116 | veor d17,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1117 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1118 | vbsl d30,d20,d19 @ Maj(a,b,c) |
| 1119 | veor d17,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1120 | vadd.i64 d21,d27 |
| 1121 | vadd.i64 d30,d27 |
| 1122 | @ vadd.i64 d17,d30 |
| 1123 | vshr.u64 d24,d21,#14 @ 15 |
| 1124 | #if 15<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1125 | vld1.64 {d15},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1126 | #endif |
| 1127 | vshr.u64 d25,d21,#18 |
| 1128 | #if 15>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1129 | vadd.i64 d17,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1130 | #endif |
| 1131 | vshr.u64 d26,d21,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1132 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1133 | vsli.64 d24,d21,#50 |
| 1134 | vsli.64 d25,d21,#46 |
| 1135 | vmov d29,d21 |
| 1136 | vsli.64 d26,d21,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1137 | #if 15<16 && defined(__ARMEL__) |
| 1138 | vrev64.8 d15,d15 |
| 1139 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1140 | veor d25,d24 |
| 1141 | vbsl d29,d22,d23 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1142 | vshr.u64 d24,d17,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1143 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1144 | vadd.i64 d27,d29,d16 |
| 1145 | vshr.u64 d25,d17,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1146 | vsli.64 d24,d17,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1147 | vadd.i64 d27,d26 |
| 1148 | vshr.u64 d26,d17,#39 |
| 1149 | vadd.i64 d28,d15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1150 | vsli.64 d25,d17,#30 |
| 1151 | veor d30,d17,d18 |
| 1152 | vsli.64 d26,d17,#25 |
| 1153 | veor d16,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1154 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1155 | vbsl d30,d19,d18 @ Maj(a,b,c) |
| 1156 | veor d16,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1157 | vadd.i64 d20,d27 |
| 1158 | vadd.i64 d30,d27 |
| 1159 | @ vadd.i64 d16,d30 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1160 | mov r12,#4 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1161 | .L16_79_neon: |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1162 | subs r12,#1 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1163 | vshr.u64 q12,q7,#19 |
| 1164 | vshr.u64 q13,q7,#61 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1165 | vadd.i64 d16,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1166 | vshr.u64 q15,q7,#6 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1167 | vsli.64 q12,q7,#45 |
| 1168 | vext.8 q14,q0,q1,#8 @ X[i+1] |
| 1169 | vsli.64 q13,q7,#3 |
| 1170 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1171 | vshr.u64 q12,q14,#1 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1172 | veor q15,q13 @ sigma1(X[i+14]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1173 | vshr.u64 q13,q14,#8 |
| 1174 | vadd.i64 q0,q15 |
| 1175 | vshr.u64 q15,q14,#7 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1176 | vsli.64 q12,q14,#63 |
| 1177 | vsli.64 q13,q14,#56 |
| 1178 | vext.8 q14,q4,q5,#8 @ X[i+9] |
| 1179 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1180 | vshr.u64 d24,d20,#14 @ from NEON_00_15 |
| 1181 | vadd.i64 q0,q14 |
| 1182 | vshr.u64 d25,d20,#18 @ from NEON_00_15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1183 | veor q15,q13 @ sigma0(X[i+1]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1184 | vshr.u64 d26,d20,#41 @ from NEON_00_15 |
| 1185 | vadd.i64 q0,q15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1186 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1187 | vsli.64 d24,d20,#50 |
| 1188 | vsli.64 d25,d20,#46 |
| 1189 | vmov d29,d20 |
| 1190 | vsli.64 d26,d20,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1191 | #if 16<16 && defined(__ARMEL__) |
| 1192 | vrev64.8 , |
| 1193 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1194 | veor d25,d24 |
| 1195 | vbsl d29,d21,d22 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1196 | vshr.u64 d24,d16,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1197 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1198 | vadd.i64 d27,d29,d23 |
| 1199 | vshr.u64 d25,d16,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1200 | vsli.64 d24,d16,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1201 | vadd.i64 d27,d26 |
| 1202 | vshr.u64 d26,d16,#39 |
| 1203 | vadd.i64 d28,d0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1204 | vsli.64 d25,d16,#30 |
| 1205 | veor d30,d16,d17 |
| 1206 | vsli.64 d26,d16,#25 |
| 1207 | veor d23,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1208 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1209 | vbsl d30,d18,d17 @ Maj(a,b,c) |
| 1210 | veor d23,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1211 | vadd.i64 d19,d27 |
| 1212 | vadd.i64 d30,d27 |
| 1213 | @ vadd.i64 d23,d30 |
| 1214 | vshr.u64 d24,d19,#14 @ 17 |
| 1215 | #if 17<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1216 | vld1.64 {d1},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1217 | #endif |
| 1218 | vshr.u64 d25,d19,#18 |
| 1219 | #if 17>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1220 | vadd.i64 d23,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1221 | #endif |
| 1222 | vshr.u64 d26,d19,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1223 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1224 | vsli.64 d24,d19,#50 |
| 1225 | vsli.64 d25,d19,#46 |
| 1226 | vmov d29,d19 |
| 1227 | vsli.64 d26,d19,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1228 | #if 17<16 && defined(__ARMEL__) |
| 1229 | vrev64.8 , |
| 1230 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1231 | veor d25,d24 |
| 1232 | vbsl d29,d20,d21 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1233 | vshr.u64 d24,d23,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1234 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1235 | vadd.i64 d27,d29,d22 |
| 1236 | vshr.u64 d25,d23,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1237 | vsli.64 d24,d23,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1238 | vadd.i64 d27,d26 |
| 1239 | vshr.u64 d26,d23,#39 |
| 1240 | vadd.i64 d28,d1 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1241 | vsli.64 d25,d23,#30 |
| 1242 | veor d30,d23,d16 |
| 1243 | vsli.64 d26,d23,#25 |
| 1244 | veor d22,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1245 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1246 | vbsl d30,d17,d16 @ Maj(a,b,c) |
| 1247 | veor d22,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1248 | vadd.i64 d18,d27 |
| 1249 | vadd.i64 d30,d27 |
| 1250 | @ vadd.i64 d22,d30 |
| 1251 | vshr.u64 q12,q0,#19 |
| 1252 | vshr.u64 q13,q0,#61 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1253 | vadd.i64 d22,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1254 | vshr.u64 q15,q0,#6 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1255 | vsli.64 q12,q0,#45 |
| 1256 | vext.8 q14,q1,q2,#8 @ X[i+1] |
| 1257 | vsli.64 q13,q0,#3 |
| 1258 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1259 | vshr.u64 q12,q14,#1 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1260 | veor q15,q13 @ sigma1(X[i+14]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1261 | vshr.u64 q13,q14,#8 |
| 1262 | vadd.i64 q1,q15 |
| 1263 | vshr.u64 q15,q14,#7 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1264 | vsli.64 q12,q14,#63 |
| 1265 | vsli.64 q13,q14,#56 |
| 1266 | vext.8 q14,q5,q6,#8 @ X[i+9] |
| 1267 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1268 | vshr.u64 d24,d18,#14 @ from NEON_00_15 |
| 1269 | vadd.i64 q1,q14 |
| 1270 | vshr.u64 d25,d18,#18 @ from NEON_00_15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1271 | veor q15,q13 @ sigma0(X[i+1]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1272 | vshr.u64 d26,d18,#41 @ from NEON_00_15 |
| 1273 | vadd.i64 q1,q15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1274 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1275 | vsli.64 d24,d18,#50 |
| 1276 | vsli.64 d25,d18,#46 |
| 1277 | vmov d29,d18 |
| 1278 | vsli.64 d26,d18,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1279 | #if 18<16 && defined(__ARMEL__) |
| 1280 | vrev64.8 , |
| 1281 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1282 | veor d25,d24 |
| 1283 | vbsl d29,d19,d20 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1284 | vshr.u64 d24,d22,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1285 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1286 | vadd.i64 d27,d29,d21 |
| 1287 | vshr.u64 d25,d22,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1288 | vsli.64 d24,d22,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1289 | vadd.i64 d27,d26 |
| 1290 | vshr.u64 d26,d22,#39 |
| 1291 | vadd.i64 d28,d2 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1292 | vsli.64 d25,d22,#30 |
| 1293 | veor d30,d22,d23 |
| 1294 | vsli.64 d26,d22,#25 |
| 1295 | veor d21,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1296 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1297 | vbsl d30,d16,d23 @ Maj(a,b,c) |
| 1298 | veor d21,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1299 | vadd.i64 d17,d27 |
| 1300 | vadd.i64 d30,d27 |
| 1301 | @ vadd.i64 d21,d30 |
| 1302 | vshr.u64 d24,d17,#14 @ 19 |
| 1303 | #if 19<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1304 | vld1.64 {d3},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1305 | #endif |
| 1306 | vshr.u64 d25,d17,#18 |
| 1307 | #if 19>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1308 | vadd.i64 d21,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1309 | #endif |
| 1310 | vshr.u64 d26,d17,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1311 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1312 | vsli.64 d24,d17,#50 |
| 1313 | vsli.64 d25,d17,#46 |
| 1314 | vmov d29,d17 |
| 1315 | vsli.64 d26,d17,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1316 | #if 19<16 && defined(__ARMEL__) |
| 1317 | vrev64.8 , |
| 1318 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1319 | veor d25,d24 |
| 1320 | vbsl d29,d18,d19 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1321 | vshr.u64 d24,d21,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1322 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1323 | vadd.i64 d27,d29,d20 |
| 1324 | vshr.u64 d25,d21,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1325 | vsli.64 d24,d21,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1326 | vadd.i64 d27,d26 |
| 1327 | vshr.u64 d26,d21,#39 |
| 1328 | vadd.i64 d28,d3 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1329 | vsli.64 d25,d21,#30 |
| 1330 | veor d30,d21,d22 |
| 1331 | vsli.64 d26,d21,#25 |
| 1332 | veor d20,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1333 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1334 | vbsl d30,d23,d22 @ Maj(a,b,c) |
| 1335 | veor d20,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1336 | vadd.i64 d16,d27 |
| 1337 | vadd.i64 d30,d27 |
| 1338 | @ vadd.i64 d20,d30 |
| 1339 | vshr.u64 q12,q1,#19 |
| 1340 | vshr.u64 q13,q1,#61 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1341 | vadd.i64 d20,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1342 | vshr.u64 q15,q1,#6 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1343 | vsli.64 q12,q1,#45 |
| 1344 | vext.8 q14,q2,q3,#8 @ X[i+1] |
| 1345 | vsli.64 q13,q1,#3 |
| 1346 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1347 | vshr.u64 q12,q14,#1 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1348 | veor q15,q13 @ sigma1(X[i+14]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1349 | vshr.u64 q13,q14,#8 |
| 1350 | vadd.i64 q2,q15 |
| 1351 | vshr.u64 q15,q14,#7 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1352 | vsli.64 q12,q14,#63 |
| 1353 | vsli.64 q13,q14,#56 |
| 1354 | vext.8 q14,q6,q7,#8 @ X[i+9] |
| 1355 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1356 | vshr.u64 d24,d16,#14 @ from NEON_00_15 |
| 1357 | vadd.i64 q2,q14 |
| 1358 | vshr.u64 d25,d16,#18 @ from NEON_00_15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1359 | veor q15,q13 @ sigma0(X[i+1]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1360 | vshr.u64 d26,d16,#41 @ from NEON_00_15 |
| 1361 | vadd.i64 q2,q15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1362 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1363 | vsli.64 d24,d16,#50 |
| 1364 | vsli.64 d25,d16,#46 |
| 1365 | vmov d29,d16 |
| 1366 | vsli.64 d26,d16,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1367 | #if 20<16 && defined(__ARMEL__) |
| 1368 | vrev64.8 , |
| 1369 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1370 | veor d25,d24 |
| 1371 | vbsl d29,d17,d18 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1372 | vshr.u64 d24,d20,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1373 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1374 | vadd.i64 d27,d29,d19 |
| 1375 | vshr.u64 d25,d20,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1376 | vsli.64 d24,d20,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1377 | vadd.i64 d27,d26 |
| 1378 | vshr.u64 d26,d20,#39 |
| 1379 | vadd.i64 d28,d4 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1380 | vsli.64 d25,d20,#30 |
| 1381 | veor d30,d20,d21 |
| 1382 | vsli.64 d26,d20,#25 |
| 1383 | veor d19,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1384 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1385 | vbsl d30,d22,d21 @ Maj(a,b,c) |
| 1386 | veor d19,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1387 | vadd.i64 d23,d27 |
| 1388 | vadd.i64 d30,d27 |
| 1389 | @ vadd.i64 d19,d30 |
| 1390 | vshr.u64 d24,d23,#14 @ 21 |
| 1391 | #if 21<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1392 | vld1.64 {d5},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1393 | #endif |
| 1394 | vshr.u64 d25,d23,#18 |
| 1395 | #if 21>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1396 | vadd.i64 d19,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1397 | #endif |
| 1398 | vshr.u64 d26,d23,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1399 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1400 | vsli.64 d24,d23,#50 |
| 1401 | vsli.64 d25,d23,#46 |
| 1402 | vmov d29,d23 |
| 1403 | vsli.64 d26,d23,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1404 | #if 21<16 && defined(__ARMEL__) |
| 1405 | vrev64.8 , |
| 1406 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1407 | veor d25,d24 |
| 1408 | vbsl d29,d16,d17 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1409 | vshr.u64 d24,d19,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1410 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1411 | vadd.i64 d27,d29,d18 |
| 1412 | vshr.u64 d25,d19,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1413 | vsli.64 d24,d19,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1414 | vadd.i64 d27,d26 |
| 1415 | vshr.u64 d26,d19,#39 |
| 1416 | vadd.i64 d28,d5 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1417 | vsli.64 d25,d19,#30 |
| 1418 | veor d30,d19,d20 |
| 1419 | vsli.64 d26,d19,#25 |
| 1420 | veor d18,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1421 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1422 | vbsl d30,d21,d20 @ Maj(a,b,c) |
| 1423 | veor d18,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1424 | vadd.i64 d22,d27 |
| 1425 | vadd.i64 d30,d27 |
| 1426 | @ vadd.i64 d18,d30 |
| 1427 | vshr.u64 q12,q2,#19 |
| 1428 | vshr.u64 q13,q2,#61 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1429 | vadd.i64 d18,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1430 | vshr.u64 q15,q2,#6 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1431 | vsli.64 q12,q2,#45 |
| 1432 | vext.8 q14,q3,q4,#8 @ X[i+1] |
| 1433 | vsli.64 q13,q2,#3 |
| 1434 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1435 | vshr.u64 q12,q14,#1 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1436 | veor q15,q13 @ sigma1(X[i+14]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1437 | vshr.u64 q13,q14,#8 |
| 1438 | vadd.i64 q3,q15 |
| 1439 | vshr.u64 q15,q14,#7 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1440 | vsli.64 q12,q14,#63 |
| 1441 | vsli.64 q13,q14,#56 |
| 1442 | vext.8 q14,q7,q0,#8 @ X[i+9] |
| 1443 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1444 | vshr.u64 d24,d22,#14 @ from NEON_00_15 |
| 1445 | vadd.i64 q3,q14 |
| 1446 | vshr.u64 d25,d22,#18 @ from NEON_00_15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1447 | veor q15,q13 @ sigma0(X[i+1]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1448 | vshr.u64 d26,d22,#41 @ from NEON_00_15 |
| 1449 | vadd.i64 q3,q15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1450 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1451 | vsli.64 d24,d22,#50 |
| 1452 | vsli.64 d25,d22,#46 |
| 1453 | vmov d29,d22 |
| 1454 | vsli.64 d26,d22,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1455 | #if 22<16 && defined(__ARMEL__) |
| 1456 | vrev64.8 , |
| 1457 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1458 | veor d25,d24 |
| 1459 | vbsl d29,d23,d16 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1460 | vshr.u64 d24,d18,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1461 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1462 | vadd.i64 d27,d29,d17 |
| 1463 | vshr.u64 d25,d18,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1464 | vsli.64 d24,d18,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1465 | vadd.i64 d27,d26 |
| 1466 | vshr.u64 d26,d18,#39 |
| 1467 | vadd.i64 d28,d6 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1468 | vsli.64 d25,d18,#30 |
| 1469 | veor d30,d18,d19 |
| 1470 | vsli.64 d26,d18,#25 |
| 1471 | veor d17,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1472 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1473 | vbsl d30,d20,d19 @ Maj(a,b,c) |
| 1474 | veor d17,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1475 | vadd.i64 d21,d27 |
| 1476 | vadd.i64 d30,d27 |
| 1477 | @ vadd.i64 d17,d30 |
| 1478 | vshr.u64 d24,d21,#14 @ 23 |
| 1479 | #if 23<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1480 | vld1.64 {d7},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1481 | #endif |
| 1482 | vshr.u64 d25,d21,#18 |
| 1483 | #if 23>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1484 | vadd.i64 d17,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1485 | #endif |
| 1486 | vshr.u64 d26,d21,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1487 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1488 | vsli.64 d24,d21,#50 |
| 1489 | vsli.64 d25,d21,#46 |
| 1490 | vmov d29,d21 |
| 1491 | vsli.64 d26,d21,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1492 | #if 23<16 && defined(__ARMEL__) |
| 1493 | vrev64.8 , |
| 1494 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1495 | veor d25,d24 |
| 1496 | vbsl d29,d22,d23 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1497 | vshr.u64 d24,d17,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1498 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1499 | vadd.i64 d27,d29,d16 |
| 1500 | vshr.u64 d25,d17,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1501 | vsli.64 d24,d17,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1502 | vadd.i64 d27,d26 |
| 1503 | vshr.u64 d26,d17,#39 |
| 1504 | vadd.i64 d28,d7 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1505 | vsli.64 d25,d17,#30 |
| 1506 | veor d30,d17,d18 |
| 1507 | vsli.64 d26,d17,#25 |
| 1508 | veor d16,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1509 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1510 | vbsl d30,d19,d18 @ Maj(a,b,c) |
| 1511 | veor d16,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1512 | vadd.i64 d20,d27 |
| 1513 | vadd.i64 d30,d27 |
| 1514 | @ vadd.i64 d16,d30 |
| 1515 | vshr.u64 q12,q3,#19 |
| 1516 | vshr.u64 q13,q3,#61 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1517 | vadd.i64 d16,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1518 | vshr.u64 q15,q3,#6 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1519 | vsli.64 q12,q3,#45 |
| 1520 | vext.8 q14,q4,q5,#8 @ X[i+1] |
| 1521 | vsli.64 q13,q3,#3 |
| 1522 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1523 | vshr.u64 q12,q14,#1 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1524 | veor q15,q13 @ sigma1(X[i+14]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1525 | vshr.u64 q13,q14,#8 |
| 1526 | vadd.i64 q4,q15 |
| 1527 | vshr.u64 q15,q14,#7 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1528 | vsli.64 q12,q14,#63 |
| 1529 | vsli.64 q13,q14,#56 |
| 1530 | vext.8 q14,q0,q1,#8 @ X[i+9] |
| 1531 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1532 | vshr.u64 d24,d20,#14 @ from NEON_00_15 |
| 1533 | vadd.i64 q4,q14 |
| 1534 | vshr.u64 d25,d20,#18 @ from NEON_00_15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1535 | veor q15,q13 @ sigma0(X[i+1]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1536 | vshr.u64 d26,d20,#41 @ from NEON_00_15 |
| 1537 | vadd.i64 q4,q15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1538 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1539 | vsli.64 d24,d20,#50 |
| 1540 | vsli.64 d25,d20,#46 |
| 1541 | vmov d29,d20 |
| 1542 | vsli.64 d26,d20,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1543 | #if 24<16 && defined(__ARMEL__) |
| 1544 | vrev64.8 , |
| 1545 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1546 | veor d25,d24 |
| 1547 | vbsl d29,d21,d22 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1548 | vshr.u64 d24,d16,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1549 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1550 | vadd.i64 d27,d29,d23 |
| 1551 | vshr.u64 d25,d16,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1552 | vsli.64 d24,d16,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1553 | vadd.i64 d27,d26 |
| 1554 | vshr.u64 d26,d16,#39 |
| 1555 | vadd.i64 d28,d8 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1556 | vsli.64 d25,d16,#30 |
| 1557 | veor d30,d16,d17 |
| 1558 | vsli.64 d26,d16,#25 |
| 1559 | veor d23,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1560 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1561 | vbsl d30,d18,d17 @ Maj(a,b,c) |
| 1562 | veor d23,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1563 | vadd.i64 d19,d27 |
| 1564 | vadd.i64 d30,d27 |
| 1565 | @ vadd.i64 d23,d30 |
| 1566 | vshr.u64 d24,d19,#14 @ 25 |
| 1567 | #if 25<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1568 | vld1.64 {d9},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1569 | #endif |
| 1570 | vshr.u64 d25,d19,#18 |
| 1571 | #if 25>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1572 | vadd.i64 d23,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1573 | #endif |
| 1574 | vshr.u64 d26,d19,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1575 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1576 | vsli.64 d24,d19,#50 |
| 1577 | vsli.64 d25,d19,#46 |
| 1578 | vmov d29,d19 |
| 1579 | vsli.64 d26,d19,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1580 | #if 25<16 && defined(__ARMEL__) |
| 1581 | vrev64.8 , |
| 1582 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1583 | veor d25,d24 |
| 1584 | vbsl d29,d20,d21 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1585 | vshr.u64 d24,d23,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1586 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1587 | vadd.i64 d27,d29,d22 |
| 1588 | vshr.u64 d25,d23,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1589 | vsli.64 d24,d23,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1590 | vadd.i64 d27,d26 |
| 1591 | vshr.u64 d26,d23,#39 |
| 1592 | vadd.i64 d28,d9 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1593 | vsli.64 d25,d23,#30 |
| 1594 | veor d30,d23,d16 |
| 1595 | vsli.64 d26,d23,#25 |
| 1596 | veor d22,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1597 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1598 | vbsl d30,d17,d16 @ Maj(a,b,c) |
| 1599 | veor d22,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1600 | vadd.i64 d18,d27 |
| 1601 | vadd.i64 d30,d27 |
| 1602 | @ vadd.i64 d22,d30 |
| 1603 | vshr.u64 q12,q4,#19 |
| 1604 | vshr.u64 q13,q4,#61 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1605 | vadd.i64 d22,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1606 | vshr.u64 q15,q4,#6 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1607 | vsli.64 q12,q4,#45 |
| 1608 | vext.8 q14,q5,q6,#8 @ X[i+1] |
| 1609 | vsli.64 q13,q4,#3 |
| 1610 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1611 | vshr.u64 q12,q14,#1 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1612 | veor q15,q13 @ sigma1(X[i+14]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1613 | vshr.u64 q13,q14,#8 |
| 1614 | vadd.i64 q5,q15 |
| 1615 | vshr.u64 q15,q14,#7 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1616 | vsli.64 q12,q14,#63 |
| 1617 | vsli.64 q13,q14,#56 |
| 1618 | vext.8 q14,q1,q2,#8 @ X[i+9] |
| 1619 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1620 | vshr.u64 d24,d18,#14 @ from NEON_00_15 |
| 1621 | vadd.i64 q5,q14 |
| 1622 | vshr.u64 d25,d18,#18 @ from NEON_00_15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1623 | veor q15,q13 @ sigma0(X[i+1]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1624 | vshr.u64 d26,d18,#41 @ from NEON_00_15 |
| 1625 | vadd.i64 q5,q15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1626 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1627 | vsli.64 d24,d18,#50 |
| 1628 | vsli.64 d25,d18,#46 |
| 1629 | vmov d29,d18 |
| 1630 | vsli.64 d26,d18,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1631 | #if 26<16 && defined(__ARMEL__) |
| 1632 | vrev64.8 , |
| 1633 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1634 | veor d25,d24 |
| 1635 | vbsl d29,d19,d20 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1636 | vshr.u64 d24,d22,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1637 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1638 | vadd.i64 d27,d29,d21 |
| 1639 | vshr.u64 d25,d22,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1640 | vsli.64 d24,d22,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1641 | vadd.i64 d27,d26 |
| 1642 | vshr.u64 d26,d22,#39 |
| 1643 | vadd.i64 d28,d10 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1644 | vsli.64 d25,d22,#30 |
| 1645 | veor d30,d22,d23 |
| 1646 | vsli.64 d26,d22,#25 |
| 1647 | veor d21,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1648 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1649 | vbsl d30,d16,d23 @ Maj(a,b,c) |
| 1650 | veor d21,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1651 | vadd.i64 d17,d27 |
| 1652 | vadd.i64 d30,d27 |
| 1653 | @ vadd.i64 d21,d30 |
| 1654 | vshr.u64 d24,d17,#14 @ 27 |
| 1655 | #if 27<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1656 | vld1.64 {d11},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1657 | #endif |
| 1658 | vshr.u64 d25,d17,#18 |
| 1659 | #if 27>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1660 | vadd.i64 d21,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1661 | #endif |
| 1662 | vshr.u64 d26,d17,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1663 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1664 | vsli.64 d24,d17,#50 |
| 1665 | vsli.64 d25,d17,#46 |
| 1666 | vmov d29,d17 |
| 1667 | vsli.64 d26,d17,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1668 | #if 27<16 && defined(__ARMEL__) |
| 1669 | vrev64.8 , |
| 1670 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1671 | veor d25,d24 |
| 1672 | vbsl d29,d18,d19 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1673 | vshr.u64 d24,d21,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1674 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1675 | vadd.i64 d27,d29,d20 |
| 1676 | vshr.u64 d25,d21,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1677 | vsli.64 d24,d21,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1678 | vadd.i64 d27,d26 |
| 1679 | vshr.u64 d26,d21,#39 |
| 1680 | vadd.i64 d28,d11 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1681 | vsli.64 d25,d21,#30 |
| 1682 | veor d30,d21,d22 |
| 1683 | vsli.64 d26,d21,#25 |
| 1684 | veor d20,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1685 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1686 | vbsl d30,d23,d22 @ Maj(a,b,c) |
| 1687 | veor d20,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1688 | vadd.i64 d16,d27 |
| 1689 | vadd.i64 d30,d27 |
| 1690 | @ vadd.i64 d20,d30 |
| 1691 | vshr.u64 q12,q5,#19 |
| 1692 | vshr.u64 q13,q5,#61 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1693 | vadd.i64 d20,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1694 | vshr.u64 q15,q5,#6 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1695 | vsli.64 q12,q5,#45 |
| 1696 | vext.8 q14,q6,q7,#8 @ X[i+1] |
| 1697 | vsli.64 q13,q5,#3 |
| 1698 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1699 | vshr.u64 q12,q14,#1 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1700 | veor q15,q13 @ sigma1(X[i+14]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1701 | vshr.u64 q13,q14,#8 |
| 1702 | vadd.i64 q6,q15 |
| 1703 | vshr.u64 q15,q14,#7 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1704 | vsli.64 q12,q14,#63 |
| 1705 | vsli.64 q13,q14,#56 |
| 1706 | vext.8 q14,q2,q3,#8 @ X[i+9] |
| 1707 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1708 | vshr.u64 d24,d16,#14 @ from NEON_00_15 |
| 1709 | vadd.i64 q6,q14 |
| 1710 | vshr.u64 d25,d16,#18 @ from NEON_00_15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1711 | veor q15,q13 @ sigma0(X[i+1]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1712 | vshr.u64 d26,d16,#41 @ from NEON_00_15 |
| 1713 | vadd.i64 q6,q15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1714 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1715 | vsli.64 d24,d16,#50 |
| 1716 | vsli.64 d25,d16,#46 |
| 1717 | vmov d29,d16 |
| 1718 | vsli.64 d26,d16,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1719 | #if 28<16 && defined(__ARMEL__) |
| 1720 | vrev64.8 , |
| 1721 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1722 | veor d25,d24 |
| 1723 | vbsl d29,d17,d18 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1724 | vshr.u64 d24,d20,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1725 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1726 | vadd.i64 d27,d29,d19 |
| 1727 | vshr.u64 d25,d20,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1728 | vsli.64 d24,d20,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1729 | vadd.i64 d27,d26 |
| 1730 | vshr.u64 d26,d20,#39 |
| 1731 | vadd.i64 d28,d12 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1732 | vsli.64 d25,d20,#30 |
| 1733 | veor d30,d20,d21 |
| 1734 | vsli.64 d26,d20,#25 |
| 1735 | veor d19,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1736 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1737 | vbsl d30,d22,d21 @ Maj(a,b,c) |
| 1738 | veor d19,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1739 | vadd.i64 d23,d27 |
| 1740 | vadd.i64 d30,d27 |
| 1741 | @ vadd.i64 d19,d30 |
| 1742 | vshr.u64 d24,d23,#14 @ 29 |
| 1743 | #if 29<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1744 | vld1.64 {d13},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1745 | #endif |
| 1746 | vshr.u64 d25,d23,#18 |
| 1747 | #if 29>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1748 | vadd.i64 d19,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1749 | #endif |
| 1750 | vshr.u64 d26,d23,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1751 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1752 | vsli.64 d24,d23,#50 |
| 1753 | vsli.64 d25,d23,#46 |
| 1754 | vmov d29,d23 |
| 1755 | vsli.64 d26,d23,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1756 | #if 29<16 && defined(__ARMEL__) |
| 1757 | vrev64.8 , |
| 1758 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1759 | veor d25,d24 |
| 1760 | vbsl d29,d16,d17 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1761 | vshr.u64 d24,d19,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1762 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1763 | vadd.i64 d27,d29,d18 |
| 1764 | vshr.u64 d25,d19,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1765 | vsli.64 d24,d19,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1766 | vadd.i64 d27,d26 |
| 1767 | vshr.u64 d26,d19,#39 |
| 1768 | vadd.i64 d28,d13 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1769 | vsli.64 d25,d19,#30 |
| 1770 | veor d30,d19,d20 |
| 1771 | vsli.64 d26,d19,#25 |
| 1772 | veor d18,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1773 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1774 | vbsl d30,d21,d20 @ Maj(a,b,c) |
| 1775 | veor d18,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1776 | vadd.i64 d22,d27 |
| 1777 | vadd.i64 d30,d27 |
| 1778 | @ vadd.i64 d18,d30 |
| 1779 | vshr.u64 q12,q6,#19 |
| 1780 | vshr.u64 q13,q6,#61 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1781 | vadd.i64 d18,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1782 | vshr.u64 q15,q6,#6 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1783 | vsli.64 q12,q6,#45 |
| 1784 | vext.8 q14,q7,q0,#8 @ X[i+1] |
| 1785 | vsli.64 q13,q6,#3 |
| 1786 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1787 | vshr.u64 q12,q14,#1 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1788 | veor q15,q13 @ sigma1(X[i+14]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1789 | vshr.u64 q13,q14,#8 |
| 1790 | vadd.i64 q7,q15 |
| 1791 | vshr.u64 q15,q14,#7 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1792 | vsli.64 q12,q14,#63 |
| 1793 | vsli.64 q13,q14,#56 |
| 1794 | vext.8 q14,q3,q4,#8 @ X[i+9] |
| 1795 | veor q15,q12 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1796 | vshr.u64 d24,d22,#14 @ from NEON_00_15 |
| 1797 | vadd.i64 q7,q14 |
| 1798 | vshr.u64 d25,d22,#18 @ from NEON_00_15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1799 | veor q15,q13 @ sigma0(X[i+1]) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1800 | vshr.u64 d26,d22,#41 @ from NEON_00_15 |
| 1801 | vadd.i64 q7,q15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1802 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1803 | vsli.64 d24,d22,#50 |
| 1804 | vsli.64 d25,d22,#46 |
| 1805 | vmov d29,d22 |
| 1806 | vsli.64 d26,d22,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1807 | #if 30<16 && defined(__ARMEL__) |
| 1808 | vrev64.8 , |
| 1809 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1810 | veor d25,d24 |
| 1811 | vbsl d29,d23,d16 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1812 | vshr.u64 d24,d18,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1813 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1814 | vadd.i64 d27,d29,d17 |
| 1815 | vshr.u64 d25,d18,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1816 | vsli.64 d24,d18,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1817 | vadd.i64 d27,d26 |
| 1818 | vshr.u64 d26,d18,#39 |
| 1819 | vadd.i64 d28,d14 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1820 | vsli.64 d25,d18,#30 |
| 1821 | veor d30,d18,d19 |
| 1822 | vsli.64 d26,d18,#25 |
| 1823 | veor d17,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1824 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1825 | vbsl d30,d20,d19 @ Maj(a,b,c) |
| 1826 | veor d17,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1827 | vadd.i64 d21,d27 |
| 1828 | vadd.i64 d30,d27 |
| 1829 | @ vadd.i64 d17,d30 |
| 1830 | vshr.u64 d24,d21,#14 @ 31 |
| 1831 | #if 31<16 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1832 | vld1.64 {d15},[r1]! @ handles unaligned |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1833 | #endif |
| 1834 | vshr.u64 d25,d21,#18 |
| 1835 | #if 31>0 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1836 | vadd.i64 d17,d30 @ h+=Maj from the past |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1837 | #endif |
| 1838 | vshr.u64 d26,d21,#41 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1839 | vld1.64 {d28},[r3,:64]! @ K[i++] |
| 1840 | vsli.64 d24,d21,#50 |
| 1841 | vsli.64 d25,d21,#46 |
| 1842 | vmov d29,d21 |
| 1843 | vsli.64 d26,d21,#23 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1844 | #if 31<16 && defined(__ARMEL__) |
| 1845 | vrev64.8 , |
| 1846 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1847 | veor d25,d24 |
| 1848 | vbsl d29,d22,d23 @ Ch(e,f,g) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1849 | vshr.u64 d24,d17,#28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1850 | veor d26,d25 @ Sigma1(e) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1851 | vadd.i64 d27,d29,d16 |
| 1852 | vshr.u64 d25,d17,#34 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1853 | vsli.64 d24,d17,#36 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1854 | vadd.i64 d27,d26 |
| 1855 | vshr.u64 d26,d17,#39 |
| 1856 | vadd.i64 d28,d15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1857 | vsli.64 d25,d17,#30 |
| 1858 | veor d30,d17,d18 |
| 1859 | vsli.64 d26,d17,#25 |
| 1860 | veor d16,d24,d25 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1861 | vadd.i64 d27,d28 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1862 | vbsl d30,d19,d18 @ Maj(a,b,c) |
| 1863 | veor d16,d26 @ Sigma0(a) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1864 | vadd.i64 d20,d27 |
| 1865 | vadd.i64 d30,d27 |
| 1866 | @ vadd.i64 d16,d30 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1867 | bne .L16_79_neon |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1868 | |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1869 | vadd.i64 d16,d30 @ h+=Maj from the past |
| 1870 | vldmia r0,{d24,d25,d26,d27,d28,d29,d30,d31} @ load context to temp |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1871 | vadd.i64 q8,q12 @ vectorized accumulate |
| 1872 | vadd.i64 q9,q13 |
| 1873 | vadd.i64 q10,q14 |
| 1874 | vadd.i64 q11,q15 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1875 | vstmia r0,{d16,d17,d18,d19,d20,d21,d22,d23} @ save context |
| 1876 | teq r1,r2 |
| 1877 | sub r3,#640 @ rewind K512 |
| 1878 | bne .Loop_neon |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1879 | |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1880 | VFP_ABI_POP |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1881 | bx lr @ .word 0xe12fff1e |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1882 | .size sha512_block_data_order_neon,.-sha512_block_data_order_neon |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1883 | #endif |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1884 | .byte 83,72,65,53,49,50,32,98,108,111,99,107,32,116,114,97,110,115,102,111,114,109,32,102,111,114,32,65,82,77,118,52,47,78,69,79,78,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0 |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1885 | .align 2 |
Adam Langley | e9ada86 | 2015-05-11 17:20:37 -0700 | [diff] [blame] | 1886 | .align 2 |
| 1887 | #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__) |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1888 | .comm OPENSSL_armcap_P,4,4 |
Adam Langley | 13066f1 | 2015-02-13 14:47:35 -0800 | [diff] [blame] | 1889 | .hidden OPENSSL_armcap_P |
Adam Langley | d9e397b | 2015-01-22 14:27:53 -0800 | [diff] [blame] | 1890 | #endif |
David Benjamin | 4969cc9 | 2016-04-22 15:02:23 -0400 | [diff] [blame] | 1891 | #endif |
Robert Sloan | 726e9d1 | 2018-09-11 11:45:04 -0700 | [diff] [blame] | 1892 | #endif // !OPENSSL_NO_ASM |