x86: support avx_sae & avx_rm in cs_x86 struct. this also updates Python & Java bindings following the core's change
diff --git a/bindings/java/TestX86.java b/bindings/java/TestX86.java
index 0aec400..b12cb0b 100644
--- a/bindings/java/TestX86.java
+++ b/bindings/java/TestX86.java
@@ -73,6 +73,12 @@
     if (operands.avxCC != 0)
         System.out.printf("\tavx_cc: %u\n", operands.avxCC);
 
+    if (operands.avxSae)
+        System.out.printf("\tavx_sae: TRUE\n");
+
+    if (operands.avxRm != 0)
+        System.out.printf("\tavx_rm: %u\n", operands.avxRm);
+
     int count = ins.opCount(X86_OP_IMM);
     if (count > 0) {
       System.out.printf("\timm_count: %d\n", count);
diff --git a/bindings/java/capstone/X86.java b/bindings/java/capstone/X86.java
index c43fe20..28f66a8 100644
--- a/bindings/java/capstone/X86.java
+++ b/bindings/java/capstone/X86.java
@@ -78,6 +78,8 @@
     public int sib_base;
     public int sse_cc;
     public int avx_cc;
+    public boolean avx_sae;
+    public int avx_rm;
 
     public char op_count;
 
@@ -92,7 +94,7 @@
     @Override
     public List getFieldOrder() {
       return Arrays.asList("prefix", "opcode", "addr_size",
-          "modrm", "sib", "disp", "sib_index", "sib_scale", "sib_base", "sse_cc", "avx_cc", "op_count", "op");
+          "modrm", "sib", "disp", "sib_index", "sib_scale", "sib_base", "sse_cc", "avx_cc", "avx_sae", "avx_rm", "op_count", "op");
     }
   }
 
@@ -126,6 +128,8 @@
       sibBase = e.sib_base;
       sseCC = e.sse_cc;
       avxCC = e.avx_cc;
+      avxSae = e.avx_sae;
+      avxRm = e.avx_rm;
       op = new Operand[e.op_count];
       for (int i=0; i<e.op_count; i++)
         op[i] = e.op[i];
diff --git a/bindings/java/capstone/X86_const.java b/bindings/java/capstone/X86_const.java
index aec756f..c2835be 100644
--- a/bindings/java/capstone/X86_const.java
+++ b/bindings/java/capstone/X86_const.java
@@ -310,6 +310,14 @@
 	public static final int X86_AVX_CC_GT_OQ = 31;
 	public static final int X86_AVX_CC_TRUE_US = 32;
 
+	// AVX static rounding mode type
+
+	public static final int X86_AVX_RM_INVALID = 0;
+	public static final int X86_AVX_RM_RN = 1;
+	public static final int X86_AVX_RM_RD = 2;
+	public static final int X86_AVX_RM_RU = 3;
+	public static final int X86_AVX_RM_RZ = 4;
+
 	// X86 instructions
 
 	public static final int X86_INS_INVALID = 0;