fix some potential format string bugs in arm64, arm & mips
diff --git a/arch/AArch64/AArch64GenAsmWriter.inc b/arch/AArch64/AArch64GenAsmWriter.inc
index 8987188..df707f8 100644
--- a/arch/AArch64/AArch64GenAsmWriter.inc
+++ b/arch/AArch64/AArch64GenAsmWriter.inc
@@ -3729,7 +3729,7 @@
   uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)];
   uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)];
   uint64_t Bits = (Bits2 << 32) | Bits1;
-  SStream_concat(O, AsmStrs+(Bits & 4095)-1);
+  SStream_concat(O, "%s",AsmStrs+(Bits & 4095)-1);
 
   // printf("Frag-0 : %lu\n", (Bits >> 12) & 15);
   // Fragment 0 encoded into 4 bits for 15 unique commands.
diff --git a/arch/ARM/ARMGenAsmWriter.inc b/arch/ARM/ARMGenAsmWriter.inc
index 3e28452..2bfb39d 100644
--- a/arch/ARM/ARMGenAsmWriter.inc
+++ b/arch/ARM/ARMGenAsmWriter.inc
@@ -6114,7 +6114,7 @@
   uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)];
   uint64_t Bits = (Bits2 << 32) | Bits1;
   //assert(Bits != 0 && "Cannot print this instruction.");
-  SStream_concat(O, AsmStrs+(Bits & 4095)-1);
+  SStream_concat(O, "%s", AsmStrs+(Bits & 4095)-1);
 
   //printf("Frag-0: %lu\n", (Bits >> 12) & 31);
   // Fragment 0 encoded into 5 bits for 29 unique commands.
diff --git a/arch/Mips/MipsGenAsmWriter.inc b/arch/Mips/MipsGenAsmWriter.inc
index 42e2e84..fe1b836 100644
--- a/arch/Mips/MipsGenAsmWriter.inc
+++ b/arch/Mips/MipsGenAsmWriter.inc
@@ -3696,7 +3696,7 @@
   uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)];
   uint64_t Bits = (Bits2 << 32) | Bits1;
   //assert(Bits != 0 && "Cannot print this instruction.");
-  SStream_concat(O, AsmStrs+(Bits & 8191)-1);
+  SStream_concat(O, "%s", AsmStrs+(Bits & 8191)-1);
 
   // Fragment 0 encoded into 3 bits for 6 unique commands.
   //printf("\nFrag-0: %llu\n", (Bits >> 13) & 7);