| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |*Assembly Writer Source Fragment *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| /* Capstone Disassembler Engine */ |
| /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */ |
| |
| /// printInstruction - This method is automatically generated by tablegen |
| /// from the instruction set description. |
| static void AArch64InstPrinter_printInstruction(MCInst *MI, SStream *O) |
| { |
| static uint32_t OpInfo[] = { |
| 0U, // PHI |
| 0U, // INLINEASM |
| 0U, // PROLOG_LABEL |
| 0U, // EH_LABEL |
| 0U, // GC_LABEL |
| 0U, // KILL |
| 0U, // EXTRACT_SUBREG |
| 0U, // INSERT_SUBREG |
| 0U, // IMPLICIT_DEF |
| 0U, // SUBREG_TO_REG |
| 0U, // COPY_TO_REGCLASS |
| 2407U, // DBG_VALUE |
| 0U, // REG_SEQUENCE |
| 0U, // COPY |
| 2400U, // BUNDLE |
| 2417U, // LIFETIME_START |
| 2387U, // LIFETIME_END |
| 5845U, // ADCSwww |
| 5845U, // ADCSxxx |
| 4664U, // ADCwww |
| 4664U, // ADCxxx |
| 1108418751U, // ADDHN2vvv_16b8h |
| 1142038719U, // ADDHN2vvv_4s2d |
| 1175658687U, // ADDHN2vvv_8h4s |
| 2216961313U, // ADDHNvvv_2s2d |
| 2250581281U, // ADDHNvvv_4h4s |
| 2183537953U, // ADDHNvvv_8b8h |
| 2283873683U, // ADDP_16B |
| 2217158035U, // ADDP_2D |
| 2317624723U, // ADDP_2S |
| 2351244691U, // ADDP_4H |
| 2250384787U, // ADDP_4S |
| 2384864659U, // ADDP_8B |
| 2183341459U, // ADDP_8H |
| 270539040U, // ADDPvv_D_2D |
| 5857U, // ADDSwww_asr |
| 5857U, // ADDSwww_lsl |
| 5857U, // ADDSwww_lsr |
| 5857U, // ADDSwww_sxtb |
| 5857U, // ADDSwww_sxth |
| 5857U, // ADDSwww_sxtw |
| 5857U, // ADDSwww_sxtx |
| 5857U, // ADDSwww_uxtb |
| 5857U, // ADDSwww_uxth |
| 5857U, // ADDSwww_uxtw |
| 5857U, // ADDSwww_uxtx |
| 5857U, // ADDSxxw_sxtb |
| 5857U, // ADDSxxw_sxth |
| 5857U, // ADDSxxw_sxtw |
| 5857U, // ADDSxxw_uxtb |
| 5857U, // ADDSxxw_uxth |
| 5857U, // ADDSxxw_uxtw |
| 5857U, // ADDSxxx_asr |
| 5857U, // ADDSxxx_lsl |
| 5857U, // ADDSxxx_lsr |
| 5857U, // ADDSxxx_sxtx |
| 5857U, // ADDSxxx_uxtx |
| 6346U, // ADDddd |
| 2283872875U, // ADDvvv_16B |
| 2217157227U, // ADDvvv_2D |
| 2317623915U, // ADDvvv_2S |
| 2351243883U, // ADDvvv_4H |
| 2250383979U, // ADDvvv_4S |
| 2384863851U, // ADDvvv_8B |
| 2183340651U, // ADDvvv_8H |
| 3221231329U, // ADDwwi_lsl0_S |
| 3152154U, // ADDwwi_lsl0_cmp |
| 3221230187U, // ADDwwi_lsl0_s |
| 5857U, // ADDwwi_lsl12_S |
| 4200730U, // ADDwwi_lsl12_cmp |
| 4715U, // ADDwwi_lsl12_s |
| 4715U, // ADDwww_asr |
| 4715U, // ADDwww_lsl |
| 4715U, // ADDwww_lsr |
| 4715U, // ADDwww_sxtb |
| 4715U, // ADDwww_sxth |
| 4715U, // ADDwww_sxtw |
| 4715U, // ADDwww_sxtx |
| 4715U, // ADDwww_uxtb |
| 4715U, // ADDwww_uxth |
| 4715U, // ADDwww_uxtw |
| 4715U, // ADDwww_uxtx |
| 3221231329U, // ADDxxi_lsl0_S |
| 3152154U, // ADDxxi_lsl0_cmp |
| 3221230187U, // ADDxxi_lsl0_s |
| 5857U, // ADDxxi_lsl12_S |
| 4200730U, // ADDxxi_lsl12_cmp |
| 4715U, // ADDxxi_lsl12_s |
| 4715U, // ADDxxw_sxtb |
| 4715U, // ADDxxw_sxth |
| 4715U, // ADDxxw_sxtw |
| 4715U, // ADDxxw_uxtb |
| 4715U, // ADDxxw_uxth |
| 4715U, // ADDxxw_uxtw |
| 4715U, // ADDxxx_asr |
| 4715U, // ADDxxx_lsl |
| 4715U, // ADDxxx_lsr |
| 4715U, // ADDxxx_sxtx |
| 4715U, // ADDxxx_uxtx |
| 0U, // ADJCALLSTACKDOWN |
| 0U, // ADJCALLSTACKUP |
| 5248478U, // ADRPxi |
| 6297137U, // ADRxi |
| 1073747687U, // ANDSwwi |
| 5863U, // ANDSwww_asr |
| 5863U, // ANDSwww_lsl |
| 5863U, // ANDSwww_lsr |
| 5863U, // ANDSwww_ror |
| 2147489511U, // ANDSxxi |
| 5863U, // ANDSxxx_asr |
| 5863U, // ANDSxxx_lsl |
| 5863U, // ANDSxxx_lsr |
| 5863U, // ANDSxxx_ror |
| 2283872939U, // ANDvvv_16B |
| 2384863915U, // ANDvvv_8B |
| 1073746603U, // ANDwwi |
| 4779U, // ANDwww_asr |
| 4779U, // ANDwww_lsl |
| 4779U, // ANDwww_lsr |
| 4779U, // ANDwww_ror |
| 2147488427U, // ANDxxi |
| 4779U, // ANDxxx_asr |
| 4779U, // ANDxxx_lsl |
| 4779U, // ANDxxx_lsr |
| 4779U, // ANDxxx_ror |
| 5743U, // ASRVwww |
| 5743U, // ASRVxxx |
| 5743U, // ASRwwi |
| 5743U, // ASRxxi |
| 0U, // ATOMIC_CMP_SWAP_I16 |
| 0U, // ATOMIC_CMP_SWAP_I32 |
| 0U, // ATOMIC_CMP_SWAP_I64 |
| 0U, // ATOMIC_CMP_SWAP_I8 |
| 0U, // ATOMIC_LOAD_ADD_I16 |
| 0U, // ATOMIC_LOAD_ADD_I32 |
| 0U, // ATOMIC_LOAD_ADD_I64 |
| 0U, // ATOMIC_LOAD_ADD_I8 |
| 0U, // ATOMIC_LOAD_AND_I16 |
| 0U, // ATOMIC_LOAD_AND_I32 |
| 0U, // ATOMIC_LOAD_AND_I64 |
| 0U, // ATOMIC_LOAD_AND_I8 |
| 0U, // ATOMIC_LOAD_MAX_I16 |
| 0U, // ATOMIC_LOAD_MAX_I32 |
| 0U, // ATOMIC_LOAD_MAX_I64 |
| 0U, // ATOMIC_LOAD_MAX_I8 |
| 0U, // ATOMIC_LOAD_MIN_I16 |
| 0U, // ATOMIC_LOAD_MIN_I32 |
| 0U, // ATOMIC_LOAD_MIN_I64 |
| 0U, // ATOMIC_LOAD_MIN_I8 |
| 0U, // ATOMIC_LOAD_NAND_I16 |
| 0U, // ATOMIC_LOAD_NAND_I32 |
| 0U, // ATOMIC_LOAD_NAND_I64 |
| 0U, // ATOMIC_LOAD_NAND_I8 |
| 0U, // ATOMIC_LOAD_OR_I16 |
| 0U, // ATOMIC_LOAD_OR_I32 |
| 0U, // ATOMIC_LOAD_OR_I64 |
| 0U, // ATOMIC_LOAD_OR_I8 |
| 0U, // ATOMIC_LOAD_SUB_I16 |
| 0U, // ATOMIC_LOAD_SUB_I32 |
| 0U, // ATOMIC_LOAD_SUB_I64 |
| 0U, // ATOMIC_LOAD_SUB_I8 |
| 0U, // ATOMIC_LOAD_UMAX_I16 |
| 0U, // ATOMIC_LOAD_UMAX_I32 |
| 0U, // ATOMIC_LOAD_UMAX_I64 |
| 0U, // ATOMIC_LOAD_UMAX_I8 |
| 0U, // ATOMIC_LOAD_UMIN_I16 |
| 0U, // ATOMIC_LOAD_UMIN_I32 |
| 0U, // ATOMIC_LOAD_UMIN_I64 |
| 0U, // ATOMIC_LOAD_UMIN_I8 |
| 0U, // ATOMIC_LOAD_XOR_I16 |
| 0U, // ATOMIC_LOAD_XOR_I32 |
| 0U, // ATOMIC_LOAD_XOR_I64 |
| 0U, // ATOMIC_LOAD_XOR_I8 |
| 0U, // ATOMIC_SWAP_I16 |
| 0U, // ATOMIC_SWAP_I32 |
| 0U, // ATOMIC_SWAP_I64 |
| 0U, // ATOMIC_SWAP_I8 |
| 14142U, // ATix |
| 3228570531U, // BFIwwii |
| 7345059U, // BFIxxii |
| 1081087208U, // BFMwwii |
| 1081087208U, // BFMxxii |
| 1081087103U, // BFXILwwii |
| 1081087103U, // BFXILxxii |
| 5851U, // BICSwww_asr |
| 5851U, // BICSwww_lsl |
| 5851U, // BICSwww_lsr |
| 5851U, // BICSwww_ror |
| 5851U, // BICSxxx_asr |
| 5851U, // BICSxxx_lsl |
| 5851U, // BICSxxx_lsr |
| 5851U, // BICSxxx_ror |
| 310651075U, // BICvi_lsl_2S |
| 344271043U, // BICvi_lsl_4H |
| 310520003U, // BICvi_lsl_4S |
| 344139971U, // BICvi_lsl_8H |
| 2283872829U, // BICvvv_16B |
| 2384863805U, // BICvvv_8B |
| 4669U, // BICwww_asr |
| 4669U, // BICwww_lsl |
| 4669U, // BICwww_lsr |
| 4669U, // BICwww_ror |
| 4669U, // BICxxx_asr |
| 4669U, // BICxxx_lsl |
| 4669U, // BICxxx_lsr |
| 4669U, // BICxxx_ror |
| 1209082580U, // BIFvvv_16B |
| 1310073556U, // BIFvvv_8B |
| 1209083734U, // BITvvv_16B |
| 1310074710U, // BITvvv_8B |
| 530005U, // BLRx |
| 17402U, // BLimm |
| 529350U, // BRKi |
| 529965U, // BRx |
| 1209083058U, // BSLvvv_16B |
| 1310074034U, // BSLvvv_8B |
| 22864U, // Bcc |
| 16752U, // Bimm |
| 9443476U, // CBNZw |
| 9443476U, // CBNZx |
| 9443447U, // CBZw |
| 9443447U, // CBZx |
| 5434U, // CCMNwi |
| 5434U, // CCMNww |
| 5434U, // CCMNxi |
| 5434U, // CCMNxx |
| 5535U, // CCMPwi |
| 5535U, // CCMPww |
| 5535U, // CCMPxi |
| 5535U, // CCMPxx |
| 530517U, // CLREXi |
| 369104627U, // CLSww |
| 369104627U, // CLSxx |
| 369105039U, // CLZww |
| 369105039U, // CLZxx |
| 2283873825U, // CMEQvvi_16B |
| 2217158177U, // CMEQvvi_2D |
| 2317624865U, // CMEQvvi_2S |
| 2351244833U, // CMEQvvi_4H |
| 2250384929U, // CMEQvvi_4S |
| 2384864801U, // CMEQvvi_8B |
| 2183341601U, // CMEQvvi_8H |
| 2283873825U, // CMEQvvv_16B |
| 2217158177U, // CMEQvvv_2D |
| 2317624865U, // CMEQvvv_2S |
| 2351244833U, // CMEQvvv_4H |
| 2250384929U, // CMEQvvv_4S |
| 2384864801U, // CMEQvvv_8B |
| 2183341601U, // CMEQvvv_8H |
| 2283872952U, // CMGEvvi_16B |
| 2217157304U, // CMGEvvi_2D |
| 2317623992U, // CMGEvvi_2S |
| 2351243960U, // CMGEvvi_4H |
| 2250384056U, // CMGEvvi_4S |
| 2384863928U, // CMGEvvi_8B |
| 2183340728U, // CMGEvvi_8H |
| 2283872952U, // CMGEvvv_16B |
| 2217157304U, // CMGEvvv_2D |
| 2317623992U, // CMGEvvv_2S |
| 2351243960U, // CMGEvvv_4H |
| 2250384056U, // CMGEvvv_4S |
| 2384863928U, // CMGEvvv_8B |
| 2183340728U, // CMGEvvv_8H |
| 2283874127U, // CMGTvvi_16B |
| 2217158479U, // CMGTvvi_2D |
| 2317625167U, // CMGTvvi_2S |
| 2351245135U, // CMGTvvi_4H |
| 2250385231U, // CMGTvvi_4S |
| 2384865103U, // CMGTvvi_8B |
| 2183341903U, // CMGTvvi_8H |
| 2283874127U, // CMGTvvv_16B |
| 2217158479U, // CMGTvvv_2D |
| 2317625167U, // CMGTvvv_2S |
| 2351245135U, // CMGTvvv_4H |
| 2250385231U, // CMGTvvv_4S |
| 2384865103U, // CMGTvvv_8B |
| 2183341903U, // CMGTvvv_8H |
| 2283873192U, // CMHIvvv_16B |
| 2217157544U, // CMHIvvv_2D |
| 2317624232U, // CMHIvvv_2S |
| 2351244200U, // CMHIvvv_4H |
| 2250384296U, // CMHIvvv_4S |
| 2384864168U, // CMHIvvv_8B |
| 2183340968U, // CMHIvvv_8H |
| 2283874029U, // CMHSvvv_16B |
| 2217158381U, // CMHSvvv_2D |
| 2317625069U, // CMHSvvv_2S |
| 2351245037U, // CMHSvvv_4H |
| 2250385133U, // CMHSvvv_4S |
| 2384865005U, // CMHSvvv_8B |
| 2183341805U, // CMHSvvv_8H |
| 2283872959U, // CMLEvvi_16B |
| 2217157311U, // CMLEvvi_2D |
| 2317623999U, // CMLEvvi_2S |
| 2351243967U, // CMLEvvi_4H |
| 2250384063U, // CMLEvvi_4S |
| 2384863935U, // CMLEvvi_8B |
| 2183340735U, // CMLEvvi_8H |
| 2283874145U, // CMLTvvi_16B |
| 2217158497U, // CMLTvvi_2D |
| 2317625185U, // CMLTvvi_2S |
| 2351245153U, // CMLTvvi_4H |
| 2250385249U, // CMLTvvi_4S |
| 2384865121U, // CMLTvvi_8B |
| 2183341921U, // CMLTvvi_8H |
| 3221230907U, // CMNww_asr |
| 5435U, // CMNww_lsl |
| 1073747259U, // CMNww_lsr |
| 2147489083U, // CMNww_sxtb |
| 3221230907U, // CMNww_sxth |
| 5435U, // CMNww_sxtw |
| 1073747259U, // CMNww_sxtx |
| 2147489083U, // CMNww_uxtb |
| 3221230907U, // CMNww_uxth |
| 5435U, // CMNww_uxtw |
| 1073747259U, // CMNww_uxtx |
| 2147489083U, // CMNxw_sxtb |
| 3221230907U, // CMNxw_sxth |
| 5435U, // CMNxw_sxtw |
| 2147489083U, // CMNxw_uxtb |
| 3221230907U, // CMNxw_uxth |
| 5435U, // CMNxw_uxtw |
| 3221230907U, // CMNxx_asr |
| 5435U, // CMNxx_lsl |
| 1073747259U, // CMNxx_lsr |
| 1073747259U, // CMNxx_sxtx |
| 1073747259U, // CMNxx_uxtx |
| 3221231008U, // CMPww_asr |
| 5536U, // CMPww_lsl |
| 1073747360U, // CMPww_lsr |
| 2147489184U, // CMPww_sxtb |
| 3221231008U, // CMPww_sxth |
| 5536U, // CMPww_sxtw |
| 1073747360U, // CMPww_sxtx |
| 2147489184U, // CMPww_uxtb |
| 3221231008U, // CMPww_uxth |
| 5536U, // CMPww_uxtw |
| 1073747360U, // CMPww_uxtx |
| 2147489184U, // CMPxw_sxtb |
| 3221231008U, // CMPxw_sxth |
| 5536U, // CMPxw_sxtw |
| 2147489184U, // CMPxw_uxtb |
| 3221231008U, // CMPxw_uxth |
| 5536U, // CMPxw_uxtw |
| 3221231008U, // CMPxx_asr |
| 5536U, // CMPxx_lsl |
| 1073747360U, // CMPxx_lsr |
| 1073747360U, // CMPxx_sxtx |
| 1073747360U, // CMPxx_uxtx |
| 2283874164U, // CMTSTvvv_16B |
| 2217158516U, // CMTSTvvv_2D |
| 2317625204U, // CMTSTvvv_2S |
| 2351245172U, // CMTSTvvv_4H |
| 2250385268U, // CMTSTvvv_4S |
| 2384865140U, // CMTSTvvv_8B |
| 2183341940U, // CMTSTvvv_8H |
| 4459U, // CRC32B_www |
| 4467U, // CRC32CB_www |
| 4860U, // CRC32CH_www |
| 6135U, // CRC32CW_www |
| 6220U, // CRC32CX_wwx |
| 4852U, // CRC32H_www |
| 6113U, // CRC32W_www |
| 6194U, // CRC32X_wwx |
| 5185U, // CSELwwwc |
| 5185U, // CSELxxxc |
| 4679U, // CSINCwwwc |
| 4679U, // CSINCxxxc |
| 6088U, // CSINVwwwc |
| 6088U, // CSINVxxxc |
| 4845U, // CSNEGwwwc |
| 4845U, // CSNEGxxxc |
| 528385U, // DCPS1i |
| 528642U, // DCPS2i |
| 528681U, // DCPS3i |
| 25145U, // DCix |
| 29052U, // DMBi |
| 2432U, // DRPS |
| 29141U, // DSBi |
| 5440U, // EONwww_asr |
| 5440U, // EONwww_lsl |
| 5440U, // EONwww_lsr |
| 5440U, // EONwww_ror |
| 5440U, // EONxxx_asr |
| 5440U, // EONxxx_lsl |
| 5440U, // EONxxx_lsr |
| 5440U, // EONxxx_ror |
| 2283873888U, // EORvvv_16B |
| 2384864864U, // EORvvv_8B |
| 1073747552U, // EORwwi |
| 5728U, // EORwww_asr |
| 5728U, // EORwww_lsl |
| 5728U, // EORwww_lsr |
| 5728U, // EORwww_ror |
| 2147489376U, // EORxxi |
| 5728U, // EORxxx_asr |
| 5728U, // EORxxx_lsl |
| 5728U, // EORxxx_lsr |
| 5728U, // EORxxx_ror |
| 2437U, // ERET |
| 5775U, // EXTRwwwi |
| 5775U, // EXTRxxxi |
| 0U, // F128CSEL |
| 2217157208U, // FABDvvv_2D |
| 2317623896U, // FABDvvv_2S |
| 2250383960U, // FABDvvv_4S |
| 369104579U, // FABSdd |
| 369104579U, // FABSss |
| 2217157296U, // FACGEvvv_2D |
| 2317623984U, // FACGEvvv_2S |
| 2250384048U, // FACGEvvv_4S |
| 2217158471U, // FACGTvvv_2D |
| 2317625159U, // FACGTvvv_2S |
| 2250385223U, // FACGTvvv_4S |
| 2217158034U, // FADDP_2D |
| 2317624722U, // FADDP_2S |
| 2250384786U, // FADDP_4S |
| 270539039U, // FADDPvv_D_2D |
| 404756767U, // FADDPvv_S_2S |
| 4714U, // FADDddd |
| 4714U, // FADDsss |
| 2217157226U, // FADDvvv_2D |
| 2317623914U, // FADDvvv_2S |
| 2250383978U, // FADDvvv_4S |
| 4805U, // FCCMPEdd |
| 4805U, // FCCMPEss |
| 5534U, // FCCMPdd |
| 5534U, // FCCMPss |
| 2217158176U, // FCMEQvvi_2D |
| 2317624864U, // FCMEQvvi_2S |
| 2250384928U, // FCMEQvvi_4S |
| 2217158176U, // FCMEQvvv_2D |
| 2317624864U, // FCMEQvvv_2S |
| 2250384928U, // FCMEQvvv_4S |
| 2217157303U, // FCMGEvvi_2D |
| 2317623991U, // FCMGEvvi_2S |
| 2250384055U, // FCMGEvvi_4S |
| 2217157303U, // FCMGEvvv_2D |
| 2317623991U, // FCMGEvvv_2S |
| 2250384055U, // FCMGEvvv_4S |
| 2217158478U, // FCMGTvvi_2D |
| 2317625166U, // FCMGTvvi_2S |
| 2250385230U, // FCMGTvvi_4S |
| 2217158478U, // FCMGTvvv_2D |
| 2317625166U, // FCMGTvvv_2S |
| 2250385230U, // FCMGTvvv_4S |
| 2217157310U, // FCMLEvvi_2D |
| 2317623998U, // FCMLEvvi_2S |
| 2250384062U, // FCMLEvvi_4S |
| 2217158496U, // FCMLTvvi_2D |
| 2317625184U, // FCMLTvvi_2S |
| 2250385248U, // FCMLTvvi_4S |
| 369104293U, // FCMPdd_quiet |
| 369103565U, // FCMPdd_sig |
| 10491301U, // FCMPdi_quiet |
| 10490573U, // FCMPdi_sig |
| 10491301U, // FCMPsi_quiet |
| 10490573U, // FCMPsi_sig |
| 369104293U, // FCMPss_quiet |
| 369103565U, // FCMPss_sig |
| 5184U, // FCSELdddc |
| 5184U, // FCSELsssc |
| 369104571U, // FCVTASwd |
| 369104571U, // FCVTASws |
| 369104571U, // FCVTASxd |
| 369104571U, // FCVTASxs |
| 369104769U, // FCVTAUwd |
| 369104769U, // FCVTAUws |
| 369104769U, // FCVTAUxd |
| 369104769U, // FCVTAUxs |
| 369104638U, // FCVTMSwd |
| 369104638U, // FCVTMSws |
| 369104638U, // FCVTMSxd |
| 369104638U, // FCVTMSxs |
| 369104785U, // FCVTMUwd |
| 369104785U, // FCVTMUws |
| 369104785U, // FCVTMUxd |
| 369104785U, // FCVTMUxs |
| 369104651U, // FCVTNSwd |
| 369104651U, // FCVTNSws |
| 369104651U, // FCVTNSxd |
| 369104651U, // FCVTNSxs |
| 369104793U, // FCVTNUwd |
| 369104793U, // FCVTNUws |
| 369104793U, // FCVTNUxd |
| 369104793U, // FCVTNUxs |
| 369104667U, // FCVTPSwd |
| 369104667U, // FCVTPSws |
| 369104667U, // FCVTPSxd |
| 369104667U, // FCVTPSxs |
| 369104801U, // FCVTPUwd |
| 369104801U, // FCVTPUws |
| 369104801U, // FCVTPUxd |
| 369104801U, // FCVTPUxs |
| 369104694U, // FCVTZSwd |
| 3221231414U, // FCVTZSwdi |
| 369104694U, // FCVTZSws |
| 3221231414U, // FCVTZSwsi |
| 369104694U, // FCVTZSxd |
| 3221231414U, // FCVTZSxdi |
| 369104694U, // FCVTZSxs |
| 3221231414U, // FCVTZSxsi |
| 369104809U, // FCVTZUwd |
| 3221231529U, // FCVTZUwdi |
| 369104809U, // FCVTZUws |
| 3221231529U, // FCVTZUwsi |
| 369104809U, // FCVTZUxd |
| 3221231529U, // FCVTZUxdi |
| 369104809U, // FCVTZUxs |
| 3221231529U, // FCVTZUxsi |
| 369104763U, // FCVTdh |
| 369104763U, // FCVTds |
| 369104763U, // FCVThd |
| 369104763U, // FCVThs |
| 369104763U, // FCVTsd |
| 369104763U, // FCVTsh |
| 6070U, // FDIVddd |
| 6070U, // FDIVsss |
| 2217158582U, // FDIVvvv_2D |
| 2317625270U, // FDIVvvv_2S |
| 2250385334U, // FDIVvvv_4S |
| 4750U, // FMADDdddd |
| 4750U, // FMADDssss |
| 270539060U, // FMAXNMPvv_D_2D |
| 404756788U, // FMAXNMPvv_S_2S |
| 2217158068U, // FMAXNMPvvv_2D |
| 2317624756U, // FMAXNMPvvv_2S |
| 2250384820U, // FMAXNMPvvv_4S |
| 5377U, // FMAXNMddd |
| 5377U, // FMAXNMsss |
| 2217157889U, // FMAXNMvvv_2D |
| 2317624577U, // FMAXNMvvv_2S |
| 2250384641U, // FMAXNMvvv_4S |
| 270539076U, // FMAXPvv_D_2D |
| 404756804U, // FMAXPvv_S_2S |
| 2217158136U, // FMAXPvvv_2D |
| 2317624824U, // FMAXPvvv_2S |
| 2250384888U, // FMAXPvvv_4S |
| 6202U, // FMAXddd |
| 6202U, // FMAXsss |
| 2217158714U, // FMAXvvv_2D |
| 2317625402U, // FMAXvvv_2S |
| 2250385466U, // FMAXvvv_4S |
| 270539051U, // FMINNMPvv_D_2D |
| 404756779U, // FMINNMPvv_S_2S |
| 2217158059U, // FMINNMPvvv_2D |
| 2317624747U, // FMINNMPvvv_2S |
| 2250384811U, // FMINNMPvvv_4S |
| 5369U, // FMINNMddd |
| 5369U, // FMINNMsss |
| 2217157881U, // FMINNMvvv_2D |
| 2317624569U, // FMINNMvvv_2S |
| 2250384633U, // FMINNMvvv_4S |
| 270539069U, // FMINPvv_D_2D |
| 404756797U, // FMINPvv_S_2S |
| 2217158083U, // FMINPvvv_2D |
| 2317624771U, // FMINPvvv_2S |
| 2250384835U, // FMINPvvv_4S |
| 5416U, // FMINddd |
| 5416U, // FMINsss |
| 2217157928U, // FMINvvv_2D |
| 2317624616U, // FMINvvv_2S |
| 2250384680U, // FMINvvv_4S |
| 1142366531U, // FMLAvvv_2D |
| 1242833219U, // FMLAvvv_2S |
| 1175593283U, // FMLAvvv_4S |
| 1142367992U, // FMLSvvv_2D |
| 1242834680U, // FMLSvvv_2S |
| 1175594744U, // FMLSvvv_4S |
| 369104847U, // FMOVdd |
| 11540431U, // FMOVdi |
| 369104847U, // FMOVdx |
| 11540431U, // FMOVsi |
| 369104847U, // FMOVss |
| 369104847U, // FMOVsw |
| 12003279U, // FMOVvi_2D |
| 11806671U, // FMOVvi_2S |
| 11675599U, // FMOVvi_4S |
| 13182927U, // FMOVvx |
| 369104847U, // FMOVws |
| 369104847U, // FMOVxd |
| 438310863U, // FMOVxv |
| 4630U, // FMSUBdddd |
| 4630U, // FMSUBssss |
| 2217158760U, // FMULXvvv_2D |
| 2317625448U, // FMULXvvv_2S |
| 2250385512U, // FMULXvvv_4S |
| 5332U, // FMULddd |
| 5332U, // FMULsss |
| 2217157844U, // FMULvvv_2D |
| 2317624532U, // FMULvvv_2S |
| 2250384596U, // FMULvvv_4S |
| 369103591U, // FNEGdd |
| 369103591U, // FNEGss |
| 4757U, // FNMADDdddd |
| 4757U, // FNMADDssss |
| 4637U, // FNMSUBdddd |
| 4637U, // FNMSUBssss |
| 5338U, // FNMULddd |
| 5338U, // FNMULsss |
| 2217158419U, // FRECPSvvv_2D |
| 2317625107U, // FRECPSvvv_2S |
| 2250385171U, // FRECPSvvv_4S |
| 369103203U, // FRINTAdd |
| 369103203U, // FRINTAss |
| 369103800U, // FRINTIdd |
| 369103800U, // FRINTIss |
| 369104137U, // FRINTMdd |
| 369104137U, // FRINTMss |
| 369104236U, // FRINTNdd |
| 369104236U, // FRINTNss |
| 369104356U, // FRINTPdd |
| 369104356U, // FRINTPss |
| 369105007U, // FRINTXdd |
| 369105007U, // FRINTXss |
| 369105056U, // FRINTZdd |
| 369105056U, // FRINTZss |
| 2217158440U, // FRSQRTSvvv_2D |
| 2317625128U, // FRSQRTSvvv_2S |
| 2250385192U, // FRSQRTSvvv_4S |
| 369104749U, // FSQRTdd |
| 369104749U, // FSQRTss |
| 4610U, // FSUBddd |
| 4610U, // FSUBsss |
| 2217157122U, // FSUBvvv_2D |
| 2317623810U, // FSUBvvv_2S |
| 2250383874U, // FSUBvvv_4S |
| 530279U, // HINTi |
| 530267U, // HLTi |
| 528974U, // HVCi |
| 557630U, // ICi |
| 369132094U, // ICix |
| 1545217798U, // INSELb |
| 517547782U, // INSELd |
| 1612392198U, // INSELh |
| 1646012166U, // INSELs |
| 377104134U, // INSbw |
| 618211078U, // INSdx |
| 377169670U, // INShw |
| 377235206U, // INSsw |
| 37338U, // ISBi |
| 638390657U, // LDAR_byte |
| 638391847U, // LDAR_dword |
| 638391078U, // LDAR_hword |
| 638391847U, // LDAR_word |
| 671094257U, // LDAXP_dword |
| 671094257U, // LDAXP_word |
| 638390711U, // LDAXR_byte |
| 638391969U, // LDAXR_dword |
| 638391132U, // LDAXR_hword |
| 638391969U, // LDAXR_word |
| 671094798U, // LDPSWx |
| 1744836622U, // LDPSWx_PostInd |
| 1744836622U, // LDPSWx_PreInd |
| 2148340191U, // LDRSBw |
| 712839647U, // LDRSBw_PostInd |
| 3229422047U, // LDRSBw_PreInd |
| 856558U, // LDRSBw_U |
| 856543U, // LDRSBw_Wm_RegOffset |
| 856543U, // LDRSBw_Xm_RegOffset |
| 2148340191U, // LDRSBx |
| 712839647U, // LDRSBx_PostInd |
| 3229422047U, // LDRSBx_PreInd |
| 856558U, // LDRSBx_U |
| 856543U, // LDRSBx_Wm_RegOffset |
| 856543U, // LDRSBx_Xm_RegOffset |
| 1074598778U, // LDRSHw |
| 712840058U, // LDRSHw_PostInd |
| 3229422458U, // LDRSHw_PreInd |
| 856969U, // LDRSHw_U |
| 856954U, // LDRSHw_Wm_RegOffset |
| 856954U, // LDRSHw_Xm_RegOffset |
| 1074598778U, // LDRSHx |
| 712840058U, // LDRSHx_PostInd |
| 3229422458U, // LDRSHx_PreInd |
| 856969U, // LDRSHx_U |
| 856954U, // LDRSHx_Wm_RegOffset |
| 856954U, // LDRSHx_Xm_RegOffset |
| 2148341781U, // LDRSWx |
| 712841237U, // LDRSWx_PostInd |
| 3229423637U, // LDRSWx_PreInd |
| 858133U, // LDRSWx_Wm_RegOffset |
| 858133U, // LDRSWx_Xm_RegOffset |
| 9443349U, // LDRSWx_lit |
| 9442870U, // LDRd_lit |
| 9442870U, // LDRq_lit |
| 9442870U, // LDRs_lit |
| 9442870U, // LDRw_lit |
| 9442870U, // LDRx_lit |
| 856550U, // LDTRSBw |
| 856550U, // LDTRSBx |
| 856961U, // LDTRSHw |
| 856961U, // LDTRSHx |
| 858140U, // LDTRSWx |
| 858148U, // LDURSWx |
| 671094285U, // LDXP_dword |
| 671094285U, // LDXP_word |
| 638390719U, // LDXR_byte |
| 638391976U, // LDXR_dword |
| 638391140U, // LDXR_hword |
| 638391976U, // LDXR_word |
| 1074598701U, // LS16_LDR |
| 856910U, // LS16_LDUR |
| 712839981U, // LS16_PostInd_LDR |
| 712876865U, // LS16_PostInd_STR |
| 3229422381U, // LS16_PreInd_LDR |
| 3229459265U, // LS16_PreInd_STR |
| 1074598721U, // LS16_STR |
| 856917U, // LS16_STUR |
| 856890U, // LS16_UnPriv_LDR |
| 856903U, // LS16_UnPriv_STR |
| 856877U, // LS16_Wm_RegOffset_LDR |
| 856897U, // LS16_Wm_RegOffset_STR |
| 856877U, // LS16_Xm_RegOffset_LDR |
| 856897U, // LS16_Xm_RegOffset_STR |
| 2148341302U, // LS32_LDR |
| 857749U, // LS32_LDUR |
| 712840758U, // LS32_PostInd_LDR |
| 712877700U, // LS32_PostInd_STR |
| 3229423158U, // LS32_PreInd_LDR |
| 3229460100U, // LS32_PreInd_STR |
| 2148341380U, // LS32_STR |
| 857755U, // LS32_STUR |
| 857726U, // LS32_UnPriv_LDR |
| 857737U, // LS32_UnPriv_STR |
| 857654U, // LS32_Wm_RegOffset_LDR |
| 857732U, // LS32_Wm_RegOffset_STR |
| 857654U, // LS32_Xm_RegOffset_LDR |
| 857732U, // LS32_Xm_RegOffset_STR |
| 3222083126U, // LS64_LDR |
| 857749U, // LS64_LDUR |
| 712840758U, // LS64_PostInd_LDR |
| 712877700U, // LS64_PostInd_STR |
| 3229423158U, // LS64_PreInd_LDR |
| 3229460100U, // LS64_PreInd_STR |
| 3222083204U, // LS64_STR |
| 857755U, // LS64_STUR |
| 857726U, // LS64_UnPriv_LDR |
| 857737U, // LS64_UnPriv_STR |
| 857654U, // LS64_Wm_RegOffset_LDR |
| 857732U, // LS64_Wm_RegOffset_STR |
| 857654U, // LS64_Xm_RegOffset_LDR |
| 857732U, // LS64_Xm_RegOffset_STR |
| 2148340104U, // LS8_LDR |
| 856489U, // LS8_LDUR |
| 712839560U, // LS8_PostInd_LDR |
| 712876444U, // LS8_PostInd_STR |
| 3229421960U, // LS8_PreInd_LDR |
| 3229458844U, // LS8_PreInd_STR |
| 2148340124U, // LS8_STR |
| 856496U, // LS8_STUR |
| 856469U, // LS8_UnPriv_LDR |
| 856482U, // LS8_UnPriv_STR |
| 856456U, // LS8_Wm_RegOffset_LDR |
| 856476U, // LS8_Wm_RegOffset_STR |
| 856456U, // LS8_Xm_RegOffset_LDR |
| 856476U, // LS8_Xm_RegOffset_STR |
| 857654U, // LSFP128_LDR |
| 857749U, // LSFP128_LDUR |
| 712840758U, // LSFP128_PostInd_LDR |
| 712877700U, // LSFP128_PostInd_STR |
| 3229423158U, // LSFP128_PreInd_LDR |
| 3229460100U, // LSFP128_PreInd_STR |
| 857732U, // LSFP128_STR |
| 857755U, // LSFP128_STUR |
| 857654U, // LSFP128_Wm_RegOffset_LDR |
| 857732U, // LSFP128_Wm_RegOffset_STR |
| 857654U, // LSFP128_Xm_RegOffset_LDR |
| 857732U, // LSFP128_Xm_RegOffset_STR |
| 1074599478U, // LSFP16_LDR |
| 857749U, // LSFP16_LDUR |
| 712840758U, // LSFP16_PostInd_LDR |
| 712877700U, // LSFP16_PostInd_STR |
| 3229423158U, // LSFP16_PreInd_LDR |
| 3229460100U, // LSFP16_PreInd_STR |
| 1074599556U, // LSFP16_STR |
| 857755U, // LSFP16_STUR |
| 857654U, // LSFP16_Wm_RegOffset_LDR |
| 857732U, // LSFP16_Wm_RegOffset_STR |
| 857654U, // LSFP16_Xm_RegOffset_LDR |
| 857732U, // LSFP16_Xm_RegOffset_STR |
| 2148341302U, // LSFP32_LDR |
| 857749U, // LSFP32_LDUR |
| 712840758U, // LSFP32_PostInd_LDR |
| 712877700U, // LSFP32_PostInd_STR |
| 3229423158U, // LSFP32_PreInd_LDR |
| 3229460100U, // LSFP32_PreInd_STR |
| 2148341380U, // LSFP32_STR |
| 857755U, // LSFP32_STUR |
| 857654U, // LSFP32_Wm_RegOffset_LDR |
| 857732U, // LSFP32_Wm_RegOffset_STR |
| 857654U, // LSFP32_Xm_RegOffset_LDR |
| 857732U, // LSFP32_Xm_RegOffset_STR |
| 3222083126U, // LSFP64_LDR |
| 857749U, // LSFP64_LDUR |
| 712840758U, // LSFP64_PostInd_LDR |
| 712877700U, // LSFP64_PostInd_STR |
| 3229423158U, // LSFP64_PreInd_LDR |
| 3229460100U, // LSFP64_PreInd_STR |
| 3222083204U, // LSFP64_STR |
| 857755U, // LSFP64_STUR |
| 857654U, // LSFP64_Wm_RegOffset_LDR |
| 857732U, // LSFP64_Wm_RegOffset_STR |
| 857654U, // LSFP64_Xm_RegOffset_LDR |
| 857732U, // LSFP64_Xm_RegOffset_STR |
| 2148341302U, // LSFP8_LDR |
| 857749U, // LSFP8_LDUR |
| 712840758U, // LSFP8_PostInd_LDR |
| 712877700U, // LSFP8_PostInd_STR |
| 3229423158U, // LSFP8_PreInd_LDR |
| 3229460100U, // LSFP8_PreInd_STR |
| 2148341380U, // LSFP8_STR |
| 857755U, // LSFP8_STUR |
| 857654U, // LSFP8_Wm_RegOffset_LDR |
| 857732U, // LSFP8_Wm_RegOffset_STR |
| 857654U, // LSFP8_Xm_RegOffset_LDR |
| 857732U, // LSFP8_Xm_RegOffset_STR |
| 671094169U, // LSFPPair128_LDR |
| 671094205U, // LSFPPair128_NonTemp_LDR |
| 671094232U, // LSFPPair128_NonTemp_STR |
| 1744835993U, // LSFPPair128_PostInd_LDR |
| 1752212972U, // LSFPPair128_PostInd_STR |
| 1744835993U, // LSFPPair128_PreInd_LDR |
| 1752212972U, // LSFPPair128_PreInd_STR |
| 671094252U, // LSFPPair128_STR |
| 671094169U, // LSFPPair32_LDR |
| 671094205U, // LSFPPair32_NonTemp_LDR |
| 671094232U, // LSFPPair32_NonTemp_STR |
| 1744835993U, // LSFPPair32_PostInd_LDR |
| 1752212972U, // LSFPPair32_PostInd_STR |
| 1744835993U, // LSFPPair32_PreInd_LDR |
| 1752212972U, // LSFPPair32_PreInd_STR |
| 671094252U, // LSFPPair32_STR |
| 671094169U, // LSFPPair64_LDR |
| 671094205U, // LSFPPair64_NonTemp_LDR |
| 671094232U, // LSFPPair64_NonTemp_STR |
| 1744835993U, // LSFPPair64_PostInd_LDR |
| 1752212972U, // LSFPPair64_PostInd_STR |
| 1744835993U, // LSFPPair64_PreInd_LDR |
| 1752212972U, // LSFPPair64_PreInd_STR |
| 671094252U, // LSFPPair64_STR |
| 5307U, // LSLVwww |
| 5307U, // LSLVxxx |
| 5307U, // LSLwwi |
| 5307U, // LSLxxi |
| 671094169U, // LSPair32_LDR |
| 671094205U, // LSPair32_NonTemp_LDR |
| 671094232U, // LSPair32_NonTemp_STR |
| 1744835993U, // LSPair32_PostInd_LDR |
| 1752212972U, // LSPair32_PostInd_STR |
| 1744835993U, // LSPair32_PreInd_LDR |
| 1752212972U, // LSPair32_PreInd_STR |
| 671094252U, // LSPair32_STR |
| 671094169U, // LSPair64_LDR |
| 671094205U, // LSPair64_NonTemp_LDR |
| 671094232U, // LSPair64_NonTemp_STR |
| 1744835993U, // LSPair64_PostInd_LDR |
| 1752212972U, // LSPair64_PostInd_STR |
| 1744835993U, // LSPair64_PreInd_LDR |
| 1752212972U, // LSPair64_PreInd_STR |
| 671094252U, // LSPair64_STR |
| 5748U, // LSRVwww |
| 5748U, // LSRVxxx |
| 5748U, // LSRwwi |
| 5748U, // LSRxxi |
| 4751U, // MADDwwww |
| 4751U, // MADDxxxx |
| 1209082180U, // MLAvvv_16B |
| 1242833220U, // MLAvvv_2S |
| 1276453188U, // MLAvvv_4H |
| 1175593284U, // MLAvvv_4S |
| 1310073156U, // MLAvvv_8B |
| 1108549956U, // MLAvvv_8H |
| 1209083641U, // MLSvvv_16B |
| 1242834681U, // MLSvvv_2S |
| 1276454649U, // MLSvvv_4H |
| 1175594745U, // MLSvvv_4S |
| 1310074617U, // MLSvvv_8B |
| 1108551417U, // MLSvvv_8H |
| 14686382U, // MOVIdi |
| 384902080U, // MOVIvi_16B |
| 15149230U, // MOVIvi_2D |
| 385229760U, // MOVIvi_8B |
| 754198748U, // MOVIvi_lsl_2S |
| 787818716U, // MOVIvi_lsl_4H |
| 754067676U, // MOVIvi_lsl_4S |
| 787687644U, // MOVIvi_lsl_8H |
| 821307612U, // MOVIvi_msl_2S |
| 821176540U, // MOVIvi_msl_4S |
| 16782283U, // MOVKwii |
| 16782283U, // MOVKxii |
| 17831308U, // MOVNwii |
| 17831308U, // MOVNxii |
| 17832104U, // MOVZwii |
| 17832104U, // MOVZxii |
| 18880291U, // MRSxi |
| 46713U, // MSRii |
| 50809U, // MSRix |
| 4631U, // MSUBwwww |
| 4631U, // MSUBxxxx |
| 2283873493U, // MULvvv_16B |
| 2317624533U, // MULvvv_2S |
| 2351244501U, // MULvvv_4H |
| 2250384597U, // MULvvv_4S |
| 2384864469U, // MULvvv_8B |
| 2183341269U, // MULvvv_8H |
| 754198742U, // MVNIvi_lsl_2S |
| 787818710U, // MVNIvi_lsl_4H |
| 754067670U, // MVNIvi_lsl_4S |
| 787687638U, // MVNIvi_lsl_8H |
| 821307606U, // MVNIvi_msl_2S |
| 821176534U, // MVNIvi_msl_4S |
| 3221230983U, // MVNww_asr |
| 5511U, // MVNww_lsl |
| 1073747335U, // MVNww_lsr |
| 1073747335U, // MVNww_ror |
| 3221230983U, // MVNxx_asr |
| 5511U, // MVNxx_lsl |
| 1073747335U, // MVNxx_lsr |
| 1073747335U, // MVNxx_ror |
| 2283873639U, // ORNvvv_16B |
| 2384864615U, // ORNvvv_8B |
| 5479U, // ORNwww_asr |
| 5479U, // ORNwww_lsl |
| 5479U, // ORNwww_lsr |
| 5479U, // ORNwww_ror |
| 5479U, // ORNxxx_asr |
| 5479U, // ORNxxx_lsl |
| 5479U, // ORNxxx_lsr |
| 5479U, // ORNxxx_ror |
| 310651211U, // ORRvi_lsl_2S |
| 344271179U, // ORRvi_lsl_4H |
| 310520139U, // ORRvi_lsl_4S |
| 344140107U, // ORRvi_lsl_8H |
| 2283873898U, // ORRvvv_16B |
| 2384864874U, // ORRvvv_8B |
| 1073747562U, // ORRwwi |
| 5738U, // ORRwww_asr |
| 5738U, // ORRwww_lsl |
| 5738U, // ORRwww_lsr |
| 5738U, // ORRwww_ror |
| 2147489386U, // ORRxxi |
| 5738U, // ORRxxx_asr |
| 5738U, // ORRxxx_lsl |
| 5738U, // ORRxxx_lsr |
| 5738U, // ORRxxx_ror |
| 2284003459U, // PMULL2vvv_8h16b |
| 2384667805U, // PMULLvvv_8h8b |
| 2283873505U, // PMULvvv_16B |
| 2384864481U, // PMULvvv_8B |
| 3222131955U, // PRFM |
| 906483U, // PRFM_Wm_RegOffset |
| 906483U, // PRFM_Xm_RegOffset |
| 9491699U, // PRFM_lit |
| 906513U, // PRFUM |
| 1108418807U, // QRSHRUNvvi_16B |
| 69477757U, // QRSHRUNvvi_2S |
| 103097725U, // QRSHRUNvvi_4H |
| 1142038775U, // QRSHRUNvvi_4S |
| 36054397U, // QRSHRUNvvi_8B |
| 1175658743U, // QRSHRUNvvi_8H |
| 1108418797U, // QSHRUNvvi_16B |
| 69477748U, // QSHRUNvvi_2S |
| 103097716U, // QSHRUNvvi_4H |
| 1142038765U, // QSHRUNvvi_4S |
| 36054388U, // QSHRUNvvi_8B |
| 1175658733U, // QSHRUNvvi_8H |
| 1108418750U, // RADDHN2vvv_16b8h |
| 1142038718U, // RADDHN2vvv_4s2d |
| 1175658686U, // RADDHN2vvv_8h4s |
| 2216961312U, // RADDHNvvv_2s2d |
| 2250581280U, // RADDHNvvv_4h4s |
| 2183537952U, // RADDHNvvv_8b8h |
| 369104725U, // RBITww |
| 369104725U, // RBITxx |
| 0U, // RET |
| 530242U, // RETx |
| 369103152U, // REV16ww |
| 369103152U, // REV16xx |
| 369102856U, // REV32xx |
| 369104817U, // REVww |
| 369104817U, // REVxx |
| 5733U, // RORVwww |
| 5733U, // RORVxxx |
| 1108418779U, // RSHRNvvi_16B |
| 69477719U, // RSHRNvvi_2S |
| 103097687U, // RSHRNvvi_4H |
| 1142038747U, // RSHRNvvi_4S |
| 36054359U, // RSHRNvvi_8B |
| 1175658715U, // RSHRNvvi_8H |
| 1108418741U, // RSUBHN2vvv_16b8h |
| 1142038709U, // RSUBHN2vvv_4s2d |
| 1175658677U, // RSUBHN2vvv_8h4s |
| 2216961304U, // RSUBHNvvv_2s2d |
| 2250581272U, // RSUBHNvvv_4h4s |
| 2183537944U, // RSUBHNvvv_8b8h |
| 1175920655U, // SABAL2vvv_2d2s |
| 1108484111U, // SABAL2vvv_4s4h |
| 1209212943U, // SABAL2vvv_8h8b |
| 1243030481U, // SABALvvv_2d2s |
| 1276257233U, // SABALvvv_4s4h |
| 1309877201U, // SABALvvv_8h8b |
| 1209082167U, // SABAvvv_16B |
| 1242833207U, // SABAvvv_2S |
| 1276453175U, // SABAvvv_4H |
| 1175593271U, // SABAvvv_4S |
| 1310073143U, // SABAvvv_8B |
| 1108549943U, // SABAvvv_8H |
| 2250711113U, // SABDL2vvv_2d2s |
| 2183274569U, // SABDL2vvv_4s4h |
| 2284003401U, // SABDL2vvv_8h8b |
| 2317820948U, // SABDLvvv_2d2s |
| 2351047700U, // SABDLvvv_4s4h |
| 2384667668U, // SABDLvvv_8h8b |
| 2283872862U, // SABDvvv_16B |
| 2317623902U, // SABDvvv_2S |
| 2351243870U, // SABDvvv_4H |
| 2250383966U, // SABDvvv_4S |
| 2384863838U, // SABDvvv_8B |
| 2183340638U, // SABDvvv_8H |
| 2250711129U, // SADDL2vvv_2d4s |
| 2183274585U, // SADDL2vvv_4s8h |
| 2284003417U, // SADDL2vvv_8h16b |
| 2317820978U, // SADDLvvv_2d2s |
| 2351047730U, // SADDLvvv_4s4h |
| 2384667698U, // SADDLvvv_8h8b |
| 2217156889U, // SADDW2vvv_2d4s |
| 2250383641U, // SADDW2vvv_4s8h |
| 2183340313U, // SADDW2vvv_8h16b |
| 2217158656U, // SADDWvvv_2d2s |
| 2250385408U, // SADDWvvv_4s4h |
| 2183342080U, // SADDWvvv_8h8b |
| 5839U, // SBCSwww |
| 5839U, // SBCSxxx |
| 4659U, // SBCwww |
| 4659U, // SBCxxx |
| 2147489921U, // SBFIZwwii |
| 3221231745U, // SBFIZxxii |
| 5351U, // SBFMwwii |
| 5351U, // SBFMxxii |
| 6236U, // SBFXwwii |
| 6236U, // SBFXxxii |
| 369103577U, // SCVTFdw |
| 3221230297U, // SCVTFdwi |
| 369103577U, // SCVTFdx |
| 3221230297U, // SCVTFdxi |
| 369103577U, // SCVTFsw |
| 3221230297U, // SCVTFswi |
| 369103577U, // SCVTFsx |
| 3221230297U, // SCVTFsxi |
| 6076U, // SDIVwww |
| 6076U, // SDIVxxx |
| 2283872896U, // SHADDvvv_16B |
| 2317623936U, // SHADDvvv_2S |
| 2351243904U, // SHADDvvv_4H |
| 2250384000U, // SHADDvvv_4S |
| 2384863872U, // SHADDvvv_8B |
| 2183340672U, // SHADDvvv_8H |
| 136389705U, // SHLvvi_16B |
| 69674057U, // SHLvvi_2D |
| 170140745U, // SHLvvi_2S |
| 203760713U, // SHLvvi_4H |
| 102900809U, // SHLvvi_4S |
| 237380681U, // SHLvvi_8B |
| 35857481U, // SHLvvi_8H |
| 1108418761U, // SHRNvvi_16B |
| 69477703U, // SHRNvvi_2S |
| 103097671U, // SHRNvvi_4H |
| 1142038729U, // SHRNvvi_4S |
| 36054343U, // SHRNvvi_8B |
| 1175658697U, // SHRNvvi_8H |
| 2283872776U, // SHSUBvvv_16B |
| 2317623816U, // SHSUBvvv_2S |
| 2351243784U, // SHSUBvvv_4H |
| 2250383880U, // SHSUBvvv_4S |
| 2384863752U, // SHSUBvvv_8B |
| 2183340552U, // SHSUBvvv_8H |
| 1209082798U, // SLIvvi_16B |
| 1142367150U, // SLIvvi_2D |
| 1242833838U, // SLIvvi_2S |
| 1276453806U, // SLIvvi_4H |
| 1175593902U, // SLIvvi_4S |
| 1310073774U, // SLIvvi_8B |
| 1108550574U, // SLIvvi_8H |
| 5154U, // SMADDLxwwx |
| 2283873791U, // SMAXPvvv_16B |
| 2317624831U, // SMAXPvvv_2S |
| 2351244799U, // SMAXPvvv_4H |
| 2250384895U, // SMAXPvvv_4S |
| 2384864767U, // SMAXPvvv_8B |
| 2183341567U, // SMAXPvvv_8H |
| 2283874368U, // SMAXvvv_16B |
| 2317625408U, // SMAXvvv_2S |
| 2351245376U, // SMAXvvv_4H |
| 2250385472U, // SMAXvvv_4S |
| 2384865344U, // SMAXvvv_8B |
| 2183342144U, // SMAXvvv_8H |
| 528962U, // SMCi |
| 2283873738U, // SMINPvvv_16B |
| 2317624778U, // SMINPvvv_2S |
| 2351244746U, // SMINPvvv_4H |
| 2250384842U, // SMINPvvv_4S |
| 2384864714U, // SMINPvvv_8B |
| 2183341514U, // SMINPvvv_8H |
| 2283873582U, // SMINvvv_16B |
| 2317624622U, // SMINvvv_2S |
| 2351244590U, // SMINvvv_4H |
| 2250384686U, // SMINvvv_4S |
| 2384864558U, // SMINvvv_8B |
| 2183341358U, // SMINvvv_8H |
| 1175920681U, // SMLAL2vvv_2d4s |
| 1108484137U, // SMLAL2vvv_4s8h |
| 1209212969U, // SMLAL2vvv_8h16b |
| 1243030504U, // SMLALvvv_2d2s |
| 1276257256U, // SMLALvvv_4s4h |
| 1309877224U, // SMLALvvv_8h8b |
| 1175920805U, // SMLSL2vvv_2d4s |
| 1108484261U, // SMLSL2vvv_4s8h |
| 1209213093U, // SMLSL2vvv_8h16b |
| 1243030720U, // SMLSLvvv_2d2s |
| 1276257472U, // SMLSLvvv_4s4h |
| 1309877440U, // SMLSLvvv_8h8b |
| 471865301U, // SMOVwb |
| 538974165U, // SMOVwh |
| 471865301U, // SMOVxb |
| 538974165U, // SMOVxh |
| 572528597U, // SMOVxs |
| 5110U, // SMSUBLxwwx |
| 4888U, // SMULHxxx |
| 2250711179U, // SMULL2vvv_2d4s |
| 2183274635U, // SMULL2vvv_4s8h |
| 2284003467U, // SMULL2vvv_8h16b |
| 2317821092U, // SMULLvvv_2d2s |
| 2351047844U, // SMULLvvv_4s4h |
| 2384667812U, // SMULLvvv_8h8b |
| 6344U, // SQADDbbb |
| 6344U, // SQADDddd |
| 6344U, // SQADDhhh |
| 6344U, // SQADDsss |
| 2283872925U, // SQADDvvv_16B |
| 2217157277U, // SQADDvvv_2D |
| 2317623965U, // SQADDvvv_2S |
| 2351243933U, // SQADDvvv_4H |
| 2250384029U, // SQADDvvv_4S |
| 2384863901U, // SQADDvvv_8B |
| 2183340701U, // SQADDvvv_8H |
| 1175920671U, // SQDMLAL2vvv_2d4s |
| 1108484127U, // SQDMLAL2vvv_4s8h |
| 1243030495U, // SQDMLALvvv_2d2s |
| 1276257247U, // SQDMLALvvv_4s4h |
| 1175920795U, // SQDMLSL2vvv_2d4s |
| 1108484251U, // SQDMLSL2vvv_4s8h |
| 1243030711U, // SQDMLSLvvv_2d2s |
| 1276257463U, // SQDMLSLvvv_4s4h |
| 2317624069U, // SQDMULHvvv_2S |
| 2351244037U, // SQDMULHvvv_4H |
| 2250384133U, // SQDMULHvvv_4S |
| 2183340805U, // SQDMULHvvv_8H |
| 2250711161U, // SQDMULL2vvv_2d4s |
| 2183274617U, // SQDMULL2vvv_4s8h |
| 2317821076U, // SQDMULLvvv_2d2s |
| 2351047828U, // SQDMULLvvv_4s4h |
| 2317624078U, // SQRDMULHvvv_2S |
| 2351244046U, // SQRDMULHvvv_4H |
| 2250384142U, // SQRDMULHvvv_4S |
| 2183340814U, // SQRDMULHvvv_8H |
| 6384U, // SQRSHLbbb |
| 6384U, // SQRSHLddd |
| 6384U, // SQRSHLhhh |
| 6384U, // SQRSHLsss |
| 2283873365U, // SQRSHLvvv_16B |
| 2217157717U, // SQRSHLvvv_2D |
| 2317624405U, // SQRSHLvvv_2S |
| 2351244373U, // SQRSHLvvv_4H |
| 2250384469U, // SQRSHLvvv_4S |
| 2384864341U, // SQRSHLvvv_8B |
| 2183341141U, // SQRSHLvvv_8H |
| 1108418777U, // SQRSHRNvvi_16B |
| 69477717U, // SQRSHRNvvi_2S |
| 103097685U, // SQRSHRNvvi_4H |
| 1142038745U, // SQRSHRNvvi_4S |
| 36054357U, // SQRSHRNvvi_8B |
| 1175658713U, // SQRSHRNvvi_8H |
| 136390537U, // SQSHLUvvi_16B |
| 69674889U, // SQSHLUvvi_2D |
| 170141577U, // SQSHLUvvi_2S |
| 203761545U, // SQSHLUvvi_4H |
| 102901641U, // SQSHLUvvi_4S |
| 237381513U, // SQSHLUvvi_8B |
| 35858313U, // SQSHLUvvi_8H |
| 6370U, // SQSHLbbb |
| 6370U, // SQSHLddd |
| 6370U, // SQSHLhhh |
| 6370U, // SQSHLsss |
| 136389703U, // SQSHLvvi_16B |
| 69674055U, // SQSHLvvi_2D |
| 170140743U, // SQSHLvvi_2S |
| 203760711U, // SQSHLvvi_4H |
| 102900807U, // SQSHLvvi_4S |
| 237380679U, // SQSHLvvi_8B |
| 35857479U, // SQSHLvvi_8H |
| 2283873351U, // SQSHLvvv_16B |
| 2217157703U, // SQSHLvvv_2D |
| 2317624391U, // SQSHLvvv_2S |
| 2351244359U, // SQSHLvvv_4H |
| 2250384455U, // SQSHLvvv_4S |
| 2384864327U, // SQSHLvvv_8B |
| 2183341127U, // SQSHLvvv_8H |
| 1108418759U, // SQSHRNvvi_16B |
| 69477701U, // SQSHRNvvi_2S |
| 103097669U, // SQSHRNvvi_4H |
| 1142038727U, // SQSHRNvvi_4S |
| 36054341U, // SQSHRNvvi_8B |
| 1175658695U, // SQSHRNvvi_8H |
| 6325U, // SQSUBbbb |
| 6325U, // SQSUBddd |
| 6325U, // SQSUBhhh |
| 6325U, // SQSUBsss |
| 2283872805U, // SQSUBvvv_16B |
| 2217157157U, // SQSUBvvv_2D |
| 2317623845U, // SQSUBvvv_2S |
| 2351243813U, // SQSUBvvv_4H |
| 2250383909U, // SQSUBvvv_4S |
| 2384863781U, // SQSUBvvv_8B |
| 2183340581U, // SQSUBvvv_8H |
| 2283872880U, // SRHADDvvv_16B |
| 2317623920U, // SRHADDvvv_2S |
| 2351243888U, // SRHADDvvv_4H |
| 2250383984U, // SRHADDvvv_4S |
| 2384863856U, // SRHADDvvv_8B |
| 2183340656U, // SRHADDvvv_8H |
| 1209082803U, // SRIvvi_16B |
| 1142367155U, // SRIvvi_2D |
| 1242833843U, // SRIvvi_2S |
| 1276453811U, // SRIvvi_4H |
| 1175593907U, // SRIvvi_4S |
| 1310073779U, // SRIvvi_8B |
| 1108550579U, // SRIvvi_8H |
| 6400U, // SRSHLddd |
| 2283873381U, // SRSHLvvv_16B |
| 2217157733U, // SRSHLvvv_2D |
| 2317624421U, // SRSHLvvv_2S |
| 2351244389U, // SRSHLvvv_4H |
| 2250384485U, // SRSHLvvv_4S |
| 2384864357U, // SRSHLvvv_8B |
| 2183341157U, // SRSHLvvv_8H |
| 136390203U, // SRSHRvvi_16B |
| 69674555U, // SRSHRvvi_2D |
| 170141243U, // SRSHRvvi_2S |
| 203761211U, // SRSHRvvi_4H |
| 102901307U, // SRSHRvvi_4S |
| 237381179U, // SRSHRvvi_8B |
| 35857979U, // SRSHRvvi_8H |
| 1209082185U, // SRSRAvvi_16B |
| 1142366537U, // SRSRAvvi_2D |
| 1242833225U, // SRSRAvvi_2S |
| 1276453193U, // SRSRAvvi_4H |
| 1175593289U, // SRSRAvvi_4S |
| 1310073161U, // SRSRAvvi_8B |
| 1108549961U, // SRSRAvvi_8H |
| 136519785U, // SSHLLvvi_16B |
| 170337414U, // SSHLLvvi_2S |
| 203564166U, // SSHLLvvi_4H |
| 103227497U, // SSHLLvvi_4S |
| 237184134U, // SSHLLvvi_8B |
| 35790953U, // SSHLLvvi_8H |
| 6414U, // SSHLddd |
| 2283873395U, // SSHLvvv_16B |
| 2217157747U, // SSHLvvv_2D |
| 2317624435U, // SSHLvvv_2S |
| 2351244403U, // SSHLvvv_4H |
| 2250384499U, // SSHLvvv_4S |
| 2384864371U, // SSHLvvv_8B |
| 2183341171U, // SSHLvvv_8H |
| 136390217U, // SSHRvvi_16B |
| 69674569U, // SSHRvvi_2D |
| 170141257U, // SSHRvvi_2S |
| 203761225U, // SSHRvvi_4H |
| 102901321U, // SSHRvvi_4S |
| 237381193U, // SSHRvvi_8B |
| 35857993U, // SSHRvvi_8H |
| 1209082199U, // SSRAvvi_16B |
| 1142366551U, // SSRAvvi_2D |
| 1242833239U, // SSRAvvi_2S |
| 1276453207U, // SSRAvvi_4H |
| 1175593303U, // SSRAvvi_4S |
| 1310073175U, // SSRAvvi_8B |
| 1108549975U, // SSRAvvi_8H |
| 2250711097U, // SSUBL2vvv_2d4s |
| 2183274553U, // SSUBL2vvv_4s8h |
| 2284003385U, // SSUBL2vvv_8h16b |
| 2317820934U, // SSUBLvvv_2d2s |
| 2351047686U, // SSUBLvvv_4s4h |
| 2384667654U, // SSUBLvvv_8h8b |
| 2217156873U, // SSUBW2vvv_2d4s |
| 2250383625U, // SSUBW2vvv_4s8h |
| 2183340297U, // SSUBW2vvv_8h16b |
| 2217158633U, // SSUBWvvv_2d2s |
| 2250385385U, // SSUBWvvv_4s4h |
| 2183342057U, // SSUBWvvv_8h8b |
| 638390670U, // STLR_byte |
| 638391898U, // STLR_dword |
| 638391091U, // STLR_hword |
| 638391898U, // STLR_word |
| 5651U, // STLXP_dword |
| 5651U, // STLXP_word |
| 671093190U, // STLXR_byte |
| 671094446U, // STLXR_dword |
| 671093611U, // STLXR_hword |
| 671094446U, // STLXR_word |
| 5658U, // STXP_dword |
| 5658U, // STXP_word |
| 671093198U, // STXR_byte |
| 671094453U, // STXR_dword |
| 671093619U, // STXR_hword |
| 671094453U, // STXR_word |
| 1108418742U, // SUBHN2vvv_16b8h |
| 1142038710U, // SUBHN2vvv_4s2d |
| 1175658678U, // SUBHN2vvv_8h4s |
| 2216961305U, // SUBHNvvv_2s2d |
| 2250581273U, // SUBHNvvv_4h4s |
| 2183537945U, // SUBHNvvv_8b8h |
| 5833U, // SUBSwww_asr |
| 5833U, // SUBSwww_lsl |
| 5833U, // SUBSwww_lsr |
| 5833U, // SUBSwww_sxtb |
| 5833U, // SUBSwww_sxth |
| 5833U, // SUBSwww_sxtw |
| 5833U, // SUBSwww_sxtx |
| 5833U, // SUBSwww_uxtb |
| 5833U, // SUBSwww_uxth |
| 5833U, // SUBSwww_uxtw |
| 5833U, // SUBSwww_uxtx |
| 5833U, // SUBSxxw_sxtb |
| 5833U, // SUBSxxw_sxth |
| 5833U, // SUBSxxw_sxtw |
| 5833U, // SUBSxxw_uxtb |
| 5833U, // SUBSxxw_uxth |
| 5833U, // SUBSxxw_uxtw |
| 5833U, // SUBSxxx_asr |
| 5833U, // SUBSxxx_lsl |
| 5833U, // SUBSxxx_lsr |
| 5833U, // SUBSxxx_sxtx |
| 5833U, // SUBSxxx_uxtx |
| 6327U, // SUBddd |
| 2283872771U, // SUBvvv_16B |
| 2217157123U, // SUBvvv_2D |
| 2317623811U, // SUBvvv_2S |
| 2351243779U, // SUBvvv_4H |
| 2250383875U, // SUBvvv_4S |
| 2384863747U, // SUBvvv_8B |
| 2183340547U, // SUBvvv_8H |
| 3221231305U, // SUBwwi_lsl0_S |
| 3152166U, // SUBwwi_lsl0_cmp |
| 3221230083U, // SUBwwi_lsl0_s |
| 5833U, // SUBwwi_lsl12_S |
| 4200742U, // SUBwwi_lsl12_cmp |
| 4611U, // SUBwwi_lsl12_s |
| 4611U, // SUBwww_asr |
| 4611U, // SUBwww_lsl |
| 4611U, // SUBwww_lsr |
| 4611U, // SUBwww_sxtb |
| 4611U, // SUBwww_sxth |
| 4611U, // SUBwww_sxtw |
| 4611U, // SUBwww_sxtx |
| 4611U, // SUBwww_uxtb |
| 4611U, // SUBwww_uxth |
| 4611U, // SUBwww_uxtw |
| 4611U, // SUBwww_uxtx |
| 3221231305U, // SUBxxi_lsl0_S |
| 3152166U, // SUBxxi_lsl0_cmp |
| 3221230083U, // SUBxxi_lsl0_s |
| 5833U, // SUBxxi_lsl12_S |
| 4200742U, // SUBxxi_lsl12_cmp |
| 4611U, // SUBxxi_lsl12_s |
| 4611U, // SUBxxw_sxtb |
| 4611U, // SUBxxw_sxth |
| 4611U, // SUBxxw_sxtw |
| 4611U, // SUBxxw_uxtb |
| 4611U, // SUBxxw_uxth |
| 4611U, // SUBxxw_uxtw |
| 4611U, // SUBxxx_asr |
| 4611U, // SUBxxx_lsl |
| 4611U, // SUBxxx_lsr |
| 4611U, // SUBxxx_sxtx |
| 4611U, // SUBxxx_uxtx |
| 528979U, // SVCi |
| 369103350U, // SXTBww |
| 369103350U, // SXTBxw |
| 369103761U, // SXTHww |
| 369103761U, // SXTHxw |
| 369104940U, // SXTWxw |
| 1073747150U, // SYSLxicci |
| 19928881U, // SYSiccix |
| 0U, // TAIL_BRx |
| 0U, // TAIL_Bimm |
| 2147489946U, // TBNZwii |
| 2147489946U, // TBNZxii |
| 2147489916U, // TBZwii |
| 2147489916U, // TBZxii |
| 0U, // TC_RETURNdi |
| 0U, // TC_RETURNxi |
| 582557U, // TLBIi |
| 369157021U, // TLBIix |
| 0U, // TLSDESCCALL |
| 0U, // TLSDESC_BLRx |
| 3221231478U, // TSTww_asr |
| 6006U, // TSTww_lsl |
| 1073747830U, // TSTww_lsr |
| 1073747830U, // TSTww_ror |
| 3221231478U, // TSTxx_asr |
| 6006U, // TSTxx_lsl |
| 1073747830U, // TSTxx_lsr |
| 1073747830U, // TSTxx_ror |
| 1175920663U, // UABAL2vvv_2d2s |
| 1108484119U, // UABAL2vvv_4s4h |
| 1209212951U, // UABAL2vvv_8h8b |
| 1243030488U, // UABALvvv_2d2s |
| 1276257240U, // UABALvvv_4s4h |
| 1309877208U, // UABALvvv_8h8b |
| 1209082173U, // UABAvvv_16B |
| 1242833213U, // UABAvvv_2S |
| 1276453181U, // UABAvvv_4H |
| 1175593277U, // UABAvvv_4S |
| 1310073149U, // UABAvvv_8B |
| 1108549949U, // UABAvvv_8H |
| 2250711121U, // UABDL2vvv_2d2s |
| 2183274577U, // UABDL2vvv_4s4h |
| 2284003409U, // UABDL2vvv_8h8b |
| 2317820955U, // UABDLvvv_2d2s |
| 2351047707U, // UABDLvvv_4s4h |
| 2384667675U, // UABDLvvv_8h8b |
| 2283872868U, // UABDvvv_16B |
| 2317623908U, // UABDvvv_2S |
| 2351243876U, // UABDvvv_4H |
| 2250383972U, // UABDvvv_4S |
| 2384863844U, // UABDvvv_8B |
| 2183340644U, // UABDvvv_8H |
| 2250711137U, // UADDL2vvv_2d4s |
| 2183274593U, // UADDL2vvv_4s8h |
| 2284003425U, // UADDL2vvv_8h16b |
| 2317820985U, // UADDLvvv_2d2s |
| 2351047737U, // UADDLvvv_4s4h |
| 2384667705U, // UADDLvvv_8h8b |
| 2217156897U, // UADDW2vvv_2d4s |
| 2250383649U, // UADDW2vvv_4s8h |
| 2183340321U, // UADDW2vvv_8h16b |
| 2217158663U, // UADDWvvv_2d2s |
| 2250385415U, // UADDWvvv_4s4h |
| 2183342087U, // UADDWvvv_8h8b |
| 2147489928U, // UBFIZwwii |
| 3221231752U, // UBFIZxxii |
| 5357U, // UBFMwwii |
| 5357U, // UBFMxxii |
| 6242U, // UBFXwwii |
| 6242U, // UBFXxxii |
| 369103584U, // UCVTFdw |
| 3221230304U, // UCVTFdwi |
| 369103584U, // UCVTFdx |
| 3221230304U, // UCVTFdxi |
| 369103584U, // UCVTFsw |
| 3221230304U, // UCVTFswi |
| 369103584U, // UCVTFsx |
| 3221230304U, // UCVTFsxi |
| 6082U, // UDIVwww |
| 6082U, // UDIVxxx |
| 2283872903U, // UHADDvvv_16B |
| 2317623943U, // UHADDvvv_2S |
| 2351243911U, // UHADDvvv_4H |
| 2250384007U, // UHADDvvv_4S |
| 2384863879U, // UHADDvvv_8B |
| 2183340679U, // UHADDvvv_8H |
| 2283872783U, // UHSUBvvv_16B |
| 2317623823U, // UHSUBvvv_2S |
| 2351243791U, // UHSUBvvv_4H |
| 2250383887U, // UHSUBvvv_4S |
| 2384863759U, // UHSUBvvv_8B |
| 2183340559U, // UHSUBvvv_8H |
| 5162U, // UMADDLxwwx |
| 2283873798U, // UMAXPvvv_16B |
| 2317624838U, // UMAXPvvv_2S |
| 2351244806U, // UMAXPvvv_4H |
| 2250384902U, // UMAXPvvv_4S |
| 2384864774U, // UMAXPvvv_8B |
| 2183341574U, // UMAXPvvv_8H |
| 2283874374U, // UMAXvvv_16B |
| 2317625414U, // UMAXvvv_2S |
| 2351245382U, // UMAXvvv_4H |
| 2250385478U, // UMAXvvv_4S |
| 2384865350U, // UMAXvvv_8B |
| 2183342150U, // UMAXvvv_8H |
| 2283873745U, // UMINPvvv_16B |
| 2317624785U, // UMINPvvv_2S |
| 2351244753U, // UMINPvvv_4H |
| 2250384849U, // UMINPvvv_4S |
| 2384864721U, // UMINPvvv_8B |
| 2183341521U, // UMINPvvv_8H |
| 2283873588U, // UMINvvv_16B |
| 2317624628U, // UMINvvv_2S |
| 2351244596U, // UMINvvv_4H |
| 2250384692U, // UMINvvv_4S |
| 2384864564U, // UMINvvv_8B |
| 2183341364U, // UMINvvv_8H |
| 1175920689U, // UMLAL2vvv_2d4s |
| 1108484145U, // UMLAL2vvv_4s8h |
| 1209212977U, // UMLAL2vvv_8h16b |
| 1243030511U, // UMLALvvv_2d2s |
| 1276257263U, // UMLALvvv_4s4h |
| 1309877231U, // UMLALvvv_8h8b |
| 1175920813U, // UMLSL2vvv_2d4s |
| 1108484269U, // UMLSL2vvv_4s8h |
| 1209213101U, // UMLSL2vvv_8h16b |
| 1243030727U, // UMLSLvvv_2d2s |
| 1276257479U, // UMLSLvvv_4s4h |
| 1309877447U, // UMLSLvvv_8h8b |
| 471865307U, // UMOVwb |
| 538974171U, // UMOVwh |
| 572528603U, // UMOVws |
| 438310875U, // UMOVxd |
| 5118U, // UMSUBLxwwx |
| 4895U, // UMULHxxx |
| 2250711187U, // UMULL2vvv_2d4s |
| 2183274643U, // UMULL2vvv_4s8h |
| 2284003475U, // UMULL2vvv_8h16b |
| 2317821099U, // UMULLvvv_2d2s |
| 2351047851U, // UMULLvvv_4s4h |
| 2384667819U, // UMULLvvv_8h8b |
| 6351U, // UQADDbbb |
| 6351U, // UQADDddd |
| 6351U, // UQADDhhh |
| 6351U, // UQADDsss |
| 2283872932U, // UQADDvvv_16B |
| 2217157284U, // UQADDvvv_2D |
| 2317623972U, // UQADDvvv_2S |
| 2351243940U, // UQADDvvv_4H |
| 2250384036U, // UQADDvvv_4S |
| 2384863908U, // UQADDvvv_8B |
| 2183340708U, // UQADDvvv_8H |
| 6392U, // UQRSHLbbb |
| 6392U, // UQRSHLddd |
| 6392U, // UQRSHLhhh |
| 6392U, // UQRSHLsss |
| 2283873373U, // UQRSHLvvv_16B |
| 2217157725U, // UQRSHLvvv_2D |
| 2317624413U, // UQRSHLvvv_2S |
| 2351244381U, // UQRSHLvvv_4H |
| 2250384477U, // UQRSHLvvv_4S |
| 2384864349U, // UQRSHLvvv_8B |
| 2183341149U, // UQRSHLvvv_8H |
| 1108418787U, // UQRSHRNvvi_16B |
| 69477726U, // UQRSHRNvvi_2S |
| 103097694U, // UQRSHRNvvi_4H |
| 1142038755U, // UQRSHRNvvi_4S |
| 36054366U, // UQRSHRNvvi_8B |
| 1175658723U, // UQRSHRNvvi_8H |
| 6377U, // UQSHLbbb |
| 6377U, // UQSHLddd |
| 6377U, // UQSHLhhh |
| 6377U, // UQSHLsss |
| 136389710U, // UQSHLvvi_16B |
| 69674062U, // UQSHLvvi_2D |
| 170140750U, // UQSHLvvi_2S |
| 203760718U, // UQSHLvvi_4H |
| 102900814U, // UQSHLvvi_4S |
| 237380686U, // UQSHLvvi_8B |
| 35857486U, // UQSHLvvi_8H |
| 2283873358U, // UQSHLvvv_16B |
| 2217157710U, // UQSHLvvv_2D |
| 2317624398U, // UQSHLvvv_2S |
| 2351244366U, // UQSHLvvv_4H |
| 2250384462U, // UQSHLvvv_4S |
| 2384864334U, // UQSHLvvv_8B |
| 2183341134U, // UQSHLvvv_8H |
| 1108418768U, // UQSHRNvvi_16B |
| 69477709U, // UQSHRNvvi_2S |
| 103097677U, // UQSHRNvvi_4H |
| 1142038736U, // UQSHRNvvi_4S |
| 36054349U, // UQSHRNvvi_8B |
| 1175658704U, // UQSHRNvvi_8H |
| 6332U, // UQSUBbbb |
| 6332U, // UQSUBddd |
| 6332U, // UQSUBhhh |
| 6332U, // UQSUBsss |
| 2283872812U, // UQSUBvvv_16B |
| 2217157164U, // UQSUBvvv_2D |
| 2317623852U, // UQSUBvvv_2S |
| 2351243820U, // UQSUBvvv_4H |
| 2250383916U, // UQSUBvvv_4S |
| 2384863788U, // UQSUBvvv_8B |
| 2183340588U, // UQSUBvvv_8H |
| 2283872888U, // URHADDvvv_16B |
| 2317623928U, // URHADDvvv_2S |
| 2351243896U, // URHADDvvv_4H |
| 2250383992U, // URHADDvvv_4S |
| 2384863864U, // URHADDvvv_8B |
| 2183340664U, // URHADDvvv_8H |
| 6407U, // URSHLddd |
| 2283873388U, // URSHLvvv_16B |
| 2217157740U, // URSHLvvv_2D |
| 2317624428U, // URSHLvvv_2S |
| 2351244396U, // URSHLvvv_4H |
| 2250384492U, // URSHLvvv_4S |
| 2384864364U, // URSHLvvv_8B |
| 2183341164U, // URSHLvvv_8H |
| 136390210U, // URSHRvvi_16B |
| 69674562U, // URSHRvvi_2D |
| 170141250U, // URSHRvvi_2S |
| 203761218U, // URSHRvvi_4H |
| 102901314U, // URSHRvvi_4S |
| 237381186U, // URSHRvvi_8B |
| 35857986U, // URSHRvvi_8H |
| 1209082192U, // URSRAvvi_16B |
| 1142366544U, // URSRAvvi_2D |
| 1242833232U, // URSRAvvi_2S |
| 1276453200U, // URSRAvvi_4H |
| 1175593296U, // URSRAvvi_4S |
| 1310073168U, // URSRAvvi_8B |
| 1108549968U, // URSRAvvi_8H |
| 136519793U, // USHLLvvi_16B |
| 170337421U, // USHLLvvi_2S |
| 203564173U, // USHLLvvi_4H |
| 103227505U, // USHLLvvi_4S |
| 237184141U, // USHLLvvi_8B |
| 35790961U, // USHLLvvi_8H |
| 6420U, // USHLddd |
| 2283873401U, // USHLvvv_16B |
| 2217157753U, // USHLvvv_2D |
| 2317624441U, // USHLvvv_2S |
| 2351244409U, // USHLvvv_4H |
| 2250384505U, // USHLvvv_4S |
| 2384864377U, // USHLvvv_8B |
| 2183341177U, // USHLvvv_8H |
| 136390223U, // USHRvvi_16B |
| 69674575U, // USHRvvi_2D |
| 170141263U, // USHRvvi_2S |
| 203761231U, // USHRvvi_4H |
| 102901327U, // USHRvvi_4S |
| 237381199U, // USHRvvi_8B |
| 35857999U, // USHRvvi_8H |
| 1209082205U, // USRAvvi_16B |
| 1142366557U, // USRAvvi_2D |
| 1242833245U, // USRAvvi_2S |
| 1276453213U, // USRAvvi_4H |
| 1175593309U, // USRAvvi_4S |
| 1310073181U, // USRAvvi_8B |
| 1108549981U, // USRAvvi_8H |
| 2250711105U, // USUBL2vvv_2d4s |
| 2183274561U, // USUBL2vvv_4s8h |
| 2284003393U, // USUBL2vvv_8h16b |
| 2317820941U, // USUBLvvv_2d2s |
| 2351047693U, // USUBLvvv_4s4h |
| 2384667661U, // USUBLvvv_8h8b |
| 2217156881U, // USUBW2vvv_2d4s |
| 2250383633U, // USUBW2vvv_4s8h |
| 2183340305U, // USUBW2vvv_8h16b |
| 2217158640U, // USUBWvvv_2d2s |
| 2250385392U, // USUBWvvv_4s4h |
| 2183342064U, // USUBWvvv_8h8b |
| 369103356U, // UXTBww |
| 369103356U, // UXTBxw |
| 369103767U, // UXTHww |
| 369103767U, // UXTHxw |
| 69674806U, // VCVTf2xs_2D |
| 170141494U, // VCVTf2xs_2S |
| 102901558U, // VCVTf2xs_4S |
| 69674921U, // VCVTf2xu_2D |
| 170141609U, // VCVTf2xu_2S |
| 102901673U, // VCVTf2xu_4S |
| 69673689U, // VCVTxs2f_2D |
| 170140377U, // VCVTxs2f_2S |
| 102900441U, // VCVTxs2f_4S |
| 69673696U, // VCVTxu2f_2D |
| 170140384U, // VCVTxu2f_2S |
| 102900448U, // VCVTxu2f_4S |
| 0U |
| }; |
| |
| static uint16_t OpInfo2[] = { |
| 0U, // PHI |
| 0U, // INLINEASM |
| 0U, // PROLOG_LABEL |
| 0U, // EH_LABEL |
| 0U, // GC_LABEL |
| 0U, // KILL |
| 0U, // EXTRACT_SUBREG |
| 0U, // INSERT_SUBREG |
| 0U, // IMPLICIT_DEF |
| 0U, // SUBREG_TO_REG |
| 0U, // COPY_TO_REGCLASS |
| 0U, // DBG_VALUE |
| 0U, // REG_SEQUENCE |
| 0U, // COPY |
| 0U, // BUNDLE |
| 0U, // LIFETIME_START |
| 0U, // LIFETIME_END |
| 0U, // ADCSwww |
| 0U, // ADCSxxx |
| 0U, // ADCwww |
| 0U, // ADCxxx |
| 16U, // ADDHN2vvv_16b8h |
| 32U, // ADDHN2vvv_4s2d |
| 48U, // ADDHN2vvv_8h4s |
| 32U, // ADDHNvvv_2s2d |
| 48U, // ADDHNvvv_4h4s |
| 16U, // ADDHNvvv_8b8h |
| 64U, // ADDP_16B |
| 32U, // ADDP_2D |
| 80U, // ADDP_2S |
| 96U, // ADDP_4H |
| 48U, // ADDP_4S |
| 112U, // ADDP_8B |
| 16U, // ADDP_8H |
| 0U, // ADDPvv_D_2D |
| 128U, // ADDSwww_asr |
| 384U, // ADDSwww_lsl |
| 640U, // ADDSwww_lsr |
| 896U, // ADDSwww_sxtb |
| 1152U, // ADDSwww_sxth |
| 1408U, // ADDSwww_sxtw |
| 1664U, // ADDSwww_sxtx |
| 1920U, // ADDSwww_uxtb |
| 2176U, // ADDSwww_uxth |
| 2432U, // ADDSwww_uxtw |
| 2688U, // ADDSwww_uxtx |
| 896U, // ADDSxxw_sxtb |
| 1152U, // ADDSxxw_sxth |
| 1408U, // ADDSxxw_sxtw |
| 1920U, // ADDSxxw_uxtb |
| 2176U, // ADDSxxw_uxth |
| 2432U, // ADDSxxw_uxtw |
| 128U, // ADDSxxx_asr |
| 384U, // ADDSxxx_lsl |
| 640U, // ADDSxxx_lsr |
| 1664U, // ADDSxxx_sxtx |
| 2688U, // ADDSxxx_uxtx |
| 0U, // ADDddd |
| 64U, // ADDvvv_16B |
| 32U, // ADDvvv_2D |
| 80U, // ADDvvv_2S |
| 96U, // ADDvvv_4H |
| 48U, // ADDvvv_4S |
| 112U, // ADDvvv_8B |
| 16U, // ADDvvv_8H |
| 0U, // ADDwwi_lsl0_S |
| 0U, // ADDwwi_lsl0_cmp |
| 0U, // ADDwwi_lsl0_s |
| 1U, // ADDwwi_lsl12_S |
| 0U, // ADDwwi_lsl12_cmp |
| 1U, // ADDwwi_lsl12_s |
| 128U, // ADDwww_asr |
| 384U, // ADDwww_lsl |
| 640U, // ADDwww_lsr |
| 896U, // ADDwww_sxtb |
| 1152U, // ADDwww_sxth |
| 1408U, // ADDwww_sxtw |
| 1664U, // ADDwww_sxtx |
| 1920U, // ADDwww_uxtb |
| 2176U, // ADDwww_uxth |
| 2432U, // ADDwww_uxtw |
| 2688U, // ADDwww_uxtx |
| 0U, // ADDxxi_lsl0_S |
| 0U, // ADDxxi_lsl0_cmp |
| 0U, // ADDxxi_lsl0_s |
| 1U, // ADDxxi_lsl12_S |
| 0U, // ADDxxi_lsl12_cmp |
| 1U, // ADDxxi_lsl12_s |
| 896U, // ADDxxw_sxtb |
| 1152U, // ADDxxw_sxth |
| 1408U, // ADDxxw_sxtw |
| 1920U, // ADDxxw_uxtb |
| 2176U, // ADDxxw_uxth |
| 2432U, // ADDxxw_uxtw |
| 128U, // ADDxxx_asr |
| 384U, // ADDxxx_lsl |
| 640U, // ADDxxx_lsr |
| 1664U, // ADDxxx_sxtx |
| 2688U, // ADDxxx_uxtx |
| 0U, // ADJCALLSTACKDOWN |
| 0U, // ADJCALLSTACKUP |
| 0U, // ADRPxi |
| 0U, // ADRxi |
| 1U, // ANDSwwi |
| 128U, // ANDSwww_asr |
| 384U, // ANDSwww_lsl |
| 640U, // ANDSwww_lsr |
| 2944U, // ANDSwww_ror |
| 1U, // ANDSxxi |
| 128U, // ANDSxxx_asr |
| 384U, // ANDSxxx_lsl |
| 640U, // ANDSxxx_lsr |
| 2944U, // ANDSxxx_ror |
| 64U, // ANDvvv_16B |
| 112U, // ANDvvv_8B |
| 1U, // ANDwwi |
| 128U, // ANDwww_asr |
| 384U, // ANDwww_lsl |
| 640U, // ANDwww_lsr |
| 2944U, // ANDwww_ror |
| 1U, // ANDxxi |
| 128U, // ANDxxx_asr |
| 384U, // ANDxxx_lsl |
| 640U, // ANDxxx_lsr |
| 2944U, // ANDxxx_ror |
| 0U, // ASRVwww |
| 0U, // ASRVxxx |
| 0U, // ASRwwi |
| 0U, // ASRxxi |
| 0U, // ATOMIC_CMP_SWAP_I16 |
| 0U, // ATOMIC_CMP_SWAP_I32 |
| 0U, // ATOMIC_CMP_SWAP_I64 |
| 0U, // ATOMIC_CMP_SWAP_I8 |
| 0U, // ATOMIC_LOAD_ADD_I16 |
| 0U, // ATOMIC_LOAD_ADD_I32 |
| 0U, // ATOMIC_LOAD_ADD_I64 |
| 0U, // ATOMIC_LOAD_ADD_I8 |
| 0U, // ATOMIC_LOAD_AND_I16 |
| 0U, // ATOMIC_LOAD_AND_I32 |
| 0U, // ATOMIC_LOAD_AND_I64 |
| 0U, // ATOMIC_LOAD_AND_I8 |
| 0U, // ATOMIC_LOAD_MAX_I16 |
| 0U, // ATOMIC_LOAD_MAX_I32 |
| 0U, // ATOMIC_LOAD_MAX_I64 |
| 0U, // ATOMIC_LOAD_MAX_I8 |
| 0U, // ATOMIC_LOAD_MIN_I16 |
| 0U, // ATOMIC_LOAD_MIN_I32 |
| 0U, // ATOMIC_LOAD_MIN_I64 |
| 0U, // ATOMIC_LOAD_MIN_I8 |
| 0U, // ATOMIC_LOAD_NAND_I16 |
| 0U, // ATOMIC_LOAD_NAND_I32 |
| 0U, // ATOMIC_LOAD_NAND_I64 |
| 0U, // ATOMIC_LOAD_NAND_I8 |
| 0U, // ATOMIC_LOAD_OR_I16 |
| 0U, // ATOMIC_LOAD_OR_I32 |
| 0U, // ATOMIC_LOAD_OR_I64 |
| 0U, // ATOMIC_LOAD_OR_I8 |
| 0U, // ATOMIC_LOAD_SUB_I16 |
| 0U, // ATOMIC_LOAD_SUB_I32 |
| 0U, // ATOMIC_LOAD_SUB_I64 |
| 0U, // ATOMIC_LOAD_SUB_I8 |
| 0U, // ATOMIC_LOAD_UMAX_I16 |
| 0U, // ATOMIC_LOAD_UMAX_I32 |
| 0U, // ATOMIC_LOAD_UMAX_I64 |
| 0U, // ATOMIC_LOAD_UMAX_I8 |
| 0U, // ATOMIC_LOAD_UMIN_I16 |
| 0U, // ATOMIC_LOAD_UMIN_I32 |
| 0U, // ATOMIC_LOAD_UMIN_I64 |
| 0U, // ATOMIC_LOAD_UMIN_I8 |
| 0U, // ATOMIC_LOAD_XOR_I16 |
| 0U, // ATOMIC_LOAD_XOR_I32 |
| 0U, // ATOMIC_LOAD_XOR_I64 |
| 0U, // ATOMIC_LOAD_XOR_I8 |
| 0U, // ATOMIC_SWAP_I16 |
| 0U, // ATOMIC_SWAP_I32 |
| 0U, // ATOMIC_SWAP_I64 |
| 0U, // ATOMIC_SWAP_I8 |
| 0U, // ATix |
| 1U, // BFIwwii |
| 2U, // BFIxxii |
| 3202U, // BFMwwii |
| 3202U, // BFMxxii |
| 3458U, // BFXILwwii |
| 3458U, // BFXILxxii |
| 128U, // BICSwww_asr |
| 384U, // BICSwww_lsl |
| 640U, // BICSwww_lsr |
| 2944U, // BICSwww_ror |
| 128U, // BICSxxx_asr |
| 384U, // BICSxxx_lsl |
| 640U, // BICSxxx_lsr |
| 2944U, // BICSxxx_ror |
| 0U, // BICvi_lsl_2S |
| 0U, // BICvi_lsl_4H |
| 0U, // BICvi_lsl_4S |
| 0U, // BICvi_lsl_8H |
| 64U, // BICvvv_16B |
| 112U, // BICvvv_8B |
| 128U, // BICwww_asr |
| 384U, // BICwww_lsl |
| 640U, // BICwww_lsr |
| 2944U, // BICwww_ror |
| 128U, // BICxxx_asr |
| 384U, // BICxxx_lsl |
| 640U, // BICxxx_lsr |
| 2944U, // BICxxx_ror |
| 64U, // BIFvvv_16B |
| 112U, // BIFvvv_8B |
| 64U, // BITvvv_16B |
| 112U, // BITvvv_8B |
| 0U, // BLRx |
| 0U, // BLimm |
| 0U, // BRKi |
| 0U, // BRx |
| 64U, // BSLvvv_16B |
| 112U, // BSLvvv_8B |
| 0U, // Bcc |
| 0U, // Bimm |
| 0U, // CBNZw |
| 0U, // CBNZx |
| 0U, // CBZw |
| 0U, // CBZx |
| 3712U, // CCMNwi |
| 3712U, // CCMNww |
| 3712U, // CCMNxi |
| 3712U, // CCMNxx |
| 3712U, // CCMPwi |
| 3712U, // CCMPww |
| 3712U, // CCMPxi |
| 3712U, // CCMPxx |
| 0U, // CLREXi |
| 0U, // CLSww |
| 0U, // CLSxx |
| 0U, // CLZww |
| 0U, // CLZxx |
| 2U, // CMEQvvi_16B |
| 2U, // CMEQvvi_2D |
| 2U, // CMEQvvi_2S |
| 2U, // CMEQvvi_4H |
| 2U, // CMEQvvi_4S |
| 2U, // CMEQvvi_8B |
| 2U, // CMEQvvi_8H |
| 64U, // CMEQvvv_16B |
| 32U, // CMEQvvv_2D |
| 80U, // CMEQvvv_2S |
| 96U, // CMEQvvv_4H |
| 48U, // CMEQvvv_4S |
| 112U, // CMEQvvv_8B |
| 16U, // CMEQvvv_8H |
| 2U, // CMGEvvi_16B |
| 2U, // CMGEvvi_2D |
| 2U, // CMGEvvi_2S |
| 2U, // CMGEvvi_4H |
| 2U, // CMGEvvi_4S |
| 2U, // CMGEvvi_8B |
| 2U, // CMGEvvi_8H |
| 64U, // CMGEvvv_16B |
| 32U, // CMGEvvv_2D |
| 80U, // CMGEvvv_2S |
| 96U, // CMGEvvv_4H |
| 48U, // CMGEvvv_4S |
| 112U, // CMGEvvv_8B |
| 16U, // CMGEvvv_8H |
| 2U, // CMGTvvi_16B |
| 2U, // CMGTvvi_2D |
| 2U, // CMGTvvi_2S |
| 2U, // CMGTvvi_4H |
| 2U, // CMGTvvi_4S |
| 2U, // CMGTvvi_8B |
| 2U, // CMGTvvi_8H |
| 64U, // CMGTvvv_16B |
| 32U, // CMGTvvv_2D |
| 80U, // CMGTvvv_2S |
| 96U, // CMGTvvv_4H |
| 48U, // CMGTvvv_4S |
| 112U, // CMGTvvv_8B |
| 16U, // CMGTvvv_8H |
| 64U, // CMHIvvv_16B |
| 32U, // CMHIvvv_2D |
| 80U, // CMHIvvv_2S |
| 96U, // CMHIvvv_4H |
| 48U, // CMHIvvv_4S |
| 112U, // CMHIvvv_8B |
| 16U, // CMHIvvv_8H |
| 64U, // CMHSvvv_16B |
| 32U, // CMHSvvv_2D |
| 80U, // CMHSvvv_2S |
| 96U, // CMHSvvv_4H |
| 48U, // CMHSvvv_4S |
| 112U, // CMHSvvv_8B |
| 16U, // CMHSvvv_8H |
| 2U, // CMLEvvi_16B |
| 2U, // CMLEvvi_2D |
| 2U, // CMLEvvi_2S |
| 2U, // CMLEvvi_4H |
| 2U, // CMLEvvi_4S |
| 2U, // CMLEvvi_8B |
| 2U, // CMLEvvi_8H |
| 2U, // CMLTvvi_16B |
| 2U, // CMLTvvi_2D |
| 2U, // CMLTvvi_2S |
| 2U, // CMLTvvi_4H |
| 2U, // CMLTvvi_4S |
| 2U, // CMLTvvi_8B |
| 2U, // CMLTvvi_8H |
| 2U, // CMNww_asr |
| 3U, // CMNww_lsl |
| 3U, // CMNww_lsr |
| 3U, // CMNww_sxtb |
| 3U, // CMNww_sxth |
| 4U, // CMNww_sxtw |
| 4U, // CMNww_sxtx |
| 4U, // CMNww_uxtb |
| 4U, // CMNww_uxth |
| 5U, // CMNww_uxtw |
| 5U, // CMNww_uxtx |
| 3U, // CMNxw_sxtb |
| 3U, // CMNxw_sxth |
| 4U, // CMNxw_sxtw |
| 4U, // CMNxw_uxtb |
| 4U, // CMNxw_uxth |
| 5U, // CMNxw_uxtw |
| 2U, // CMNxx_asr |
| 3U, // CMNxx_lsl |
| 3U, // CMNxx_lsr |
| 4U, // CMNxx_sxtx |
| 5U, // CMNxx_uxtx |
| 2U, // CMPww_asr |
| 3U, // CMPww_lsl |
| 3U, // CMPww_lsr |
| 3U, // CMPww_sxtb |
| 3U, // CMPww_sxth |
| 4U, // CMPww_sxtw |
| 4U, // CMPww_sxtx |
| 4U, // CMPww_uxtb |
| 4U, // CMPww_uxth |
| 5U, // CMPww_uxtw |
| 5U, // CMPww_uxtx |
| 3U, // CMPxw_sxtb |
| 3U, // CMPxw_sxth |
| 4U, // CMPxw_sxtw |
| 4U, // CMPxw_uxtb |
| 4U, // CMPxw_uxth |
| 5U, // CMPxw_uxtw |
| 2U, // CMPxx_asr |
| 3U, // CMPxx_lsl |
| 3U, // CMPxx_lsr |
| 4U, // CMPxx_sxtx |
| 5U, // CMPxx_uxtx |
| 64U, // CMTSTvvv_16B |
| 32U, // CMTSTvvv_2D |
| 80U, // CMTSTvvv_2S |
| 96U, // CMTSTvvv_4H |
| 48U, // CMTSTvvv_4S |
| 112U, // CMTSTvvv_8B |
| 16U, // CMTSTvvv_8H |
| 0U, // CRC32B_www |
| 0U, // CRC32CB_www |
| 0U, // CRC32CH_www |
| 0U, // CRC32CW_www |
| 0U, // CRC32CX_wwx |
| 0U, // CRC32H_www |
| 0U, // CRC32W_www |
| 0U, // CRC32X_wwx |
| 3712U, // CSELwwwc |
| 3712U, // CSELxxxc |
| 3712U, // CSINCwwwc |
| 3712U, // CSINCxxxc |
| 3712U, // CSINVwwwc |
| 3712U, // CSINVxxxc |
| 3712U, // CSNEGwwwc |
| 3712U, // CSNEGxxxc |
| 0U, // DCPS1i |
| 0U, // DCPS2i |
| 0U, // DCPS3i |
| 0U, // DCix |
| 0U, // DMBi |
| 0U, // DRPS |
| 0U, // DSBi |
| 128U, // EONwww_asr |
| 384U, // EONwww_lsl |
| 640U, // EONwww_lsr |
| 2944U, // EONwww_ror |
| 128U, // EONxxx_asr |
| 384U, // EONxxx_lsl |
| 640U, // EONxxx_lsr |
| 2944U, // EONxxx_ror |
| 64U, // EORvvv_16B |
| 112U, // EORvvv_8B |
| 1U, // EORwwi |
| 128U, // EORwww_asr |
| 384U, // EORwww_lsl |
| 640U, // EORwww_lsr |
| 2944U, // EORwww_ror |
| 1U, // EORxxi |
| 128U, // EORxxx_asr |
| 384U, // EORxxx_lsl |
| 640U, // EORxxx_lsr |
| 2944U, // EORxxx_ror |
| 0U, // ERET |
| 3968U, // EXTRwwwi |
| 3968U, // EXTRxxxi |
| 0U, // F128CSEL |
| 32U, // FABDvvv_2D |
| 80U, // FABDvvv_2S |
| 48U, // FABDvvv_4S |
| 0U, // FABSdd |
| 0U, // FABSss |
| 32U, // FACGEvvv_2D |
| 80U, // FACGEvvv_2S |
| 48U, // FACGEvvv_4S |
| 32U, // FACGTvvv_2D |
| 80U, // FACGTvvv_2S |
| 48U, // FACGTvvv_4S |
| 32U, // FADDP_2D |
| 80U, // FADDP_2S |
| 48U, // FADDP_4S |
| 0U, // FADDPvv_D_2D |
| 0U, // FADDPvv_S_2S |
| 0U, // FADDddd |
| 0U, // FADDsss |
| 32U, // FADDvvv_2D |
| 80U, // FADDvvv_2S |
| 48U, // FADDvvv_4S |
| 3712U, // FCCMPEdd |
| 3712U, // FCCMPEss |
| 3712U, // FCCMPdd |
| 3712U, // FCCMPss |
| 5U, // FCMEQvvi_2D |
| 5U, // FCMEQvvi_2S |
| 5U, // FCMEQvvi_4S |
| 32U, // FCMEQvvv_2D |
| 80U, // FCMEQvvv_2S |
| 48U, // FCMEQvvv_4S |
| 5U, // FCMGEvvi_2D |
| 5U, // FCMGEvvi_2S |
| 5U, // FCMGEvvi_4S |
| 32U, // FCMGEvvv_2D |
| 80U, // FCMGEvvv_2S |
| 48U, // FCMGEvvv_4S |
| 5U, // FCMGTvvi_2D |
| 5U, // FCMGTvvi_2S |
| 5U, // FCMGTvvi_4S |
| 32U, // FCMGTvvv_2D |
| 80U, // FCMGTvvv_2S |
| 48U, // FCMGTvvv_4S |
| 5U, // FCMLEvvi_2D |
| 5U, // FCMLEvvi_2S |
| 5U, // FCMLEvvi_4S |
| 5U, // FCMLTvvi_2D |
| 5U, // FCMLTvvi_2S |
| 5U, // FCMLTvvi_4S |
| 0U, // FCMPdd_quiet |
| 0U, // FCMPdd_sig |
| 0U, // FCMPdi_quiet |
| 0U, // FCMPdi_sig |
| 0U, // FCMPsi_quiet |
| 0U, // FCMPsi_sig |
| 0U, // FCMPss_quiet |
| 0U, // FCMPss_sig |
| 3712U, // FCSELdddc |
| 3712U, // FCSELsssc |
| 0U, // FCVTASwd |
| 0U, // FCVTASws |
| 0U, // FCVTASxd |
| 0U, // FCVTASxs |
| 0U, // FCVTAUwd |
| 0U, // FCVTAUws |
| 0U, // FCVTAUxd |
| 0U, // FCVTAUxs |
| 0U, // FCVTMSwd |
| 0U, // FCVTMSws |
| 0U, // FCVTMSxd |
| 0U, // FCVTMSxs |
| 0U, // FCVTMUwd |
| 0U, // FCVTMUws |
| 0U, // FCVTMUxd |
| 0U, // FCVTMUxs |
| 0U, // FCVTNSwd |
| 0U, // FCVTNSws |
| 0U, // FCVTNSxd |
| 0U, // FCVTNSxs |
| 0U, // FCVTNUwd |
| 0U, // FCVTNUws |
| 0U, // FCVTNUxd |
| 0U, // FCVTNUxs |
| 0U, // FCVTPSwd |
| 0U, // FCVTPSws |
| 0U, // FCVTPSxd |
| 0U, // FCVTPSxs |
| 0U, // FCVTPUwd |
| 0U, // FCVTPUws |
| 0U, // FCVTPUxd |
| 0U, // FCVTPUxs |
| 0U, // FCVTZSwd |
| 5U, // FCVTZSwdi |
| 0U, // FCVTZSws |
| 5U, // FCVTZSwsi |
| 0U, // FCVTZSxd |
| 5U, // FCVTZSxdi |
| 0U, // FCVTZSxs |
| 5U, // FCVTZSxsi |
| 0U, // FCVTZUwd |
| 5U, // FCVTZUwdi |
| 0U, // FCVTZUws |
| 5U, // FCVTZUwsi |
| 0U, // FCVTZUxd |
| 5U, // FCVTZUxdi |
| 0U, // FCVTZUxs |
| 5U, // FCVTZUxsi |
| 0U, // FCVTdh |
| 0U, // FCVTds |
| 0U, // FCVThd |
| 0U, // FCVThs |
| 0U, // FCVTsd |
| 0U, // FCVTsh |
| 0U, // FDIVddd |
| 0U, // FDIVsss |
| 32U, // FDIVvvv_2D |
| 80U, // FDIVvvv_2S |
| 48U, // FDIVvvv_4S |
| 3968U, // FMADDdddd |
| 3968U, // FMADDssss |
| 0U, // FMAXNMPvv_D_2D |
| 0U, // FMAXNMPvv_S_2S |
| 32U, // FMAXNMPvvv_2D |
| 80U, // FMAXNMPvvv_2S |
| 48U, // FMAXNMPvvv_4S |
| 0U, // FMAXNMddd |
| 0U, // FMAXNMsss |
| 32U, // FMAXNMvvv_2D |
| 80U, // FMAXNMvvv_2S |
| 48U, // FMAXNMvvv_4S |
| 0U, // FMAXPvv_D_2D |
| 0U, // FMAXPvv_S_2S |
| 32U, // FMAXPvvv_2D |
| 80U, // FMAXPvvv_2S |
| 48U, // FMAXPvvv_4S |
| 0U, // FMAXddd |
| 0U, // FMAXsss |
| 32U, // FMAXvvv_2D |
| 80U, // FMAXvvv_2S |
| 48U, // FMAXvvv_4S |
| 0U, // FMINNMPvv_D_2D |
| 0U, // FMINNMPvv_S_2S |
| 32U, // FMINNMPvvv_2D |
| 80U, // FMINNMPvvv_2S |
| 48U, // FMINNMPvvv_4S |
| 0U, // FMINNMddd |
| 0U, // FMINNMsss |
| 32U, // FMINNMvvv_2D |
| 80U, // FMINNMvvv_2S |
| 48U, // FMINNMvvv_4S |
| 0U, // FMINPvv_D_2D |
| 0U, // FMINPvv_S_2S |
| 32U, // FMINPvvv_2D |
| 80U, // FMINPvvv_2S |
| 48U, // FMINPvvv_4S |
| 0U, // FMINddd |
| 0U, // FMINsss |
| 32U, // FMINvvv_2D |
| 80U, // FMINvvv_2S |
| 48U, // FMINvvv_4S |
| 32U, // FMLAvvv_2D |
| 80U, // FMLAvvv_2S |
| 48U, // FMLAvvv_4S |
| 32U, // FMLSvvv_2D |
| 80U, // FMLSvvv_2S |
| 48U, // FMLSvvv_4S |
| 0U, // FMOVdd |
| 0U, // FMOVdi |
| 0U, // FMOVdx |
| 0U, // FMOVsi |
| 0U, // FMOVss |
| 0U, // FMOVsw |
| 0U, // FMOVvi_2D |
| 0U, // FMOVvi_2S |
| 0U, // FMOVvi_4S |
| 0U, // FMOVvx |
| 0U, // FMOVws |
| 0U, // FMOVxd |
| 6U, // FMOVxv |
| 3968U, // FMSUBdddd |
| 3968U, // FMSUBssss |
| 32U, // FMULXvvv_2D |
| 80U, // FMULXvvv_2S |
| 48U, // FMULXvvv_4S |
| 0U, // FMULddd |
| 0U, // FMULsss |
| 32U, // FMULvvv_2D |
| 80U, // FMULvvv_2S |
| 48U, // FMULvvv_4S |
| 0U, // FNEGdd |
| 0U, // FNEGss |
| 3968U, // FNMADDdddd |
| 3968U, // FNMADDssss |
| 3968U, // FNMSUBdddd |
| 3968U, // FNMSUBssss |
| 0U, // FNMULddd |
| 0U, // FNMULsss |
| 32U, // FRECPSvvv_2D |
| 80U, // FRECPSvvv_2S |
| 48U, // FRECPSvvv_4S |
| 0U, // FRINTAdd |
| 0U, // FRINTAss |
| 0U, // FRINTIdd |
| 0U, // FRINTIss |
| 0U, // FRINTMdd |
| 0U, // FRINTMss |
| 0U, // FRINTNdd |
| 0U, // FRINTNss |
| 0U, // FRINTPdd |
| 0U, // FRINTPss |
| 0U, // FRINTXdd |
| 0U, // FRINTXss |
| 0U, // FRINTZdd |
| 0U, // FRINTZss |
| 32U, // FRSQRTSvvv_2D |
| 80U, // FRSQRTSvvv_2S |
| 48U, // FRSQRTSvvv_4S |
| 0U, // FSQRTdd |
| 0U, // FSQRTss |
| 0U, // FSUBddd |
| 0U, // FSUBsss |
| 32U, // FSUBvvv_2D |
| 80U, // FSUBvvv_2S |
| 48U, // FSUBvvv_4S |
| 0U, // HINTi |
| 0U, // HLTi |
| 0U, // HVCi |
| 0U, // ICi |
| 0U, // ICix |
| 6U, // INSELb |
| 0U, // INSELd |
| 6U, // INSELh |
| 6U, // INSELs |
| 0U, // INSbw |
| 0U, // INSdx |
| 0U, // INShw |
| 0U, // INSsw |
| 0U, // ISBi |
| 0U, // LDAR_byte |
| 0U, // LDAR_dword |
| 0U, // LDAR_hword |
| 0U, // LDAR_word |
| 144U, // LDAXP_dword |
| 144U, // LDAXP_word |
| 0U, // LDAXR_byte |
| 0U, // LDAXR_dword |
| 0U, // LDAXR_hword |
| 0U, // LDAXR_word |
| 4224U, // LDPSWx |
| 4514U, // LDPSWx_PostInd |
| 20866U, // LDPSWx_PreInd |
| 6U, // LDRSBw |
| 0U, // LDRSBw_PostInd |
| 6U, // LDRSBw_PreInd |
| 7U, // LDRSBw_U |
| 4736U, // LDRSBw_Wm_RegOffset |
| 4992U, // LDRSBw_Xm_RegOffset |
| 6U, // LDRSBx |
| 0U, // LDRSBx_PostInd |
| 6U, // LDRSBx_PreInd |
| 7U, // LDRSBx_U |
| 4736U, // LDRSBx_Wm_RegOffset |
| 4992U, // LDRSBx_Xm_RegOffset |
| 7U, // LDRSHw |
| 0U, // LDRSHw_PostInd |
| 6U, // LDRSHw_PreInd |
| 7U, // LDRSHw_U |
| 5248U, // LDRSHw_Wm_RegOffset |
| 5504U, // LDRSHw_Xm_RegOffset |
| 7U, // LDRSHx |
| 0U, // LDRSHx_PostInd |
| 6U, // LDRSHx_PreInd |
| 7U, // LDRSHx_U |
| 5248U, // LDRSHx_Wm_RegOffset |
| 5504U, // LDRSHx_Xm_RegOffset |
| 7U, // LDRSWx |
| 0U, // LDRSWx_PostInd |
| 6U, // LDRSWx_PreInd |
| 5760U, // LDRSWx_Wm_RegOffset |
| 6016U, // LDRSWx_Xm_RegOffset |
| 0U, // LDRSWx_lit |
| 0U, // LDRd_lit |
| 0U, // LDRq_lit |
| 0U, // LDRs_lit |
| 0U, // LDRw_lit |
| 0U, // LDRx_lit |
| 7U, // LDTRSBw |
| 7U, // LDTRSBx |
| 7U, // LDTRSHw |
| 7U, // LDTRSHx |
| 7U, // LDTRSWx |
| 7U, // LDURSWx |
| 144U, // LDXP_dword |
| 144U, // LDXP_word |
| 0U, // LDXR_byte |
| 0U, // LDXR_dword |
| 0U, // LDXR_hword |
| 0U, // LDXR_word |
| 7U, // LS16_LDR |
| 7U, // LS16_LDUR |
| 0U, // LS16_PostInd_LDR |
| 0U, // LS16_PostInd_STR |
| 6U, // LS16_PreInd_LDR |
| 6U, // LS16_PreInd_STR |
| 7U, // LS16_STR |
| 7U, // LS16_STUR |
| 7U, // LS16_UnPriv_LDR |
| 7U, // LS16_UnPriv_STR |
| 5248U, // LS16_Wm_RegOffset_LDR |
| 5248U, // LS16_Wm_RegOffset_STR |
| 5504U, // LS16_Xm_RegOffset_LDR |
| 5504U, // LS16_Xm_RegOffset_STR |
| 7U, // LS32_LDR |
| 7U, // LS32_LDUR |
| 0U, // LS32_PostInd_LDR |
| 0U, // LS32_PostInd_STR |
| 6U, // LS32_PreInd_LDR |
| 6U, // LS32_PreInd_STR |
| 7U, // LS32_STR |
| 7U, // LS32_STUR |
| 7U, // LS32_UnPriv_LDR |
| 7U, // LS32_UnPriv_STR |
| 5760U, // LS32_Wm_RegOffset_LDR |
| 5760U, // LS32_Wm_RegOffset_STR |
| 6016U, // LS32_Xm_RegOffset_LDR |
| 6016U, // LS32_Xm_RegOffset_STR |
| 7U, // LS64_LDR |
| 7U, // LS64_LDUR |
| 0U, // LS64_PostInd_LDR |
| 0U, // LS64_PostInd_STR |
| 6U, // LS64_PreInd_LDR |
| 6U, // LS64_PreInd_STR |
| 7U, // LS64_STR |
| 7U, // LS64_STUR |
| 7U, // LS64_UnPriv_LDR |
| 7U, // LS64_UnPriv_STR |
| 6272U, // LS64_Wm_RegOffset_LDR |
| 6272U, // LS64_Wm_RegOffset_STR |
| 6528U, // LS64_Xm_RegOffset_LDR |
| 6528U, // LS64_Xm_RegOffset_STR |
| 6U, // LS8_LDR |
| 7U, // LS8_LDUR |
| 0U, // LS8_PostInd_LDR |
| 0U, // LS8_PostInd_STR |
| 6U, // LS8_PreInd_LDR |
| 6U, // LS8_PreInd_STR |
| 6U, // LS8_STR |
| 7U, // LS8_STUR |
| 7U, // LS8_UnPriv_LDR |
| 7U, // LS8_UnPriv_STR |
| 4736U, // LS8_Wm_RegOffset_LDR |
| 4736U, // LS8_Wm_RegOffset_STR |
| 4992U, // LS8_Xm_RegOffset_LDR |
| 4992U, // LS8_Xm_RegOffset_STR |
| 8U, // LSFP128_LDR |
| 7U, // LSFP128_LDUR |
| 0U, // LSFP128_PostInd_LDR |
| 0U, // LSFP128_PostInd_STR |
| 6U, // LSFP128_PreInd_LDR |
| 6U, // LSFP128_PreInd_STR |
| 8U, // LSFP128_STR |
| 7U, // LSFP128_STUR |
| 6784U, // LSFP128_Wm_RegOffset_LDR |
| 6784U, // LSFP128_Wm_RegOffset_STR |
| 7040U, // LSFP128_Xm_RegOffset_LDR |
| 7040U, // LSFP128_Xm_RegOffset_STR |
| 7U, // LSFP16_LDR |
| 7U, // LSFP16_LDUR |
| 0U, // LSFP16_PostInd_LDR |
| 0U, // LSFP16_PostInd_STR |
| 6U, // LSFP16_PreInd_LDR |
| 6U, // LSFP16_PreInd_STR |
| 7U, // LSFP16_STR |
| 7U, // LSFP16_STUR |
| 5248U, // LSFP16_Wm_RegOffset_LDR |
| 5248U, // LSFP16_Wm_RegOffset_STR |
| 5504U, // LSFP16_Xm_RegOffset_LDR |
| 5504U, // LSFP16_Xm_RegOffset_STR |
| 7U, // LSFP32_LDR |
| 7U, // LSFP32_LDUR |
| 0U, // LSFP32_PostInd_LDR |
| 0U, // LSFP32_PostInd_STR |
| 6U, // LSFP32_PreInd_LDR |
| 6U, // LSFP32_PreInd_STR |
| 7U, // LSFP32_STR |
| 7U, // LSFP32_STUR |
| 5760U, // LSFP32_Wm_RegOffset_LDR |
| 5760U, // LSFP32_Wm_RegOffset_STR |
| 6016U, // LSFP32_Xm_RegOffset_LDR |
| 6016U, // LSFP32_Xm_RegOffset_STR |
| 7U, // LSFP64_LDR |
| 7U, // LSFP64_LDUR |
| 0U, // LSFP64_PostInd_LDR |
| 0U, // LSFP64_PostInd_STR |
| 6U, // LSFP64_PreInd_LDR |
| 6U, // LSFP64_PreInd_STR |
| 7U, // LSFP64_STR |
| 7U, // LSFP64_STUR |
| 6272U, // LSFP64_Wm_RegOffset_LDR |
| 6272U, // LSFP64_Wm_RegOffset_STR |
| 6528U, // LSFP64_Xm_RegOffset_LDR |
| 6528U, // LSFP64_Xm_RegOffset_STR |
| 6U, // LSFP8_LDR |
| 7U, // LSFP8_LDUR |
| 0U, // LSFP8_PostInd_LDR |
| 0U, // LSFP8_PostInd_STR |
| 6U, // LSFP8_PreInd_LDR |
| 6U, // LSFP8_PreInd_STR |
| 6U, // LSFP8_STR |
| 7U, // LSFP8_STUR |
| 4736U, // LSFP8_Wm_RegOffset_LDR |
| 4736U, // LSFP8_Wm_RegOffset_STR |
| 4992U, // LSFP8_Xm_RegOffset_LDR |
| 4992U, // LSFP8_Xm_RegOffset_STR |
| 7296U, // LSFPPair128_LDR |
| 7296U, // LSFPPair128_NonTemp_LDR |
| 7296U, // LSFPPair128_NonTemp_STR |
| 7586U, // LSFPPair128_PostInd_LDR |
| 7586U, // LSFPPair128_PostInd_STR |
| 23938U, // LSFPPair128_PreInd_LDR |
| 23938U, // LSFPPair128_PreInd_STR |
| 7296U, // LSFPPair128_STR |
| 4224U, // LSFPPair32_LDR |
| 4224U, // LSFPPair32_NonTemp_LDR |
| 4224U, // LSFPPair32_NonTemp_STR |
| 4514U, // LSFPPair32_PostInd_LDR |
| 4514U, // LSFPPair32_PostInd_STR |
| 20866U, // LSFPPair32_PreInd_LDR |
| 20866U, // LSFPPair32_PreInd_STR |
| 4224U, // LSFPPair32_STR |
| 7808U, // LSFPPair64_LDR |
| 7808U, // LSFPPair64_NonTemp_LDR |
| 7808U, // LSFPPair64_NonTemp_STR |
| 8098U, // LSFPPair64_PostInd_LDR |
| 8098U, // LSFPPair64_PostInd_STR |
| 24450U, // LSFPPair64_PreInd_LDR |
| 24450U, // LSFPPair64_PreInd_STR |
| 7808U, // LSFPPair64_STR |
| 0U, // LSLVwww |
| 0U, // LSLVxxx |
| 0U, // LSLwwi |
| 0U, // LSLxxi |
| 4224U, // LSPair32_LDR |
| 4224U, // LSPair32_NonTemp_LDR |
| 4224U, // LSPair32_NonTemp_STR |
| 4514U, // LSPair32_PostInd_LDR |
| 4514U, // LSPair32_PostInd_STR |
| 20866U, // LSPair32_PreInd_LDR |
| 20866U, // LSPair32_PreInd_STR |
| 4224U, // LSPair32_STR |
| 7808U, // LSPair64_LDR |
| 7808U, // LSPair64_NonTemp_LDR |
| 7808U, // LSPair64_NonTemp_STR |
| 8098U, // LSPair64_PostInd_LDR |
| 8098U, // LSPair64_PostInd_STR |
| 24450U, // LSPair64_PreInd_LDR |
| 24450U, // LSPair64_PreInd_STR |
| 7808U, // LSPair64_STR |
| 0U, // LSRVwww |
| 0U, // LSRVxxx |
| 0U, // LSRwwi |
| 0U, // LSRxxi |
| 3968U, // MADDwwww |
| 3968U, // MADDxxxx |
| 64U, // MLAvvv_16B |
| 80U, // MLAvvv_2S |
| 96U, // MLAvvv_4H |
| 48U, // MLAvvv_4S |
| 112U, // MLAvvv_8B |
| 16U, // MLAvvv_8H |
| 64U, // MLSvvv_16B |
| 80U, // MLSvvv_2S |
| 96U, // MLSvvv_4H |
| 48U, // MLSvvv_4S |
| 112U, // MLSvvv_8B |
| 16U, // MLSvvv_8H |
| 0U, // MOVIdi |
| 0U, // MOVIvi_16B |
| 0U, // MOVIvi_2D |
| 0U, // MOVIvi_8B |
| 0U, // MOVIvi_lsl_2S |
| 0U, // MOVIvi_lsl_4H |
| 0U, // MOVIvi_lsl_4S |
| 0U, // MOVIvi_lsl_8H |
| 0U, // MOVIvi_msl_2S |
| 0U, // MOVIvi_msl_4S |
| 0U, // MOVKwii |
| 0U, // MOVKxii |
| 0U, // MOVNwii |
| 0U, // MOVNxii |
| 0U, // MOVZwii |
| 0U, // MOVZxii |
| 0U, // MRSxi |
| 0U, // MSRii |
| 0U, // MSRix |
| 3968U, // MSUBwwww |
| 3968U, // MSUBxxxx |
| 64U, // MULvvv_16B |
| 80U, // MULvvv_2S |
| 96U, // MULvvv_4H |
| 48U, // MULvvv_4S |
| 112U, // MULvvv_8B |
| 16U, // MULvvv_8H |
| 0U, // MVNIvi_lsl_2S |
| 0U, // MVNIvi_lsl_4H |
| 0U, // MVNIvi_lsl_4S |
| 0U, // MVNIvi_lsl_8H |
| 0U, // MVNIvi_msl_2S |
| 0U, // MVNIvi_msl_4S |
| 2U, // MVNww_asr |
| 3U, // MVNww_lsl |
| 3U, // MVNww_lsr |
| 8U, // MVNww_ror |
| 2U, // MVNxx_asr |
| 3U, // MVNxx_lsl |
| 3U, // MVNxx_lsr |
| 8U, // MVNxx_ror |
| 64U, // ORNvvv_16B |
| 112U, // ORNvvv_8B |
| 128U, // ORNwww_asr |
| 384U, // ORNwww_lsl |
| 640U, // ORNwww_lsr |
| 2944U, // ORNwww_ror |
| 128U, // ORNxxx_asr |
| 384U, // ORNxxx_lsl |
| 640U, // ORNxxx_lsr |
| 2944U, // ORNxxx_ror |
| 0U, // ORRvi_lsl_2S |
| 0U, // ORRvi_lsl_4H |
| 0U, // ORRvi_lsl_4S |
| 0U, // ORRvi_lsl_8H |
| 64U, // ORRvvv_16B |
| 112U, // ORRvvv_8B |
| 1U, // ORRwwi |
| 128U, // ORRwww_asr |
| 384U, // ORRwww_lsl |
| 640U, // ORRwww_lsr |
| 2944U, // ORRwww_ror |
| 1U, // ORRxxi |
| 128U, // ORRxxx_asr |
| 384U, // ORRxxx_lsl |
| 640U, // ORRxxx_lsr |
| 2944U, // ORRxxx_ror |
| 64U, // PMULL2vvv_8h16b |
| 112U, // PMULLvvv_8h8b |
| 64U, // PMULvvv_16B |
| 112U, // PMULvvv_8B |
| 7U, // PRFM |
| 6272U, // PRFM_Wm_RegOffset |
| 6528U, // PRFM_Xm_RegOffset |
| 0U, // PRFM_lit |
| 7U, // PRFUM |
| 2U, // QRSHRUNvvi_16B |
| 0U, // QRSHRUNvvi_2S |
| 0U, // QRSHRUNvvi_4H |
| 2U, // QRSHRUNvvi_4S |
| 0U, // QRSHRUNvvi_8B |
| 2U, // QRSHRUNvvi_8H |
| 2U, // QSHRUNvvi_16B |
| 0U, // QSHRUNvvi_2S |
| 0U, // QSHRUNvvi_4H |
| 2U, // QSHRUNvvi_4S |
| 0U, // QSHRUNvvi_8B |
| 2U, // QSHRUNvvi_8H |
| 16U, // RADDHN2vvv_16b8h |
| 32U, // RADDHN2vvv_4s2d |
| 48U, // RADDHN2vvv_8h4s |
| 32U, // RADDHNvvv_2s2d |
| 48U, // RADDHNvvv_4h4s |
| 16U, // RADDHNvvv_8b8h |
| 0U, // RBITww |
| 0U, // RBITxx |
| 0U, // RET |
| 0U, // RETx |
| 0U, // REV16ww |
| 0U, // REV16xx |
| 0U, // REV32xx |
| 0U, // REVww |
| 0U, // REVxx |
| 0U, // RORVwww |
| 0U, // RORVxxx |
| 2U, // RSHRNvvi_16B |
| 0U, // RSHRNvvi_2S |
| 0U, // RSHRNvvi_4H |
| 2U, // RSHRNvvi_4S |
| 0U, // RSHRNvvi_8B |
| 2U, // RSHRNvvi_8H |
| 16U, // RSUBHN2vvv_16b8h |
| 32U, // RSUBHN2vvv_4s2d |
| 48U, // RSUBHN2vvv_8h4s |
| 32U, // RSUBHNvvv_2s2d |
| 48U, // RSUBHNvvv_4h4s |
| 16U, // RSUBHNvvv_8b8h |
| 48U, // SABAL2vvv_2d2s |
| 16U, // SABAL2vvv_4s4h |
| 64U, // SABAL2vvv_8h8b |
| 80U, // SABALvvv_2d2s |
| 96U, // SABALvvv_4s4h |
| 112U, // SABALvvv_8h8b |
| 64U, // SABAvvv_16B |
| 80U, // SABAvvv_2S |
| 96U, // SABAvvv_4H |
| 48U, // SABAvvv_4S |
| 112U, // SABAvvv_8B |
| 16U, // SABAvvv_8H |
| 48U, // SABDL2vvv_2d2s |
| 16U, // SABDL2vvv_4s4h |
| 64U, // SABDL2vvv_8h8b |
| 80U, // SABDLvvv_2d2s |
| 96U, // SABDLvvv_4s4h |
| 112U, // SABDLvvv_8h8b |
| 64U, // SABDvvv_16B |
| 80U, // SABDvvv_2S |
| 96U, // SABDvvv_4H |
| 48U, // SABDvvv_4S |
| 112U, // SABDvvv_8B |
| 16U, // SABDvvv_8H |
| 48U, // SADDL2vvv_2d4s |
| 16U, // SADDL2vvv_4s8h |
| 64U, // SADDL2vvv_8h16b |
| 80U, // SADDLvvv_2d2s |
| 96U, // SADDLvvv_4s4h |
| 112U, // SADDLvvv_8h8b |
| 48U, // SADDW2vvv_2d4s |
| 16U, // SADDW2vvv_4s8h |
| 64U, // SADDW2vvv_8h16b |
| 80U, // SADDWvvv_2d2s |
| 96U, // SADDWvvv_4s4h |
| 112U, // SADDWvvv_8h8b |
| 0U, // SBCSwww |
| 0U, // SBCSxxx |
| 0U, // SBCwww |
| 0U, // SBCxxx |
| 8U, // SBFIZwwii |
| 8U, // SBFIZxxii |
| 3968U, // SBFMwwii |
| 3968U, // SBFMxxii |
| 8320U, // SBFXwwii |
| 8320U, // SBFXxxii |
| 0U, // SCVTFdw |
| 5U, // SCVTFdwi |
| 0U, // SCVTFdx |
| 5U, // SCVTFdxi |
| 0U, // SCVTFsw |
| 5U, // SCVTFswi |
| 0U, // SCVTFsx |
| 5U, // SCVTFsxi |
| 0U, // SDIVwww |
| 0U, // SDIVxxx |
| 64U, // SHADDvvv_16B |
| 80U, // SHADDvvv_2S |
| 96U, // SHADDvvv_4H |
| 48U, // SHADDvvv_4S |
| 112U, // SHADDvvv_8B |
| 16U, // SHADDvvv_8H |
| 0U, // SHLvvi_16B |
| 0U, // SHLvvi_2D |
| 0U, // SHLvvi_2S |
| 0U, // SHLvvi_4H |
| 0U, // SHLvvi_4S |
| 0U, // SHLvvi_8B |
| 0U, // SHLvvi_8H |
| 2U, // SHRNvvi_16B |
| 0U, // SHRNvvi_2S |
| 0U, // SHRNvvi_4H |
| 2U, // SHRNvvi_4S |
| 0U, // SHRNvvi_8B |
| 2U, // SHRNvvi_8H |
| 64U, // SHSUBvvv_16B |
| 80U, // SHSUBvvv_2S |
| 96U, // SHSUBvvv_4H |
| 48U, // SHSUBvvv_4S |
| 112U, // SHSUBvvv_8B |
| 16U, // SHSUBvvv_8H |
| 2U, // SLIvvi_16B |
| 2U, // SLIvvi_2D |
| 2U, // SLIvvi_2S |
| 2U, // SLIvvi_4H |
| 2U, // SLIvvi_4S |
| 2U, // SLIvvi_8B |
| 2U, // SLIvvi_8H |
| 3968U, // SMADDLxwwx |
| 64U, // SMAXPvvv_16B |
| 80U, // SMAXPvvv_2S |
| 96U, // SMAXPvvv_4H |
| 48U, // SMAXPvvv_4S |
| 112U, // SMAXPvvv_8B |
| 16U, // SMAXPvvv_8H |
| 64U, // SMAXvvv_16B |
| 80U, // SMAXvvv_2S |
| 96U, // SMAXvvv_4H |
| 48U, // SMAXvvv_4S |
| 112U, // SMAXvvv_8B |
| 16U, // SMAXvvv_8H |
| 0U, // SMCi |
| 64U, // SMINPvvv_16B |
| 80U, // SMINPvvv_2S |
| 96U, // SMINPvvv_4H |
| 48U, // SMINPvvv_4S |
| 112U, // SMINPvvv_8B |
| 16U, // SMINPvvv_8H |
| 64U, // SMINvvv_16B |
| 80U, // SMINvvv_2S |
| 96U, // SMINvvv_4H |
| 48U, // SMINvvv_4S |
| 112U, // SMINvvv_8B |
| 16U, // SMINvvv_8H |
| 48U, // SMLAL2vvv_2d4s |
| 16U, // SMLAL2vvv_4s8h |
| 64U, // SMLAL2vvv_8h16b |
| 80U, // SMLALvvv_2d2s |
| 96U, // SMLALvvv_4s4h |
| 112U, // SMLALvvv_8h8b |
| 48U, // SMLSL2vvv_2d4s |
| 16U, // SMLSL2vvv_4s8h |
| 64U, // SMLSL2vvv_8h16b |
| 80U, // SMLSLvvv_2d2s |
| 96U, // SMLSLvvv_4s4h |
| 112U, // SMLSLvvv_8h8b |
| 9U, // SMOVwb |
| 9U, // SMOVwh |
| 9U, // SMOVxb |
| 9U, // SMOVxh |
| 9U, // SMOVxs |
| 3968U, // SMSUBLxwwx |
| 0U, // SMULHxxx |
| 48U, // SMULL2vvv_2d4s |
| 16U, // SMULL2vvv_4s8h |
| 64U, // SMULL2vvv_8h16b |
| 80U, // SMULLvvv_2d2s |
| 96U, // SMULLvvv_4s4h |
| 112U, // SMULLvvv_8h8b |
| 0U, // SQADDbbb |
| 0U, // SQADDddd |
| 0U, // SQADDhhh |
| 0U, // SQADDsss |
| 64U, // SQADDvvv_16B |
| 32U, // SQADDvvv_2D |
| 80U, // SQADDvvv_2S |
| 96U, // SQADDvvv_4H |
| 48U, // SQADDvvv_4S |
| 112U, // SQADDvvv_8B |
| 16U, // SQADDvvv_8H |
| 48U, // SQDMLAL2vvv_2d4s |
| 16U, // SQDMLAL2vvv_4s8h |
| 80U, // SQDMLALvvv_2d2s |
| 96U, // SQDMLALvvv_4s4h |
| 48U, // SQDMLSL2vvv_2d4s |
| 16U, // SQDMLSL2vvv_4s8h |
| 80U, // SQDMLSLvvv_2d2s |
| 96U, // SQDMLSLvvv_4s4h |
| 80U, // SQDMULHvvv_2S |
| 96U, // SQDMULHvvv_4H |
| 48U, // SQDMULHvvv_4S |
| 16U, // SQDMULHvvv_8H |
| 48U, // SQDMULL2vvv_2d4s |
| 16U, // SQDMULL2vvv_4s8h |
| 80U, // SQDMULLvvv_2d2s |
| 96U, // SQDMULLvvv_4s4h |
| 80U, // SQRDMULHvvv_2S |
| 96U, // SQRDMULHvvv_4H |
| 48U, // SQRDMULHvvv_4S |
| 16U, // SQRDMULHvvv_8H |
| 0U, // SQRSHLbbb |
| 0U, // SQRSHLddd |
| 0U, // SQRSHLhhh |
| 0U, // SQRSHLsss |
| 64U, // SQRSHLvvv_16B |
| 32U, // SQRSHLvvv_2D |
| 80U, // SQRSHLvvv_2S |
| 96U, // SQRSHLvvv_4H |
| 48U, // SQRSHLvvv_4S |
| 112U, // SQRSHLvvv_8B |
| 16U, // SQRSHLvvv_8H |
| 2U, // SQRSHRNvvi_16B |
| 0U, // SQRSHRNvvi_2S |
| 0U, // SQRSHRNvvi_4H |
| 2U, // SQRSHRNvvi_4S |
| 0U, // SQRSHRNvvi_8B |
| 2U, // SQRSHRNvvi_8H |
| 0U, // SQSHLUvvi_16B |
| 0U, // SQSHLUvvi_2D |
| 0U, // SQSHLUvvi_2S |
| 0U, // SQSHLUvvi_4H |
| 0U, // SQSHLUvvi_4S |
| 0U, // SQSHLUvvi_8B |
| 0U, // SQSHLUvvi_8H |
| 0U, // SQSHLbbb |
| 0U, // SQSHLddd |
| 0U, // SQSHLhhh |
| 0U, // SQSHLsss |
| 0U, // SQSHLvvi_16B |
| 0U, // SQSHLvvi_2D |
| 0U, // SQSHLvvi_2S |
| 0U, // SQSHLvvi_4H |
| 0U, // SQSHLvvi_4S |
| 0U, // SQSHLvvi_8B |
| 0U, // SQSHLvvi_8H |
| 64U, // SQSHLvvv_16B |
| 32U, // SQSHLvvv_2D |
| 80U, // SQSHLvvv_2S |
| 96U, // SQSHLvvv_4H |
| 48U, // SQSHLvvv_4S |
| 112U, // SQSHLvvv_8B |
| 16U, // SQSHLvvv_8H |
| 2U, // SQSHRNvvi_16B |
| 0U, // SQSHRNvvi_2S |
| 0U, // SQSHRNvvi_4H |
| 2U, // SQSHRNvvi_4S |
| 0U, // SQSHRNvvi_8B |
| 2U, // SQSHRNvvi_8H |
| 0U, // SQSUBbbb |
| 0U, // SQSUBddd |
| 0U, // SQSUBhhh |
| 0U, // SQSUBsss |
| 64U, // SQSUBvvv_16B |
| 32U, // SQSUBvvv_2D |
| 80U, // SQSUBvvv_2S |
| 96U, // SQSUBvvv_4H |
| 48U, // SQSUBvvv_4S |
| 112U, // SQSUBvvv_8B |
| 16U, // SQSUBvvv_8H |
| 64U, // SRHADDvvv_16B |
| 80U, // SRHADDvvv_2S |
| 96U, // SRHADDvvv_4H |
| 48U, // SRHADDvvv_4S |
| 112U, // SRHADDvvv_8B |
| 16U, // SRHADDvvv_8H |
| 2U, // SRIvvi_16B |
| 2U, // SRIvvi_2D |
| 2U, // SRIvvi_2S |
| 2U, // SRIvvi_4H |
| 2U, // SRIvvi_4S |
| 2U, // SRIvvi_8B |
| 2U, // SRIvvi_8H |
| 0U, // SRSHLddd |
| 64U, // SRSHLvvv_16B |
| 32U, // SRSHLvvv_2D |
| 80U, // SRSHLvvv_2S |
| 96U, // SRSHLvvv_4H |
| 48U, // SRSHLvvv_4S |
| 112U, // SRSHLvvv_8B |
| 16U, // SRSHLvvv_8H |
| 0U, // SRSHRvvi_16B |
| 0U, // SRSHRvvi_2D |
| 0U, // SRSHRvvi_2S |
| 0U, // SRSHRvvi_4H |
| 0U, // SRSHRvvi_4S |
| 0U, // SRSHRvvi_8B |
| 0U, // SRSHRvvi_8H |
| 2U, // SRSRAvvi_16B |
| 2U, // SRSRAvvi_2D |
| 2U, // SRSRAvvi_2S |
| 2U, // SRSRAvvi_4H |
| 2U, // SRSRAvvi_4S |
| 2U, // SRSRAvvi_8B |
| 2U, // SRSRAvvi_8H |
| 0U, // SSHLLvvi_16B |
| 0U, // SSHLLvvi_2S |
| 0U, // SSHLLvvi_4H |
| 0U, // SSHLLvvi_4S |
| 0U, // SSHLLvvi_8B |
| 0U, // SSHLLvvi_8H |
| 0U, // SSHLddd |
| 64U, // SSHLvvv_16B |
| 32U, // SSHLvvv_2D |
| 80U, // SSHLvvv_2S |
| 96U, // SSHLvvv_4H |
| 48U, // SSHLvvv_4S |
| 112U, // SSHLvvv_8B |
| 16U, // SSHLvvv_8H |
| 0U, // SSHRvvi_16B |
| 0U, // SSHRvvi_2D |
| 0U, // SSHRvvi_2S |
| 0U, // SSHRvvi_4H |
| 0U, // SSHRvvi_4S |
| 0U, // SSHRvvi_8B |
| 0U, // SSHRvvi_8H |
| 2U, // SSRAvvi_16B |
| 2U, // SSRAvvi_2D |
| 2U, // SSRAvvi_2S |
| 2U, // SSRAvvi_4H |
| 2U, // SSRAvvi_4S |
| 2U, // SSRAvvi_8B |
| 2U, // SSRAvvi_8H |
| 48U, // SSUBL2vvv_2d4s |
| 16U, // SSUBL2vvv_4s8h |
| 64U, // SSUBL2vvv_8h16b |
| 80U, // SSUBLvvv_2d2s |
| 96U, // SSUBLvvv_4s4h |
| 112U, // SSUBLvvv_8h8b |
| 48U, // SSUBW2vvv_2d4s |
| 16U, // SSUBW2vvv_4s8h |
| 64U, // SSUBW2vvv_8h16b |
| 80U, // SSUBWvvv_2d2s |
| 96U, // SSUBWvvv_4s4h |
| 112U, // SSUBWvvv_8h8b |
| 0U, // STLR_byte |
| 0U, // STLR_dword |
| 0U, // STLR_hword |
| 0U, // STLR_word |
| 176U, // STLXP_dword |
| 176U, // STLXP_word |
| 144U, // STLXR_byte |
| 144U, // STLXR_dword |
| 144U, // STLXR_hword |
| 144U, // STLXR_word |
| 176U, // STXP_dword |
| 176U, // STXP_word |
| 144U, // STXR_byte |
| 144U, // STXR_dword |
| 144U, // STXR_hword |
| 144U, // STXR_word |
| 16U, // SUBHN2vvv_16b8h |
| 32U, // SUBHN2vvv_4s2d |
| 48U, // SUBHN2vvv_8h4s |
| 32U, // SUBHNvvv_2s2d |
| 48U, // SUBHNvvv_4h4s |
| 16U, // SUBHNvvv_8b8h |
| 128U, // SUBSwww_asr |
| 384U, // SUBSwww_lsl |
| 640U, // SUBSwww_lsr |
| 896U, // SUBSwww_sxtb |
| 1152U, // SUBSwww_sxth |
| 1408U, // SUBSwww_sxtw |
| 1664U, // SUBSwww_sxtx |
| 1920U, // SUBSwww_uxtb |
| 2176U, // SUBSwww_uxth |
| 2432U, // SUBSwww_uxtw |
| 2688U, // SUBSwww_uxtx |
| 896U, // SUBSxxw_sxtb |
| 1152U, // SUBSxxw_sxth |
| 1408U, // SUBSxxw_sxtw |
| 1920U, // SUBSxxw_uxtb |
| 2176U, // SUBSxxw_uxth |
| 2432U, // SUBSxxw_uxtw |
| 128U, // SUBSxxx_asr |
| 384U, // SUBSxxx_lsl |
| 640U, // SUBSxxx_lsr |
| 1664U, // SUBSxxx_sxtx |
| 2688U, // SUBSxxx_uxtx |
| 0U, // SUBddd |
| 64U, // SUBvvv_16B |
| 32U, // SUBvvv_2D |
| 80U, // SUBvvv_2S |
| 96U, // SUBvvv_4H |
| 48U, // SUBvvv_4S |
| 112U, // SUBvvv_8B |
| 16U, // SUBvvv_8H |
| 0U, // SUBwwi_lsl0_S |
| 0U, // SUBwwi_lsl0_cmp |
| 0U, // SUBwwi_lsl0_s |
| 1U, // SUBwwi_lsl12_S |
| 0U, // SUBwwi_lsl12_cmp |
| 1U, // SUBwwi_lsl12_s |
| 128U, // SUBwww_asr |
| 384U, // SUBwww_lsl |
| 640U, // SUBwww_lsr |
| 896U, // SUBwww_sxtb |
| 1152U, // SUBwww_sxth |
| 1408U, // SUBwww_sxtw |
| 1664U, // SUBwww_sxtx |
| 1920U, // SUBwww_uxtb |
| 2176U, // SUBwww_uxth |
| 2432U, // SUBwww_uxtw |
| 2688U, // SUBwww_uxtx |
| 0U, // SUBxxi_lsl0_S |
| 0U, // SUBxxi_lsl0_cmp |
| 0U, // SUBxxi_lsl0_s |
| 1U, // SUBxxi_lsl12_S |
| 0U, // SUBxxi_lsl12_cmp |
| 1U, // SUBxxi_lsl12_s |
| 896U, // SUBxxw_sxtb |
| 1152U, // SUBxxw_sxth |
| 1408U, // SUBxxw_sxtw |
| 1920U, // SUBxxw_uxtb |
| 2176U, // SUBxxw_uxth |
| 2432U, // SUBxxw_uxtw |
| 128U, // SUBxxx_asr |
| 384U, // SUBxxx_lsl |
| 640U, // SUBxxx_lsr |
| 1664U, // SUBxxx_sxtx |
| 2688U, // SUBxxx_uxtx |
| 0U, // SVCi |
| 0U, // SXTBww |
| 0U, // SXTBxw |
| 0U, // SXTHww |
| 0U, // SXTHxw |
| 0U, // SXTWxw |
| 9U, // SYSLxicci |
| 0U, // SYSiccix |
| 0U, // TAIL_BRx |
| 0U, // TAIL_Bimm |
| 9U, // TBNZwii |
| 9U, // TBNZxii |
| 9U, // TBZwii |
| 9U, // TBZxii |
| 0U, // TC_RETURNdi |
| 0U, // TC_RETURNxi |
| 0U, // TLBIi |
| 0U, // TLBIix |
| 0U, // TLSDESCCALL |
| 0U, // TLSDESC_BLRx |
| 2U, // TSTww_asr |
| 3U, // TSTww_lsl |
| 3U, // TSTww_lsr |
| 8U, // TSTww_ror |
| 2U, // TSTxx_asr |
| 3U, // TSTxx_lsl |
| 3U, // TSTxx_lsr |
| 8U, // TSTxx_ror |
| 48U, // UABAL2vvv_2d2s |
| 16U, // UABAL2vvv_4s4h |
| 64U, // UABAL2vvv_8h8b |
| 80U, // UABALvvv_2d2s |
| 96U, // UABALvvv_4s4h |
| 112U, // UABALvvv_8h8b |
| 64U, // UABAvvv_16B |
| 80U, // UABAvvv_2S |
| 96U, // UABAvvv_4H |
| 48U, // UABAvvv_4S |
| 112U, // UABAvvv_8B |
| 16U, // UABAvvv_8H |
| 48U, // UABDL2vvv_2d2s |
| 16U, // UABDL2vvv_4s4h |
| 64U, // UABDL2vvv_8h8b |
| 80U, // UABDLvvv_2d2s |
| 96U, // UABDLvvv_4s4h |
| 112U, // UABDLvvv_8h8b |
| 64U, // UABDvvv_16B |
| 80U, // UABDvvv_2S |
| 96U, // UABDvvv_4H |
| 48U, // UABDvvv_4S |
| 112U, // UABDvvv_8B |
| 16U, // UABDvvv_8H |
| 48U, // UADDL2vvv_2d4s |
| 16U, // UADDL2vvv_4s8h |
| 64U, // UADDL2vvv_8h16b |
| 80U, // UADDLvvv_2d2s |
| 96U, // UADDLvvv_4s4h |
| 112U, // UADDLvvv_8h8b |
| 48U, // UADDW2vvv_2d4s |
| 16U, // UADDW2vvv_4s8h |
| 64U, // UADDW2vvv_8h16b |
| 80U, // UADDWvvv_2d2s |
| 96U, // UADDWvvv_4s4h |
| 112U, // UADDWvvv_8h8b |
| 8U, // UBFIZwwii |
| 8U, // UBFIZxxii |
| 3968U, // UBFMwwii |
| 3968U, // UBFMxxii |
| 8320U, // UBFXwwii |
| 8320U, // UBFXxxii |
| 0U, // UCVTFdw |
| 5U, // UCVTFdwi |
| 0U, // UCVTFdx |
| 5U, // UCVTFdxi |
| 0U, // UCVTFsw |
| 5U, // UCVTFswi |
| 0U, // UCVTFsx |
| 5U, // UCVTFsxi |
| 0U, // UDIVwww |
| 0U, // UDIVxxx |
| 64U, // UHADDvvv_16B |
| 80U, // UHADDvvv_2S |
| 96U, // UHADDvvv_4H |
| 48U, // UHADDvvv_4S |
| 112U, // UHADDvvv_8B |
| 16U, // UHADDvvv_8H |
| 64U, // UHSUBvvv_16B |
| 80U, // UHSUBvvv_2S |
| 96U, // UHSUBvvv_4H |
| 48U, // UHSUBvvv_4S |
| 112U, // UHSUBvvv_8B |
| 16U, // UHSUBvvv_8H |
| 3968U, // UMADDLxwwx |
| 64U, // UMAXPvvv_16B |
| 80U, // UMAXPvvv_2S |
| 96U, // UMAXPvvv_4H |
| 48U, // UMAXPvvv_4S |
| 112U, // UMAXPvvv_8B |
| 16U, // UMAXPvvv_8H |
| 64U, // UMAXvvv_16B |
| 80U, // UMAXvvv_2S |
| 96U, // UMAXvvv_4H |
| 48U, // UMAXvvv_4S |
| 112U, // UMAXvvv_8B |
| 16U, // UMAXvvv_8H |
| 64U, // UMINPvvv_16B |
| 80U, // UMINPvvv_2S |
| 96U, // UMINPvvv_4H |
| 48U, // UMINPvvv_4S |
| 112U, // UMINPvvv_8B |
| 16U, // UMINPvvv_8H |
| 64U, // UMINvvv_16B |
| 80U, // UMINvvv_2S |
| 96U, // UMINvvv_4H |
| 48U, // UMINvvv_4S |
| 112U, // UMINvvv_8B |
| 16U, // UMINvvv_8H |
| 48U, // UMLAL2vvv_2d4s |
| 16U, // UMLAL2vvv_4s8h |
| 64U, // UMLAL2vvv_8h16b |
| 80U, // UMLALvvv_2d2s |
| 96U, // UMLALvvv_4s4h |
| 112U, // UMLALvvv_8h8b |
| 48U, // UMLSL2vvv_2d4s |
| 16U, // UMLSL2vvv_4s8h |
| 64U, // UMLSL2vvv_8h16b |
| 80U, // UMLSLvvv_2d2s |
| 96U, // UMLSLvvv_4s4h |
| 112U, // UMLSLvvv_8h8b |
| 9U, // UMOVwb |
| 9U, // UMOVwh |
| 9U, // UMOVws |
| 9U, // UMOVxd |
| 3968U, // UMSUBLxwwx |
| 0U, // UMULHxxx |
| 48U, // UMULL2vvv_2d4s |
| 16U, // UMULL2vvv_4s8h |
| 64U, // UMULL2vvv_8h16b |
| 80U, // UMULLvvv_2d2s |
| 96U, // UMULLvvv_4s4h |
| 112U, // UMULLvvv_8h8b |
| 0U, // UQADDbbb |
| 0U, // UQADDddd |
| 0U, // UQADDhhh |
| 0U, // UQADDsss |
| 64U, // UQADDvvv_16B |
| 32U, // UQADDvvv_2D |
| 80U, // UQADDvvv_2S |
| 96U, // UQADDvvv_4H |
| 48U, // UQADDvvv_4S |
| 112U, // UQADDvvv_8B |
| 16U, // UQADDvvv_8H |
| 0U, // UQRSHLbbb |
| 0U, // UQRSHLddd |
| 0U, // UQRSHLhhh |
| 0U, // UQRSHLsss |
| 64U, // UQRSHLvvv_16B |
| 32U, // UQRSHLvvv_2D |
| 80U, // UQRSHLvvv_2S |
| 96U, // UQRSHLvvv_4H |
| 48U, // UQRSHLvvv_4S |
| 112U, // UQRSHLvvv_8B |
| 16U, // UQRSHLvvv_8H |
| 2U, // UQRSHRNvvi_16B |
| 0U, // UQRSHRNvvi_2S |
| 0U, // UQRSHRNvvi_4H |
| 2U, // UQRSHRNvvi_4S |
| 0U, // UQRSHRNvvi_8B |
| 2U, // UQRSHRNvvi_8H |
| 0U, // UQSHLbbb |
| 0U, // UQSHLddd |
| 0U, // UQSHLhhh |
| 0U, // UQSHLsss |
| 0U, // UQSHLvvi_16B |
| 0U, // UQSHLvvi_2D |
| 0U, // UQSHLvvi_2S |
| 0U, // UQSHLvvi_4H |
| 0U, // UQSHLvvi_4S |
| 0U, // UQSHLvvi_8B |
| 0U, // UQSHLvvi_8H |
| 64U, // UQSHLvvv_16B |
| 32U, // UQSHLvvv_2D |
| 80U, // UQSHLvvv_2S |
| 96U, // UQSHLvvv_4H |
| 48U, // UQSHLvvv_4S |
| 112U, // UQSHLvvv_8B |
| 16U, // UQSHLvvv_8H |
| 2U, // UQSHRNvvi_16B |
| 0U, // UQSHRNvvi_2S |
| 0U, // UQSHRNvvi_4H |
| 2U, // UQSHRNvvi_4S |
| 0U, // UQSHRNvvi_8B |
| 2U, // UQSHRNvvi_8H |
| 0U, // UQSUBbbb |
| 0U, // UQSUBddd |
| 0U, // UQSUBhhh |
| 0U, // UQSUBsss |
| 64U, // UQSUBvvv_16B |
| 32U, // UQSUBvvv_2D |
| 80U, // UQSUBvvv_2S |
| 96U, // UQSUBvvv_4H |
| 48U, // UQSUBvvv_4S |
| 112U, // UQSUBvvv_8B |
| 16U, // UQSUBvvv_8H |
| 64U, // URHADDvvv_16B |
| 80U, // URHADDvvv_2S |
| 96U, // URHADDvvv_4H |
| 48U, // URHADDvvv_4S |
| 112U, // URHADDvvv_8B |
| 16U, // URHADDvvv_8H |
| 0U, // URSHLddd |
| 64U, // URSHLvvv_16B |
| 32U, // URSHLvvv_2D |
| 80U, // URSHLvvv_2S |
| 96U, // URSHLvvv_4H |
| 48U, // URSHLvvv_4S |
| 112U, // URSHLvvv_8B |
| 16U, // URSHLvvv_8H |
| 0U, // URSHRvvi_16B |
| 0U, // URSHRvvi_2D |
| 0U, // URSHRvvi_2S |
| 0U, // URSHRvvi_4H |
| 0U, // URSHRvvi_4S |
| 0U, // URSHRvvi_8B |
| 0U, // URSHRvvi_8H |
| 2U, // URSRAvvi_16B |
| 2U, // URSRAvvi_2D |
| 2U, // URSRAvvi_2S |
| 2U, // URSRAvvi_4H |
| 2U, // URSRAvvi_4S |
| 2U, // URSRAvvi_8B |
| 2U, // URSRAvvi_8H |
| 0U, // USHLLvvi_16B |
| 0U, // USHLLvvi_2S |
| 0U, // USHLLvvi_4H |
| 0U, // USHLLvvi_4S |
| 0U, // USHLLvvi_8B |
| 0U, // USHLLvvi_8H |
| 0U, // USHLddd |
| 64U, // USHLvvv_16B |
| 32U, // USHLvvv_2D |
| 80U, // USHLvvv_2S |
| 96U, // USHLvvv_4H |
| 48U, // USHLvvv_4S |
| 112U, // USHLvvv_8B |
| 16U, // USHLvvv_8H |
| 0U, // USHRvvi_16B |
| 0U, // USHRvvi_2D |
| 0U, // USHRvvi_2S |
| 0U, // USHRvvi_4H |
| 0U, // USHRvvi_4S |
| 0U, // USHRvvi_8B |
| 0U, // USHRvvi_8H |
| 2U, // USRAvvi_16B |
| 2U, // USRAvvi_2D |
| 2U, // USRAvvi_2S |
| 2U, // USRAvvi_4H |
| 2U, // USRAvvi_4S |
| 2U, // USRAvvi_8B |
| 2U, // USRAvvi_8H |
| 48U, // USUBL2vvv_2d4s |
| 16U, // USUBL2vvv_4s8h |
| 64U, // USUBL2vvv_8h16b |
| 80U, // USUBLvvv_2d2s |
| 96U, // USUBLvvv_4s4h |
| 112U, // USUBLvvv_8h8b |
| 48U, // USUBW2vvv_2d4s |
| 16U, // USUBW2vvv_4s8h |
| 64U, // USUBW2vvv_8h16b |
| 80U, // USUBWvvv_2d2s |
| 96U, // USUBWvvv_4s4h |
| 112U, // USUBWvvv_8h8b |
| 0U, // UXTBww |
| 0U, // UXTBxw |
| 0U, // UXTHww |
| 0U, // UXTHxw |
| 0U, // VCVTf2xs_2D |
| 0U, // VCVTf2xs_2S |
| 0U, // VCVTf2xs_4S |
| 0U, // VCVTf2xu_2D |
| 0U, // VCVTf2xu_2S |
| 0U, // VCVTf2xu_4S |
| 0U, // VCVTxs2f_2D |
| 0U, // VCVTxs2f_2S |
| 0U, // VCVTxs2f_4S |
| 0U, // VCVTxu2f_2D |
| 0U, // VCVTxu2f_2S |
| 0U, // VCVTxu2f_4S |
| 0U |
| }; |
| |
| char AsmStrs[] = { |
| /* 0 */ 'd', 'c', 'p', 's', '1', 9, 0, |
| /* 7 */ 'r', 'e', 'v', '3', '2', 9, 0, |
| /* 14 */ 's', 'a', 'b', 'a', 'l', '2', 9, 0, |
| /* 22 */ 'u', 'a', 'b', 'a', 'l', '2', 9, 0, |
| /* 30 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', '2', 9, 0, |
| /* 40 */ 's', 'm', 'l', 'a', 'l', '2', 9, 0, |
| /* 48 */ 'u', 'm', 'l', 'a', 'l', '2', 9, 0, |
| /* 56 */ 's', 's', 'u', 'b', 'l', '2', 9, 0, |
| /* 64 */ 'u', 's', 'u', 'b', 'l', '2', 9, 0, |
| /* 72 */ 's', 'a', 'b', 'd', 'l', '2', 9, 0, |
| /* 80 */ 'u', 'a', 'b', 'd', 'l', '2', 9, 0, |
| /* 88 */ 's', 'a', 'd', 'd', 'l', '2', 9, 0, |
| /* 96 */ 'u', 'a', 'd', 'd', 'l', '2', 9, 0, |
| /* 104 */ 's', 's', 'h', 'l', 'l', '2', 9, 0, |
| /* 112 */ 'u', 's', 'h', 'l', 'l', '2', 9, 0, |
| /* 120 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', '2', 9, 0, |
| /* 130 */ 'p', 'm', 'u', 'l', 'l', '2', 9, 0, |
| /* 138 */ 's', 'm', 'u', 'l', 'l', '2', 9, 0, |
| /* 146 */ 'u', 'm', 'u', 'l', 'l', '2', 9, 0, |
| /* 154 */ 's', 'q', 'd', 'm', 'l', 's', 'l', '2', 9, 0, |
| /* 164 */ 's', 'm', 'l', 's', 'l', '2', 9, 0, |
| /* 172 */ 'u', 'm', 'l', 's', 'l', '2', 9, 0, |
| /* 180 */ 'r', 's', 'u', 'b', 'h', 'n', '2', 9, 0, |
| /* 189 */ 'r', 'a', 'd', 'd', 'h', 'n', '2', 9, 0, |
| /* 198 */ 's', 'q', 's', 'h', 'r', 'n', '2', 9, 0, |
| /* 207 */ 'u', 'q', 's', 'h', 'r', 'n', '2', 9, 0, |
| /* 216 */ 's', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0, |
| /* 226 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0, |
| /* 236 */ 's', 'q', 's', 'h', 'r', 'u', 'n', '2', 9, 0, |
| /* 246 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', '2', 9, 0, |
| /* 257 */ 'd', 'c', 'p', 's', '2', 9, 0, |
| /* 264 */ 's', 's', 'u', 'b', 'w', '2', 9, 0, |
| /* 272 */ 'u', 's', 'u', 'b', 'w', '2', 9, 0, |
| /* 280 */ 's', 'a', 'd', 'd', 'w', '2', 9, 0, |
| /* 288 */ 'u', 'a', 'd', 'd', 'w', '2', 9, 0, |
| /* 296 */ 'd', 'c', 'p', 's', '3', 9, 0, |
| /* 303 */ 'r', 'e', 'v', '1', '6', 9, 0, |
| /* 310 */ 's', 'a', 'b', 'a', 9, 0, |
| /* 316 */ 'u', 'a', 'b', 'a', 9, 0, |
| /* 322 */ 'f', 'm', 'l', 'a', 9, 0, |
| /* 328 */ 's', 'r', 's', 'r', 'a', 9, 0, |
| /* 335 */ 'u', 'r', 's', 'r', 'a', 9, 0, |
| /* 342 */ 's', 's', 'r', 'a', 9, 0, |
| /* 348 */ 'u', 's', 'r', 'a', 9, 0, |
| /* 354 */ 'f', 'r', 'i', 'n', 't', 'a', 9, 0, |
| /* 362 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0, |
| /* 370 */ 'c', 'r', 'c', '3', '2', 'c', 'b', 9, 0, |
| /* 379 */ 'd', 'm', 'b', 9, 0, |
| /* 384 */ 'l', 'd', 'a', 'r', 'b', 9, 0, |
| /* 391 */ 'l', 'd', 'r', 'b', 9, 0, |
| /* 397 */ 's', 't', 'l', 'r', 'b', 9, 0, |
| /* 404 */ 'l', 'd', 't', 'r', 'b', 9, 0, |
| /* 411 */ 's', 't', 'r', 'b', 9, 0, |
| /* 417 */ 's', 't', 't', 'r', 'b', 9, 0, |
| /* 424 */ 'l', 'd', 'u', 'r', 'b', 9, 0, |
| /* 431 */ 's', 't', 'u', 'r', 'b', 9, 0, |
| /* 438 */ 'l', 'd', 'a', 'x', 'r', 'b', 9, 0, |
| /* 446 */ 'l', 'd', 'x', 'r', 'b', 9, 0, |
| /* 453 */ 's', 't', 'l', 'x', 'r', 'b', 9, 0, |
| /* 461 */ 's', 't', 'x', 'r', 'b', 9, 0, |
| /* 468 */ 'd', 's', 'b', 9, 0, |
| /* 473 */ 'i', 's', 'b', 9, 0, |
| /* 478 */ 'l', 'd', 'r', 's', 'b', 9, 0, |
| /* 485 */ 'l', 'd', 't', 'r', 's', 'b', 9, 0, |
| /* 493 */ 'l', 'd', 'u', 'r', 's', 'b', 9, 0, |
| /* 501 */ 's', 'x', 't', 'b', 9, 0, |
| /* 507 */ 'u', 'x', 't', 'b', 9, 0, |
| /* 513 */ 'f', 's', 'u', 'b', 9, 0, |
| /* 519 */ 's', 'h', 's', 'u', 'b', 9, 0, |
| /* 526 */ 'u', 'h', 's', 'u', 'b', 9, 0, |
| /* 533 */ 'f', 'm', 's', 'u', 'b', 9, 0, |
| /* 540 */ 'f', 'n', 'm', 's', 'u', 'b', 9, 0, |
| /* 548 */ 's', 'q', 's', 'u', 'b', 9, 0, |
| /* 555 */ 'u', 'q', 's', 'u', 'b', 9, 0, |
| /* 562 */ 's', 'b', 'c', 9, 0, |
| /* 567 */ 'a', 'd', 'c', 9, 0, |
| /* 572 */ 'b', 'i', 'c', 9, 0, |
| /* 577 */ 's', 'm', 'c', 9, 0, |
| /* 582 */ 'c', 's', 'i', 'n', 'c', 9, 0, |
| /* 589 */ 'h', 'v', 'c', 9, 0, |
| /* 594 */ 's', 'v', 'c', 9, 0, |
| /* 599 */ 'f', 'a', 'b', 'd', 9, 0, |
| /* 605 */ 's', 'a', 'b', 'd', 9, 0, |
| /* 611 */ 'u', 'a', 'b', 'd', 9, 0, |
| /* 617 */ 'f', 'a', 'd', 'd', 9, 0, |
| /* 623 */ 's', 'r', 'h', 'a', 'd', 'd', 9, 0, |
| /* 631 */ 'u', 'r', 'h', 'a', 'd', 'd', 9, 0, |
| /* 639 */ 's', 'h', 'a', 'd', 'd', 9, 0, |
| /* 646 */ 'u', 'h', 'a', 'd', 'd', 9, 0, |
| /* 653 */ 'f', 'm', 'a', 'd', 'd', 9, 0, |
| /* 660 */ 'f', 'n', 'm', 'a', 'd', 'd', 9, 0, |
| /* 668 */ 's', 'q', 'a', 'd', 'd', 9, 0, |
| /* 675 */ 'u', 'q', 'a', 'd', 'd', 9, 0, |
| /* 682 */ 'a', 'n', 'd', 9, 0, |
| /* 687 */ 'f', 'a', 'c', 'g', 'e', 9, 0, |
| /* 694 */ 'f', 'c', 'm', 'g', 'e', 9, 0, |
| /* 701 */ 'f', 'c', 'm', 'l', 'e', 9, 0, |
| /* 708 */ 'f', 'c', 'c', 'm', 'p', 'e', 9, 0, |
| /* 716 */ 'f', 'c', 'm', 'p', 'e', 9, 0, |
| /* 723 */ 'b', 'i', 'f', 9, 0, |
| /* 728 */ 's', 'c', 'v', 't', 'f', 9, 0, |
| /* 735 */ 'u', 'c', 'v', 't', 'f', 9, 0, |
| /* 742 */ 'f', 'n', 'e', 'g', 9, 0, |
| /* 748 */ 'c', 's', 'n', 'e', 'g', 9, 0, |
| /* 755 */ 'c', 'r', 'c', '3', '2', 'h', 9, 0, |
| /* 763 */ 'c', 'r', 'c', '3', '2', 'c', 'h', 9, 0, |
| /* 772 */ 's', 'q', 'd', 'm', 'u', 'l', 'h', 9, 0, |
| /* 781 */ 's', 'q', 'r', 'd', 'm', 'u', 'l', 'h', 9, 0, |
| /* 791 */ 's', 'm', 'u', 'l', 'h', 9, 0, |
| /* 798 */ 'u', 'm', 'u', 'l', 'h', 9, 0, |
| /* 805 */ 'l', 'd', 'a', 'r', 'h', 9, 0, |
| /* 812 */ 'l', 'd', 'r', 'h', 9, 0, |
| /* 818 */ 's', 't', 'l', 'r', 'h', 9, 0, |
| /* 825 */ 'l', 'd', 't', 'r', 'h', 9, 0, |
| /* 832 */ 's', 't', 'r', 'h', 9, 0, |
| /* 838 */ 's', 't', 't', 'r', 'h', 9, 0, |
| /* 845 */ 'l', 'd', 'u', 'r', 'h', 9, 0, |
| /* 852 */ 's', 't', 'u', 'r', 'h', 9, 0, |
| /* 859 */ 'l', 'd', 'a', 'x', 'r', 'h', 9, 0, |
| /* 867 */ 'l', 'd', 'x', 'r', 'h', 9, 0, |
| /* 874 */ 's', 't', 'l', 'x', 'r', 'h', 9, 0, |
| /* 882 */ 's', 't', 'x', 'r', 'h', 9, 0, |
| /* 889 */ 'l', 'd', 'r', 's', 'h', 9, 0, |
| /* 896 */ 'l', 'd', 't', 'r', 's', 'h', 9, 0, |
| /* 904 */ 'l', 'd', 'u', 'r', 's', 'h', 9, 0, |
| /* 912 */ 's', 'x', 't', 'h', 9, 0, |
| /* 918 */ 'u', 'x', 't', 'h', 9, 0, |
| /* 924 */ 't', 'l', 'b', 'i', 9, 0, |
| /* 930 */ 'b', 'f', 'i', 9, 0, |
| /* 935 */ 'c', 'm', 'h', 'i', 9, 0, |
| /* 941 */ 's', 'l', 'i', 9, 0, |
| /* 946 */ 's', 'r', 'i', 9, 0, |
| /* 951 */ 'f', 'r', 'i', 'n', 't', 'i', 9, 0, |
| /* 959 */ 'm', 'o', 'v', 'i', 9, 0, |
| /* 965 */ 'b', 'r', 'k', 9, 0, |
| /* 970 */ 'm', 'o', 'v', 'k', 9, 0, |
| /* 976 */ 's', 'a', 'b', 'a', 'l', 9, 0, |
| /* 983 */ 'u', 'a', 'b', 'a', 'l', 9, 0, |
| /* 990 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', 9, 0, |
| /* 999 */ 's', 'm', 'l', 'a', 'l', 9, 0, |
| /* 1006 */ 'u', 'm', 'l', 'a', 'l', 9, 0, |
| /* 1013 */ 's', 'm', 's', 'u', 'b', 'l', 9, 0, |
| /* 1021 */ 'u', 'm', 's', 'u', 'b', 'l', 9, 0, |
| /* 1029 */ 's', 's', 'u', 'b', 'l', 9, 0, |
| /* 1036 */ 'u', 's', 'u', 'b', 'l', 9, 0, |
| /* 1043 */ 's', 'a', 'b', 'd', 'l', 9, 0, |
| /* 1050 */ 'u', 'a', 'b', 'd', 'l', 9, 0, |
| /* 1057 */ 's', 'm', 'a', 'd', 'd', 'l', 9, 0, |
| /* 1065 */ 'u', 'm', 'a', 'd', 'd', 'l', 9, 0, |
| /* 1073 */ 's', 'a', 'd', 'd', 'l', 9, 0, |
| /* 1080 */ 'u', 'a', 'd', 'd', 'l', 9, 0, |
| /* 1087 */ 'f', 'c', 's', 'e', 'l', 9, 0, |
| /* 1094 */ 's', 'q', 's', 'h', 'l', 9, 0, |
| /* 1101 */ 'u', 'q', 's', 'h', 'l', 9, 0, |
| /* 1108 */ 's', 'q', 'r', 's', 'h', 'l', 9, 0, |
| /* 1116 */ 'u', 'q', 'r', 's', 'h', 'l', 9, 0, |
| /* 1124 */ 's', 'r', 's', 'h', 'l', 9, 0, |
| /* 1131 */ 'u', 'r', 's', 'h', 'l', 9, 0, |
| /* 1138 */ 's', 's', 'h', 'l', 9, 0, |
| /* 1144 */ 'u', 's', 'h', 'l', 9, 0, |
| /* 1150 */ 'b', 'f', 'x', 'i', 'l', 9, 0, |
| /* 1157 */ 's', 's', 'h', 'l', 'l', 9, 0, |
| /* 1164 */ 'u', 's', 'h', 'l', 'l', 9, 0, |
| /* 1171 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', 9, 0, |
| /* 1180 */ 'p', 'm', 'u', 'l', 'l', 9, 0, |
| /* 1187 */ 's', 'm', 'u', 'l', 'l', 9, 0, |
| /* 1194 */ 'u', 'm', 'u', 'l', 'l', 9, 0, |
| /* 1201 */ 'b', 's', 'l', 9, 0, |
| /* 1206 */ 's', 'q', 'd', 'm', 'l', 's', 'l', 9, 0, |
| /* 1215 */ 's', 'm', 'l', 's', 'l', 9, 0, |
| /* 1222 */ 'u', 'm', 'l', 's', 'l', 9, 0, |
| /* 1229 */ 's', 'y', 's', 'l', 9, 0, |
| /* 1235 */ 'f', 'm', 'u', 'l', 9, 0, |
| /* 1241 */ 'f', 'n', 'm', 'u', 'l', 9, 0, |
| /* 1248 */ 'p', 'm', 'u', 'l', 9, 0, |
| /* 1254 */ 's', 'b', 'f', 'm', 9, 0, |
| /* 1260 */ 'u', 'b', 'f', 'm', 9, 0, |
| /* 1266 */ 'p', 'r', 'f', 'm', 9, 0, |
| /* 1272 */ 'f', 'm', 'i', 'n', 'n', 'm', 9, 0, |
| /* 1280 */ 'f', 'm', 'a', 'x', 'n', 'm', 9, 0, |
| /* 1288 */ 'f', 'r', 'i', 'n', 't', 'm', 9, 0, |
| /* 1296 */ 'p', 'r', 'f', 'u', 'm', 9, 0, |
| /* 1303 */ 'r', 's', 'u', 'b', 'h', 'n', 9, 0, |
| /* 1311 */ 'r', 'a', 'd', 'd', 'h', 'n', 9, 0, |
| /* 1319 */ 'f', 'm', 'i', 'n', 9, 0, |
| /* 1325 */ 's', 'm', 'i', 'n', 9, 0, |
| /* 1331 */ 'u', 'm', 'i', 'n', 9, 0, |
| /* 1337 */ 'c', 'c', 'm', 'n', 9, 0, |
| /* 1343 */ 'e', 'o', 'n', 9, 0, |
| /* 1348 */ 's', 'q', 's', 'h', 'r', 'n', 9, 0, |
| /* 1356 */ 'u', 'q', 's', 'h', 'r', 'n', 9, 0, |
| /* 1364 */ 's', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, |
| /* 1373 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, |
| /* 1382 */ 'o', 'r', 'n', 9, 0, |
| /* 1387 */ 'f', 'r', 'i', 'n', 't', 'n', 9, 0, |
| /* 1395 */ 's', 'q', 's', 'h', 'r', 'u', 'n', 9, 0, |
| /* 1404 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', 9, 0, |
| /* 1414 */ 'm', 'v', 'n', 9, 0, |
| /* 1419 */ 'm', 'o', 'v', 'n', 9, 0, |
| /* 1425 */ 'f', 'a', 'd', 'd', 'p', 9, 0, |
| /* 1432 */ 'l', 'd', 'p', 9, 0, |
| /* 1437 */ 'f', 'c', 'c', 'm', 'p', 9, 0, |
| /* 1444 */ 'f', 'c', 'm', 'p', 9, 0, |
| /* 1450 */ 'f', 'm', 'i', 'n', 'n', 'm', 'p', 9, 0, |
| /* 1459 */ 'f', 'm', 'a', 'x', 'n', 'm', 'p', 9, 0, |
| /* 1468 */ 'l', 'd', 'n', 'p', 9, 0, |
| /* 1474 */ 'f', 'm', 'i', 'n', 'p', 9, 0, |
| /* 1481 */ 's', 'm', 'i', 'n', 'p', 9, 0, |
| /* 1488 */ 'u', 'm', 'i', 'n', 'p', 9, 0, |
| /* 1495 */ 's', 't', 'n', 'p', 9, 0, |
| /* 1501 */ 'a', 'd', 'r', 'p', 9, 0, |
| /* 1507 */ 'f', 'r', 'i', 'n', 't', 'p', 9, 0, |
| /* 1515 */ 's', 't', 'p', 9, 0, |
| /* 1520 */ 'l', 'd', 'a', 'x', 'p', 9, 0, |
| /* 1527 */ 'f', 'm', 'a', 'x', 'p', 9, 0, |
| /* 1534 */ 's', 'm', 'a', 'x', 'p', 9, 0, |
| /* 1541 */ 'u', 'm', 'a', 'x', 'p', 9, 0, |
| /* 1548 */ 'l', 'd', 'x', 'p', 9, 0, |
| /* 1554 */ 's', 't', 'l', 'x', 'p', 9, 0, |
| /* 1561 */ 's', 't', 'x', 'p', 9, 0, |
| /* 1567 */ 'f', 'c', 'm', 'e', 'q', 9, 0, |
| /* 1574 */ 'l', 'd', 'a', 'r', 9, 0, |
| /* 1580 */ 'b', 'r', 9, 0, |
| /* 1584 */ 'a', 'd', 'r', 9, 0, |
| /* 1589 */ 'l', 'd', 'r', 9, 0, |
| /* 1594 */ 's', 'r', 's', 'h', 'r', 9, 0, |
| /* 1601 */ 'u', 'r', 's', 'h', 'r', 9, 0, |
| /* 1608 */ 's', 's', 'h', 'r', 9, 0, |
| /* 1614 */ 'u', 's', 'h', 'r', 9, 0, |
| /* 1620 */ 'b', 'l', 'r', 9, 0, |
| /* 1625 */ 's', 't', 'l', 'r', 9, 0, |
| /* 1631 */ 'e', 'o', 'r', 9, 0, |
| /* 1636 */ 'r', 'o', 'r', 9, 0, |
| /* 1641 */ 'o', 'r', 'r', 9, 0, |
| /* 1646 */ 'a', 's', 'r', 9, 0, |
| /* 1651 */ 'l', 's', 'r', 9, 0, |
| /* 1656 */ 'm', 's', 'r', 9, 0, |
| /* 1661 */ 'l', 'd', 't', 'r', 9, 0, |
| /* 1667 */ 's', 't', 'r', 9, 0, |
| /* 1672 */ 's', 't', 't', 'r', 9, 0, |
| /* 1678 */ 'e', 'x', 't', 'r', 9, 0, |
| /* 1684 */ 'l', 'd', 'u', 'r', 9, 0, |
| /* 1690 */ 's', 't', 'u', 'r', 9, 0, |
| /* 1696 */ 'l', 'd', 'a', 'x', 'r', 9, 0, |
| /* 1703 */ 'l', 'd', 'x', 'r', 9, 0, |
| /* 1709 */ 's', 't', 'l', 'x', 'r', 9, 0, |
| /* 1716 */ 's', 't', 'x', 'r', 9, 0, |
| /* 1722 */ 'f', 'c', 'v', 't', 'a', 's', 9, 0, |
| /* 1730 */ 'f', 'a', 'b', 's', 9, 0, |
| /* 1736 */ 's', 'u', 'b', 's', 9, 0, |
| /* 1742 */ 's', 'b', 'c', 's', 9, 0, |
| /* 1748 */ 'a', 'd', 'c', 's', 9, 0, |
| /* 1754 */ 'b', 'i', 'c', 's', 9, 0, |
| /* 1760 */ 'a', 'd', 'd', 's', 9, 0, |
| /* 1766 */ 'a', 'n', 'd', 's', 9, 0, |
| /* 1772 */ 'c', 'm', 'h', 's', 9, 0, |
| /* 1778 */ 'c', 'l', 's', 9, 0, |
| /* 1783 */ 'f', 'm', 'l', 's', 9, 0, |
| /* 1789 */ 'f', 'c', 'v', 't', 'm', 's', 9, 0, |
| /* 1797 */ 'i', 'n', 's', 9, 0, |
| /* 1802 */ 'f', 'c', 'v', 't', 'n', 's', 9, 0, |
| /* 1810 */ 'f', 'r', 'e', 'c', 'p', 's', 9, 0, |
| /* 1818 */ 'f', 'c', 'v', 't', 'p', 's', 9, 0, |
| /* 1826 */ 'm', 'r', 's', 9, 0, |
| /* 1831 */ 'f', 'r', 's', 'q', 'r', 't', 's', 9, 0, |
| /* 1840 */ 's', 'y', 's', 9, 0, |
| /* 1845 */ 'f', 'c', 'v', 't', 'z', 's', 9, 0, |
| /* 1853 */ 'a', 't', 9, 0, |
| /* 1857 */ 'r', 'e', 't', 9, 0, |
| /* 1862 */ 'f', 'a', 'c', 'g', 't', 9, 0, |
| /* 1869 */ 'f', 'c', 'm', 'g', 't', 9, 0, |
| /* 1876 */ 'r', 'b', 'i', 't', 9, 0, |
| /* 1882 */ 'h', 'l', 't', 9, 0, |
| /* 1887 */ 'f', 'c', 'm', 'l', 't', 9, 0, |
| /* 1894 */ 'h', 'i', 'n', 't', 9, 0, |
| /* 1900 */ 'f', 's', 'q', 'r', 't', 9, 0, |
| /* 1907 */ 'c', 'm', 't', 's', 't', 9, 0, |
| /* 1914 */ 'f', 'c', 'v', 't', 9, 0, |
| /* 1920 */ 'f', 'c', 'v', 't', 'a', 'u', 9, 0, |
| /* 1928 */ 's', 'q', 's', 'h', 'l', 'u', 9, 0, |
| /* 1936 */ 'f', 'c', 'v', 't', 'm', 'u', 9, 0, |
| /* 1944 */ 'f', 'c', 'v', 't', 'n', 'u', 9, 0, |
| /* 1952 */ 'f', 'c', 'v', 't', 'p', 'u', 9, 0, |
| /* 1960 */ 'f', 'c', 'v', 't', 'z', 'u', 9, 0, |
| /* 1968 */ 'r', 'e', 'v', 9, 0, |
| /* 1973 */ 'f', 'd', 'i', 'v', 9, 0, |
| /* 1979 */ 's', 'd', 'i', 'v', 9, 0, |
| /* 1985 */ 'u', 'd', 'i', 'v', 9, 0, |
| /* 1991 */ 'c', 's', 'i', 'n', 'v', 9, 0, |
| /* 1998 */ 'f', 'm', 'o', 'v', 9, 0, |
| /* 2004 */ 's', 'm', 'o', 'v', 9, 0, |
| /* 2010 */ 'u', 'm', 'o', 'v', 9, 0, |
| /* 2016 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0, |
| /* 2024 */ 's', 's', 'u', 'b', 'w', 9, 0, |
| /* 2031 */ 'u', 's', 'u', 'b', 'w', 9, 0, |
| /* 2038 */ 'c', 'r', 'c', '3', '2', 'c', 'w', 9, 0, |
| /* 2047 */ 's', 'a', 'd', 'd', 'w', 9, 0, |
| /* 2054 */ 'u', 'a', 'd', 'd', 'w', 9, 0, |
| /* 2061 */ 'l', 'd', 'p', 's', 'w', 9, 0, |
| /* 2068 */ 'l', 'd', 'r', 's', 'w', 9, 0, |
| /* 2075 */ 'l', 'd', 't', 'r', 's', 'w', 9, 0, |
| /* 2083 */ 'l', 'd', 'u', 'r', 's', 'w', 9, 0, |
| /* 2091 */ 's', 'x', 't', 'w', 9, 0, |
| /* 2097 */ 'c', 'r', 'c', '3', '2', 'x', 9, 0, |
| /* 2105 */ 'f', 'm', 'a', 'x', 9, 0, |
| /* 2111 */ 's', 'm', 'a', 'x', 9, 0, |
| /* 2117 */ 'u', 'm', 'a', 'x', 9, 0, |
| /* 2123 */ 'c', 'r', 'c', '3', '2', 'c', 'x', 9, 0, |
| /* 2132 */ 'c', 'l', 'r', 'e', 'x', 9, 0, |
| /* 2139 */ 's', 'b', 'f', 'x', 9, 0, |
| /* 2145 */ 'u', 'b', 'f', 'x', 9, 0, |
| /* 2151 */ 'f', 'm', 'u', 'l', 'x', 9, 0, |
| /* 2158 */ 'f', 'r', 'i', 'n', 't', 'x', 9, 0, |
| /* 2166 */ 'c', 'b', 'z', 9, 0, |
| /* 2171 */ 't', 'b', 'z', 9, 0, |
| /* 2176 */ 's', 'b', 'f', 'i', 'z', 9, 0, |
| /* 2183 */ 'u', 'b', 'f', 'i', 'z', 9, 0, |
| /* 2190 */ 'c', 'l', 'z', 9, 0, |
| /* 2195 */ 'c', 'b', 'n', 'z', 9, 0, |
| /* 2201 */ 't', 'b', 'n', 'z', 9, 0, |
| /* 2207 */ 'f', 'r', 'i', 'n', 't', 'z', 9, 0, |
| /* 2215 */ 'm', 'o', 'v', 'z', 9, 0, |
| /* 2221 */ 'm', 'o', 'v', 'i', 9, 32, 0, |
| /* 2228 */ 's', 'q', 's', 'u', 'b', 32, 0, |
| /* 2235 */ 'u', 'q', 's', 'u', 'b', 32, 0, |
| /* 2242 */ 'b', 'i', 'c', 32, 0, |
| /* 2247 */ 's', 'q', 'a', 'd', 'd', 32, 0, |
| /* 2254 */ 'u', 'q', 'a', 'd', 'd', 32, 0, |
| /* 2261 */ 'm', 'v', 'n', 'i', 32, 0, |
| /* 2267 */ 'm', 'o', 'v', 'i', 32, 0, |
| /* 2273 */ 's', 'q', 's', 'h', 'l', 32, 0, |
| /* 2280 */ 'u', 'q', 's', 'h', 'l', 32, 0, |
| /* 2287 */ 's', 'q', 'r', 's', 'h', 'l', 32, 0, |
| /* 2295 */ 'u', 'q', 'r', 's', 'h', 'l', 32, 0, |
| /* 2303 */ 's', 'r', 's', 'h', 'l', 32, 0, |
| /* 2310 */ 'u', 'r', 's', 'h', 'l', 32, 0, |
| /* 2317 */ 's', 's', 'h', 'l', 32, 0, |
| /* 2323 */ 'u', 's', 'h', 'l', 32, 0, |
| /* 2329 */ 'c', 'm', 'n', 32, 0, |
| /* 2334 */ 'f', 'a', 'd', 'd', 'p', 32, 0, |
| /* 2341 */ 'c', 'm', 'p', 32, 0, |
| /* 2346 */ 'f', 'm', 'i', 'n', 'n', 'm', 'p', 32, 0, |
| /* 2355 */ 'f', 'm', 'a', 'x', 'n', 'm', 'p', 32, 0, |
| /* 2364 */ 'f', 'm', 'i', 'n', 'p', 32, 0, |
| /* 2371 */ 'f', 'm', 'a', 'x', 'p', 32, 0, |
| /* 2378 */ 'o', 'r', 'r', 32, 0, |
| /* 2383 */ 'b', '.', 0, |
| /* 2386 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, |
| /* 2399 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, |
| /* 2406 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, |
| /* 2416 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, |
| /* 2431 */ 'd', 'r', 'p', 's', 0, |
| /* 2436 */ 'e', 'r', 'e', 't', 0, |
| }; |
| |
| // Emit the opcode for the instruction. |
| uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)]; |
| uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)]; |
| uint64_t Bits = (Bits2 << 32) | Bits1; |
| SStream_concat(O, "%s",AsmStrs+(Bits & 4095)-1); |
| |
| // printf("Frag-0 : %lu\n", (Bits >> 12) & 15); |
| // Fragment 0 encoded into 4 bits for 15 unique commands. |
| switch ((Bits >> 12) & 15) { |
| default: // unreachable. |
| case 0: |
| // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, DRPS, ERET |
| return; |
| break; |
| case 1: |
| // ADCSwww, ADCSxxx, ADCwww, ADCxxx, ADDPvv_D_2D, ADDSwww_asr, ADDSwww_ls... |
| printOperand(MI, 0, O); |
| break; |
| case 2: |
| // ADDHN2vvv_16b8h, ADDHN2vvv_4s2d, ADDHN2vvv_8h4s, ADDHNvvv_2s2d, ADDHNv... |
| printVPRRegister(MI, 0, O); |
| break; |
| case 3: |
| // ATix |
| printNamedImmOperand(&AArch64_ATMapper, MI, 0, O); |
| SStream_concat(O, ", "); |
| printOperand(MI, 1, O); |
| return; |
| break; |
| case 4: |
| // BLimm, Bimm |
| printLabelOperand(MI, 0, O, 26, 4); |
| return; |
| break; |
| case 5: |
| // Bcc |
| printCondCodeOperand(MI, 0, O); |
| SStream_concat(O, " "); |
| printLabelOperand(MI, 1, O, 19, 4); |
| return; |
| break; |
| case 6: |
| // DCix |
| printNamedImmOperand(&AArch64_DCMapper, MI, 0, O); |
| SStream_concat(O, ", "); |
| printOperand(MI, 1, O); |
| return; |
| break; |
| case 7: |
| // DMBi, DSBi |
| printNamedImmOperand(&AArch64_DBarrierMapper, MI, 0, O); |
| return; |
| break; |
| case 8: |
| // ICi, ICix |
| printNamedImmOperand(&AArch64_ICMapper, MI, 0, O); |
| break; |
| case 9: |
| // ISBi |
| printNamedImmOperand(&AArch64_ISBMapper, MI, 0, O); |
| return; |
| break; |
| case 10: |
| // LS16_PostInd_STR, LS16_PreInd_STR, LS32_PostInd_STR, LS32_PreInd_STR, ... |
| printOperand(MI, 1, O); |
| break; |
| case 11: |
| // MSRii |
| printNamedImmOperand(&AArch64_PStateMapper, MI, 0, O); |
| SStream_concat(O, ", "); |
| printOperand(MI, 1, O); |
| return; |
| break; |
| case 12: |
| // MSRix |
| printMSROperand(MI, 0, O); |
| SStream_concat(O, ", "); |
| printOperand(MI, 1, O); |
| return; |
| break; |
| case 13: |
| // PRFM, PRFM_Wm_RegOffset, PRFM_Xm_RegOffset, PRFM_lit, PRFUM |
| printNamedImmOperand(&AArch64_PRFMMapper, MI, 0, O); |
| break; |
| case 14: |
| // TLBIi, TLBIix |
| printNamedImmOperand(&AArch64_TLBIMapper, MI, 0, O); |
| break; |
| } |
| |
| |
| // printf(">> Frag-1: %lu\n", (Bits >> 16) & 15); |
| // Fragment 1 encoded into 4 bits for 14 unique commands. |
| switch ((Bits >> 16) & 15) { |
| default: // unreachable. |
| case 0: |
| // ADCSwww, ADCSxxx, ADCwww, ADCxxx, ADDPvv_D_2D, ADDSwww_asr, ADDSwww_ls... |
| SStream_concat(O, ", "); |
| break; |
| case 1: |
| // ADDHN2vvv_16b8h, ADDP_16B, ADDvvv_16B, ANDvvv_16B, BICvvv_16B, BIFvvv_... |
| SStream_concat(O, ".16b, "); |
| break; |
| case 2: |
| // ADDHN2vvv_4s2d, ADDP_4S, ADDvvv_4S, BICvi_lsl_4S, CMEQvvi_4S, CMEQvvv_... |
| SStream_concat(O, ".4s, "); |
| break; |
| case 3: |
| // ADDHN2vvv_8h4s, ADDP_8H, ADDvvv_8H, BICvi_lsl_8H, CMEQvvi_8H, CMEQvvv_... |
| SStream_concat(O, ".8h, "); |
| break; |
| case 4: |
| // ADDHNvvv_2s2d, ADDP_2S, ADDvvv_2S, BICvi_lsl_2S, CMEQvvi_2S, CMEQvvv_2... |
| SStream_concat(O, ".2s, "); |
| break; |
| case 5: |
| // ADDHNvvv_4h4s, ADDP_4H, ADDvvv_4H, BICvi_lsl_4H, CMEQvvi_4H, CMEQvvv_4... |
| SStream_concat(O, ".4h, "); |
| break; |
| case 6: |
| // ADDHNvvv_8b8h, ADDP_8B, ADDvvv_8B, ANDvvv_8B, BICvvv_8B, BIFvvv_8B, BI... |
| SStream_concat(O, ".8b, "); |
| break; |
| case 7: |
| // ADDP_2D, ADDvvv_2D, CMEQvvi_2D, CMEQvvv_2D, CMGEvvi_2D, CMGEvvv_2D, CM... |
| SStream_concat(O, ".2d, "); |
| break; |
| case 8: |
| // BLRx, BRKi, BRx, CLREXi, DCPS1i, DCPS2i, DCPS3i, HINTi, HLTi, HVCi, IC... |
| return; |
| break; |
| case 9: |
| // FMOVvx, INSELd, INSdx |
| SStream_concat(O, ".d["); |
| set_mem_access(MI, true); |
| break; |
| case 10: |
| // INSELb, INSbw |
| SStream_concat(O, ".b["); |
| set_mem_access(MI, true); |
| printNeonUImm8OperandBare(MI, 3, O); |
| SStream_concat(O, "], "); |
| set_mem_access(MI, false); |
| break; |
| case 11: |
| // INSELh, INShw |
| SStream_concat(O, ".h["); |
| set_mem_access(MI, true); |
| printNeonUImm8OperandBare(MI, 3, O); |
| SStream_concat(O, "], "); |
| set_mem_access(MI, false); |
| break; |
| case 12: |
| // INSELs, INSsw |
| SStream_concat(O, ".s["); |
| set_mem_access(MI, true); |
| printNeonUImm8OperandBare(MI, 3, O); |
| SStream_concat(O, "], "); |
| set_mem_access(MI, false); |
| break; |
| case 13: |
| // LDAR_byte, LDAR_dword, LDAR_hword, LDAR_word, LDAXR_byte, LDAXR_dword,... |
| SStream_concat(O, ", ["); |
| set_mem_access(MI, true); |
| break; |
| } |
| |
| |
| // printf(">> Frag-2: %lu\n", (Bits >> 20) & 31); |
| // Fragment 2 encoded into 5 bits for 20 unique commands. |
| switch ((Bits >> 20) & 31) { |
| default: // unreachable. |
| case 0: |
| // ADCSwww, ADCSxxx, ADCwww, ADCxxx, ADDSwww_asr, ADDSwww_lsl, ADDSwww_ls... |
| printOperand(MI, 1, O); |
| break; |
| case 1: |
| // ADDHN2vvv_16b8h, ADDHN2vvv_4s2d, ADDHN2vvv_8h4s, BIFvvv_16B, BIFvvv_8B... |
| printVPRRegister(MI, 2, O); |
| break; |
| case 2: |
| // ADDHNvvv_2s2d, ADDHNvvv_4h4s, ADDHNvvv_8b8h, ADDP_16B, ADDP_2D, ADDP_2... |
| printVPRRegister(MI, 1, O); |
| break; |
| case 3: |
| // ADDwwi_lsl0_cmp, ADDxxi_lsl0_cmp, SUBwwi_lsl0_cmp, SUBxxi_lsl0_cmp |
| printAddSubImmLSL0Operand(MI, 1, O); |
| return; |
| break; |
| case 4: |
| // ADDwwi_lsl12_cmp, ADDxxi_lsl12_cmp, SUBwwi_lsl12_cmp, SUBxxi_lsl12_cmp |
| printAddSubImmLSL12Operand(MI, 1, O); |
| return; |
| break; |
| case 5: |
| // ADRPxi |
| printLabelOperand(MI, 1, O, 21, 4096); |
| return; |
| break; |
| case 6: |
| // ADRxi |
| printLabelOperand(MI, 1, O, 21, 1); |
| return; |
| break; |
| case 7: |
| // BFIwwii, BFIxxii, BFMwwii, BFMxxii, BFXILwwii, BFXILxxii, INSbw, INShw... |
| printOperand(MI, 2, O); |
| break; |
| case 8: |
| // BICvi_lsl_2S, BICvi_lsl_4H, BICvi_lsl_4S, BICvi_lsl_8H, ORRvi_lsl_2S, ... |
| printNeonUImm8Operand(MI, 2, O); |
| break; |
| case 9: |
| // CBNZw, CBNZx, CBZw, CBZx, LDRSWx_lit, LDRd_lit, LDRq_lit, LDRs_lit, LD... |
| printLabelOperand(MI, 1, O, 19, 4); |
| return; |
| break; |
| case 10: |
| // FCMPdi_quiet, FCMPdi_sig, FCMPsi_quiet, FCMPsi_sig |
| printFPZeroOperand(MI, 1, O); |
| return; |
| break; |
| case 11: |
| // FMOVdi, FMOVsi, FMOVvi_2D, FMOVvi_2S, FMOVvi_4S |
| printFPImmOperand(MI, 1, O); |
| return; |
| break; |
| case 12: |
| // FMOVvx |
| printBareImmOperand(MI, 2, O); |
| SStream_concat(O, "], "); |
| set_mem_access(MI, false); |
| printOperand(MI, 1, O); |
| return; |
| break; |
| case 13: |
| // INSELd, INSdx |
| printNeonUImm8OperandBare(MI, 3, O); |
| SStream_concat(O, "], "); |
| set_mem_access(MI, false); |
| break; |
| case 14: |
| // MOVIdi, MOVIvi_2D |
| printNeonUImm64MaskOperand(MI, 1, O); |
| return; |
| break; |
| case 15: |
| // MOVIvi_16B, MOVIvi_8B, MOVIvi_lsl_2S, MOVIvi_lsl_4H, MOVIvi_lsl_4S, MO... |
| printNeonUImm8Operand(MI, 1, O); |
| break; |
| case 16: |
| // MOVKwii, MOVKxii |
| printMoveWideImmOperand(MI, 2, O); |
| return; |
| break; |
| case 17: |
| // MOVNwii, MOVNxii, MOVZwii, MOVZxii |
| printMoveWideImmOperand(MI, 1, O); |
| return; |
| break; |
| case 18: |
| // MRSxi |
| printMRSOperand(MI, 1, O); |
| return; |
| break; |
| case 19: |
| // SYSiccix |
| printCRxOperand(MI, 1, O); |
| SStream_concat(O, ", "); |
| printCRxOperand(MI, 2, O); |
| SStream_concat(O, ", "); |
| printOperand(MI, 3, O); |
| SStream_concat(O, ", "); |
| printOperand(MI, 4, O); |
| return; |
| break; |
| } |
| |
| |
| // printf(">> Frag-3: %lu\n", (Bits >> 25) & 31); |
| // Fragment 3 encoded into 5 bits for 25 unique commands. |
| switch ((Bits >> 25) & 31) { |
| default: // unreachable. |
| case 0: |
| // ADCSwww, ADCSxxx, ADCwww, ADCxxx, ADDSwww_asr, ADDSwww_lsl, ADDSwww_ls... |
| SStream_concat(O, ", "); |
| break; |
| case 1: |
| // ADDHN2vvv_16b8h, ADDHNvvv_8b8h, ADDP_8H, ADDvvv_8H, CMEQvvi_8H, CMEQvv... |
| SStream_concat(O, ".8h, "); |
| break; |
| case 2: |
| // ADDHN2vvv_4s2d, ADDHNvvv_2s2d, ADDP_2D, ADDvvv_2D, CMEQvvi_2D, CMEQvvv... |
| SStream_concat(O, ".2d, "); |
| break; |
| case 3: |
| // ADDHN2vvv_8h4s, ADDHNvvv_4h4s, ADDP_4S, ADDvvv_4S, CMEQvvi_4S, CMEQvvv... |
| SStream_concat(O, ".4s, "); |
| break; |
| case 4: |
| // ADDP_16B, ADDvvv_16B, ANDvvv_16B, BICvvv_16B, BIFvvv_16B, BITvvv_16B, ... |
| SStream_concat(O, ".16b, "); |
| break; |
| case 5: |
| // ADDP_2S, ADDvvv_2S, CMEQvvi_2S, CMEQvvv_2S, CMGEvvi_2S, CMGEvvv_2S, CM... |
| SStream_concat(O, ".2s, "); |
| break; |
| case 6: |
| // ADDP_4H, ADDvvv_4H, CMEQvvi_4H, CMEQvvv_4H, CMGEvvi_4H, CMGEvvv_4H, CM... |
| SStream_concat(O, ".4h, "); |
| break; |
| case 7: |
| // ADDP_8B, ADDvvv_8B, ANDvvv_8B, BICvvv_8B, BIFvvv_8B, BITvvv_8B, BSLvvv... |
| SStream_concat(O, ".8b, "); |
| break; |
| case 8: |
| // ADDPvv_D_2D, FADDPvv_D_2D, FMAXNMPvv_D_2D, FMAXPvv_D_2D, FMINNMPvv_D_2... |
| SStream_concat(O, ".2d"); |
| return; |
| break; |
| case 9: |
| // BICvi_lsl_2S, BICvi_lsl_4S, ORRvi_lsl_2S, ORRvi_lsl_4S |
| printNeonMovImmShiftOperand(MI, 3, O, A64SE_LSL, false); |
| return; |
| break; |
| case 10: |
| // BICvi_lsl_4H, BICvi_lsl_8H, ORRvi_lsl_4H, ORRvi_lsl_8H |
| printNeonMovImmShiftOperand(MI, 3, O, A64SE_LSL, true); |
| return; |
| break; |
| case 11: |
| // CLSww, CLSxx, CLZww, CLZxx, FABSdd, FABSss, FCMPdd_quiet, FCMPdd_sig, ... |
| return; |
| break; |
| case 12: |
| // FADDPvv_S_2S, FMAXNMPvv_S_2S, FMAXPvv_S_2S, FMINNMPvv_S_2S, FMINPvv_S_... |
| SStream_concat(O, ".2s"); |
| return; |
| break; |
| case 13: |
| // FMOVxv, UMOVxd |
| SStream_concat(O, ".d["); |
| set_mem_access(MI, true); |
| break; |
| case 14: |
| // INSELb, SMOVwb, SMOVxb, UMOVwb |
| SStream_concat(O, ".b["); |
| set_mem_access(MI, true); |
| break; |
| case 15: |
| // INSELd |
| printVPRRegister(MI, 2, O); |
| SStream_concat(O, ".d["); |
| set_mem_access(MI, true); |
| printNeonUImm8OperandBare(MI, 4, O); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 16: |
| // INSELh, SMOVwh, SMOVxh, UMOVwh |
| SStream_concat(O, ".h["); |
| set_mem_access(MI, true); |
| break; |
| case 17: |
| // INSELs, SMOVxs, UMOVws |
| SStream_concat(O, ".s["); |
| set_mem_access(MI, true); |
| break; |
| case 18: |
| // INSdx |
| printOperand(MI, 2, O); |
| return; |
| break; |
| case 19: |
| // LDAR_byte, LDAR_dword, LDAR_hword, LDAR_word, LDAXR_byte, LDAXR_dword,... |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 20: |
| // LDAXP_dword, LDAXP_word, LDPSWx, LDPSWx_PostInd, LDPSWx_PreInd, LDXP_d... |
| SStream_concat(O, ", ["); |
| set_mem_access(MI, true); |
| break; |
| case 21: |
| // LDRSBw_PostInd, LDRSBx_PostInd, LDRSHw_PostInd, LDRSHx_PostInd, LDRSWx... |
| SStream_concat(O, "], "); |
| set_mem_access(MI, false); |
| printOffsetSImm9Operand(MI, 3, O); |
| return; |
| break; |
| case 22: |
| // MOVIvi_lsl_2S, MOVIvi_lsl_4S, MVNIvi_lsl_2S, MVNIvi_lsl_4S |
| printNeonMovImmShiftOperand(MI, 2, O, A64SE_LSL, false); |
| return; |
| break; |
| case 23: |
| // MOVIvi_lsl_4H, MOVIvi_lsl_8H, MVNIvi_lsl_4H, MVNIvi_lsl_8H |
| printNeonMovImmShiftOperand(MI, 2, O, A64SE_LSL, true); |
| return; |
| break; |
| case 24: |
| // MOVIvi_msl_2S, MOVIvi_msl_4S, MVNIvi_msl_2S, MVNIvi_msl_4S |
| printNeonMovImmShiftOperand(MI, 2, O, A64SE_MSL, false); |
| return; |
| break; |
| } |
| |
| |
| // printf(">> Frag-4: %lu\n", (Bits >> 30) & 63); |
| // Fragment 4 encoded into 6 bits for 39 unique commands. |
| switch ((Bits >> 30) & 63) { |
| default: // unreachable. |
| case 0: |
| // ADCSwww, ADCSxxx, ADCwww, ADCxxx, ADDSwww_asr, ADDSwww_lsl, ADDSwww_ls... |
| printOperand(MI, 2, O); |
| break; |
| case 1: |
| // ADDHN2vvv_16b8h, ADDHN2vvv_4s2d, ADDHN2vvv_8h4s, BIFvvv_16B, BIFvvv_8B... |
| printVPRRegister(MI, 3, O); |
| break; |
| case 2: |
| // ADDHNvvv_2s2d, ADDHNvvv_4h4s, ADDHNvvv_8b8h, ADDP_16B, ADDP_2D, ADDP_2... |
| printVPRRegister(MI, 2, O); |
| break; |
| case 3: |
| // ADDwwi_lsl0_S, ADDwwi_lsl0_s, ADDxxi_lsl0_S, ADDxxi_lsl0_s, SUBwwi_lsl... |
| printAddSubImmLSL0Operand(MI, 2, O); |
| return; |
| break; |
| case 4: |
| // ADDwwi_lsl12_S, ADDwwi_lsl12_s, ADDxxi_lsl12_S, ADDxxi_lsl12_s, SUBwwi... |
| printAddSubImmLSL12Operand(MI, 2, O); |
| return; |
| break; |
| case 5: |
| // ANDSwwi, ANDwwi, EORwwi, ORRwwi |
| printLogicalImmOperand(MI, 2, O, 32); |
| return; |
| break; |
| case 6: |
| // ANDSxxi, ANDxxi, EORxxi, ORRxxi |
| printLogicalImmOperand(MI, 2, O, 64); |
| return; |
| break; |
| case 7: |
| // BFIwwii |
| printBFILSBOperand(MI, 3, O, 32); |
| SStream_concat(O, ", "); |
| printBFIWidthOperand(MI, 4, O); |
| return; |
| break; |
| case 8: |
| // BFIxxii |
| printBFILSBOperand(MI, 3, O, 64); |
| SStream_concat(O, ", "); |
| printBFIWidthOperand(MI, 4, O); |
| return; |
| break; |
| case 9: |
| // BFMwwii, BFMxxii, BFXILwwii, BFXILxxii, LDPSWx_PostInd, LDPSWx_PreInd,... |
| printOperand(MI, 3, O); |
| break; |
| case 10: |
| // CMEQvvi_16B, CMEQvvi_2D, CMEQvvi_2S, CMEQvvi_4H, CMEQvvi_4S, CMEQvvi_8... |
| printNeonUImm0Operand(MI, 2, O); |
| return; |
| break; |
| case 11: |
| // CMNww_asr, CMNxx_asr, CMPww_asr, CMPxx_asr, MVNww_asr, MVNxx_asr, TSTw... |
| printShiftOperand(MI, 2, O, A64SE_ASR); |
| return; |
| break; |
| case 12: |
| // CMNww_lsl, CMNxx_lsl, CMPww_lsl, CMPxx_lsl, MVNww_lsl, MVNxx_lsl, TSTw... |
| printShiftOperand(MI, 2, O, A64SE_LSL); |
| return; |
| break; |
| case 13: |
| // CMNww_lsr, CMNxx_lsr, CMPww_lsr, CMPxx_lsr, MVNww_lsr, MVNxx_lsr, TSTw... |
| printShiftOperand(MI, 2, O, A64SE_LSR); |
| return; |
| break; |
| case 14: |
| // CMNww_sxtb, CMNxw_sxtb, CMPww_sxtb, CMPxw_sxtb |
| printRegExtendOperand(MI, 2, O, A64SE_SXTB); |
| return; |
| break; |
| case 15: |
| // CMNww_sxth, CMNxw_sxth, CMPww_sxth, CMPxw_sxth |
| printRegExtendOperand(MI, 2, O, A64SE_SXTH); |
| return; |
| break; |
| case 16: |
| // CMNww_sxtw, CMNxw_sxtw, CMPww_sxtw, CMPxw_sxtw |
| printRegExtendOperand(MI, 2, O, A64SE_SXTW); |
| return; |
| break; |
| case 17: |
| // CMNww_sxtx, CMNxx_sxtx, CMPww_sxtx, CMPxx_sxtx |
| printRegExtendOperand(MI, 2, O, A64SE_SXTX); |
| return; |
| break; |
| case 18: |
| // CMNww_uxtb, CMNxw_uxtb, CMPww_uxtb, CMPxw_uxtb |
| printRegExtendOperand(MI, 2, O, A64SE_UXTB); |
| return; |
| break; |
| case 19: |
| // CMNww_uxth, CMNxw_uxth, CMPww_uxth, CMPxw_uxth |
| printRegExtendOperand(MI, 2, O, A64SE_UXTH); |
| return; |
| break; |
| case 20: |
| // CMNww_uxtw, CMNxw_uxtw, CMPww_uxtw, CMPxw_uxtw |
| printRegExtendOperand(MI, 2, O, A64SE_UXTW); |
| return; |
| break; |
| case 21: |
| // CMNww_uxtx, CMNxx_uxtx, CMPww_uxtx, CMPxx_uxtx |
| printRegExtendOperand(MI, 2, O, A64SE_UXTX); |
| return; |
| break; |
| case 22: |
| // FCMEQvvi_2D, FCMEQvvi_2S, FCMEQvvi_4S, FCMGEvvi_2D, FCMGEvvi_2S, FCMGE... |
| printFPZeroOperand(MI, 2, O); |
| return; |
| break; |
| case 23: |
| // FCVTZSwdi, FCVTZSwsi, FCVTZSxdi, FCVTZSxsi, FCVTZUwdi, FCVTZUwsi, FCVT... |
| printCVTFixedPosOperand(MI, 2, O); |
| return; |
| break; |
| case 24: |
| // FMOVxv |
| printBareImmOperand(MI, 2, O); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 25: |
| // INSELb, INSELh, INSELs |
| printNeonUImm8OperandBare(MI, 4, O); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 26: |
| // LDRSBw, LDRSBx, LS8_LDR, LS8_STR, LSFP8_LDR, LSFP8_STR |
| printOffsetUImm12Operand(MI, 2, O, 1); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 27: |
| // LDRSBw_PreInd, LDRSBx_PreInd, LDRSHw_PreInd, LDRSHx_PreInd, LDRSWx_Pre... |
| printOffsetSImm9Operand(MI, 3, O); |
| SStream_concat(O, "]!"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 28: |
| // LDRSBw_U, LDRSBx_U, LDRSHw_U, LDRSHx_U, LDTRSBw, LDTRSBx, LDTRSHw, LDT... |
| printOffsetSImm9Operand(MI, 2, O); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 29: |
| // LDRSHw, LDRSHx, LS16_LDR, LS16_STR, LSFP16_LDR, LSFP16_STR |
| printOffsetUImm12Operand(MI, 2, O, 2); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 30: |
| // LDRSWx, LS32_LDR, LS32_STR, LSFP32_LDR, LSFP32_STR |
| printOffsetUImm12Operand(MI, 2, O, 4); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 31: |
| // LS64_LDR, LS64_STR, LSFP64_LDR, LSFP64_STR, PRFM |
| printOffsetUImm12Operand(MI, 2, O, 8); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 32: |
| // LSFP128_LDR, LSFP128_STR |
| printOffsetUImm12Operand(MI, 2, O, 16); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 33: |
| // MVNww_ror, MVNxx_ror, TSTww_ror, TSTxx_ror |
| printShiftOperand(MI, 2, O, A64SE_ROR); |
| return; |
| break; |
| case 34: |
| // SBFIZwwii, UBFIZwwii |
| printBFILSBOperand(MI, 2, O, 32); |
| SStream_concat(O, ", "); |
| printBFIWidthOperand(MI, 3, O); |
| return; |
| break; |
| case 35: |
| // SBFIZxxii, UBFIZxxii |
| printBFILSBOperand(MI, 2, O, 64); |
| SStream_concat(O, ", "); |
| printBFIWidthOperand(MI, 3, O); |
| return; |
| break; |
| case 36: |
| // SMOVwb, SMOVwh, SMOVxb, SMOVxh, SMOVxs, UMOVwb, UMOVwh, UMOVws, UMOVxd |
| printNeonUImm8OperandBare(MI, 2, O); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 37: |
| // SYSLxicci |
| printCRxOperand(MI, 2, O); |
| SStream_concat(O, ", "); |
| printCRxOperand(MI, 3, O); |
| SStream_concat(O, ", "); |
| printOperand(MI, 4, O); |
| return; |
| break; |
| case 38: |
| // TBNZwii, TBNZxii, TBZwii, TBZxii |
| printLabelOperand(MI, 2, O, 14, 4); |
| return; |
| break; |
| } |
| |
| |
| // printf(">> Frag-5: %lu\n", (Bits >> 36) & 15); |
| // Fragment 5 encoded into 4 bits for 12 unique commands. |
| switch ((Bits >> 36) & 15) { |
| default: // unreachable. |
| case 0: |
| // ADCSwww, ADCSxxx, ADCwww, ADCxxx, ADDddd, ASRVwww, ASRVxxx, ASRwwi, AS... |
| return; |
| break; |
| case 1: |
| // ADDHN2vvv_16b8h, ADDHNvvv_8b8h, ADDP_8H, ADDvvv_8H, CMEQvvv_8H, CMGEvv... |
| SStream_concat(O, ".8h"); |
| return; |
| break; |
| case 2: |
| // ADDHN2vvv_4s2d, ADDHNvvv_2s2d, ADDP_2D, ADDvvv_2D, CMEQvvv_2D, CMGEvvv... |
| SStream_concat(O, ".2d"); |
| return; |
| break; |
| case 3: |
| // ADDHN2vvv_8h4s, ADDHNvvv_4h4s, ADDP_4S, ADDvvv_4S, CMEQvvv_4S, CMGEvvv... |
| SStream_concat(O, ".4s"); |
| return; |
| break; |
| case 4: |
| // ADDP_16B, ADDvvv_16B, ANDvvv_16B, BICvvv_16B, BIFvvv_16B, BITvvv_16B, ... |
| SStream_concat(O, ".16b"); |
| return; |
| break; |
| case 5: |
| // ADDP_2S, ADDvvv_2S, CMEQvvv_2S, CMGEvvv_2S, CMGTvvv_2S, CMHIvvv_2S, CM... |
| SStream_concat(O, ".2s"); |
| return; |
| break; |
| case 6: |
| // ADDP_4H, ADDvvv_4H, CMEQvvv_4H, CMGEvvv_4H, CMGTvvv_4H, CMHIvvv_4H, CM... |
| SStream_concat(O, ".4h"); |
| return; |
| break; |
| case 7: |
| // ADDP_8B, ADDvvv_8B, ANDvvv_8B, BICvvv_8B, BIFvvv_8B, BITvvv_8B, BSLvvv... |
| SStream_concat(O, ".8b"); |
| return; |
| break; |
| case 8: |
| // ADDSwww_asr, ADDSwww_lsl, ADDSwww_lsr, ADDSwww_sxtb, ADDSwww_sxth, ADD... |
| SStream_concat(O, ", "); |
| break; |
| case 9: |
| // LDAXP_dword, LDAXP_word, LDXP_dword, LDXP_word, STLXR_byte, STLXR_dwor... |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 10: |
| // LDPSWx_PostInd, LSFPPair128_PostInd_LDR, LSFPPair128_PostInd_STR, LSFP... |
| SStream_concat(O, "], "); |
| set_mem_access(MI, false); |
| break; |
| case 11: |
| // STLXP_dword, STLXP_word, STXP_dword, STXP_word |
| SStream_concat(O, ", ["); |
| set_mem_access(MI, true); |
| printOperand(MI, 3, O); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| } |
| |
| |
| // printf(">> Frag-6: %lu\n", (Bits >> 40) & 63); |
| // Fragment 6 encoded into 6 bits for 33 unique commands. |
| switch ((Bits >> 40) & 63) { |
| default: // unreachable. |
| case 0: |
| // ADDSwww_asr, ADDSxxx_asr, ADDwww_asr, ADDxxx_asr, ANDSwww_asr, ANDSxxx... |
| printShiftOperand(MI, 3, O, A64SE_ASR); |
| return; |
| break; |
| case 1: |
| // ADDSwww_lsl, ADDSxxx_lsl, ADDwww_lsl, ADDxxx_lsl, ANDSwww_lsl, ANDSxxx... |
| printShiftOperand(MI, 3, O, A64SE_LSL); |
| return; |
| break; |
| case 2: |
| // ADDSwww_lsr, ADDSxxx_lsr, ADDwww_lsr, ADDxxx_lsr, ANDSwww_lsr, ANDSxxx... |
| printShiftOperand(MI, 3, O, A64SE_LSR); |
| return; |
| break; |
| case 3: |
| // ADDSwww_sxtb, ADDSxxw_sxtb, ADDwww_sxtb, ADDxxw_sxtb, SUBSwww_sxtb, SU... |
| printRegExtendOperand(MI, 3, O, A64SE_SXTB); |
| return; |
| break; |
| case 4: |
| // ADDSwww_sxth, ADDSxxw_sxth, ADDwww_sxth, ADDxxw_sxth, SUBSwww_sxth, SU... |
| printRegExtendOperand(MI, 3, O, A64SE_SXTH); |
| return; |
| break; |
| case 5: |
| // ADDSwww_sxtw, ADDSxxw_sxtw, ADDwww_sxtw, ADDxxw_sxtw, SUBSwww_sxtw, SU... |
| printRegExtendOperand(MI, 3, O, A64SE_SXTW); |
| return; |
| break; |
| case 6: |
| // ADDSwww_sxtx, ADDSxxx_sxtx, ADDwww_sxtx, ADDxxx_sxtx, SUBSwww_sxtx, SU... |
| printRegExtendOperand(MI, 3, O, A64SE_SXTX); |
| return; |
| break; |
| case 7: |
| // ADDSwww_uxtb, ADDSxxw_uxtb, ADDwww_uxtb, ADDxxw_uxtb, SUBSwww_uxtb, SU... |
| printRegExtendOperand(MI, 3, O, A64SE_UXTB); |
| return; |
| break; |
| case 8: |
| // ADDSwww_uxth, ADDSxxw_uxth, ADDwww_uxth, ADDxxw_uxth, SUBSwww_uxth, SU... |
| printRegExtendOperand(MI, 3, O, A64SE_UXTH); |
| return; |
| break; |
| case 9: |
| // ADDSwww_uxtw, ADDSxxw_uxtw, ADDwww_uxtw, ADDxxw_uxtw, SUBSwww_uxtw, SU... |
| printRegExtendOperand(MI, 3, O, A64SE_UXTW); |
| return; |
| break; |
| case 10: |
| // ADDSwww_uxtx, ADDSxxx_uxtx, ADDwww_uxtx, ADDxxx_uxtx, SUBSwww_uxtx, SU... |
| printRegExtendOperand(MI, 3, O, A64SE_UXTX); |
| return; |
| break; |
| case 11: |
| // ANDSwww_ror, ANDSxxx_ror, ANDwww_ror, ANDxxx_ror, BICSwww_ror, BICSxxx... |
| printShiftOperand(MI, 3, O, A64SE_ROR); |
| return; |
| break; |
| case 12: |
| // BFMwwii, BFMxxii |
| printOperand(MI, 4, O); |
| return; |
| break; |
| case 13: |
| // BFXILwwii, BFXILxxii |
| printBFXWidthOperand(MI, 4, O); |
| return; |
| break; |
| case 14: |
| // CCMNwi, CCMNww, CCMNxi, CCMNxx, CCMPwi, CCMPww, CCMPxi, CCMPxx, CSELww... |
| printCondCodeOperand(MI, 3, O); |
| return; |
| break; |
| case 15: |
| // EXTRwwwi, EXTRxxxi, FMADDdddd, FMADDssss, FMSUBdddd, FMSUBssss, FNMADD... |
| printOperand(MI, 3, O); |
| return; |
| break; |
| case 16: |
| // LDPSWx, LSFPPair32_LDR, LSFPPair32_NonTemp_LDR, LSFPPair32_NonTemp_STR... |
| printSImm7ScaledOperand(MI, 3, O, 4); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 17: |
| // LDPSWx_PostInd, LDPSWx_PreInd, LSFPPair32_PostInd_LDR, LSFPPair32_Post... |
| printSImm7ScaledOperand(MI, 4, O, 4); |
| break; |
| case 18: |
| // LDRSBw_Wm_RegOffset, LDRSBx_Wm_RegOffset, LS8_Wm_RegOffset_LDR, LS8_Wm... |
| printAddrRegExtendOperand(MI, 3, O, 1, 32); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 19: |
| // LDRSBw_Xm_RegOffset, LDRSBx_Xm_RegOffset, LS8_Xm_RegOffset_LDR, LS8_Xm... |
| printAddrRegExtendOperand(MI, 3, O, 1, 64); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 20: |
| // LDRSHw_Wm_RegOffset, LDRSHx_Wm_RegOffset, LS16_Wm_RegOffset_LDR, LS16_... |
| printAddrRegExtendOperand(MI, 3, O, 2, 32); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 21: |
| // LDRSHw_Xm_RegOffset, LDRSHx_Xm_RegOffset, LS16_Xm_RegOffset_LDR, LS16_... |
| printAddrRegExtendOperand(MI, 3, O, 2, 64); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 22: |
| // LDRSWx_Wm_RegOffset, LS32_Wm_RegOffset_LDR, LS32_Wm_RegOffset_STR, LSF... |
| printAddrRegExtendOperand(MI, 3, O, 4, 32); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 23: |
| // LDRSWx_Xm_RegOffset, LS32_Xm_RegOffset_LDR, LS32_Xm_RegOffset_STR, LSF... |
| printAddrRegExtendOperand(MI, 3, O, 4, 64); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 24: |
| // LS64_Wm_RegOffset_LDR, LS64_Wm_RegOffset_STR, LSFP64_Wm_RegOffset_LDR,... |
| printAddrRegExtendOperand(MI, 3, O, 8, 32); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 25: |
| // LS64_Xm_RegOffset_LDR, LS64_Xm_RegOffset_STR, LSFP64_Xm_RegOffset_LDR,... |
| printAddrRegExtendOperand(MI, 3, O, 8, 64); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 26: |
| // LSFP128_Wm_RegOffset_LDR, LSFP128_Wm_RegOffset_STR |
| printAddrRegExtendOperand(MI, 3, O, 16, 32); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 27: |
| // LSFP128_Xm_RegOffset_LDR, LSFP128_Xm_RegOffset_STR |
| printAddrRegExtendOperand(MI, 3, O, 16, 64); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 28: |
| // LSFPPair128_LDR, LSFPPair128_NonTemp_LDR, LSFPPair128_NonTemp_STR, LSF... |
| printSImm7ScaledOperand(MI, 3, O, 16); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 29: |
| // LSFPPair128_PostInd_LDR, LSFPPair128_PostInd_STR, LSFPPair128_PreInd_L... |
| printSImm7ScaledOperand(MI, 4, O, 16); |
| break; |
| case 30: |
| // LSFPPair64_LDR, LSFPPair64_NonTemp_LDR, LSFPPair64_NonTemp_STR, LSFPPa... |
| printSImm7ScaledOperand(MI, 3, O, 8); |
| SStream_concat(O, "]"); |
| set_mem_access(MI, false); |
| return; |
| break; |
| case 31: |
| // LSFPPair64_PostInd_LDR, LSFPPair64_PostInd_STR, LSFPPair64_PreInd_LDR,... |
| printSImm7ScaledOperand(MI, 4, O, 8); |
| break; |
| case 32: |
| // SBFXwwii, SBFXxxii, UBFXwwii, UBFXxxii |
| printBFXWidthOperand(MI, 3, O); |
| return; |
| break; |
| } |
| |
| |
| // printf(">> Frag-7: %lu\n", (Bits >> 46) & 1); |
| // Fragment 7 encoded into 1 bits for 2 unique commands. |
| if ((Bits >> 46) & 1) { |
| // LDPSWx_PreInd, LSFPPair128_PreInd_LDR, LSFPPair128_PreInd_STR, LSFPPai... |
| SStream_concat(O, "]!"); // qqq |
| set_mem_access(MI, false); |
| return; |
| } else { |
| // LDPSWx_PostInd, LSFPPair128_PostInd_LDR, LSFPPair128_PostInd_STR, LSFP... |
| return; |
| } |
| } |
| |
| |
| /// getRegisterName - This method is automatically generated by tblgen |
| /// from the register set description. This returns the assembler name |
| /// for the specified register. |
| static char *getRegisterName(unsigned RegNo) |
| { |
| //assert(RegNo && RegNo < 228 && "Invalid register number!"); |
| |
| static char AsmStrs[] = { |
| /* 0 */ 'b', '1', '0', 0, |
| /* 4 */ 'd', '1', '0', 0, |
| /* 8 */ 'h', '1', '0', 0, |
| /* 12 */ 'q', '1', '0', 0, |
| /* 16 */ 's', '1', '0', 0, |
| /* 20 */ 'w', '1', '0', 0, |
| /* 24 */ 'x', '1', '0', 0, |
| /* 28 */ 'b', '2', '0', 0, |
| /* 32 */ 'd', '2', '0', 0, |
| /* 36 */ 'h', '2', '0', 0, |
| /* 40 */ 'q', '2', '0', 0, |
| /* 44 */ 's', '2', '0', 0, |
| /* 48 */ 'w', '2', '0', 0, |
| /* 52 */ 'x', '2', '0', 0, |
| /* 56 */ 'b', '3', '0', 0, |
| /* 60 */ 'd', '3', '0', 0, |
| /* 64 */ 'h', '3', '0', 0, |
| /* 68 */ 'q', '3', '0', 0, |
| /* 72 */ 's', '3', '0', 0, |
| /* 76 */ 'w', '3', '0', 0, |
| /* 80 */ 'x', '3', '0', 0, |
| /* 84 */ 'b', '0', 0, |
| /* 87 */ 'd', '0', 0, |
| /* 90 */ 'h', '0', 0, |
| /* 93 */ 'q', '0', 0, |
| /* 96 */ 's', '0', 0, |
| /* 99 */ 'w', '0', 0, |
| /* 102 */ 'x', '0', 0, |
| /* 105 */ 'b', '1', '1', 0, |
| /* 109 */ 'd', '1', '1', 0, |
| /* 113 */ 'h', '1', '1', 0, |
| /* 117 */ 'q', '1', '1', 0, |
| /* 121 */ 's', '1', '1', 0, |
| /* 125 */ 'w', '1', '1', 0, |
| /* 129 */ 'x', '1', '1', 0, |
| /* 133 */ 'b', '2', '1', 0, |
| /* 137 */ 'd', '2', '1', 0, |
| /* 141 */ 'h', '2', '1', 0, |
| /* 145 */ 'q', '2', '1', 0, |
| /* 149 */ 's', '2', '1', 0, |
| /* 153 */ 'w', '2', '1', 0, |
| /* 157 */ 'x', '2', '1', 0, |
| /* 161 */ 'b', '3', '1', 0, |
| /* 165 */ 'd', '3', '1', 0, |
| /* 169 */ 'h', '3', '1', 0, |
| /* 173 */ 'q', '3', '1', 0, |
| /* 177 */ 's', '3', '1', 0, |
| /* 181 */ 'b', '1', 0, |
| /* 184 */ 'd', '1', 0, |
| /* 187 */ 'h', '1', 0, |
| /* 190 */ 'q', '1', 0, |
| /* 193 */ 's', '1', 0, |
| /* 196 */ 'w', '1', 0, |
| /* 199 */ 'x', '1', 0, |
| /* 202 */ 'b', '1', '2', 0, |
| /* 206 */ 'd', '1', '2', 0, |
| /* 210 */ 'h', '1', '2', 0, |
| /* 214 */ 'q', '1', '2', 0, |
| /* 218 */ 's', '1', '2', 0, |
| /* 222 */ 'w', '1', '2', 0, |
| /* 226 */ 'x', '1', '2', 0, |
| /* 230 */ 'b', '2', '2', 0, |
| /* 234 */ 'd', '2', '2', 0, |
| /* 238 */ 'h', '2', '2', 0, |
| /* 242 */ 'q', '2', '2', 0, |
| /* 246 */ 's', '2', '2', 0, |
| /* 250 */ 'w', '2', '2', 0, |
| /* 254 */ 'x', '2', '2', 0, |
| /* 258 */ 'b', '2', 0, |
| /* 261 */ 'd', '2', 0, |
| /* 264 */ 'h', '2', 0, |
| /* 267 */ 'q', '2', 0, |
| /* 270 */ 's', '2', 0, |
| /* 273 */ 'w', '2', 0, |
| /* 276 */ 'x', '2', 0, |
| /* 279 */ 'b', '1', '3', 0, |
| /* 283 */ 'd', '1', '3', 0, |
| /* 287 */ 'h', '1', '3', 0, |
| /* 291 */ 'q', '1', '3', 0, |
| /* 295 */ 's', '1', '3', 0, |
| /* 299 */ 'w', '1', '3', 0, |
| /* 303 */ 'x', '1', '3', 0, |
| /* 307 */ 'b', '2', '3', 0, |
| /* 311 */ 'd', '2', '3', 0, |
| /* 315 */ 'h', '2', '3', 0, |
| /* 319 */ 'q', '2', '3', 0, |
| /* 323 */ 's', '2', '3', 0, |
| /* 327 */ 'w', '2', '3', 0, |
| /* 331 */ 'x', '2', '3', 0, |
| /* 335 */ 'b', '3', 0, |
| /* 338 */ 'd', '3', 0, |
| /* 341 */ 'h', '3', 0, |
| /* 344 */ 'q', '3', 0, |
| /* 347 */ 's', '3', 0, |
| /* 350 */ 'w', '3', 0, |
| /* 353 */ 'x', '3', 0, |
| /* 356 */ 'b', '1', '4', 0, |
| /* 360 */ 'd', '1', '4', 0, |
| /* 364 */ 'h', '1', '4', 0, |
| /* 368 */ 'q', '1', '4', 0, |
| /* 372 */ 's', '1', '4', 0, |
| /* 376 */ 'w', '1', '4', 0, |
| /* 380 */ 'x', '1', '4', 0, |
| /* 384 */ 'b', '2', '4', 0, |
| /* 388 */ 'd', '2', '4', 0, |
| /* 392 */ 'h', '2', '4', 0, |
| /* 396 */ 'q', '2', '4', 0, |
| /* 400 */ 's', '2', '4', 0, |
| /* 404 */ 'w', '2', '4', 0, |
| /* 408 */ 'x', '2', '4', 0, |
| /* 412 */ 'b', '4', 0, |
| /* 415 */ 'd', '4', 0, |
| /* 418 */ 'h', '4', 0, |
| /* 421 */ 'q', '4', 0, |
| /* 424 */ 's', '4', 0, |
| /* 427 */ 'w', '4', 0, |
| /* 430 */ 'x', '4', 0, |
| /* 433 */ 'b', '1', '5', 0, |
| /* 437 */ 'd', '1', '5', 0, |
| /* 441 */ 'h', '1', '5', 0, |
| /* 445 */ 'q', '1', '5', 0, |
| /* 449 */ 's', '1', '5', 0, |
| /* 453 */ 'w', '1', '5', 0, |
| /* 457 */ 'x', '1', '5', 0, |
| /* 461 */ 'b', '2', '5', 0, |
| /* 465 */ 'd', '2', '5', 0, |
| /* 469 */ 'h', '2', '5', 0, |
| /* 473 */ 'q', '2', '5', 0, |
| /* 477 */ 's', '2', '5', 0, |
| /* 481 */ 'w', '2', '5', 0, |
| /* 485 */ 'x', '2', '5', 0, |
| /* 489 */ 'b', '5', 0, |
| /* 492 */ 'd', '5', 0, |
| /* 495 */ 'h', '5', 0, |
| /* 498 */ 'q', '5', 0, |
| /* 501 */ 's', '5', 0, |
| /* 504 */ 'w', '5', 0, |
| /* 507 */ 'x', '5', 0, |
| /* 510 */ 'b', '1', '6', 0, |
| /* 514 */ 'd', '1', '6', 0, |
| /* 518 */ 'h', '1', '6', 0, |
| /* 522 */ 'q', '1', '6', 0, |
| /* 526 */ 's', '1', '6', 0, |
| /* 530 */ 'w', '1', '6', 0, |
| /* 534 */ 'x', '1', '6', 0, |
| /* 538 */ 'b', '2', '6', 0, |
| /* 542 */ 'd', '2', '6', 0, |
| /* 546 */ 'h', '2', '6', 0, |
| /* 550 */ 'q', '2', '6', 0, |
| /* 554 */ 's', '2', '6', 0, |
| /* 558 */ 'w', '2', '6', 0, |
| /* 562 */ 'x', '2', '6', 0, |
| /* 566 */ 'b', '6', 0, |
| /* 569 */ 'd', '6', 0, |
| /* 572 */ 'h', '6', 0, |
| /* 575 */ 'q', '6', 0, |
| /* 578 */ 's', '6', 0, |
| /* 581 */ 'w', '6', 0, |
| /* 584 */ 'x', '6', 0, |
| /* 587 */ 'b', '1', '7', 0, |
| /* 591 */ 'd', '1', '7', 0, |
| /* 595 */ 'h', '1', '7', 0, |
| /* 599 */ 'q', '1', '7', 0, |
| /* 603 */ 's', '1', '7', 0, |
| /* 607 */ 'w', '1', '7', 0, |
| /* 611 */ 'x', '1', '7', 0, |
| /* 615 */ 'b', '2', '7', 0, |
| /* 619 */ 'd', '2', '7', 0, |
| /* 623 */ 'h', '2', '7', 0, |
| /* 627 */ 'q', '2', '7', 0, |
| /* 631 */ 's', '2', '7', 0, |
| /* 635 */ 'w', '2', '7', 0, |
| /* 639 */ 'x', '2', '7', 0, |
| /* 643 */ 'b', '7', 0, |
| /* 646 */ 'd', '7', 0, |
| /* 649 */ 'h', '7', 0, |
| /* 652 */ 'q', '7', 0, |
| /* 655 */ 's', '7', 0, |
| /* 658 */ 'w', '7', 0, |
| /* 661 */ 'x', '7', 0, |
| /* 664 */ 'b', '1', '8', 0, |
| /* 668 */ 'd', '1', '8', 0, |
| /* 672 */ 'h', '1', '8', 0, |
| /* 676 */ 'q', '1', '8', 0, |
| /* 680 */ 's', '1', '8', 0, |
| /* 684 */ 'w', '1', '8', 0, |
| /* 688 */ 'x', '1', '8', 0, |
| /* 692 */ 'b', '2', '8', 0, |
| /* 696 */ 'd', '2', '8', 0, |
| /* 700 */ 'h', '2', '8', 0, |
| /* 704 */ 'q', '2', '8', 0, |
| /* 708 */ 's', '2', '8', 0, |
| /* 712 */ 'w', '2', '8', 0, |
| /* 716 */ 'x', '2', '8', 0, |
| /* 720 */ 'b', '8', 0, |
| /* 723 */ 'd', '8', 0, |
| /* 726 */ 'h', '8', 0, |
| /* 729 */ 'q', '8', 0, |
| /* 732 */ 's', '8', 0, |
| /* 735 */ 'w', '8', 0, |
| /* 738 */ 'x', '8', 0, |
| /* 741 */ 'b', '1', '9', 0, |
| /* 745 */ 'd', '1', '9', 0, |
| /* 749 */ 'h', '1', '9', 0, |
| /* 753 */ 'q', '1', '9', 0, |
| /* 757 */ 's', '1', '9', 0, |
| /* 761 */ 'w', '1', '9', 0, |
| /* 765 */ 'x', '1', '9', 0, |
| /* 769 */ 'b', '2', '9', 0, |
| /* 773 */ 'd', '2', '9', 0, |
| /* 777 */ 'h', '2', '9', 0, |
| /* 781 */ 'q', '2', '9', 0, |
| /* 785 */ 's', '2', '9', 0, |
| /* 789 */ 'w', '2', '9', 0, |
| /* 793 */ 'x', '2', '9', 0, |
| /* 797 */ 'b', '9', 0, |
| /* 800 */ 'd', '9', 0, |
| /* 803 */ 'h', '9', 0, |
| /* 806 */ 'q', '9', 0, |
| /* 809 */ 's', '9', 0, |
| /* 812 */ 'w', '9', 0, |
| /* 815 */ 'x', '9', 0, |
| /* 818 */ 'w', 's', 'p', 0, |
| /* 822 */ 'w', 'z', 'r', 0, |
| /* 826 */ 'x', 'z', 'r', 0, |
| /* 830 */ 'n', 'z', 'c', 'v', 0, |
| }; |
| |
| static uint32_t RegAsmOffset[] = { |
| 830, 818, 822, 819, 826, 84, 181, 258, 335, 412, 489, 566, 643, 720, |
| 797, 0, 105, 202, 279, 356, 433, 510, 587, 664, 741, 28, 133, 230, |
| 307, 384, 461, 538, 615, 692, 769, 56, 161, 87, 184, 261, 338, 415, |
| 492, 569, 646, 723, 800, 4, 109, 206, 283, 360, 437, 514, 591, 668, |
| 745, 32, 137, 234, 311, 388, 465, 542, 619, 696, 773, 60, 165, 90, |
| 187, 264, 341, 418, 495, 572, 649, 726, 803, 8, 113, 210, 287, 364, |
| 441, 518, 595, 672, 749, 36, 141, 238, 315, 392, 469, 546, 623, 700, |
| 777, 64, 169, 93, 190, 267, 344, 421, 498, 575, 652, 729, 806, 12, |
| 117, 214, 291, 368, 445, 522, 599, 676, 753, 40, 145, 242, 319, 396, |
| 473, 550, 627, 704, 781, 68, 173, 96, 193, 270, 347, 424, 501, 578, |
| 655, 732, 809, 16, 121, 218, 295, 372, 449, 526, 603, 680, 757, 44, |
| 149, 246, 323, 400, 477, 554, 631, 708, 785, 72, 177, 99, 196, 273, |
| 350, 427, 504, 581, 658, 735, 812, 20, 125, 222, 299, 376, 453, 530, |
| 607, 684, 761, 48, 153, 250, 327, 404, 481, 558, 635, 712, 789, 76, |
| 102, 199, 276, 353, 430, 507, 584, 661, 738, 815, 24, 129, 226, 303, |
| 380, 457, 534, 611, 688, 765, 52, 157, 254, 331, 408, 485, 562, 639, |
| 716, 793, 80, |
| }; |
| |
| //assert (*(AsmStrs+RegAsmOffset[RegNo-1]) && |
| // "Invalid alt name index for register!"); |
| //int i; |
| //for (i = 0; i < sizeof(RegAsmOffset)/4; i++) |
| // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); |
| //printf("*************************\n"); |
| return AsmStrs+RegAsmOffset[RegNo-1]; |
| } |
| |
| #ifdef PRINT_ALIAS_INSTR |
| #undef PRINT_ALIAS_INSTR |
| |
| static bool printAliasInstr(MCInst *MI, SStream *OS, void *info) |
| { |
| char *AsmString; |
| |
| #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) |
| |
| MCRegisterInfo *MRI = (MCRegisterInfo *)info; |
| |
| switch (MCInst_getOpcode(MI)) { |
| default: return false; |
| case AArch64_ADDSwww_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (ADDSwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0) |
| AsmString = "adds $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_ADDSwww_uxtw: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_RwspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (ADDSwww_uxtw GPR32:$Rd, Rwsp:$Rn, GPR32:$Rm, 0) |
| AsmString = "adds $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_ADDSxxx_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (ADDSxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0) |
| AsmString = "adds $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_ADDSxxx_uxtx: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_RxspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (ADDSxxx_uxtx GPR64:$Rd, Rxsp:$Rn, GPR64:$Rm, 0) |
| AsmString = "adds $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_ADDwwi_lsl0_s: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32wspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32wspRegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_RwspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (ADDwwi_lsl0_s GPR32wsp:$Rd, Rwsp:$Rn, 0) |
| AsmString = "mov $\x01, $\x02"; |
| break; |
| } |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_RwspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32wspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32wspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (ADDwwi_lsl0_s Rwsp:$Rd, GPR32wsp:$Rn, 0) |
| AsmString = "mov $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64_ADDwww_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (ADDwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0) |
| AsmString = "add $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_ADDwww_uxtw: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_RwspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32wspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32wspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (ADDwww_uxtw Rwsp:$Rd, GPR32wsp:$Rn, GPR32:$Rm, 0) |
| AsmString = "add $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32wspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32wspRegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_RwspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (ADDwww_uxtw GPR32wsp:$Rd, Rwsp:$Rn, GPR32:$Rm, 0) |
| AsmString = "add $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_ADDxxi_lsl0_s: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_RxspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (ADDxxi_lsl0_s GPR64xsp:$Rd, Rxsp:$Rn, 0) |
| AsmString = "mov $\x01, $\x02"; |
| break; |
| } |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_RxspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (ADDxxi_lsl0_s Rxsp:$Rd, GPR64xsp:$Rn, 0) |
| AsmString = "mov $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64_ADDxxx_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (ADDxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0) |
| AsmString = "add $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_ADDxxx_uxtx: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_RxspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (ADDxxx_uxtx Rxsp:$Rd, GPR64xsp:$Rn, GPR64:$Rm, 0) |
| AsmString = "add $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_RxspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (ADDxxx_uxtx GPR64xsp:$Rd, Rxsp:$Rn, GPR64:$Rm, 0) |
| AsmString = "add $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_ANDSwww_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (ANDSwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0) |
| AsmString = "ands $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_ANDSxxx_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (ANDSxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0) |
| AsmString = "ands $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_ANDwww_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (ANDwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0) |
| AsmString = "and $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_ANDxxx_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (ANDxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0) |
| AsmString = "and $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_BICSwww_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (BICSwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0) |
| AsmString = "bics $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_BICSxxx_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (BICSxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0) |
| AsmString = "bics $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_BICwww_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (BICwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0) |
| AsmString = "bic $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_BICxxx_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (BICxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0) |
| AsmString = "bic $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_CLREXi: |
| if (MCInst_getNumOperands(MI) == 1 && |
| MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { |
| // (CLREXi 15) |
| AsmString = "clrex"; |
| break; |
| } |
| return false; |
| case AArch64_CMNww_lsl: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (CMNww_lsl GPR32:$Rn, GPR32:$Rm, 0) |
| AsmString = "cmn $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64_CMNww_uxtw: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_RwspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (CMNww_uxtw Rwsp:$Rn, GPR32:$Rm, 0) |
| AsmString = "cmn $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64_CMNxx_lsl: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (CMNxx_lsl GPR64:$Rn, GPR64:$Rm, 0) |
| AsmString = "cmn $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64_CMNxx_uxtx: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_RxspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (CMNxx_uxtx Rxsp:$Rn, GPR64:$Rm, 0) |
| AsmString = "cmn $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64_CMPww_lsl: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (CMPww_lsl GPR32:$Rn, GPR32:$Rm, 0) |
| AsmString = "cmp $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64_CMPww_uxtw: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_RwspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (CMPww_uxtw Rwsp:$Rn, GPR32:$Rm, 0) |
| AsmString = "cmp $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64_CMPxx_lsl: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (CMPxx_lsl GPR64:$Rn, GPR64:$Rm, 0) |
| AsmString = "cmp $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64_CMPxx_uxtx: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_RxspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (CMPxx_uxtx Rxsp:$Rn, GPR64:$Rm, 0) |
| AsmString = "cmp $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64_DCPS1i: |
| if (MCInst_getNumOperands(MI) == 1 && |
| MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { |
| // (DCPS1i 0) |
| AsmString = "dcps1"; |
| break; |
| } |
| return false; |
| case AArch64_DCPS2i: |
| if (MCInst_getNumOperands(MI) == 1 && |
| MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { |
| // (DCPS2i 0) |
| AsmString = "dcps2"; |
| break; |
| } |
| return false; |
| case AArch64_DCPS3i: |
| if (MCInst_getNumOperands(MI) == 1 && |
| MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { |
| // (DCPS3i 0) |
| AsmString = "dcps3"; |
| break; |
| } |
| return false; |
| case AArch64_EONwww_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (EONwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0) |
| AsmString = "eon $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_EONxxx_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (EONxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0) |
| AsmString = "eon $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_EORwww_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (EORwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0) |
| AsmString = "eor $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_EORxxx_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (EORxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0) |
| AsmString = "eor $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_HINTi: |
| if (MCInst_getNumOperands(MI) == 1 && |
| MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { |
| // (HINTi 0) |
| AsmString = "nop"; |
| break; |
| } |
| if (MCInst_getNumOperands(MI) == 1 && |
| MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1) { |
| // (HINTi 1) |
| AsmString = "yield"; |
| break; |
| } |
| if (MCInst_getNumOperands(MI) == 1 && |
| MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2) { |
| // (HINTi 2) |
| AsmString = "wfe"; |
| break; |
| } |
| if (MCInst_getNumOperands(MI) == 1 && |
| MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3) { |
| // (HINTi 3) |
| AsmString = "wfi"; |
| break; |
| } |
| if (MCInst_getNumOperands(MI) == 1 && |
| MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4) { |
| // (HINTi 4) |
| AsmString = "sev"; |
| break; |
| } |
| if (MCInst_getNumOperands(MI) == 1 && |
| MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5) { |
| // (HINTi 5) |
| AsmString = "sevl"; |
| break; |
| } |
| return false; |
| case AArch64_ISBi: |
| if (MCInst_getNumOperands(MI) == 1 && |
| MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { |
| // (ISBi 15) |
| AsmString = "isb"; |
| break; |
| } |
| return false; |
| case AArch64_LDPSWx: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (LDPSWx GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0) |
| AsmString = "ldpsw $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LDRSBw: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LDRSBw GPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldrsb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LDRSBw_Xm_RegOffset: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { |
| // (LDRSBw_Xm_RegOffset GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2) |
| AsmString = "ldrsb $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LDRSBx: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LDRSBx GPR64:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldrsb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LDRSBx_Xm_RegOffset: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { |
| // (LDRSBx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2) |
| AsmString = "ldrsb $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LDRSHw: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LDRSHw GPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldrsh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LDRSHw_Xm_RegOffset: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { |
| // (LDRSHw_Xm_RegOffset GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2) |
| AsmString = "ldrsh $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LDRSHx: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LDRSHx GPR64:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldrsh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LDRSHx_Xm_RegOffset: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { |
| // (LDRSHx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2) |
| AsmString = "ldrsh $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LDRSWx: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LDRSWx GPR64:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldrsw $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LDRSWx_Xm_RegOffset: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { |
| // (LDRSWx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2) |
| AsmString = "ldrsw $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LDTRSBw: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LDTRSBw GPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldtrsb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LDTRSBx: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LDTRSBx GPR64:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldtrsb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LDTRSHw: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LDTRSHw GPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldtrsh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LDTRSHx: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LDTRSHx GPR64:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldtrsh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LDTRSWx: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LDTRSWx GPR64:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldtrsw $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LDURSWx: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LDURSWx GPR64:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldursw $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS16_LDR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS16_LDR GPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldrh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS16_LDUR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS16_LDUR GPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldurh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS16_STR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS16_STR GPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "strh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS16_STUR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS16_STUR GPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "sturh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS16_UnPriv_LDR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS16_UnPriv_LDR GPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldtrh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS16_UnPriv_STR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS16_UnPriv_STR GPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "sttrh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS16_Xm_RegOffset_LDR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { |
| // (LS16_Xm_RegOffset_LDR GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2) |
| AsmString = "ldrh $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LS16_Xm_RegOffset_STR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { |
| // (LS16_Xm_RegOffset_STR GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2) |
| AsmString = "strh $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LS32_LDR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS32_LDR GPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS32_LDUR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS32_LDUR GPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS32_STR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS32_STR GPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "str $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS32_STUR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS32_STUR GPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "stur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS32_UnPriv_LDR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS32_UnPriv_LDR GPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldtr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS32_UnPriv_STR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS32_UnPriv_STR GPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "sttr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS32_Xm_RegOffset_LDR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { |
| // (LS32_Xm_RegOffset_LDR GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2) |
| AsmString = "ldr $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LS32_Xm_RegOffset_STR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { |
| // (LS32_Xm_RegOffset_STR GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2) |
| AsmString = "str $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LS64_LDR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS64_LDR GPR64:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS64_LDUR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS64_LDUR GPR64:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS64_STR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS64_STR GPR64:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "str $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS64_STUR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS64_STUR GPR64:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "stur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS64_UnPriv_LDR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS64_UnPriv_LDR GPR64:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldtr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS64_UnPriv_STR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS64_UnPriv_STR GPR64:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "sttr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS64_Xm_RegOffset_LDR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { |
| // (LS64_Xm_RegOffset_LDR GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2) |
| AsmString = "ldr $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LS64_Xm_RegOffset_STR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { |
| // (LS64_Xm_RegOffset_STR GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2) |
| AsmString = "str $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LS8_LDR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS8_LDR GPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldrb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS8_LDUR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS8_LDUR GPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldurb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS8_STR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS8_STR GPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "strb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS8_STUR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS8_STUR GPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "sturb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS8_UnPriv_LDR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS8_UnPriv_LDR GPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldtrb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS8_UnPriv_STR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LS8_UnPriv_STR GPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "sttrb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LS8_Xm_RegOffset_LDR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { |
| // (LS8_Xm_RegOffset_LDR GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2) |
| AsmString = "ldrb $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LS8_Xm_RegOffset_STR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { |
| // (LS8_Xm_RegOffset_STR GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2) |
| AsmString = "strb $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP128_LDR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LSFP128_LDR FPR128:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP128_LDUR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LSFP128_LDUR FPR128:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP128_STR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LSFP128_STR FPR128:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "str $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP128_STUR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LSFP128_STUR FPR128:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "stur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP128_Xm_RegOffset_LDR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { |
| // (LSFP128_Xm_RegOffset_LDR FPR128:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2) |
| AsmString = "ldr $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP128_Xm_RegOffset_STR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { |
| // (LSFP128_Xm_RegOffset_STR FPR128:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2) |
| AsmString = "str $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP16_LDR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR16RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LSFP16_LDR FPR16:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP16_LDUR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR16RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LSFP16_LDUR FPR16:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP16_STR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR16RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LSFP16_STR FPR16:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "str $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP16_STUR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR16RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LSFP16_STUR FPR16:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "stur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP16_Xm_RegOffset_LDR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR16RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { |
| // (LSFP16_Xm_RegOffset_LDR FPR16:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2) |
| AsmString = "ldr $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP16_Xm_RegOffset_STR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR16RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { |
| // (LSFP16_Xm_RegOffset_STR FPR16:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2) |
| AsmString = "str $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP32_LDR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LSFP32_LDR FPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP32_LDUR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LSFP32_LDUR FPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP32_STR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LSFP32_STR FPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "str $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP32_STUR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LSFP32_STUR FPR32:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "stur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP32_Xm_RegOffset_LDR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { |
| // (LSFP32_Xm_RegOffset_LDR FPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2) |
| AsmString = "ldr $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP32_Xm_RegOffset_STR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { |
| // (LSFP32_Xm_RegOffset_STR FPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2) |
| AsmString = "str $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP64_LDR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LSFP64_LDR FPR64:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP64_LDUR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LSFP64_LDUR FPR64:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP64_STR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LSFP64_STR FPR64:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "str $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP64_STUR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LSFP64_STUR FPR64:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "stur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP64_Xm_RegOffset_LDR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { |
| // (LSFP64_Xm_RegOffset_LDR FPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2) |
| AsmString = "ldr $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP64_Xm_RegOffset_STR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { |
| // (LSFP64_Xm_RegOffset_STR FPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2) |
| AsmString = "str $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP8_LDR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR8RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LSFP8_LDR FPR8:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP8_LDUR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR8RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LSFP8_LDUR FPR8:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "ldur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP8_STR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR8RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LSFP8_STR FPR8:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "str $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP8_STUR: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR8RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (LSFP8_STUR FPR8:$Rt, GPR64xsp:$Rn, 0) |
| AsmString = "stur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP8_Xm_RegOffset_LDR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR8RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { |
| // (LSFP8_Xm_RegOffset_LDR FPR8:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2) |
| AsmString = "ldr $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFP8_Xm_RegOffset_STR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR8RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { |
| // (LSFP8_Xm_RegOffset_STR FPR8:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2) |
| AsmString = "str $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFPPair128_LDR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (LSFPPair128_LDR FPR128:$Rt, FPR128:$Rt2, GPR64xsp:$Rn, 0) |
| AsmString = "ldp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFPPair128_NonTemp_LDR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (LSFPPair128_NonTemp_LDR FPR128:$Rt, FPR128:$Rt2, GPR64xsp:$Rn, 0) |
| AsmString = "ldnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFPPair128_NonTemp_STR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (LSFPPair128_NonTemp_STR FPR128:$Rt, FPR128:$Rt2, GPR64xsp:$Rn, 0) |
| AsmString = "stnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFPPair128_STR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (LSFPPair128_STR FPR128:$Rt, FPR128:$Rt2, GPR64xsp:$Rn, 0) |
| AsmString = "stp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFPPair32_LDR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (LSFPPair32_LDR FPR32:$Rt, FPR32:$Rt2, GPR64xsp:$Rn, 0) |
| AsmString = "ldp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFPPair32_NonTemp_LDR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (LSFPPair32_NonTemp_LDR FPR32:$Rt, FPR32:$Rt2, GPR64xsp:$Rn, 0) |
| AsmString = "ldnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFPPair32_NonTemp_STR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (LSFPPair32_NonTemp_STR FPR32:$Rt, FPR32:$Rt2, GPR64xsp:$Rn, 0) |
| AsmString = "stnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFPPair32_STR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (LSFPPair32_STR FPR32:$Rt, FPR32:$Rt2, GPR64xsp:$Rn, 0) |
| AsmString = "stp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFPPair64_LDR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (LSFPPair64_LDR FPR64:$Rt, FPR64:$Rt2, GPR64xsp:$Rn, 0) |
| AsmString = "ldp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFPPair64_NonTemp_LDR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (LSFPPair64_NonTemp_LDR FPR64:$Rt, FPR64:$Rt2, GPR64xsp:$Rn, 0) |
| AsmString = "ldnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFPPair64_NonTemp_STR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (LSFPPair64_NonTemp_STR FPR64:$Rt, FPR64:$Rt2, GPR64xsp:$Rn, 0) |
| AsmString = "stnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSFPPair64_STR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (LSFPPair64_STR FPR64:$Rt, FPR64:$Rt2, GPR64xsp:$Rn, 0) |
| AsmString = "stp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSPair32_LDR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (LSPair32_LDR GPR32:$Rt, GPR32:$Rt2, GPR64xsp:$Rn, 0) |
| AsmString = "ldp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSPair32_NonTemp_LDR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (LSPair32_NonTemp_LDR GPR32:$Rt, GPR32:$Rt2, GPR64xsp:$Rn, 0) |
| AsmString = "ldnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSPair32_NonTemp_STR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (LSPair32_NonTemp_STR GPR32:$Rt, GPR32:$Rt2, GPR64xsp:$Rn, 0) |
| AsmString = "stnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSPair32_STR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (LSPair32_STR GPR32:$Rt, GPR32:$Rt2, GPR64xsp:$Rn, 0) |
| AsmString = "stp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSPair64_LDR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (LSPair64_LDR GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0) |
| AsmString = "ldp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSPair64_NonTemp_LDR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (LSPair64_NonTemp_LDR GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0) |
| AsmString = "ldnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSPair64_NonTemp_STR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (LSPair64_NonTemp_STR GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0) |
| AsmString = "stnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_LSPair64_STR: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (LSPair64_STR GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0) |
| AsmString = "stp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64_MADDwwww: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_WZR) { |
| // (MADDwwww GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, WZR) |
| AsmString = "mul $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_MADDxxxx: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { |
| // (MADDxxxx GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, XZR) |
| AsmString = "mul $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_MSUBwwww: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_WZR) { |
| // (MSUBwwww GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, WZR) |
| AsmString = "mneg $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_MSUBxxxx: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { |
| // (MSUBxxxx GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, XZR) |
| AsmString = "mneg $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_MVNww_lsl: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (MVNww_lsl GPR32:$Rn, GPR32:$Rm, 0) |
| AsmString = "mvn $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64_MVNxx_lsl: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (MVNxx_lsl GPR64:$Rn, GPR64:$Rm, 0) |
| AsmString = "mvn $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64_ORNwww_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (ORNwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0) |
| AsmString = "orn $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_ORNxxx_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (ORNxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0) |
| AsmString = "orn $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_ORRwww_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (ORRwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0) |
| AsmString = "mov $\x01, $\x03"; |
| break; |
| } |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (ORRwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0) |
| AsmString = "orr $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_ORRxxx_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (ORRxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0) |
| AsmString = "mov $\x01, $\x03"; |
| break; |
| } |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (ORRxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0) |
| AsmString = "orr $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_RETx: |
| if (MCInst_getNumOperands(MI) == 1 && |
| MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_X30) { |
| // (RETx X30) |
| AsmString = "ret"; |
| break; |
| } |
| return false; |
| case AArch64_SBCSwww: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2)))) |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { |
| // (SBCSwww GPR32:$Rd, WZR, GPR32:$Rm) |
| AsmString = "ngcs $\x01, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_SBCSxxx: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2)))) |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { |
| // (SBCSxxx GPR64:$Rd, XZR, GPR64:$Rm) |
| AsmString = "ngcs $\x01, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_SBCwww: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2)))) |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { |
| // (SBCwww GPR32:$Rd, WZR, GPR32:$Rm) |
| AsmString = "ngc $\x01, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_SBCxxx: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2)))) |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { |
| // (SBCxxx GPR64:$Rd, XZR, GPR64:$Rm) |
| AsmString = "ngc $\x01, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_SMADDLxwwx: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { |
| // (SMADDLxwwx GPR64:$Rd, GPR32:$Rn, GPR32:$Rm, XZR) |
| AsmString = "smull $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_SMSUBLxwwx: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { |
| // (SMSUBLxwwx GPR64:$Rd, GPR32:$Rn, GPR32:$Rm, XZR) |
| AsmString = "smnegl $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_SUBSwww_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (SUBSwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0) |
| AsmString = "subs $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (SUBSwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0) |
| AsmString = "negs $\x01, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_SUBSwww_uxtw: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_RwspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (SUBSwww_uxtw GPR32:$Rd, Rwsp:$Rn, GPR32:$Rm, 0) |
| AsmString = "subs $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_SUBSxxx_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (SUBSxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0) |
| AsmString = "subs $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (SUBSxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0) |
| AsmString = "negs $\x01, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_SUBSxxx_uxtx: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_RxspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (SUBSxxx_uxtx GPR64:$Rd, Rxsp:$Rn, GPR64:$Rm, 0) |
| AsmString = "subs $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_SUBwww_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (SUBwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0) |
| AsmString = "sub $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (SUBwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0) |
| AsmString = "neg $\x01, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_SUBwww_uxtw: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_RwspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32wspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32wspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (SUBwww_uxtw Rwsp:$Rd, GPR32wsp:$Rn, GPR32:$Rm, 0) |
| AsmString = "sub $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32wspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32wspRegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_RwspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (SUBwww_uxtw GPR32wsp:$Rd, Rwsp:$Rn, GPR32:$Rm, 0) |
| AsmString = "sub $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_SUBxxx_lsl: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (SUBxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0) |
| AsmString = "sub $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (SUBxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0) |
| AsmString = "neg $\x01, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_SUBxxx_uxtx: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_RxspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (SUBxxx_uxtx Rxsp:$Rd, GPR64xsp:$Rn, GPR64:$Rm, 0) |
| AsmString = "sub $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_RxspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && |
| MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { |
| // (SUBxxx_uxtx GPR64xsp:$Rd, Rxsp:$Rn, GPR64:$Rm, 0) |
| AsmString = "sub $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_TSTww_lsl: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (TSTww_lsl GPR32:$Rn, GPR32:$Rm, 0) |
| AsmString = "tst $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64_TSTxx_lsl: |
| if (MCInst_getNumOperands(MI) == 3 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && |
| MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
| MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
| // (TSTxx_lsl GPR64:$Rn, GPR64:$Rm, 0) |
| AsmString = "tst $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64_UMADDLxwwx: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { |
| // (UMADDLxwwx GPR64:$Rd, GPR32:$Rn, GPR32:$Rm, XZR) |
| AsmString = "umull $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64_UMSUBLxwwx: |
| if (MCInst_getNumOperands(MI) == 4 && |
| MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
| //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && |
| MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && |
| MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
| //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
| GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && |
| MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { |
| // (UMSUBLxwwx GPR64:$Rd, GPR32:$Rn, GPR32:$Rm, XZR) |
| AsmString = "umnegl $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| } |
| |
| char *tmp = strdup(AsmString), *AsmMnem, *AsmOps; |
| AsmMnem = tmp; |
| AsmOps = strchr(tmp, ' '); |
| if (AsmOps) { |
| *AsmOps = '\0'; |
| AsmOps += 1; |
| } |
| |
| SStream_concat(OS, "%s", AsmMnem); |
| if (AsmOps) { |
| SStream_concat(OS, "\t"); |
| |
| char *c; |
| for (c = AsmOps; *c; c++) { |
| if (*c == '$') { |
| c += 1; |
| printOperand(MI, *c - 1, OS); |
| } else { |
| SStream_concat(OS, "%c", *c); |
| } |
| } |
| } |
| |
| free(tmp); |
| |
| return true; |
| } |
| |
| #endif // PRINT_ALIAS_INSTR |