initial support for PPC
diff --git a/MCInst.h b/MCInst.h
index 434cc10..73d959a 100644
--- a/MCInst.h
+++ b/MCInst.h
@@ -25,6 +25,7 @@
#include "include/capstone.h"
typedef struct MCInst MCInst;
+typedef struct cs_struct cs_struct;
typedef struct MCOperand MCOperand;
/// MCOperand - Instances of this class represent operands of the MCInst class.
@@ -126,10 +127,10 @@
cs_arm64 arm64; // ARM64 architecture (aka AArch64)
cs_arm arm; // ARM architecture (including Thumb/Thumb2)
cs_mips mips; // MIPS architecture
+ cs_ppc ppc; // PowerPC architecture
};
} cs_insn_flat;
-
/// MCInst - Instances of this class represent a single low-level machine
/// instruction.
struct MCInst {
@@ -137,12 +138,11 @@
MCOperand Operands[32];
unsigned size; // number of operands
cs_insn_flat flat_insn; // insn to be exposed to public
- cs_mode mode; // to be referenced by internal code
unsigned OpcodePub;
- cs_opt_value detail;
int insn_size; // instruction size
int x86_segment; // remove when segment mem ref hack is redundant.
uint64_t address; // address of this insn
+ cs_struct *csh; // save the main csh
};
void MCInst_Init(MCInst *inst);
diff --git a/Makefile b/Makefile
index 6b2dc58..d71b7ee 100644
--- a/Makefile
+++ b/Makefile
@@ -29,18 +29,40 @@
LIBOBJ =
LIBOBJ += cs.o utils.o SStream.o MCInstrDesc.o MCRegisterInfo.o
+
+ifneq (,$(findstring powerpc,$(CAPSTONE_ARCHS)))
+ LIBOBJ += arch/PowerPC/PPCDisassembler.o
+ LIBOBJ += arch/PowerPC/PPCInstPrinter.o
+# LIBOBJ += arch/PowerPC/mapping.o
+ LIBOBJ += arch/PowerPC/module.o
+endif
ifneq (,$(findstring arm,$(CAPSTONE_ARCHS)))
- LIBOBJ += arch/ARM/ARMDisassembler.o arch/ARM/ARMInstPrinter.o arch/ARM/mapping.o arch/ARM/module.o
+ LIBOBJ += arch/ARM/ARMDisassembler.o
+ LIBOBJ += arch/ARM/ARMInstPrinter.o
+ LIBOBJ += arch/ARM/mapping.o
+ LIBOBJ += arch/ARM/module.o
endif
ifneq (,$(findstring x86,$(CAPSTONE_ARCHS)))
- LIBOBJ += arch/X86/X86DisassemblerDecoder.o arch/X86/X86Disassembler.o arch/X86/X86IntelInstPrinter.o arch/X86/X86ATTInstPrinter.o arch/X86/mapping.o arch/X86/module.o
+ LIBOBJ += arch/X86/X86DisassemblerDecoder.o
+ LIBOBJ += arch/X86/X86Disassembler.o
+ LIBOBJ += arch/X86/X86IntelInstPrinter.o
+ LIBOBJ += arch/X86/X86ATTInstPrinter.o
+ LIBOBJ += arch/X86/mapping.o arch/X86/module.o
endif
ifneq (,$(findstring mips,$(CAPSTONE_ARCHS)))
- LIBOBJ += arch/Mips/MipsDisassembler.o arch/Mips/MipsInstPrinter.o arch/Mips/mapping.o arch/Mips/module.o
+ LIBOBJ += arch/Mips/MipsDisassembler.o
+ LIBOBJ += arch/Mips/MipsInstPrinter.o
+ LIBOBJ += arch/Mips/mapping.o
+ LIBOBJ += arch/Mips/module.o
endif
ifneq (,$(findstring aarch64,$(CAPSTONE_ARCHS)))
- LIBOBJ += arch/AArch64/AArch64BaseInfo.o arch/AArch64/AArch64Disassembler.o arch/AArch64/AArch64InstPrinter.o arch/AArch64/mapping.o arch/AArch64/module.o
+ LIBOBJ += arch/AArch64/AArch64BaseInfo.o
+ LIBOBJ += arch/AArch64/AArch64Disassembler.o
+ LIBOBJ += arch/AArch64/AArch64InstPrinter.o
+ LIBOBJ += arch/AArch64/mapping.o
+ LIBOBJ += arch/AArch64/module.o
endif
+
LIBOBJ += MCInst.o
# OSX?
diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c
index 11baf01..3c6848e 100644
--- a/arch/AArch64/AArch64InstPrinter.c
+++ b/arch/AArch64/AArch64InstPrinter.c
@@ -21,6 +21,7 @@
#include "AArch64InstPrinter.h"
#include "AArch64BaseInfo.h"
#include "../../MCInst.h"
+#include "../../cs_priv.h"
#include "../../SStream.h"
#include "../../MCRegisterInfo.h"
#include "../../MathExtras.h"
@@ -35,7 +36,7 @@
static bool doing_mem = false;
static void set_mem_access(MCInst *MI, bool status)
{
- if (MI->detail != CS_OPT_ON)
+ if (MI->csh->detail != CS_OPT_ON)
return;
doing_mem = status;
@@ -70,7 +71,7 @@
else
SStream_concat(O, "#%u", Imm);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = Imm;
MI->flat_insn.arm64.op_count++;
@@ -90,7 +91,7 @@
case 1:
if (RmSize == 32) {
Ext = "uxtw";
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].ext = ARM64_EXT_UXTW;
} else {
Ext = "lsl";
@@ -99,11 +100,11 @@
case 3:
if (RmSize == 32) {
Ext = "sxtw";
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].ext = ARM64_EXT_SXTW;
} else {
Ext = "sxtx";
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].ext = ARM64_EXT_SXTX;
}
break;
@@ -118,7 +119,7 @@
SStream_concat(O, " #0x%x", ShiftAmt);
else
SStream_concat(O, " #%u", ShiftAmt);
- if (MI->detail) {
+ if (MI->csh->detail) {
if (doing_mem) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].shift.type = ARM64_SFT_LSL;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].shift.value = ShiftAmt;
@@ -143,7 +144,7 @@
SStream_concat(O, "#0x%"PRIx64, Imm12);
else
SStream_concat(O, "#%u"PRIu64, Imm12);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = Imm12;
MI->flat_insn.arm64.op_count++;
@@ -156,7 +157,7 @@
printAddSubImmLSL0Operand(MI, OpNum, O);
SStream_concat(O, ", lsl #12");
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.value = 12;
}
@@ -170,7 +171,7 @@
SStream_concat(O, "0x%"PRIx64, imm);
else
SStream_concat(O, "%"PRIu64, imm);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = imm;
MI->flat_insn.arm64.op_count++;
@@ -187,7 +188,7 @@
SStream_concat(O, "#0x%x", LSB);
else
SStream_concat(O, "#%u", LSB);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = LSB;
MI->flat_insn.arm64.op_count++;
@@ -220,7 +221,7 @@
else
SStream_concat(O, "#%u", (ImmS - ImmR + 1));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = ImmS - ImmR + 1;
MI->flat_insn.arm64.op_count++;
@@ -232,7 +233,7 @@
MCOperand *CRx = MCInst_getOperand(MI, OpNum);
SStream_concat(O, "c%"PRIu64, MCOperand_getImm(CRx));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_CIMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = MCOperand_getImm(CRx);
MI->flat_insn.arm64.op_count++;
@@ -247,7 +248,7 @@
SStream_concat(O, "#0x%x", 64 - MCOperand_getImm(ScaleOp));
else
SStream_concat(O, "#%u", 64 - MCOperand_getImm(ScaleOp));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = 64 - MCOperand_getImm(ScaleOp);
MI->flat_insn.arm64.op_count++;
@@ -281,7 +282,7 @@
//o << '#' << format("%.8f", Val);
SStream_concat(O, "#%.8f", Val);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_FP;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].fp = Val;
MI->flat_insn.arm64.op_count++;
@@ -291,7 +292,7 @@
static void printFPZeroOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
SStream_concat(O, "#0.0");
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_FP;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].fp = 0;
MI->flat_insn.arm64.op_count++;
@@ -302,7 +303,7 @@
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
SStream_concat(O, A64CondCodeToString((A64CC_CondCodes)(MCOperand_getImm(MO))));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm64.cc = MCOperand_getImm(MO) + 1;
}
@@ -326,7 +327,7 @@
// of current instruction
SImm += MI->address;
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = SImm;
MI->flat_insn.arm64.op_count++;
@@ -348,7 +349,7 @@
SStream_concat(O, "#0x%"PRIx64, Val);
else
SStream_concat(O, "#%"PRIu64, Val);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = Val;
MI->flat_insn.arm64.op_count++;
@@ -368,7 +369,7 @@
else
SStream_concat(O, "#%u", Imm);
- if (MI->detail) {
+ if (MI->csh->detail) {
if (doing_mem) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.disp = Imm;
} else {
@@ -402,7 +403,7 @@
SStream_concat(O, " #0x%x", imm);
else
SStream_concat(O, " #%u", imm);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.type = Shift + 1;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.value = imm;
}
@@ -419,7 +420,7 @@
SStream_concat(O, "#0x%"PRIx64, imm);
else
SStream_concat(O, "#%"PRIu64, imm);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = imm;
MI->flat_insn.arm64.op_count++;
@@ -431,7 +432,7 @@
SStream_concat(O, ", lsl #0x%x", shift);
else
SStream_concat(O, ", lsl #%u", shift);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.value = shift;
}
@@ -456,7 +457,7 @@
SStream_concat(O, "#0x%"PRIx64, imm);
else
SStream_concat(O, "#%"PRIu64, imm);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = imm;
MI->flat_insn.arm64.op_count++;
@@ -508,7 +509,7 @@
SStream_concat(O, "lsl #0x%x", shift);
else
SStream_concat(O, "lsl #%u", shift);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.value = shift;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].ext = Ext - 4;
@@ -529,7 +530,7 @@
default: break; //llvm_unreachable("Unexpected shift type for printing");
}
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].ext = Ext - 4;
MCOperand *MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_getImm(MO) != 0) {
@@ -538,7 +539,7 @@
SStream_concat(O, " #0x%x", shift);
else
SStream_concat(O, " #%u", shift);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.value = shift;
}
@@ -555,7 +556,7 @@
SStream_concat(O, "#0x%x", Imm * MemScale);
else
SStream_concat(O, "#%u", Imm * MemScale);
- if (MI->detail) {
+ if (MI->csh->detail) {
if (doing_mem) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.disp = Imm * MemScale;
} else {
@@ -574,7 +575,7 @@
Name[0] = 'v';
SStream_concat(O, "%s", Name);
free(Name);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_REG;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].reg = Reg;
MI->flat_insn.arm64.op_count++;
@@ -587,7 +588,7 @@
if (MCOperand_isReg(Op)) {
unsigned Reg = MCOperand_getReg(Op);
SStream_concat(O, getRegisterName(Reg));
- if (MI->detail) {
+ if (MI->csh->detail) {
if (doing_mem) {
if (MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.base == ARM64_REG_INVALID) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.base = Reg;
@@ -606,7 +607,7 @@
SStream_concat(O, "#0x%"PRIx64, imm);
else
SStream_concat(O, "#%"PRIu64, imm);
- if (MI->detail) {
+ if (MI->csh->detail) {
if (doing_mem) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.disp = imm;
} else {
@@ -659,11 +660,11 @@
if (Imm == 0)
return;
SStream_concat(O, ", lsl");
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
} else {
SStream_concat(O, ", msl");
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.type = ARM64_SFT_MSL;
}
@@ -671,7 +672,7 @@
SStream_concat(O, " #0x%"PRIx64, Imm);
else
SStream_concat(O, " #%"PRIu64, Imm);
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.value = Imm;
}
@@ -679,7 +680,7 @@
{
SStream_concat(O, "#0");
// FIXME: vector ZERO
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = 0;
MI->flat_insn.arm64.op_count++;
@@ -699,7 +700,7 @@
SStream_concat(O, "#0x%x", Imm);
else
SStream_concat(O, "#%u", Imm);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = Imm;
MI->flat_insn.arm64.op_count++;
@@ -719,7 +720,7 @@
else
SStream_concat(O, "%u", Imm);
- if (MI->detail) {
+ if (MI->csh->detail) {
if (doing_mem) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.disp = Imm;
} else {
@@ -749,7 +750,7 @@
SStream_concat(O, "#0x%"PRIx64, Mask);
else
SStream_concat(O, "#%"PRIu64, Mask);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = Mask;
MI->flat_insn.arm64.op_count++;
diff --git a/arch/AArch64/mapping.c b/arch/AArch64/mapping.c
index cf8c8f0..0fb5ec0 100644
--- a/arch/AArch64/mapping.c
+++ b/arch/AArch64/mapping.c
@@ -2999,6 +2999,7 @@
if (detail) {
cs_struct handle;
handle.detail = detail;
+
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
insn->detail->regs_read_count = count_positive(insns[i].regs_use);
diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c
index aebf1fc..daa5fdb 100644
--- a/arch/ARM/ARMInstPrinter.c
+++ b/arch/ARM/ARMInstPrinter.c
@@ -124,7 +124,7 @@
static bool doing_mem = false;
static void set_mem_access(MCInst *MI, bool status)
{
- if (MI->detail != CS_OPT_ON)
+ if (MI->csh->detail != CS_OPT_ON)
return;
doing_mem = status;
@@ -171,7 +171,7 @@
//assert (!(ShOpc == ARM_AM_ror && !ShImm) && "Cannot have ror #0");
SStream_concat(O, ARM_AM_getShiftOpcStr(ShOpc));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.type = (arm_shifter)ShOpc;
if (ShOpc != ARM_AM_rrx) {
@@ -181,7 +181,7 @@
SStream_concat(O, "#%u", translateShiftImm(ShImm));
if (_UseMarkup)
SStream_concat(O, ">");
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.value = translateShiftImm(ShImm);
}
}
@@ -277,7 +277,7 @@
case 3: SStream_concat(O, "wfi"); break;
case 4: SStream_concat(O, "sev"); break;
case 5:
- if ((ARM_getFeatureBits(MI->mode) & ARM_HasV8Ops)) {
+ if ((ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops)) {
SStream_concat(O, "sevl"); break;
break;
}
@@ -306,7 +306,7 @@
SStream_concat(O, "\t");
printRegName(O, MCOperand_getReg(Dst));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(Dst);
MI->flat_insn.arm.op_count++;
@@ -315,7 +315,7 @@
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MO1));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO1);
MI->flat_insn.arm.op_count++;
@@ -323,7 +323,7 @@
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MO2));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO2);
MI->flat_insn.arm.op_count++;
@@ -344,7 +344,7 @@
SStream_concat(O, "\t");
printRegName(O, MCOperand_getReg(Dst));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(Dst);
MI->flat_insn.arm.op_count++;
@@ -352,7 +352,7 @@
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MO1));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO1);
MI->flat_insn.arm.op_count++;
@@ -370,7 +370,7 @@
else
SStream_concat(O, "#%u", tmp);
SStream_concat(O, markup(">"));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.type =
(arm_shifter)ARM_AM_getSORegShOp(MCOperand_getImm(MO2));
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.value = tmp;
@@ -401,7 +401,7 @@
printPredicateOperand(MI, 4, O);
SStream_concat(O, "\t{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, 1)));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 1));
MI->flat_insn.arm.op_count++;
@@ -434,7 +434,7 @@
printPredicateOperand(MI, 5, O);
SStream_concat(O, "\t{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, 0)));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
MI->flat_insn.arm.op_count++;
@@ -482,7 +482,7 @@
printPredicateOperand(MI, 1, O);
SStream_concat(O, "\t");
printRegName(O, BaseReg);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = BaseReg;
MI->flat_insn.arm.op_count++;
@@ -541,7 +541,7 @@
if (MCOperand_isReg(Op)) {
unsigned Reg = MCOperand_getReg(Op);
printRegName(O, Reg);
- if (MI->detail) {
+ if (MI->csh->detail) {
if (doing_mem) {
if (MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base == ARM_REG_INVALID)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = Reg;
@@ -564,7 +564,7 @@
// add 8 in ARM mode, or 4 in Thumb mode
if (ARM_rel_branch(MCInst_getOpcode(MI))) {
// only do this for relative branch
- if (MI->mode & CS_MODE_THUMB)
+ if (MI->csh->mode & CS_MODE_THUMB)
imm += MI->address + 4;
else
imm += MI->address + 8;
@@ -582,7 +582,7 @@
SStream_concat(O, "#-0x%x", -imm);
SStream_concat(O, markup(">"));
- if (MI->detail) {
+ if (MI->csh->detail) {
if (doing_mem)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = imm;
else {
@@ -631,7 +631,7 @@
printRegName(O, MCOperand_getReg(MO1));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO1);
@@ -648,7 +648,7 @@
SStream_concat(O, " ");
printRegName(O, MCOperand_getReg(MO2));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.value = MCOperand_getReg(MO2);
//assert(ARM_AM_getSORegOffset(MO3.getImm()) == 0);
}
@@ -659,7 +659,7 @@
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
printRegName(O, MCOperand_getReg(MO1));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO1);
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.type = MCOperand_getImm(MO2) & 7;
@@ -686,7 +686,7 @@
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
}
@@ -698,7 +698,7 @@
SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(getAM2Op(MCOperand_getImm(MO3))), tmp);
else
SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(getAM2Op(MCOperand_getImm(MO3))), tmp);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.type = (arm_shifter)getAM2Op(MCOperand_getImm(MO3));
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.value = tmp;
}
@@ -712,7 +712,7 @@
SStream_concat(O, ", ");
SStream_concat(O, ARM_AM_getAddrOpcStr(getAM2Op(MCOperand_getImm(MO3))));
printRegName(O, MCOperand_getReg(MO2));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = MCOperand_getReg(MO2);
}
@@ -729,11 +729,11 @@
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MO2));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = MCOperand_getReg(MO2);
SStream_concat(O, "]%s", markup(">"));
set_mem_access(MI, false);
@@ -746,14 +746,14 @@
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MO2));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = MCOperand_getReg(MO2);
SStream_concat(O, ", lsl %s #1%s]%s", markup("<imm:"), markup(">"), markup(">"));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.type = ARM_SFT_LSL;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.value = 1;
}
@@ -787,7 +787,7 @@
SStream_concat(O, "%s#%s%u%s", markup("<imm:"),
ARM_AM_getAddrOpcStr(getAM2Op(MCOperand_getImm(MO2))), ImmOffs,
markup(">"));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = ImmOffs;
MI->flat_insn.arm.op_count++;
@@ -797,7 +797,7 @@
SStream_concat(O, ARM_AM_getAddrOpcStr(getAM2Op(MCOperand_getImm(MO2))));
printRegName(O, MCOperand_getReg(MO1));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO1);
MI->flat_insn.arm.op_count++;
@@ -821,7 +821,7 @@
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
SStream_concat(O, "], %s", markup(">"));
set_mem_access(MI, false);
@@ -829,7 +829,7 @@
if (MCOperand_getReg(MO2)) {
SStream_concat(O, "%c", (char)op);
printRegName(O, MCOperand_getReg(MO2));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO2);
MI->flat_insn.arm.op_count++;
@@ -847,7 +847,7 @@
ARM_AM_getAddrOpcStr(op), ImmOffs,
markup(">"));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
if (op)
@@ -870,13 +870,13 @@
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
if (MCOperand_getReg(MO2)) {
SStream_concat(O, ", %s", ARM_AM_getAddrOpcStr(op));
printRegName(O, MCOperand_getReg(MO2));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = MCOperand_getReg(MO2);
if (op)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.scale = -1;
@@ -898,7 +898,7 @@
ImmOffs, markup(">"));
}
- if (MI->detail) {
+ if (MI->csh->detail) {
if (op)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = MCOperand_getImm(MO3);
else
@@ -938,7 +938,7 @@
if (MCOperand_getReg(MO1)) {
SStream_concat(O, ARM_AM_getAddrOpcStr(op));
printRegName(O, MCOperand_getReg(MO1));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = MCOperand_getReg(MO1);
MI->flat_insn.arm.op_count++;
@@ -955,7 +955,7 @@
SStream_concat(O, "%s#%s%u%s", markup("<imm:"),
ARM_AM_getAddrOpcStr(op), ImmOffs,
markup(">"));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
if (op)
@@ -977,7 +977,7 @@
else
SStream_concat(O, "%s#%s%u%s", markup("<imm:"), ((Imm & 256) ? "" : "-"),
(Imm & 0xff), markup(">"));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = Imm & 0xff;
MI->flat_insn.arm.op_count++;
@@ -991,7 +991,7 @@
SStream_concat(O, (MCOperand_getImm(MO2) ? "" : "-"));
printRegName(O, MCOperand_getReg(MO1));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO1);
MI->flat_insn.arm.op_count++;
@@ -1047,7 +1047,7 @@
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
unsigned tmp = MCOperand_getImm(MO2);
if (tmp) {
@@ -1055,7 +1055,7 @@
SStream_concat(O, ":0x%x", (tmp << 3));
else
SStream_concat(O, ":%u", (tmp << 3));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = tmp << 3;
}
SStream_concat(O, "]%s", markup(">"));
@@ -1068,7 +1068,7 @@
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
SStream_concat(O, "]%s", markup(">"));
set_mem_access(MI, false);
@@ -1082,7 +1082,7 @@
else {
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MO));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO);
MI->flat_insn.arm.op_count++;
@@ -1108,7 +1108,7 @@
else
SStream_concat(O, ", %s#%u%s", markup("<imm:"), width, markup(">"));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = lsb;
MI->flat_insn.arm.op_count++;
@@ -1122,7 +1122,7 @@
{
unsigned val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
SStream_concat(O, ARM_MB_MemBOptToString(val,
- ARM_getFeatureBits(MI->mode) & ARM_HasV8Ops));
+ ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops));
}
void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O)
@@ -1142,7 +1142,7 @@
SStream_concat(O, ", asr %s#0x%x%s", markup("<imm:"), tmp, markup(">"));
else
SStream_concat(O, ", asr %s#%u%s", markup("<imm:"), tmp, markup(">"));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.type = ARM_SFT_ASR;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.value = tmp;
}
@@ -1151,7 +1151,7 @@
SStream_concat(O, ", lsl %s#0x%x%s", markup("<imm:"), Amt, markup(">"));
else
SStream_concat(O, ", lsl %s#%u%s", markup("<imm:"), Amt, markup(">"));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.type = ARM_SFT_LSL;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.value = Amt;
}
@@ -1168,7 +1168,7 @@
SStream_concat(O, ", lsl %s#0x%x%s", markup("<imm:"), Imm, markup(">"));
else
SStream_concat(O, ", lsl %s#%u%s", markup("<imm:"), Imm, markup(">"));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.type = ARM_SFT_LSL;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.value = Imm;
}
@@ -1185,7 +1185,7 @@
SStream_concat(O, ", asr %s#0x%x%s", markup("<imm:"), Imm, markup(">"));
else
SStream_concat(O, ", asr %s#%u%s", markup("<imm:"), Imm, markup(">"));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.type = ARM_SFT_ASR;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.value = Imm;
}
@@ -1199,7 +1199,7 @@
for (i = OpNum, e = MCInst_getNumOperands(MI); i != e; ++i) {
if (i != OpNum) SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, i)));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, i));
MI->flat_insn.arm.op_count++;
@@ -1213,14 +1213,14 @@
{
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
printRegName(O, MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_0));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_0);
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_1));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_1);
MI->flat_insn.arm.op_count++;
@@ -1255,7 +1255,7 @@
if (IFlags == 0)
SStream_concat(O, "none");
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = IFlags;
MI->flat_insn.arm.op_count++;
@@ -1269,7 +1269,7 @@
unsigned SpecRegRBit = MCOperand_getImm(Op) >> 4;
unsigned Mask = MCOperand_getImm(Op) & 0xf;
- if (ARM_getFeatureBits(MI->mode) & ARM_FeatureMClass) {
+ if (ARM_getFeatureBits(MI->csh->mode) & ARM_FeatureMClass) {
unsigned SYSm = MCOperand_getImm(Op);
unsigned Opcode = MCInst_getOpcode(MI);
// For reads of the special registers ignore the "mask encoding" bits
@@ -1349,13 +1349,13 @@
// Handle the undefined 15 CC value here for printing so we don't abort().
if ((unsigned)CC == 15) {
SStream_concat(O, "<und>");
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.cc = ARM_CC_INVALID;
} else {
if (CC != ARMCC_AL) {
SStream_concat(O, ARMCC_ARMCondCodeToString(CC));
}
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.cc = CC + 1;
}
}
@@ -1365,7 +1365,7 @@
{
ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
SStream_concat(O, ARMCC_ARMCondCodeToString(CC));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.cc = CC + 1;
}
@@ -1374,7 +1374,7 @@
if (MCOperand_getReg(MCInst_getOperand(MI, OpNum))) {
//assert(MCOperand_getReg(MCInst_getOperand(MI, OpNum)) == ARM_CPSR &&
// "Expect ARM CPSR register!");
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.update_flags = true;
SStream_concat(O, "s");
}
@@ -1387,7 +1387,7 @@
SStream_concat(O, "0x%x", tmp);
else
SStream_concat(O, "%u", tmp);
- if (MI->detail) {
+ if (MI->csh->detail) {
if (doing_mem) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = tmp;
} else {
@@ -1401,7 +1401,7 @@
static void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O)
{
SStream_concat(O, "p%u", MCOperand_getImm(MCInst_getOperand(MI, OpNum)));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_PIMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
@@ -1411,7 +1411,7 @@
static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O)
{
SStream_concat(O, "c%u", MCOperand_getImm(MCInst_getOperand(MI, OpNum)));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_CIMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
@@ -1425,7 +1425,7 @@
SStream_concat(O, "{0x%x}", tmp);
else
SStream_concat(O, "{%u}", tmp);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = tmp;
MI->flat_insn.arm.op_count++;
@@ -1441,7 +1441,7 @@
SStream_concat(O, markup("<imm:"));
if (OffImm == INT32_MIN) {
SStream_concat(O, "#-0");
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = 0;
MI->flat_insn.arm.op_count++;
@@ -1455,7 +1455,7 @@
else
SStream_concat(O, "#%u", OffImm);
}
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = OffImm;
MI->flat_insn.arm.op_count++;
@@ -1472,7 +1472,7 @@
SStream_concat(O, "%s#0x%x", markup("<imm:"), tmp);
else
SStream_concat(O, "%s#%u", markup("<imm:"), tmp);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = tmp;
MI->flat_insn.arm.op_count++;
@@ -1490,7 +1490,7 @@
else
SStream_concat(O, "%s#%u", markup("<imm:"), tmp);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = tmp;
MI->flat_insn.arm.op_count++;
@@ -1531,13 +1531,13 @@
SStream_concat(O, "[");
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
unsigned RegNum = MCOperand_getReg(MO2);
if (RegNum) {
SStream_concat(O, ", ");
printRegName(O, RegNum);
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = RegNum;
}
SStream_concat(O, "]");
@@ -1560,7 +1560,7 @@
SStream_concat(O, "[");
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
unsigned ImmOffs = MCOperand_getImm(MO2);
if (ImmOffs) {
@@ -1570,7 +1570,7 @@
SStream_concat(O, "#0x%x", tmp);
else
SStream_concat(O, "#%u", tmp);
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = tmp;
SStream_concat(O, markup(">"));
}
@@ -1610,7 +1610,7 @@
unsigned Reg = MCOperand_getReg(MO1);
printRegName(O, Reg);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg;
MI->flat_insn.arm.op_count++;
@@ -1638,7 +1638,7 @@
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
int32_t OffImm = (int32_t)MCOperand_getImm(MO2);
@@ -1654,7 +1654,7 @@
else
SStream_concat(O, ", %s#%u%s", markup("<imm:"), OffImm, markup(">"));
}
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = OffImm;
SStream_concat(O, "]%s", markup(">"));
set_mem_access(MI, false);
@@ -1670,7 +1670,7 @@
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
int32_t OffImm = (int32_t)MCOperand_getImm(MO2);
@@ -1688,7 +1688,7 @@
SStream_concat(O, ", %s#%u%s", markup("<imm:"), OffImm, markup(">"));
}
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = OffImm;
SStream_concat(O, "]%s", markup(">"));
set_mem_access(MI, false);
@@ -1709,7 +1709,7 @@
SStream_concat(O, "[");
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
int32_t OffImm = (int32_t)MCOperand_getImm(MO2);
@@ -1728,7 +1728,7 @@
else
SStream_concat(O, ", %s#%u%s", markup("<imm:"), OffImm, markup(">"));
}
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = OffImm;
SStream_concat(O, "]%s", markup(">"));
@@ -1744,7 +1744,7 @@
SStream_concat(O, "[");
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
if (MCOperand_getImm(MO2)) {
SStream_concat(O, ", ");
@@ -1757,7 +1757,7 @@
else
SStream_concat(O, "#%u", tmp);
SStream_concat(O, markup(">"));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = tmp;
}
SStream_concat(O, "]%s", markup(">"));
@@ -1772,7 +1772,7 @@
SStream_concat(O, ", %s", markup("<imm:"));
if (OffImm == INT32_MIN) {
SStream_concat(O, "#-0%s", markup(">"));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = 0;
MI->flat_insn.arm.op_count++;
@@ -1786,7 +1786,7 @@
else
SStream_concat(O, "#%u%s", OffImm, markup(">"));
}
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = OffImm;
MI->flat_insn.arm.op_count++;
@@ -1805,7 +1805,7 @@
SStream_concat(O, ", %s", markup("<imm:"));
if (OffImm == INT32_MIN) {
SStream_concat(O, "#-0%s", markup(">"));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = 0;
MI->flat_insn.arm.op_count++;
@@ -1819,7 +1819,7 @@
else
SStream_concat(O, "#%u%s", OffImm, markup(">"));
}
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = OffImm;
MI->flat_insn.arm.op_count++;
@@ -1837,13 +1837,13 @@
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
//assert(MCOperand_getReg(MO2.getReg() && "Invalid so_reg load / store address!");
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MO2));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = MCOperand_getReg(MO2);
unsigned ShAmt = MCOperand_getImm(MO3);
@@ -1853,7 +1853,7 @@
SStream_concat(O, markup("<imm:"));
SStream_concat(O, "#%d", ShAmt);
SStream_concat(O, markup(">"));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.type = ARM_SFT_LSL;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.value = ShAmt;
}
@@ -1867,7 +1867,7 @@
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
SStream_concat(O, "%s#%f%s", markup("<imm:"), getFPImmFloat(MCOperand_getImm(MO)), markup(">"));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_FP;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].fp = getFPImmFloat(MCOperand_getImm(MO));
MI->flat_insn.arm.op_count++;
@@ -1883,7 +1883,7 @@
SStream_concat(O, "%s#0x%"PRIx64"%s", markup("<imm:"), Val, markup(">"));
else
SStream_concat(O, "%s#%"PRIu64"%s", markup("<imm:"), Val, markup(">"));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = Val;
MI->flat_insn.arm.op_count++;
@@ -1897,7 +1897,7 @@
SStream_concat(O, "%s#0x%x%s", markup("<imm:"), Imm + 1, markup(">"));
else
SStream_concat(O, "%s#%u%s", markup("<imm:"), Imm + 1, markup(">"));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = Imm + 1;
MI->flat_insn.arm.op_count++;
@@ -1917,7 +1917,7 @@
case 3: SStream_concat(O, "24"); break;
}
SStream_concat(O, markup(">"));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.type = ARM_SFT_ROR;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.value = Imm * 8;
}
@@ -1931,7 +1931,7 @@
SStream_concat(O, "#0x%x", tmp);
else
SStream_concat(O, "#%u", tmp);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = tmp;
MI->flat_insn.arm.op_count++;
@@ -1947,7 +1947,7 @@
SStream_concat(O, "#0x%x", tmp);
else
SStream_concat(O, "#%u", tmp);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = tmp;
MI->flat_insn.arm.op_count++;
@@ -1962,7 +1962,7 @@
SStream_concat(O, "[0x%x]",tmp);
else
SStream_concat(O, "[%u]",tmp);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = tmp;
MI->flat_insn.arm.op_count++;
@@ -1973,7 +1973,7 @@
{
SStream_concat(O, "{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
@@ -1989,14 +1989,14 @@
unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1);
SStream_concat(O, "{");
printRegName(O, Reg0);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg0;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, Reg1);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg1;
MI->flat_insn.arm.op_count++;
@@ -2012,14 +2012,14 @@
unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2);
SStream_concat(O, "{");
printRegName(O, Reg0);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg0;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, Reg1);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg1;
MI->flat_insn.arm.op_count++;
@@ -2034,21 +2034,21 @@
// sort order is guaranteed because they're all of the form D<n>.
SStream_concat(O, "{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
MI->flat_insn.arm.op_count++;
@@ -2063,28 +2063,28 @@
// sort order is guaranteed because they're all of the form D<n>.
SStream_concat(O, "{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3;
MI->flat_insn.arm.op_count++;
@@ -2096,7 +2096,7 @@
{
SStream_concat(O, "{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
@@ -2112,14 +2112,14 @@
unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1);
SStream_concat(O, "{");
printRegName(O, Reg0);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg0;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, Reg1);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg1;
MI->flat_insn.arm.op_count++;
@@ -2134,21 +2134,21 @@
// sort order is guaranteed because they're all of the form D<n>.
SStream_concat(O, "{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
MI->flat_insn.arm.op_count++;
@@ -2163,28 +2163,28 @@
// sort order is guaranteed because they're all of the form D<n>.
SStream_concat(O, "{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3;
MI->flat_insn.arm.op_count++;
@@ -2200,14 +2200,14 @@
unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2);
SStream_concat(O, "{");
printRegName(O, Reg0);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg0;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, Reg1);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg1;
MI->flat_insn.arm.op_count++;
@@ -2223,21 +2223,21 @@
// sort order is guaranteed because they're all of the form D<n>.
SStream_concat(O, "{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
MI->flat_insn.arm.op_count++;
@@ -2253,28 +2253,28 @@
// sort order is guaranteed because they're all of the form D<n>.
SStream_concat(O, "{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6;
MI->flat_insn.arm.op_count++;
@@ -2289,21 +2289,21 @@
// sort order is guaranteed because they're all of the form D<n>.
SStream_concat(O, "{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
MI->flat_insn.arm.op_count++;
@@ -2318,28 +2318,28 @@
// sort order is guaranteed because they're all of the form D<n>.
SStream_concat(O, "{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6;
MI->flat_insn.arm.op_count++;
diff --git a/arch/ARM/mapping.c b/arch/ARM/mapping.c
index a40a5be..98e5575 100644
--- a/arch/ARM/mapping.c
+++ b/arch/ARM/mapping.c
@@ -2307,6 +2307,7 @@
if (detail) {
cs_struct handle;
handle.detail = detail;
+
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
insn->detail->regs_read_count = count_positive(insns[i].regs_use);
diff --git a/arch/Mips/MipsDisassembler.c b/arch/Mips/MipsDisassembler.c
index 6fa91ad..ae2cdbe 100644
--- a/arch/Mips/MipsDisassembler.c
+++ b/arch/Mips/MipsDisassembler.c
@@ -371,7 +371,7 @@
static DecodeStatus DecodePtrRegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
- if (Inst->mode & CS_MODE_N64)
+ if (Inst->csh->mode & CS_MODE_N64)
return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
diff --git a/arch/Mips/MipsInstPrinter.c b/arch/Mips/MipsInstPrinter.c
index f566644..72a9ab6 100644
--- a/arch/Mips/MipsInstPrinter.c
+++ b/arch/Mips/MipsInstPrinter.c
@@ -21,6 +21,7 @@
#include "MipsInstPrinter.h"
#include "../../MCInst.h"
+#include "../../cs_priv.h"
#include "../../SStream.h"
#include "../../MCRegisterInfo.h"
#include "../../utils.h"
@@ -88,7 +89,7 @@
{
doing_mem = status;
- if (MI->detail != CS_OPT_ON)
+ if (MI->csh->detail != CS_OPT_ON)
return;
if (doing_mem) {
@@ -195,7 +196,7 @@
unsigned int reg = MCOperand_getReg(Op);
printRegName(O, reg);
reg = Mips_map_register(reg);
- if (MI->detail) {
+ if (MI->csh->detail) {
if (doing_mem) {
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].mem.base = reg;
} else {
@@ -222,7 +223,7 @@
SStream_concat(O, "-%"PRIu64, -imm);
}
}
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].mem.disp = imm;
} else {
if (imm >= 0) {
@@ -237,7 +238,7 @@
SStream_concat(O, "-%"PRIu64, -imm);
}
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_IMM;
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].imm = imm;
MI->flat_insn.mips.op_count++;
@@ -262,7 +263,7 @@
else
SStream_concat(O, "-%u", (short int)-imm);
}
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_IMM;
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].imm = (unsigned short int)imm;
MI->flat_insn.mips.op_count++;
@@ -280,7 +281,7 @@
SStream_concat(O, "0x%x", imm);
else
SStream_concat(O, "%u", imm);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_IMM;
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].imm = imm;
MI->flat_insn.mips.op_count++;
diff --git a/arch/X86/X86ATTInstPrinter.c b/arch/X86/X86ATTInstPrinter.c
index 94ae42d..a898ade 100644
--- a/arch/X86/X86ATTInstPrinter.c
+++ b/arch/X86/X86ATTInstPrinter.c
@@ -23,6 +23,7 @@
#include "../../utils.h"
#include "../../MCInst.h"
+#include "../../cs_priv.h"
#include "../../SStream.h"
#include "../../MCRegisterInfo.h"
#include "mapping.h"
@@ -122,7 +123,7 @@
SStream_concat(O, "%s", markup("<mem:"));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_MEM;
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.base = X86_REG_INVALID;
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.index = X86_REG_INVALID;
@@ -132,7 +133,7 @@
if (MCOperand_isImm(DispSpec)) {
int64_t imm = MCOperand_getImm(DispSpec);
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.disp = imm;
if (imm < 0) {
if (imm <= -HEX_THRESHOLD)
@@ -149,7 +150,7 @@
SStream_concat(O, "%s", markup(">"));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.x86.op_count++;
}
@@ -277,7 +278,7 @@
else
SStream_concat(O, "%"PRIu64, imm);
}
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_IMM;
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].imm = imm;
MI->flat_insn.x86.op_count++;
@@ -290,7 +291,7 @@
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
printRegName(O, MCOperand_getReg(Op));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_REG;
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].reg = MCOperand_getReg(Op);
MI->flat_insn.x86.op_count++;
@@ -309,7 +310,7 @@
else
SStream_concat(O, "%s$-%"PRIu64"%s", markup("<imm:"), -imm, markup(">"));
}
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_IMM;
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].imm = imm;
MI->flat_insn.x86.op_count++;
@@ -347,7 +348,7 @@
MCOperand *DispSpec = MCInst_getOperand(MI, Op+3);
MCOperand *SegReg = MCInst_getOperand(MI, Op+4);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_MEM;
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.base = MCOperand_getReg(BaseReg);
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.index = MCOperand_getReg(IndexReg);
@@ -365,7 +366,7 @@
if (MCOperand_isImm(DispSpec)) {
int64_t DispVal = MCOperand_getImm(DispSpec);
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.disp = DispVal;
if (DispVal || (!MCOperand_getReg(IndexReg) && !MCOperand_getReg(BaseReg))) {
if (DispVal < 0) {
@@ -392,7 +393,7 @@
SStream_concat(O, ", ");
_printOperand(MI, Op+2, O);
unsigned ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op+1));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.scale = ScaleVal;
if (ScaleVal != 1) {
SStream_concat(O, ", %s%u%s", markup("<imm:"), ScaleVal, markup(">"));
@@ -403,7 +404,7 @@
SStream_concat(O, markup(">"));
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.x86.op_count++;
}
@@ -457,7 +458,7 @@
} else
printInstruction(MI, OS);
- if (MI->detail) {
+ if (MI->csh->detail) {
// first op can be embedded in the asm by llvm.
// so we have to handle that case to not miss the first op.
char lastop[32];
diff --git a/arch/X86/X86IntelInstPrinter.c b/arch/X86/X86IntelInstPrinter.c
index fb987a9..9dc852e 100644
--- a/arch/X86/X86IntelInstPrinter.c
+++ b/arch/X86/X86IntelInstPrinter.c
@@ -23,6 +23,7 @@
#include "../../utils.h"
#include "../../MCInst.h"
+#include "../../cs_priv.h"
#include "../../SStream.h"
#include "mapping.h"
@@ -117,7 +118,7 @@
{
MCOperand *DispSpec = MCInst_getOperand(MI, Op);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_MEM;
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.base = X86_REG_INVALID;
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.index = X86_REG_INVALID;
@@ -129,7 +130,7 @@
if (MCOperand_isImm(DispSpec)) {
int64_t imm = MCOperand_getImm(DispSpec);
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.disp = imm;
if (imm < 0) {
if (imm <= -HEX_THRESHOLD)
@@ -146,7 +147,7 @@
SStream_concat(O, "]");
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.x86.op_count++;
}
@@ -233,7 +234,7 @@
} else
printInstruction(MI, O);
- if (MI->detail) {
+ if (MI->csh->detail) {
char tmp[64];
if (get_first_op(O->buffer, tmp)) {
int post;
@@ -342,7 +343,7 @@
else
SStream_concat(O, "%"PRIu64, imm);
}
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_IMM;
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].imm = imm;
MI->flat_insn.x86.op_count++;
@@ -361,7 +362,7 @@
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
printRegName(O, MCOperand_getReg(Op));
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_REG;
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].reg = MCOperand_getReg(Op);
MI->flat_insn.x86.op_count++;
@@ -380,7 +381,7 @@
SStream_concat(O, "-%"PRIu64, -imm);
}
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_IMM;
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].imm = imm;
MI->flat_insn.x86.op_count++;
@@ -418,7 +419,7 @@
MCOperand *DispSpec = MCInst_getOperand(MI, Op+3);
MCOperand *SegReg = MCInst_getOperand(MI, Op+4);
- if (MI->detail) {
+ if (MI->csh->detail) {
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_MEM;
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.base = MCOperand_getReg(BaseReg);
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.index = MCOperand_getReg(IndexReg);
@@ -453,7 +454,7 @@
//assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
} else {
int64_t DispVal = MCOperand_getImm(DispSpec);
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.disp = DispVal;
if (DispVal || (!MCOperand_getReg(IndexReg) && !MCOperand_getReg(BaseReg))) {
if (NeedPlus) {
@@ -480,7 +481,7 @@
SStream_concat(O, "]");
- if (MI->detail)
+ if (MI->csh->detail)
MI->flat_insn.x86.op_count++;
}
diff --git a/arch/X86/module.c b/arch/X86/module.c
index b5f7f8a..6c008a9 100644
--- a/arch/X86/module.c
+++ b/arch/X86/module.c
@@ -30,6 +30,7 @@
handle->errnum = CS_ERR_OPTION;
return CS_ERR_OPTION;
+ case CS_OPT_SYNTAX_DEFAULT:
case CS_OPT_SYNTAX_INTEL:
handle->printer = X86_Intel_printInst;
break;
@@ -39,6 +40,7 @@
break;
}
}
+
return CS_ERR_OK;
}
diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py
index c219072..153d361 100644
--- a/bindings/python/capstone/__init__.py
+++ b/bindings/python/capstone/__init__.py
@@ -1 +1 @@
-from capstone import Cs, CsError, cs_disasm_quick, cs_version, cs_support, CS_API_MAJOR, CS_API_MINOR, CS_ARCH_ARM, CS_ARCH_ARM64, CS_ARCH_MIPS, CS_ARCH_X86, CS_ARCH_ALL, CS_MODE_LITTLE_ENDIAN, CS_MODE_ARM, CS_MODE_THUMB, CS_OPT_SYNTAX, CS_OPT_SYNTAX_INTEL, CS_OPT_SYNTAX_ATT, CS_OPT_DETAIL, CS_OPT_ON, CS_OPT_OFF, CS_MODE_16, CS_MODE_32, CS_MODE_64, CS_MODE_BIG_ENDIAN, CS_MODE_MICRO, CS_MODE_N64
+from capstone import Cs, CsError, cs_disasm_quick, cs_version, cs_support, CS_API_MAJOR, CS_API_MINOR, CS_ARCH_ARM, CS_ARCH_ARM64, CS_ARCH_MIPS, CS_ARCH_X86, CS_ARCH_PPC, CS_ARCH_ALL, CS_MODE_LITTLE_ENDIAN, CS_MODE_ARM, CS_MODE_THUMB, CS_OPT_SYNTAX, CS_OPT_SYNTAX_DEFAULT, CS_OPT_SYNTAX_INTEL, CS_OPT_SYNTAX_ATT, CS_OPT_SYNTAX_DARWIN, CS_OPT_DETAIL, CS_OPT_ON, CS_OPT_OFF, CS_MODE_16, CS_MODE_32, CS_MODE_64, CS_MODE_BIG_ENDIAN, CS_MODE_MICRO, CS_MODE_N64
diff --git a/bindings/python/capstone/capstone.py b/bindings/python/capstone/capstone.py
index 0063152..5add33b 100644
--- a/bindings/python/capstone/capstone.py
+++ b/bindings/python/capstone/capstone.py
@@ -17,6 +17,7 @@
'CS_ARCH_ARM64',
'CS_ARCH_MIPS',
'CS_ARCH_X86',
+ 'CS_ARCH_PPC',
'CS_ARCH_ALL',
'CS_MODE_LITTLE_ENDIAN',
@@ -30,8 +31,10 @@
'CS_MODE_N64',
'CS_OPT_SYNTAX',
+ 'CS_OPT_SYNTAX_DEFAULT',
'CS_OPT_SYNTAX_INTEL',
'CS_OPT_SYNTAX_ATT',
+ 'CS_OPT_SYNTAX_DARWIN',
'CS_OPT_DETAIL',
'CS_OPT_MODE',
@@ -45,6 +48,7 @@
'CS_ERR_CSH',
'CS_ERR_MODE',
'CS_ERR_OPTION',
+ 'CS_ERR_DETAIL',
]
# Capstone C interface
@@ -58,6 +62,7 @@
CS_ARCH_ARM64 = 1
CS_ARCH_MIPS = 2
CS_ARCH_X86 = 3
+CS_ARCH_PPC = 4
CS_ARCH_ALL = 0xFFFF
# disasm mode
@@ -78,9 +83,13 @@
# Capstone option value
CS_OPT_OFF = 0 # Turn OFF an option (CS_OPT_DETAIL)
+CS_OPT_ON = 3 # Turn ON an option - this is default option for CS_OPT_DETAIL
+
+# Capstone syntax value
+CS_OPT_SYNTAX_DEFAULT = 0 # Default assembly syntax of all platforms (CS_OPT_SYNTAX)
CS_OPT_SYNTAX_INTEL = 1 # Intel X86 asm syntax - default syntax on X86 (CS_OPT_SYNTAX, CS_ARCH_X86)
CS_OPT_SYNTAX_ATT = 2 # ATT asm syntax (CS_OPT_SYNTAX, CS_ARCH_X86)
-CS_OPT_ON = 3 # Turn ON an option - this is default option for CS_OPT_DETAIL
+CS_OPT_SYNTAX_DARWIN = 2 # Darwin asm syntax prints register name with only number - (CS_OPT_SYNTAX, CS_ARCH_PPC)
# Capstone error type
CS_ERR_OK = 0 # No error: everything was fine
@@ -90,6 +99,7 @@
CS_ERR_CSH = 4 # Invalid csh argument: cs_close(), cs_errno(), cs_option()
CS_ERR_MODE = 5 # Invalid/unsupported mode: cs_open()
CS_ERR_OPTION = 6 # Invalid/unsupported option: cs_option()
+CS_ERR_DETAIL = 7 # Invalid/unsupported option: cs_option()
import ctypes, ctypes.util
@@ -201,6 +211,7 @@
CS_ERR_CSH: "Invalid csh (CsError)",
CS_ERR_MODE: "Invalid mode (CsError)",
CS_ERR_OPTION: "Invalid option (CsError)",
+ CS_ERR_DETAIL: "Details are unavailable (CsError)",
}
return messages[self.errno]
diff --git a/cs.c b/cs.c
index 58de52f..47fa14b 100644
--- a/cs.c
+++ b/cs.c
@@ -13,7 +13,7 @@
#include "utils.h"
-void (*arch_init[MAX_ARCH])(cs_struct *) = { NULL };
+cs_err (*arch_init[MAX_ARCH])(cs_struct *) = { NULL };
cs_err (*arch_option[MAX_ARCH]) (cs_struct*, cs_opt_type, size_t value);
unsigned int all_arch = 0;
@@ -33,7 +33,8 @@
{
if (arch == CS_ARCH_ALL)
return all_arch == ((1 << CS_ARCH_ARM) | (1 << CS_ARCH_ARM64) |
- (1 << CS_ARCH_MIPS) | (1 << CS_ARCH_X86));
+ (1 << CS_ARCH_MIPS) | (1 << CS_ARCH_X86) |
+ (1 << CS_ARCH_PPC));
return all_arch & (1 << arch);
}
@@ -90,6 +91,7 @@
case CS_ARCH_ARM:
case CS_ARCH_MIPS:
case CS_ARCH_ARM64:
+ case CS_ARCH_PPC:
free(ud->printer_info);
break;
default: // unsupported architecture
@@ -197,8 +199,7 @@
while (size > 0) {
MCInst_Init(&mci);
- mci.detail = handle->detail;
- mci.mode = handle->mode;
+ mci.csh = handle;
bool r = handle->disasm(ud, buffer, size, &mci, &insn_size, offset, handle->getinsn_info);
if (r) {
@@ -397,6 +398,11 @@
if (insn->detail->mips.operands[i].type == op_type)
count++;
break;
+ case CS_ARCH_PPC:
+ for (i = 0; i < insn->detail->ppc.op_count; i++)
+ if (insn->detail->ppc.operands[i].type == op_type)
+ count++;
+ break;
}
return count;
@@ -449,6 +455,14 @@
return i;
}
break;
+ case CS_ARCH_PPC:
+ for (i = 0; i < insn->detail->ppc.op_count; i++) {
+ if (insn->detail->ppc.operands[i].type == op_type)
+ count++;
+ if (count == post)
+ return i;
+ }
+ break;
}
return -1;
diff --git a/cs_priv.h b/cs_priv.h
index ec6c4de..12fcc47 100644
--- a/cs_priv.h
+++ b/cs_priv.h
@@ -27,7 +27,7 @@
unsigned int size;
} ARM_ITStatus;
-typedef struct cs_struct {
+struct cs_struct {
cs_arch arch;
cs_mode mode;
Printer_t printer; // asm printer
@@ -42,12 +42,13 @@
cs_err errnum;
ARM_ITStatus ITBlock; // for Arm only
cs_opt_value detail;
-} cs_struct;
+ int syntax; // asm syntax for simple printer such as PPC
+};
#define MAX_ARCH 8
// constructor initialization for all archs
-extern void (*arch_init[MAX_ARCH]) (cs_struct *);
+extern cs_err (*arch_init[MAX_ARCH]) (cs_struct *);
// support cs_option() for all archs
extern cs_err (*arch_option[MAX_ARCH]) (cs_struct*, cs_opt_type, size_t value);
diff --git a/include/capstone.h b/include/capstone.h
index 719f9c3..c2ee24a 100644
--- a/include/capstone.h
+++ b/include/capstone.h
@@ -29,6 +29,7 @@
CS_ARCH_ARM64, // ARM-64, also called AArch64
CS_ARCH_MIPS, // Mips architecture
CS_ARCH_X86, // X86 architecture (including x86 & x86-64)
+ CS_ARCH_PPC, // PowerPC architecture
CS_ARCH_MAX,
CS_ARCH_ALL = 0xFFFF,
} cs_arch;
@@ -57,9 +58,11 @@
// Runtime option value (associated with option type above)
typedef enum cs_opt_value {
CS_OPT_OFF = 0, // Turn OFF an option (CS_OPT_DETAIL)
- CS_OPT_SYNTAX_INTEL = 1, // X86 Intel asm syntax - default syntax on X86 (CS_OPT_SYNTAX).
+ CS_OPT_ON = 3, // Turn ON an option - default option for CS_OPT_DETAIL
+ CS_OPT_SYNTAX_DEFAULT = 0, // Default asm syntax (CS_OPT_SYNTAX).
+ CS_OPT_SYNTAX_INTEL, // X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX).
CS_OPT_SYNTAX_ATT, // X86 ATT asm syntax (CS_OPT_SYNTAX)
- CS_OPT_ON, // Turn ON an option - default option for CS_OPT_DETAIL
+ CS_OPT_SYNTAX_DARWIN, // Darwin asm syntax prints register name with only number - PPC arch (CS_OPT_SYNTAX)
} cs_opt_value;
@@ -67,6 +70,7 @@
#include "arm64.h"
#include "mips.h"
#include "x86.h"
+#include "ppc.h"
// NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON
typedef struct cs_detail {
@@ -85,6 +89,7 @@
cs_arm64 arm64; // ARM64 architecture (aka AArch64)
cs_arm arm; // ARM architecture (including Thumb/Thumb2)
cs_mips mips; // MIPS architecture
+ cs_ppc ppc; // PowerPC architecture
};
} cs_detail;
diff --git a/tests/test.c b/tests/test.c
index 9076e16..a9ed519 100644
--- a/tests/test.c
+++ b/tests/test.c
@@ -46,6 +46,7 @@
//#define ARM64_CODE "\x20\x74\x0b\xd5" // dc zva, x0
//#define ARM64_CODE "\xe1\x0b\x40\xb9" // ldr w1, [sp, #0x8]
#define ARM64_CODE "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
+#define PPC64_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80"
struct platform platforms[] = {
{
@@ -127,6 +128,22 @@
.size = sizeof(ARM64_CODE) - 1,
.comment = "ARM-64"
},
+ {
+ .arch = CS_ARCH_PPC,
+ .mode = CS_MODE_64 + CS_MODE_BIG_ENDIAN,
+ .code = (unsigned char*)PPC64_CODE,
+ .size = sizeof(PPC64_CODE) - 1,
+ .comment = "PPC-64"
+ },
+ {
+ .arch = CS_ARCH_PPC,
+ .mode = CS_MODE_64 + CS_MODE_BIG_ENDIAN,
+ .code = (unsigned char*)PPC64_CODE,
+ .size = sizeof(PPC64_CODE) - 1,
+ .opt_type = CS_OPT_SYNTAX,
+ .opt_value = CS_OPT_SYNTAX_DARWIN,
+ .comment = "PPC-64, Darwin syntax"
+ },
};
csh handle;