port Windows driver support
diff --git a/arch/AArch64/AArch64BaseInfo.c b/arch/AArch64/AArch64BaseInfo.c
index e2b3436..26eb786 100644
--- a/arch/AArch64/AArch64BaseInfo.c
+++ b/arch/AArch64/AArch64BaseInfo.c
@@ -629,7 +629,7 @@
Op2S = utostr(Op2, false);
//printf("Op1S: %s, CRnS: %s, CRmS: %s, Op2S: %s\n", Op1S, CRnS, CRmS, Op2S);
- dummy = sprintf(result, "s%s_%s_c%s_c%s_%s", Op0S, Op1S, CRnS, CRmS, Op2S);
+ dummy = cs_snprintf(result, 128, "s3_%s_c%s_c%s_%s", Op1S, CRnS, CRmS, Op2S);
(void)dummy;
cs_mem_free(Op0S);
diff --git a/arch/AArch64/AArch64BaseInfo.h b/arch/AArch64/AArch64BaseInfo.h
index 2d6e046..73859c1 100644
--- a/arch/AArch64/AArch64BaseInfo.h
+++ b/arch/AArch64/AArch64BaseInfo.h
@@ -21,7 +21,9 @@
#define CS_LLVM_AARCH64_BASEINFO_H
#include <ctype.h>
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
+#endif
#include <string.h>
#ifndef __cplusplus
diff --git a/arch/AArch64/AArch64Disassembler.c b/arch/AArch64/AArch64Disassembler.c
index 87859a5..e1654e2 100644
--- a/arch/AArch64/AArch64Disassembler.c
+++ b/arch/AArch64/AArch64Disassembler.c
@@ -1165,9 +1165,9 @@
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
MCOperand_CreateImm0(Inst, offset);
- IsLoad = fieldFromInstruction(insn, 22, 1);
+ IsLoad = fieldFromInstruction(insn, 22, 1) != 0;
IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
- IsFP = fieldFromInstruction(insn, 26, 1);
+ IsFP = fieldFromInstruction(insn, 26, 1) != 0;
// Cannot write back to a transfer register (but xzr != sp).
if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
@@ -1260,7 +1260,7 @@
unsigned Rn = fieldFromInstruction(insn, 5, 5);
unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
int32_t offset = fieldFromInstruction(insn, 15, 7);
- bool IsLoad = fieldFromInstruction(insn, 22, 1);
+ bool IsLoad = fieldFromInstruction(insn, 22, 1) != 0;
unsigned Opcode = MCInst_getOpcode(Inst);
bool NeedsDisjointWritebackTransfer = false;
diff --git a/arch/AArch64/AArch64Disassembler.h b/arch/AArch64/AArch64Disassembler.h
index a115140..c669f4e 100644
--- a/arch/AArch64/AArch64Disassembler.h
+++ b/arch/AArch64/AArch64Disassembler.h
@@ -4,7 +4,9 @@
#ifndef CS_AARCH64_DISASSEMBLER_H
#define CS_AARCH64_DISASSEMBLER_H
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
+#endif
#include "capstone/capstone.h"
#include "../../MCRegisterInfo.h"
diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c
index 1bb7ad0..7c5a26d 100644
--- a/arch/AArch64/AArch64InstPrinter.c
+++ b/arch/AArch64/AArch64InstPrinter.c
@@ -16,7 +16,7 @@
#ifdef CAPSTONE_HAS_ARM64
-#include "../../myinttypes.h"
+#include <capstone/platform.h>
#include <stdio.h>
#include <stdlib.h>
@@ -1656,7 +1656,7 @@
static void printSIMDType10Operand(MCInst *MI, unsigned OpNo, SStream *O)
{
- unsigned RawVal = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
+ uint8_t RawVal = (uint8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
uint64_t Val = AArch64_AM_decodeAdvSIMDModImmType10(RawVal);
SStream_concat(O, "#%#016llx", Val);
if (MI->csh->detail) {
diff --git a/arch/AArch64/AArch64Mapping.c b/arch/AArch64/AArch64Mapping.c
index 5b9746c..03d9eb4 100644
--- a/arch/AArch64/AArch64Mapping.c
+++ b/arch/AArch64/AArch64Mapping.c
@@ -1049,26 +1049,26 @@
switch((int)op->type) {
case ARM64_OP_REG:
if ((op->access & CS_AC_READ) && !arr_exist(regs_read, read_count, op->reg)) {
- regs_read[read_count] = op->reg;
+ regs_read[read_count] = (uint16_t)op->reg;
read_count++;
}
if ((op->access & CS_AC_WRITE) && !arr_exist(regs_write, write_count, op->reg)) {
- regs_write[write_count] = op->reg;
+ regs_write[write_count] = (uint16_t)op->reg;
write_count++;
}
break;
case ARM_OP_MEM:
// registers appeared in memory references always being read
if ((op->mem.base != ARM64_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.base)) {
- regs_read[read_count] = op->mem.base;
+ regs_read[read_count] = (uint16_t)op->mem.base;
read_count++;
}
if ((op->mem.index != ARM64_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.index)) {
- regs_read[read_count] = op->mem.index;
+ regs_read[read_count] = (uint16_t)op->mem.index;
read_count++;
}
if ((arm64->writeback) && (op->mem.base != ARM64_REG_INVALID) && !arr_exist(regs_write, write_count, op->mem.base)) {
- regs_write[write_count] = op->mem.base;
+ regs_write[write_count] = (uint16_t)op->mem.base;
write_count++;
}
default: