Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
diff --git a/arch/AArch64/AArch64BaseInfo.c b/arch/AArch64/AArch64BaseInfo.c
index 510813f..e95e0ff 100644
--- a/arch/AArch64/AArch64BaseInfo.c
+++ b/arch/AArch64/AArch64BaseInfo.c
@@ -41,7 +41,7 @@
{
char *lower = cs_strdup(s2), *c;
for (c = lower; *c; c++)
- *c = tolower((int) *c);
+ *c = (char)tolower((int) *c);
bool res = (strcmp(s1, lower) == 0);
cs_mem_free(lower);
@@ -60,7 +60,7 @@
}
*Valid = false;
- return -1;
+ return (uint32_t)-1;
}
bool NamedImmMapper_validImm(NamedImmMapper *N, uint32_t Value)
diff --git a/arch/AArch64/AArch64Disassembler.c b/arch/AArch64/AArch64Disassembler.c
index b1a67e3..64b9c9b 100644
--- a/arch/AArch64/AArch64Disassembler.c
+++ b/arch/AArch64/AArch64Disassembler.c
@@ -215,9 +215,14 @@
static uint64_t getFeatureBits(int feature)
{
// enable all features
- return -1;
+ return (uint64_t)-1;
}
+#ifdef _MSC_VER
+#pragma warning(disable:4242)
+#pragma warning(disable:4244)
+#pragma warning(disable:4706)
+#endif
#include "AArch64GenDisassemblerTables.inc"
#define GET_INSTRINFO_ENUM
@@ -308,10 +313,12 @@
static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
+ uint16_t Register;
+
if (RegNo > 31)
return MCDisassembler_Fail;
- uint16_t Register = getReg(Decoder, AArch64_GPR64RegClassID, RegNo);
+ Register = getReg(Decoder, AArch64_GPR64RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -320,10 +327,12 @@
DecodeGPR64xspRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
+ uint16_t Register;
+
if (RegNo > 31)
return MCDisassembler_Fail;
- uint16_t Register = getReg(Decoder, AArch64_GPR64xspRegClassID, RegNo);
+ Register = getReg(Decoder, AArch64_GPR64xspRegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -332,10 +341,12 @@
uint64_t Address,
void *Decoder)
{
+ uint16_t Register;
+
if (RegNo > 31)
return MCDisassembler_Fail;
- uint16_t Register = getReg(Decoder, AArch64_GPR32RegClassID, RegNo);
+ Register = getReg(Decoder, AArch64_GPR32RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -344,10 +355,12 @@
DecodeGPR32wspRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
+ uint16_t Register;
+
if (RegNo > 31)
return MCDisassembler_Fail;
- uint16_t Register = getReg(Decoder, AArch64_GPR32wspRegClassID, RegNo);
+ Register = getReg(Decoder, AArch64_GPR32wspRegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -356,10 +369,12 @@
DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
+ uint16_t Register;
+
if (RegNo > 31)
return MCDisassembler_Fail;
- uint16_t Register = getReg(Decoder, AArch64_FPR8RegClassID, RegNo);
+ Register = getReg(Decoder, AArch64_FPR8RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -368,10 +383,12 @@
DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
+ uint16_t Register;
+
if (RegNo > 31)
return MCDisassembler_Fail;
- uint16_t Register = getReg(Decoder, AArch64_FPR16RegClassID, RegNo);
+ Register = getReg(Decoder, AArch64_FPR16RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -381,10 +398,12 @@
DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
+ uint16_t Register;
+
if (RegNo > 31)
return MCDisassembler_Fail;
- uint16_t Register = getReg(Decoder, AArch64_FPR32RegClassID, RegNo);
+ Register = getReg(Decoder, AArch64_FPR32RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -393,10 +412,12 @@
DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
+ uint16_t Register;
+
if (RegNo > 31)
return MCDisassembler_Fail;
- uint16_t Register = getReg(Decoder, AArch64_FPR64RegClassID, RegNo);
+ Register = getReg(Decoder, AArch64_FPR64RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -415,10 +436,12 @@
DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
+ uint16_t Register;
+
if (RegNo > 31)
return MCDisassembler_Fail;
- uint16_t Register = getReg(Decoder, AArch64_FPR128RegClassID, RegNo);
+ Register = getReg(Decoder, AArch64_FPR128RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -438,10 +461,12 @@
uint64_t Address,
void *Decoder)
{
+ uint16_t Register;
+
if (RegNo > 30)
return MCDisassembler_Fail;
- uint16_t Register = getReg(Decoder, AArch64_GPR64noxzrRegClassID, RegNo);
+ Register = getReg(Decoder, AArch64_GPR64noxzrRegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -450,10 +475,12 @@
unsigned RegID,
void *Decoder)
{
+ uint16_t Register;
+
if (RegNo > 31)
return MCDisassembler_Fail;
- uint16_t Register = getReg(Decoder, RegID, RegNo);
+ Register = getReg(Decoder, RegID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c
index 21dc187..0f42023 100644
--- a/arch/AArch64/AArch64InstPrinter.c
+++ b/arch/AArch64/AArch64InstPrinter.c
@@ -61,7 +61,7 @@
static void printOffsetSImm9Operand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MOImm = MCInst_getOperand(MI, OpNum);
- int32_t Imm = unpackSignedImm(9, MCOperand_getImm(MOImm));
+ int32_t Imm = (int32_t)unpackSignedImm(9, MCOperand_getImm(MOImm));
if (Imm > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", Imm);
@@ -78,7 +78,7 @@
static void printAddrRegExtendOperand(MCInst *MI, unsigned OpNum,
SStream *O, unsigned MemSize, unsigned RmSize)
{
- unsigned ExtImm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ unsigned ExtImm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned OptionHi = ExtImm >> 1;
unsigned S = ExtImm & 1;
bool IsLSL = OptionHi == 1 && RmSize == 64;
@@ -143,7 +143,7 @@
SStream_concat(O, "#%u"PRIu64, Imm12);
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = Imm12;
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)Imm12;
MI->flat_insn.arm64.op_count++;
}
}
@@ -170,7 +170,7 @@
SStream_concat(O, "%"PRIu64, imm);
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = imm;
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)imm;
MI->flat_insn.arm64.op_count++;
}
}
@@ -179,7 +179,7 @@
SStream *O, unsigned RegWidth)
{
MCOperand *ImmROp = MCInst_getOperand(MI, OpNum);
- unsigned LSB = MCOperand_getImm(ImmROp) == 0 ? 0 : RegWidth - MCOperand_getImm(ImmROp);
+ unsigned LSB = MCOperand_getImm(ImmROp) == 0 ? 0 : RegWidth - (unsigned int)MCOperand_getImm(ImmROp);
if (LSB > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", LSB);
@@ -195,7 +195,7 @@
static void printBFIWidthOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *ImmSOp = MCInst_getOperand(MI, OpNum);
- unsigned Width = MCOperand_getImm(ImmSOp) + 1;
+ unsigned Width = (unsigned int)MCOperand_getImm(ImmSOp) + 1;
if (Width > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", Width);
@@ -208,8 +208,8 @@
MCOperand *ImmSOp = MCInst_getOperand(MI, OpNum);
MCOperand *ImmROp = MCInst_getOperand(MI, OpNum - 1);
- unsigned ImmR = MCOperand_getImm(ImmROp);
- unsigned ImmS = MCOperand_getImm(ImmSOp);
+ unsigned ImmR = (unsigned int)MCOperand_getImm(ImmROp);
+ unsigned ImmS = (unsigned int)MCOperand_getImm(ImmSOp);
//assert(ImmS >= ImmR && "Invalid ImmR, ImmS combination for bitfield extract");
@@ -232,7 +232,7 @@
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_CIMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = MCOperand_getImm(CRx);
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)MCOperand_getImm(CRx);
MI->flat_insn.arm64.op_count++;
}
}
@@ -247,7 +247,7 @@
SStream_concat(O, "#%u", 64 - MCOperand_getImm(ScaleOp));
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = 64 - MCOperand_getImm(ScaleOp);
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = 64 - (int32_t)MCOperand_getImm(ScaleOp);
MI->flat_insn.arm64.op_count++;
}
}
@@ -259,7 +259,7 @@
//assert(MOImm8.isImm()
// && "Immediate operand required for floating-point immediate inst");
- uint32_t Imm8 = MCOperand_getImm(MOImm8);
+ uint32_t Imm8 = (uint32_t)MCOperand_getImm(MOImm8);
uint32_t Fraction = Imm8 & 0xf;
uint32_t Exponent = (Imm8 >> 4) & 0x7;
uint32_t Negative = (Imm8 >> 7) & 0x1;
@@ -326,7 +326,7 @@
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = SImm;
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)SImm;
MI->flat_insn.arm64.op_count++;
}
@@ -341,14 +341,14 @@
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
uint64_t Val;
- A64Imms_isLogicalImmBits(RegWidth, MCOperand_getImm(MO), &Val);
+ A64Imms_isLogicalImmBits(RegWidth, (uint32_t)MCOperand_getImm(MO), &Val);
if (Val > HEX_THRESHOLD)
SStream_concat(O, "#0x%"PRIx64, Val);
else
SStream_concat(O, "#%"PRIu64, Val);
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = Val;
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)Val;
MI->flat_insn.arm64.op_count++;
}
}
@@ -359,7 +359,7 @@
MCOperand *MOImm = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MOImm)) {
- uint32_t Imm = MCOperand_getImm(MOImm) * MemSize;
+ uint32_t Imm = (uint32_t)MCOperand_getImm(MOImm) * MemSize;
if (Imm > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", Imm);
@@ -395,7 +395,7 @@
default: break; // llvm_unreachable("Invalid shift specifier in logical instruction");
}
- unsigned int imm = MCOperand_getImm(MO);
+ unsigned int imm = (unsigned int)MCOperand_getImm(MO);
if (imm > HEX_THRESHOLD)
SStream_concat(O, " #0x%x", imm);
else
@@ -419,12 +419,12 @@
SStream_concat(O, "#%"PRIu64, imm);
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = imm;
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)imm;
MI->flat_insn.arm64.op_count++;
}
if (MCOperand_getImm(ShiftMO) != 0) {
- unsigned int shift = MCOperand_getImm(ShiftMO) * 16;
+ unsigned int shift = (unsigned int)MCOperand_getImm(ShiftMO) * 16;
if (shift > HEX_THRESHOLD)
SStream_concat(O, ", lsl #0x%x", shift);
else
@@ -443,7 +443,7 @@
{
bool ValidName;
MCOperand *MO = MCInst_getOperand(MI, OpNum);
- char *Name = NamedImmMapper_toString(Mapper, MCOperand_getImm(MO), &ValidName);
+ char *Name = NamedImmMapper_toString(Mapper, (uint32_t)MCOperand_getImm(MO), &ValidName);
if (ValidName)
SStream_concat(O, Name);
@@ -455,7 +455,7 @@
SStream_concat(O, "#%"PRIu64, imm);
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = imm;
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)imm;
MI->flat_insn.arm64.op_count++;
}
}
@@ -469,7 +469,7 @@
MCOperand *MO = MCInst_getOperand(MI, OpNum);
- SysRegMapper_toString(Mapper, MCOperand_getImm(MO), &ValidName, Name);
+ SysRegMapper_toString(Mapper, (uint32_t)MCOperand_getImm(MO), &ValidName, Name);
if (ValidName) {
SStream_concat(O, Name);
}
@@ -490,6 +490,7 @@
// easily. We will only accumulate more of these hacks.
unsigned Reg0 = MCOperand_getReg(MCInst_getOperand(MI, 0));
unsigned Reg1 = MCOperand_getReg(MCInst_getOperand(MI, 1));
+ MCOperand *MO;
if (isStackReg(Reg0) || isStackReg(Reg1)) {
A64SE_ShiftExtSpecifiers LSLEquiv;
@@ -500,7 +501,7 @@
LSLEquiv = A64SE_UXTW;
if (Ext == LSLEquiv) {
- unsigned int shift = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ unsigned int shift = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (shift > HEX_THRESHOLD)
SStream_concat(O, "lsl #0x%x", shift);
else
@@ -528,9 +529,9 @@
if (MI->csh->detail)
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].ext = Ext - 4;
- MCOperand *MO = MCInst_getOperand(MI, OpNum);
+ MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_getImm(MO) != 0) {
- unsigned int shift = MCOperand_getImm(MO);
+ unsigned int shift = (unsigned int)MCOperand_getImm(MO);
if (shift > HEX_THRESHOLD)
SStream_concat(O, " #0x%x", shift);
else
@@ -546,7 +547,7 @@
SStream *O, int MemScale)
{
MCOperand *MOImm = MCInst_getOperand(MI, OpNum);
- int32_t Imm = unpackSignedImm(7, MCOperand_getImm(MOImm));
+ int32_t Imm = (int32_t)unpackSignedImm(7, MCOperand_getImm(MOImm));
if (Imm * MemScale > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", Imm * MemScale);
@@ -605,10 +606,10 @@
SStream_concat(O, "#%"PRIu64, imm);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.disp = imm;
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.disp = (int32_t)imm;
} else {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = imm;
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)imm;
MI->flat_insn.arm64.op_count++;
}
}
@@ -669,7 +670,7 @@
else
SStream_concat(O, " #%"PRIu64, Imm);
if (MI->csh->detail)
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.value = Imm;
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.value = (unsigned int)Imm;
}
static void printNeonUImm0Operand(MCInst *MI, unsigned OpNum, SStream *O)
@@ -690,7 +691,7 @@
//assert(MOUImm.isImm() &&
// "Immediate operand required for Neon vector immediate inst.");
- unsigned Imm = MCOperand_getImm(MOUImm);
+ unsigned Imm = (unsigned int)MCOperand_getImm(MOUImm);
if (Imm > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", Imm);
@@ -710,7 +711,7 @@
//assert(MOUImm.isImm()
// && "Immediate operand required for Neon vector immediate inst.");
- unsigned Imm = MCOperand_getImm(MOUImm);
+ unsigned Imm = (unsigned int)MCOperand_getImm(MOUImm);
if (Imm > HEX_THRESHOLD)
SStream_concat(O, "0x%x", Imm);
else
@@ -732,7 +733,7 @@
//assert(MOUImm8.isImm() &&
// "Immediate operand required for Neon vector immediate bytemask inst.");
- uint32_t UImm8 = MCOperand_getImm(MOUImm8);
+ uint32_t UImm8 = (uint32_t)MCOperand_getImm(MOUImm8);
uint64_t Mask = 0;
// Replicates 0x00 or 0xff byte in a 64-bit vector
@@ -748,7 +749,7 @@
SStream_concat(O, "#%"PRIu64, Mask);
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = Mask;
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)Mask;
MI->flat_insn.arm64.op_count++;
}
}
diff --git a/arch/AArch64/AArch64Mapping.c b/arch/AArch64/AArch64Mapping.c
index ff608a5..3ecada2 100644
--- a/arch/AArch64/AArch64Mapping.c
+++ b/arch/AArch64/AArch64Mapping.c
@@ -2966,8 +2966,8 @@
// some alias instruction only need to be defined locally to satisfy
// some lookup functions
// just make sure these IDs never reuse any other IDs ARM_INS_*
-#define ARM64_INS_NEGS -1
-#define ARM64_INS_NGCS -2
+#define ARM64_INS_NEGS (unsigned short)-1
+#define ARM64_INS_NGCS (unsigned short)-2
// all alias instructions & their semantic infos
static insn_map alias_insns[] = {
@@ -3003,13 +3003,13 @@
handle.detail = h->detail;
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
- insn->detail->regs_read_count = count_positive(insns[i].regs_use);
+ insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
- insn->detail->regs_write_count = count_positive(insns[i].regs_mod);
+ insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
- insn->detail->groups_count = count_positive(insns[i].groups);
+ insn->detail->groups_count = (uint8_t)count_positive(insns[i].groups);
insn->detail->arm64.update_flags = cs_reg_write((csh)&handle, insn, ARM64_REG_NZCV);
diff --git a/arch/AArch64/AArch64Module.c b/arch/AArch64/AArch64Module.c
index c3d18f6..83b4f4b 100644
--- a/arch/AArch64/AArch64Module.c
+++ b/arch/AArch64/AArch64Module.c
@@ -11,11 +11,13 @@
static cs_err init(cs_struct *ud)
{
+ MCRegisterInfo *mri;
+
// verify if requested mode is valid
if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_ARM | CS_MODE_BIG_ENDIAN))
return CS_ERR_MODE;
- MCRegisterInfo *mri = cs_mem_malloc(sizeof(*mri));
+ mri = cs_mem_malloc(sizeof(*mri));
AArch64_init(mri);
ud->printer = AArch64_printInst;