arm64: vector_index = 0 is valid. this changed invalid value of vector_index to -1
diff --git a/arch/AArch64/AArch64Disassembler.c b/arch/AArch64/AArch64Disassembler.c
index a1bcadb..600d402 100644
--- a/arch/AArch64/AArch64Disassembler.c
+++ b/arch/AArch64/AArch64Disassembler.c
@@ -224,6 +224,7 @@
{
uint32_t insn;
DecodeStatus result;
+ int i;
if (code_len < 4) {
// not enough data
@@ -233,6 +234,8 @@
if (MI->flat_insn->detail) {
memset(MI->flat_insn->detail, 0, sizeof(cs_detail));
+ for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm64.operands); i++)
+ MI->flat_insn->detail->arm64.operands[i].vector_index = -1;
}
if (ud->big_endian)
diff --git a/bindings/python/test_arm64.py b/bindings/python/test_arm64.py
index 0c3103c..5ad9b0f 100755
--- a/bindings/python/test_arm64.py
+++ b/bindings/python/test_arm64.py
@@ -72,7 +72,7 @@
if i.vess != ARM64_VESS_INVALID:
print("\t\t\tVector Element Size Specifier: %u" % i.vess)
- if i.vector_index != 0:
+ if i.vector_index != -1:
print("\t\t\tVector Index: %u" % i.vector_index)
if insn.writeback:
diff --git a/include/arm64.h b/include/arm64.h
index 9749b7d..9dcdc39 100644
--- a/include/arm64.h
+++ b/include/arm64.h
@@ -353,7 +353,7 @@
// Instruction operand
typedef struct cs_arm64_op {
- int vector_index; // Vector Index for some vector operands (or 0 if irrelevant)
+ int vector_index; // Vector Index for some vector operands (or -1 if irrelevant)
arm64_vas vas; // Vector Arrangement Specifier
arm64_vess vess; // Vector Element Size Specifier
struct {
diff --git a/tests/test_arm64.c b/tests/test_arm64.c
index cfc539d..f344dcf 100644
--- a/tests/test_arm64.c
+++ b/tests/test_arm64.c
@@ -103,7 +103,7 @@
if (op->vess != ARM64_VESS_INVALID)
printf("\t\t\tVector Element Size Specifier: %u\n", op->vess);
- if (op->vector_index != 0)
+ if (op->vector_index != -1)
printf("\t\t\tVector Index: %u\n", op->vector_index);
}